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serial: fsl_lpuart: Reset prior to registration
[linux-block.git] / drivers / tty / serial / 8250 / 8250_omap.c
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e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0
61929cf0
SAS		 2/*
3 * 8250-core based driver for the OMAP internal UART
4 *
5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
6 *
7 * Copyright (C) 2014 Sebastian Andrzej Siewior
8 *
9 */
10
7d470ebf 11#include <linux/clk.h>
61929cf0
SAS		 12#include <linux/device.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/serial_8250.h>
61929cf0 16#include <linux/serial_reg.h>
77285243 17#include <linux/tty_flip.h>
61929cf0
SAS		 18#include <linux/platform_device.h>
19#include <linux/slab.h>
20#include <linux/of.h>
4fcdff9b 21#include <linux/of_device.h>
61929cf0
SAS		 22#include <linux/of_gpio.h>
23#include <linux/of_irq.h>
24#include <linux/delay.h>
25#include <linux/pm_runtime.h>
26#include <linux/console.h>
27#include <linux/pm_qos.h>
a3e362f1 28#include <linux/pm_wakeirq.h>
31a17132 29#include <linux/dma-mapping.h>
439c7183 30#include <linux/sys_soc.h>
61929cf0
SAS		 31
32#include "8250.h"
33
34#define DEFAULT_CLK_SPEED 48000000
35
36#define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
37#define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
31a17132 38#define OMAP_DMA_TX_KICK (1 << 2)
cdb929e4
SN		 39/*
40 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
41 * The same errata is applicable to AM335x and DRA7x processors too.
42 */
43#define UART_ERRATA_CLOCK_DISABLE (1 << 3)
c26389f9 44#define UART_HAS_EFR2 BIT(4)
439c7183 45#define UART_HAS_RHR_IT_DIS BIT(5)
b67e830d 46#define UART_RX_TIMEOUT_QUIRK BIT(6)
61929cf0
SAS		 47
48#define OMAP_UART_FCR_RX_TRIG 6
49#define OMAP_UART_FCR_TX_TRIG 4
50
51/* SCR register bitmasks */
52#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
53#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
54#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
55#define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
56#define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
57#define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
58
59/* MVR register bitmasks */
60#define OMAP_UART_MVR_SCHEME_SHIFT 30
61#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
62#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
63#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
64#define OMAP_UART_MVR_MAJ_MASK 0x700
65#define OMAP_UART_MVR_MAJ_SHIFT 8
66#define OMAP_UART_MVR_MIN_MASK 0x3f
67
cdb929e4
SN		 68/* SYSC register bitmasks */
69#define OMAP_UART_SYSC_SOFTRESET (1 << 1)
70
71/* SYSS register bitmasks */
72#define OMAP_UART_SYSS_RESETDONE (1 << 0)
73
61929cf0
SAS		 74#define UART_TI752_TLR_TX 0
75#define UART_TI752_TLR_RX 4
76
77#define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
78#define TRIGGER_FCR_MASK(x) (x & 3)
79
80/* Enable XON/XOFF flow control on output */
81#define OMAP_UART_SW_TX 0x08
82/* Enable XON/XOFF flow control on input */
83#define OMAP_UART_SW_RX 0x02
84
85#define OMAP_UART_WER_MOD_WKUP 0x7f
86#define OMAP_UART_TX_WAKEUP_EN (1 << 7)
87
88#define TX_TRIGGER 1
89#define RX_TRIGGER 48
90
91#define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
92#define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
93
94#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
95
96#define OMAP_UART_REV_46 0x0406
97#define OMAP_UART_REV_52 0x0502
98#define OMAP_UART_REV_63 0x0603
99
439c7183
VR		 100/* Interrupt Enable Register 2 */
101#define UART_OMAP_IER2 0x1B
102#define UART_OMAP_IER2_RHR_IT_DIS BIT(2)
103
c26389f9
VR		 104/* Enhanced features register 2 */
105#define UART_OMAP_EFR2 0x23
106#define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6)
107
b67e830d 108/* RX FIFO occupancy indicator */
79e9e30a 109#define UART_OMAP_RX_LVL 0x19
b67e830d 110
61929cf0
SAS		 111struct omap8250_priv {
112 int line;
113 u8 habit;
114 u8 mdr1;
115 u8 efr;
116 u8 scr;
117 u8 wer;
118 u8 xon;
119 u8 xoff;
0a0661dd 120 u8 delayed_restore;
61929cf0
SAS		 121 u16 quot;
122
7229b84c
VR		 123 u8 tx_trigger;
124 u8 rx_trigger;
61929cf0
SAS		 125 bool is_suspending;
126 int wakeirq;
127 int wakeups_enabled;
128 u32 latency;
129 u32 calc_latency;
130 struct pm_qos_request pm_qos_request;
131 struct work_struct qos_work;
132 struct uart_8250_dma omap8250_dma;
eda0cd35 133 spinlock_t rx_dma_lock;
830acf9e 134 bool rx_dma_broken;
08fb00c6 135 bool throttled;
61929cf0
SAS		 136};
137
7229b84c
VR		 138struct omap8250_dma_params {
139 u32 rx_size;
140 u8 rx_trigger;
141 u8 tx_trigger;
142};
143
144struct omap8250_platdata {
145 struct omap8250_dma_params *dma_params;
146 u8 habit;
147};
148
33d9b8b2
PH		 149#ifdef CONFIG_SERIAL_8250_DMA
150static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
151#else
152static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
153#endif
154
61929cf0
SAS		 155static u32 uart_read(struct uart_8250_port *up, u32 reg)
156{
157 return readl(up->port.membase + (reg << up->port.regshift));
158}
159
4bf4ea9d
PH		 160static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
161{
162 struct uart_8250_port *up = up_to_u8250p(port);
163 struct omap8250_priv *priv = up->port.private_data;
164 u8 lcr;
165
166 serial8250_do_set_mctrl(port, mctrl);
167
fc64f7ab 168 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
4a96895f
YY		 169 /*
170 * Turn off autoRTS if RTS is lowered and restore autoRTS
171 * setting if RTS is raised
172 */
173 lcr = serial_in(up, UART_LCR);
174 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
175 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
176 priv->efr |= UART_EFR_RTS;
177 else
178 priv->efr &= ~UART_EFR_RTS;
179 serial_out(up, UART_EFR, priv->efr);
180 serial_out(up, UART_LCR, lcr);
181 }
4bf4ea9d
PH		 182}
183
61929cf0
SAS		 184/*
185 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
186 * The access to uart register after MDR1 Access
187 * causes UART to corrupt data.
188 *
189 * Need a delay =
190 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
191 * give 10 times as much
192 */
193static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
194 struct omap8250_priv *priv)
195{
196 u8 timeout = 255;
61929cf0
SAS		 197
198 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
199 udelay(2);
200 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
201 UART_FCR_CLEAR_RCVR);
202 /*
203 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
204 * TX_FIFO_E bit is 1.
205 */
206 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
207 (UART_LSR_THRE | UART_LSR_DR))) {
208 timeout--;
209 if (!timeout) {
210 /* Should *never* happen. we warn and carry on */
211 dev_crit(up->port.dev, "Errata i202: timedout %x\n",
212 serial_in(up, UART_LSR));
213 break;
214 }
215 udelay(1);
216 }
217}
218
219static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
220 struct omap8250_priv *priv)
221{
222 unsigned int uartclk = port->uartclk;
223 unsigned int div_13, div_16;
224 unsigned int abs_d13, abs_d16;
225
226 /*
227 * Old custom speed handling.
228 */
229 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
6263368c 230 priv->quot = port->custom_divisor & UART_DIV_MAX;
61929cf0
SAS		 231 /*
232 * I assume that nobody is using this. But hey, if somebody
233 * would like to specify the divisor _and_ the mode then the
234 * driver is ready and waiting for it.
235 */
236 if (port->custom_divisor & (1 << 16))
237 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
238 else
239 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
240 return;
241 }
242 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
243 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
244
245 if (!div_13)
246 div_13 = 1;
247 if (!div_16)
248 div_16 = 1;
249
250 abs_d13 = abs(baud - uartclk / 13 / div_13);
251 abs_d16 = abs(baud - uartclk / 16 / div_16);
252
253 if (abs_d13 >= abs_d16) {
254 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
255 priv->quot = div_16;
256 } else {
257 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
258 priv->quot = div_13;
259 }
260}
261
262static void omap8250_update_scr(struct uart_8250_port *up,
263 struct omap8250_priv *priv)
264{
265 u8 old_scr;
266
267 old_scr = serial_in(up, UART_OMAP_SCR);
268 if (old_scr == priv->scr)
269 return;
270
271 /*
272 * The manual recommends not to enable the DMA mode selector in the SCR
273 * (instead of the FCR) register _and_ selecting the DMA mode as one
274 * register write because this may lead to malfunction.
275 */
276 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
277 serial_out(up, UART_OMAP_SCR,
278 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
279 serial_out(up, UART_OMAP_SCR, priv->scr);
280}
281
6f03541f
SN		 282static void omap8250_update_mdr1(struct uart_8250_port *up,
283 struct omap8250_priv *priv)
284{
285 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
286 omap_8250_mdr1_errataset(up, priv);
287 else
288 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
289}
290
61929cf0
SAS		 291static void omap8250_restore_regs(struct uart_8250_port *up)
292{
293 struct omap8250_priv *priv = up->port.private_data;
0a0661dd
SAS		 294 struct uart_8250_dma *dma = up->dma;
295
296 if (dma && dma->tx_running) {
297 /*
298 * TCSANOW requests the change to occur immediately however if
299 * we have a TX-DMA operation in progress then it has been
300 * observed that it might stall and never complete. Therefore we
301 * delay DMA completes to prevent this hang from happen.
302 */
303 priv->delayed_restore = 1;
304 return;
305 }
61929cf0
SAS		 306
307 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
308 serial_out(up, UART_EFR, UART_EFR_ECB);
309
310 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
36fd95b1 311 serial8250_out_MCR(up, UART_MCR_TCRTLR);
61929cf0
SAS		 312 serial_out(up, UART_FCR, up->fcr);
313
314 omap8250_update_scr(up, priv);
315
316 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
317
318 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
319 OMAP_UART_TCR_HALT(52));
320 serial_out(up, UART_TI752_TLR,
7229b84c
VR		 321 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX |
322 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX);
61929cf0
SAS		 323
324 serial_out(up, UART_LCR, 0);
325
326 /* drop TCR + TLR access, we setup XON/XOFF later */
36fd95b1 327 serial8250_out_MCR(up, up->mcr);
61929cf0
SAS		 328 serial_out(up, UART_IER, up->ier);
329
330 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
331 serial_dl_write(up, priv->quot);
332
9719acce 333 serial_out(up, UART_EFR, priv->efr);
61929cf0
SAS		 334
335 /* Configure flow control */
336 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
337 serial_out(up, UART_XON1, priv->xon);
338 serial_out(up, UART_XOFF1, priv->xoff);
339
340 serial_out(up, UART_LCR, up->lcr);
6f03541f
SN		 341
342 omap8250_update_mdr1(up, priv);
343
61929cf0
SAS		 344 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
345}
346
347/*
348 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
349 * some differences in how we want to handle flow control.
350 */
351static void omap_8250_set_termios(struct uart_port *port,
352 struct ktermios *termios,
353 struct ktermios *old)
354{
013e3586 355 struct uart_8250_port *up = up_to_u8250p(port);
61929cf0
SAS		 356 struct omap8250_priv *priv = up->port.private_data;
357 unsigned char cval = 0;
358 unsigned int baud;
359
988c5bbe 360 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
61929cf0
SAS		 361
362 if (termios->c_cflag & CSTOPB)
363 cval |= UART_LCR_STOP;
364 if (termios->c_cflag & PARENB)
365 cval |= UART_LCR_PARITY;
366 if (!(termios->c_cflag & PARODD))
367 cval |= UART_LCR_EPAR;
368 if (termios->c_cflag & CMSPAR)
369 cval |= UART_LCR_SPAR;
370
371 /*
372 * Ask the core to calculate the divisor for us.
373 */
374 baud = uart_get_baud_rate(port, termios, old,
6263368c 375 port->uartclk / 16 / UART_DIV_MAX,
61929cf0
SAS		 376 port->uartclk / 13);
377 omap_8250_get_divisor(port, baud, priv);
378
379 /*
380 * Ok, we're now changing the port state. Do it with
381 * interrupts disabled.
382 */
383 pm_runtime_get_sync(port->dev);
384 spin_lock_irq(&port->lock);
385
386 /*
387 * Update the per-port timeout.
388 */
389 uart_update_timeout(port, termios->c_cflag, baud);
390
391 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
392 if (termios->c_iflag & INPCK)
393 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
394 if (termios->c_iflag & (IGNBRK | PARMRK))
395 up->port.read_status_mask |= UART_LSR_BI;
396
397 /*
398 * Characters to ignore
399 */
400 up->port.ignore_status_mask = 0;
401 if (termios->c_iflag & IGNPAR)
402 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
403 if (termios->c_iflag & IGNBRK) {
404 up->port.ignore_status_mask |= UART_LSR_BI;
405 /*
406 * If we're ignoring parity and break indicators,
407 * ignore overruns too (for real raw support).
408 */
409 if (termios->c_iflag & IGNPAR)
410 up->port.ignore_status_mask |= UART_LSR_OE;
411 }
412
413 /*
414 * ignore all characters if CREAD is not set
415 */
416 if ((termios->c_cflag & CREAD) == 0)
417 up->port.ignore_status_mask |= UART_LSR_DR;
418
419 /*
420 * Modem status interrupts
421 */
422 up->ier &= ~UART_IER_MSI;
423 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
424 up->ier |= UART_IER_MSI;
425
426 up->lcr = cval;
427 /* Up to here it was mostly serial8250_do_set_termios() */
428
429 /*
93ad8673 430 * We enable TRIG_GRANU for RX and TX and additionally we set
61929cf0
SAS		 431 * SCR_TX_EMPTY bit. The result is the following:
432 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
433 * - less than RX_TRIGGER number of bytes will also cause an interrupt
434 * once the UART decides that there no new bytes arriving.
435 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
436 * empty - the trigger level is ignored here.
437 *
438 * Once DMA is enabled:
439 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
440 * bytes in the TX FIFO. On each assert the DMA engine will move
441 * TX_TRIGGER bytes into the FIFO.
442 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
443 * the FIFO and move RX_TRIGGER bytes.
444 * This is because threshold and trigger values are the same.
445 */
446 up->fcr = UART_FCR_ENABLE_FIFO;
7229b84c
VR		 447 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
448 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
61929cf0
SAS		 449
450 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
451 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
452
0a0661dd
SAS		 453 if (up->dma)
454 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
455 OMAP_UART_SCR_DMAMODE_CTL;
456
61929cf0
SAS		 457 priv->xon = termios->c_cc[VSTART];
458 priv->xoff = termios->c_cc[VSTOP];
459
460 priv->efr = 0;
391f93f2
PH		 461 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
462
4a96895f 463 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
fc64f7ab
AF		 464 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
465 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
9719acce 466 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
391f93f2 467 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
9719acce 468 priv->efr |= UART_EFR_CTS;
61929cf0
SAS		 469 } else if (up->port.flags & UPF_SOFT_FLOW) {
470 /*
5bac4b3d
PH		 471 * OMAP rx s/w flow control is borked; the transmitter remains
472 * stuck off even if rx flow control is subsequently disabled
61929cf0 473 */
61929cf0
SAS		 474
475 /*
476 * IXOFF Flag:
477 * Enable XON/XOFF flow control on output.
478 * Transmit XON1, XOFF1
479 */
391f93f2
PH		 480 if (termios->c_iflag & IXOFF) {
481 up->port.status |= UPSTAT_AUTOXOFF;
61929cf0 482 priv->efr |= OMAP_UART_SW_TX;
391f93f2 483 }
61929cf0
SAS		 484 }
485 omap8250_restore_regs(up);
486
487 spin_unlock_irq(&up->port.lock);
488 pm_runtime_mark_last_busy(port->dev);
489 pm_runtime_put_autosuspend(port->dev);
490
491 /* calculate wakeup latency constraint */
492 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
493 priv->latency = priv->calc_latency;
494
495 schedule_work(&priv->qos_work);
496
497 /* Don't rewrite B0 */
498 if (tty_termios_baud_rate(termios))
499 tty_termios_encode_baud_rate(termios, baud, baud);
500}
501
502/* same as 8250 except that we may have extra flow bits set in EFR */
503static void omap_8250_pm(struct uart_port *port, unsigned int state,
504 unsigned int oldstate)
505{
3e29af27
PH		 506 struct uart_8250_port *up = up_to_u8250p(port);
507 u8 efr;
61929cf0
SAS		 508
509 pm_runtime_get_sync(port->dev);
510 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
3e29af27
PH		 511 efr = serial_in(up, UART_EFR);
512 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
61929cf0
SAS		 513 serial_out(up, UART_LCR, 0);
514
515 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
516 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
3e29af27 517 serial_out(up, UART_EFR, efr);
61929cf0
SAS		 518 serial_out(up, UART_LCR, 0);
519
520 pm_runtime_mark_last_busy(port->dev);
521 pm_runtime_put_autosuspend(port->dev);
522}
523
524static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
525 struct omap8250_priv *priv)
526{
cb3ea80b 527 static const struct soc_device_attribute k3_soc_devices[] = {
6f991850
VR		 528 { .family = "AM65X", },
529 { .family = "J721E", .revision = "SR1.0" },
530 { /* sentinel */ }
531 };
61929cf0
SAS		 532 u32 mvr, scheme;
533 u16 revision, major, minor;
534
535 mvr = uart_read(up, UART_OMAP_MVER);
536
537 /* Check revision register scheme */
538 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
539
540 switch (scheme) {
541 case 0: /* Legacy Scheme: OMAP2/3 */
542 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
543 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
544 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
545 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
546 break;
547 case 1:
548 /* New Scheme: OMAP4+ */
549 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
550 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
551 OMAP_UART_MVR_MAJ_SHIFT;
552 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
553 break;
554 default:
555 dev_warn(up->port.dev,
556 "Unknown revision, defaulting to highest\n");
557 /* highest possible revision */
558 major = 0xff;
559 minor = 0xff;
560 }
561 /* normalize revision for the driver */
562 revision = UART_BUILD_REVISION(major, minor);
563
564 switch (revision) {
565 case OMAP_UART_REV_46:
4fcdff9b 566 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
61929cf0
SAS		 567 break;
568 case OMAP_UART_REV_52:
4fcdff9b 569 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
61929cf0
SAS		 570 OMAP_UART_WER_HAS_TX_WAKEUP;
571 break;
572 case OMAP_UART_REV_63:
4fcdff9b 573 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
61929cf0
SAS		 574 OMAP_UART_WER_HAS_TX_WAKEUP;
575 break;
576 default:
577 break;
578 }
6f991850
VR		 579
580 /*
581 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't
582 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag
583 * to enable errata workaround.
584 */
585 if (soc_device_match(k3_soc_devices))
586 priv->habit &= ~UART_HAS_RHR_IT_DIS;
61929cf0
SAS		 587}
588
589static void omap8250_uart_qos_work(struct work_struct *work)
590{
591 struct omap8250_priv *priv;
592
593 priv = container_of(work, struct omap8250_priv, qos_work);
01d2b189 594 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency);
61929cf0
SAS		 595}
596
9e91597f
SAS		 597#ifdef CONFIG_SERIAL_8250_DMA
598static int omap_8250_dma_handle_irq(struct uart_port *port);
599#endif
600
601static irqreturn_t omap8250_irq(int irq, void *dev_id)
602{
603 struct uart_port *port = dev_id;
b67e830d 604 struct omap8250_priv *priv = port->private_data;
9e91597f 605 struct uart_8250_port *up = up_to_u8250p(port);
1fe0e1fa 606 unsigned int iir, lsr;
9e91597f
SAS		 607 int ret;
608
609#ifdef CONFIG_SERIAL_8250_DMA
610 if (up->dma) {
611 ret = omap_8250_dma_handle_irq(port);
612 return IRQ_RETVAL(ret);
613 }
614#endif
615
616 serial8250_rpm_get(up);
1fe0e1fa 617 lsr = serial_port_in(port, UART_LSR);
9e91597f
SAS		 618 iir = serial_port_in(port, UART_IIR);
619 ret = serial8250_handle_irq(port, iir);
b67e830d
VR		 620
621 /*
622 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after
623 * FIFO has been drained, in which case a dummy read of RX FIFO
624 * is required to clear RX TIMEOUT condition.
625 */
626 if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
627 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
628 serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
629 serial_port_in(port, UART_RX);
630 }
631
1fe0e1fa
TL		 632 /* Stop processing interrupts on input overrun */
633 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
634 unsigned long delay;
635
636 up->ier = port->serial_in(port, UART_IER);
637 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
638 port->ops->stop_rx(port);
639 } else {
640 /* Keep restarting the timer until
641 * the input overrun subsides.
642 */
643 cancel_delayed_work(&up->overrun_backoff);
644 }
645
646 delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
647 schedule_delayed_work(&up->overrun_backoff, delay);
648 }
649
9e91597f
SAS		 650 serial8250_rpm_put(up);
651
652 return IRQ_RETVAL(ret);
653}
654
61929cf0
SAS		 655static int omap_8250_startup(struct uart_port *port)
656{
9e91597f 657 struct uart_8250_port *up = up_to_u8250p(port);
61929cf0 658 struct omap8250_priv *priv = port->private_data;
61929cf0
SAS		 659 int ret;
660
661 if (priv->wakeirq) {
a3e362f1 662 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
61929cf0
SAS		 663 if (ret)
664 return ret;
61929cf0
SAS		 665 }
666
667 pm_runtime_get_sync(port->dev);
668
9e91597f
SAS		 669 up->mcr = 0;
670 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
671
672 serial_out(up, UART_LCR, UART_LCR_WLEN8);
673
674 up->lsr_saved_flags = 0;
675 up->msr_saved_flags = 0;
676
84b40e3b
V		 677 /* Disable DMA for console UART */
678 if (uart_console(port))
679 up->dma = NULL;
680
9e91597f
SAS		 681 if (up->dma) {
682 ret = serial8250_request_dma(up);
683 if (ret) {
684 dev_warn_ratelimited(port->dev,
685 "failed to request DMA\n");
686 up->dma = NULL;
687 }
688 }
689
690 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
691 dev_name(port->dev), port);
692 if (ret < 0)
61929cf0
SAS		 693 goto err;
694
9e91597f
SAS		 695 up->ier = UART_IER_RLSI | UART_IER_RDI;
696 serial_out(up, UART_IER, up->ier);
697
71504e51 698#ifdef CONFIG_PM
61929cf0
SAS		 699 up->capabilities |= UART_CAP_RPM;
700#endif
701
702 /* Enable module level wake up */
703 priv->wer = OMAP_UART_WER_MOD_WKUP;
704 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
705 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
706 serial_out(up, UART_OMAP_WER, priv->wer);
707
c26389f9 708 if (up->dma && !(priv->habit & UART_HAS_EFR2))
33d9b8b2 709 up->dma->rx_dma(up);
0a0661dd 710
61929cf0
SAS		 711 pm_runtime_mark_last_busy(port->dev);
712 pm_runtime_put_autosuspend(port->dev);
713 return 0;
714err:
715 pm_runtime_mark_last_busy(port->dev);
716 pm_runtime_put_autosuspend(port->dev);
a3e362f1 717 dev_pm_clear_wake_irq(port->dev);
61929cf0
SAS		 718 return ret;
719}
720
721static void omap_8250_shutdown(struct uart_port *port)
722{
9e91597f 723 struct uart_8250_port *up = up_to_u8250p(port);
61929cf0
SAS		 724 struct omap8250_priv *priv = port->private_data;
725
726 flush_work(&priv->qos_work);
0a0661dd 727 if (up->dma)
33d9b8b2 728 omap_8250_rx_dma_flush(up);
61929cf0
SAS		 729
730 pm_runtime_get_sync(port->dev);
731
732 serial_out(up, UART_OMAP_WER, 0);
c26389f9
VR		 733 if (priv->habit & UART_HAS_EFR2)
734 serial_out(up, UART_OMAP_EFR2, 0x0);
9e91597f
SAS		 735
736 up->ier = 0;
737 serial_out(up, UART_IER, 0);
738
739 if (up->dma)
740 serial8250_release_dma(up);
741
742 /*
743 * Disable break condition and FIFOs
744 */
745 if (up->lcr & UART_LCR_SBC)
746 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
747 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
61929cf0
SAS		 748
749 pm_runtime_mark_last_busy(port->dev);
750 pm_runtime_put_autosuspend(port->dev);
9e91597f 751 free_irq(port->irq, port);
a3e362f1 752 dev_pm_clear_wake_irq(port->dev);
61929cf0
SAS		 753}
754
755static void omap_8250_throttle(struct uart_port *port)
756{
08fb00c6 757 struct omap8250_priv *priv = port->private_data;
61929cf0 758 unsigned long flags;
61929cf0
SAS		 759
760 pm_runtime_get_sync(port->dev);
761
762 spin_lock_irqsave(&port->lock, flags);
f4b042a0 763 port->ops->stop_rx(port);
08fb00c6 764 priv->throttled = true;
61929cf0
SAS		 765 spin_unlock_irqrestore(&port->lock, flags);
766
767 pm_runtime_mark_last_busy(port->dev);
768 pm_runtime_put_autosuspend(port->dev);
769}
770
771static void omap_8250_unthrottle(struct uart_port *port)
772{
08fb00c6 773 struct omap8250_priv *priv = port->private_data;
013e3586 774 struct uart_8250_port *up = up_to_u8250p(port);
61929cf0 775 unsigned long flags;
61929cf0
SAS		 776
777 pm_runtime_get_sync(port->dev);
778
779 spin_lock_irqsave(&port->lock, flags);
08fb00c6
V		 780 priv->throttled = false;
781 if (up->dma)
782 up->dma->rx_dma(up);
61929cf0 783 up->ier |= UART_IER_RLSI | UART_IER_RDI;
f4b042a0 784 port->read_status_mask |= UART_LSR_DR;
61929cf0
SAS		 785 serial_out(up, UART_IER, up->ier);
786 spin_unlock_irqrestore(&port->lock, flags);
787
788 pm_runtime_mark_last_busy(port->dev);
789 pm_runtime_put_autosuspend(port->dev);
790}
791
31a17132 792#ifdef CONFIG_SERIAL_8250_DMA
33d9b8b2 793static int omap_8250_rx_dma(struct uart_8250_port *p);
0e31c8d1 794
78989841 795/* Must be called while priv->rx_dma_lock is held */
b74fdd23 796static void __dma_rx_do_complete(struct uart_8250_port *p)
0e31c8d1
SAS		 797{
798 struct uart_8250_dma *dma = p->dma;
799 struct tty_port *tty_port = &p->port.state->port;
439c7183 800 struct omap8250_priv *priv = p->port.private_data;
4bcf59a5
VR		 801 struct dma_chan *rxchan = dma->rxchan;
802 dma_cookie_t cookie;
0e31c8d1
SAS		 803 struct dma_tx_state state;
804 int count;
658e2ebc 805 int ret;
439c7183 806 u32 reg;
0e31c8d1 807
eda0cd35 808 if (!dma->rx_running)
78989841 809 goto out;
eda0cd35 810
4bcf59a5 811 cookie = dma->rx_cookie;
0e31c8d1 812 dma->rx_running = 0;
439c7183
VR		 813
814 /* Re-enable RX FIFO interrupt now that transfer is complete */
815 if (priv->habit & UART_HAS_RHR_IT_DIS) {
816 reg = serial_in(p, UART_OMAP_IER2);
817 reg &= ~UART_OMAP_IER2_RHR_IT_DIS;
818 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
819 }
820
4bcf59a5 821 dmaengine_tx_status(rxchan, cookie, &state);
0e31c8d1 822
4bcf59a5
VR		 823 count = dma->rx_size - state.residue + state.in_flight_bytes;
824 if (count < dma->rx_size) {
825 dmaengine_terminate_async(rxchan);
826
827 /*
828 * Poll for teardown to complete which guarantees in
829 * flight data is drained.
830 */
831 if (state.in_flight_bytes) {
832 int poll_count = 25;
0e31c8d1 833
4bcf59a5
VR		 834 while (dmaengine_tx_status(rxchan, cookie, NULL) &&
835 poll_count--)
836 cpu_relax();
0e31c8d1 837
d7e325aa 838 if (poll_count == -1)
4bcf59a5
VR		 839 dev_err(p->port.dev, "teardown incomplete\n");
840 }
841 }
7cf4df30 842 if (!count)
78989841 843 goto out;
658e2ebc
SAS		 844 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
845
846 p->port.icount.rx += ret;
847 p->port.icount.buf_overrun += count - ret;
78989841 848out:
eda0cd35 849
0e31c8d1
SAS		 850 tty_flip_buffer_push(tty_port);
851}
852
853static void __dma_rx_complete(void *param)
854{
a1bfb6eb 855 struct uart_8250_port *p = param;
08fb00c6 856 struct omap8250_priv *priv = p->port.private_data;
a1bfb6eb
V		 857 struct uart_8250_dma *dma = p->dma;
858 struct dma_tx_state state;
859 unsigned long flags;
860
861 spin_lock_irqsave(&p->port.lock, flags);
862
863 /*
864 * If the tx status is not DMA_COMPLETE, then this is a delayed
865 * completion callback. A previous RX timeout flush would have
866 * already pushed the data, so exit.
867 */
868 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
869 DMA_COMPLETE) {
870 spin_unlock_irqrestore(&p->port.lock, flags);
871 return;
872 }
873 __dma_rx_do_complete(p);
c26389f9
VR		 874 if (!priv->throttled) {
875 p->ier |= UART_IER_RLSI | UART_IER_RDI;
876 serial_out(p, UART_IER, p->ier);
877 if (!(priv->habit & UART_HAS_EFR2))
878 omap_8250_rx_dma(p);
879 }
a1bfb6eb
V		 880
881 spin_unlock_irqrestore(&p->port.lock, flags);
0e31c8d1
SAS		 882}
883
eda0cd35
JO		 884static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
885{
886 struct omap8250_priv *priv = p->port.private_data;
887 struct uart_8250_dma *dma = p->dma;
75f54acc 888 struct dma_tx_state state;
eda0cd35 889 unsigned long flags;
830acf9e 890 int ret;
eda0cd35
JO		 891
892 spin_lock_irqsave(&priv->rx_dma_lock, flags);
893
894 if (!dma->rx_running) {
895 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
896 return;
897 }
898
75f54acc
V		 899 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
900 if (ret == DMA_IN_PROGRESS) {
901 ret = dmaengine_pause(dma->rxchan);
902 if (WARN_ON_ONCE(ret))
903 priv->rx_dma_broken = true;
904 }
b74fdd23 905 __dma_rx_do_complete(p);
78989841 906 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
eda0cd35
JO		 907}
908
33d9b8b2 909static int omap_8250_rx_dma(struct uart_8250_port *p)
0e31c8d1 910{
eda0cd35 911 struct omap8250_priv *priv = p->port.private_data;
0e31c8d1 912 struct uart_8250_dma *dma = p->dma;
eda0cd35 913 int err = 0;
0e31c8d1 914 struct dma_async_tx_descriptor *desc;
eda0cd35 915 unsigned long flags;
439c7183 916 u32 reg;
0e31c8d1 917
830acf9e
SAS		 918 if (priv->rx_dma_broken)
919 return -EINVAL;
920
eda0cd35
JO		 921 spin_lock_irqsave(&priv->rx_dma_lock, flags);
922
c26389f9
VR		 923 if (dma->rx_running) {
924 enum dma_status state;
925
926 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL);
927 if (state == DMA_COMPLETE) {
928 /*
929 * Disable RX interrupts to allow RX DMA completion
930 * callback to run.
931 */
932 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
933 serial_out(p, UART_IER, p->ier);
934 }
eda0cd35 935 goto out;
c26389f9 936 }
0e31c8d1
SAS		 937
938 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
939 dma->rx_size, DMA_DEV_TO_MEM,
940 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
eda0cd35
JO		 941 if (!desc) {
942 err = -EBUSY;
943 goto out;
944 }
0e31c8d1
SAS		 945
946 dma->rx_running = 1;
947 desc->callback = __dma_rx_complete;
948 desc->callback_param = p;
949
950 dma->rx_cookie = dmaengine_submit(desc);
951
439c7183
VR		 952 /*
953 * Disable RX FIFO interrupt while RX DMA is enabled, else
954 * spurious interrupt may be raised when data is in the RX FIFO
955 * but is yet to be drained by DMA.
956 */
957 if (priv->habit & UART_HAS_RHR_IT_DIS) {
958 reg = serial_in(p, UART_OMAP_IER2);
959 reg |= UART_OMAP_IER2_RHR_IT_DIS;
960 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
961 }
962
0e31c8d1 963 dma_async_issue_pending(dma->rxchan);
eda0cd35
JO		 964out:
965 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
966 return err;
0e31c8d1
SAS		 967}
968
31a17132
SAS		 969static int omap_8250_tx_dma(struct uart_8250_port *p);
970
971static void omap_8250_dma_tx_complete(void *param)
972{
973 struct uart_8250_port *p = param;
974 struct uart_8250_dma *dma = p->dma;
975 struct circ_buf *xmit = &p->port.state->xmit;
976 unsigned long flags;
977 bool en_thri = false;
0a0661dd 978 struct omap8250_priv *priv = p->port.private_data;
31a17132
SAS		 979
980 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
981 UART_XMIT_SIZE, DMA_TO_DEVICE);
982
983 spin_lock_irqsave(&p->port.lock, flags);
984
985 dma->tx_running = 0;
986
987 xmit->tail += dma->tx_size;
988 xmit->tail &= UART_XMIT_SIZE - 1;
989 p->port.icount.tx += dma->tx_size;
990
0a0661dd
SAS		 991 if (priv->delayed_restore) {
992 priv->delayed_restore = 0;
993 omap8250_restore_regs(p);
994 }
995
31a17132
SAS		 996 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
997 uart_write_wakeup(&p->port);
998
999 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
1000 int ret;
1001
1002 ret = omap_8250_tx_dma(p);
1003 if (ret)
1004 en_thri = true;
31a17132
SAS		 1005 } else if (p->capabilities & UART_CAP_RPM) {
1006 en_thri = true;
1007 }
1008
1009 if (en_thri) {
1010 dma->tx_err = 1;
7e267b29 1011 serial8250_set_THRI(p);
31a17132
SAS		 1012 }
1013
1014 spin_unlock_irqrestore(&p->port.lock, flags);
1015}
1016
1017static int omap_8250_tx_dma(struct uart_8250_port *p)
1018{
1019 struct uart_8250_dma *dma = p->dma;
1020 struct omap8250_priv *priv = p->port.private_data;
1021 struct circ_buf *xmit = &p->port.state->xmit;
1022 struct dma_async_tx_descriptor *desc;
1023 unsigned int skip_byte = 0;
1024 int ret;
1025
1026 if (dma->tx_running)
1027 return 0;
1028 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
1029
1030 /*
1031 * Even if no data, we need to return an error for the two cases
1032 * below so serial8250_tx_chars() is invoked and properly clears
1033 * THRI and/or runtime suspend.
1034 */
1035 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
1036 ret = -EBUSY;
1037 goto err;
1038 }
7e267b29 1039 serial8250_clear_THRI(p);
31a17132
SAS		 1040 return 0;
1041 }
1042
1043 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1044 if (priv->habit & OMAP_DMA_TX_KICK) {
1045 u8 tx_lvl;
1046
1047 /*
1048 * We need to put the first byte into the FIFO in order to start
1049 * the DMA transfer. For transfers smaller than four bytes we
1050 * don't bother doing DMA at all. It seem not matter if there
1051 * are still bytes in the FIFO from the last transfer (in case
1052 * we got here directly from omap_8250_dma_tx_complete()). Bytes
1053 * leaving the FIFO seem not to trigger the DMA transfer. It is
1054 * really the byte that we put into the FIFO.
1055 * If the FIFO is already full then we most likely got here from
1056 * omap_8250_dma_tx_complete(). And this means the DMA engine
1057 * just completed its work. We don't have to wait the complete
1058 * 86us at 115200,8n1 but around 60us (not to mention lower
1059 * baudrates). So in that case we take the interrupt and try
1060 * again with an empty FIFO.
1061 */
1062 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
1063 if (tx_lvl == p->tx_loadsz) {
1064 ret = -EBUSY;
1065 goto err;
1066 }
1067 if (dma->tx_size < 4) {
1068 ret = -EINVAL;
1069 goto err;
1070 }
1071 skip_byte = 1;
1072 }
1073
1074 desc = dmaengine_prep_slave_single(dma->txchan,
1075 dma->tx_addr + xmit->tail + skip_byte,
1076 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1077 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1078 if (!desc) {
1079 ret = -EBUSY;
1080 goto err;
1081 }
1082
1083 dma->tx_running = 1;
1084
1085 desc->callback = omap_8250_dma_tx_complete;
1086 desc->callback_param = p;
1087
1088 dma->tx_cookie = dmaengine_submit(desc);
1089
1090 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1091 UART_XMIT_SIZE, DMA_TO_DEVICE);
1092
1093 dma_async_issue_pending(dma->txchan);
1094 if (dma->tx_err)
1095 dma->tx_err = 0;
1096
7e267b29 1097 serial8250_clear_THRI(p);
31a17132
SAS		 1098 if (skip_byte)
1099 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1100 return 0;
1101err:
1102 dma->tx_err = 1;
1103 return ret;
1104}
1105
33d9b8b2
PH		 1106static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1107{
1108 switch (iir & 0x3f) {
1109 case UART_IIR_RLSI:
1110 case UART_IIR_RX_TIMEOUT:
1111 case UART_IIR_RDI:
1112 omap_8250_rx_dma_flush(up);
1113 return true;
1114 }
1115 return omap_8250_rx_dma(up);
1116}
1117
f8ba5680 1118static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status)
c26389f9
VR		 1119{
1120 if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1121 (iir & UART_IIR_RDI)) {
1122 if (handle_rx_dma(up, iir)) {
1123 status = serial8250_rx_chars(up, status);
1124 omap_8250_rx_dma(up);
1125 }
1126 }
1127
1128 return status;
1129}
1130
1131static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
f8ba5680 1132 u16 status)
c26389f9
VR		 1133{
1134 /*
1135 * Queue a new transfer if FIFO has data.
1136 */
1137 if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1138 (up->ier & UART_IER_RDI)) {
1139 omap_8250_rx_dma(up);
1140 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
1141 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) {
1142 /*
1143 * Disable RX timeout, read IIR to clear
1144 * current timeout condition, clear EFR2 to
1145 * periodic timeouts, re-enable interrupts.
1146 */
1147 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1148 serial_out(up, UART_IER, up->ier);
1149 omap_8250_rx_dma_flush(up);
1150 serial_in(up, UART_IIR);
1151 serial_out(up, UART_OMAP_EFR2, 0x0);
1152 up->ier |= UART_IER_RLSI | UART_IER_RDI;
1153 serial_out(up, UART_IER, up->ier);
1154 }
1155}
1156
77285243
SAS		 1157/*
1158 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1159 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1160 * use the default routine in the non-DMA case and this one for with DMA.
1161 */
1162static int omap_8250_dma_handle_irq(struct uart_port *port)
1163{
1164 struct uart_8250_port *up = up_to_u8250p(port);
c26389f9 1165 struct omap8250_priv *priv = up->port.private_data;
f8ba5680 1166 u16 status;
77285243 1167 u8 iir;
77285243
SAS		 1168
1169 serial8250_rpm_get(up);
1170
1171 iir = serial_port_in(port, UART_IIR);
1172 if (iir & UART_IIR_NO_INT) {
1173 serial8250_rpm_put(up);
c6689dfd 1174 return IRQ_HANDLED;
77285243
SAS		 1175 }
1176
75f4e830 1177 spin_lock(&port->lock);
77285243
SAS		 1178
1179 status = serial_port_in(port, UART_LSR);
1180
c26389f9
VR		 1181 if (priv->habit & UART_HAS_EFR2)
1182 am654_8250_handle_rx_dma(up, iir, status);
1183 else
1184 status = omap_8250_handle_rx_dma(up, iir, status);
1185
77285243
SAS		 1186 serial8250_modem_status(up);
1187 if (status & UART_LSR_THRE && up->dma->tx_err) {
1188 if (uart_tx_stopped(&up->port) ||
1189 uart_circ_empty(&up->port.state->xmit)) {
1190 up->dma->tx_err = 0;
1191 serial8250_tx_chars(up);
1192 } else {
1193 /*
1194 * try again due to an earlier failer which
1195 * might have been resolved by now.
1196 */
a86f50ed 1197 if (omap_8250_tx_dma(up))
77285243
SAS		 1198 serial8250_tx_chars(up);
1199 }
1200 }
1201
75f4e830
JH		 1202 uart_unlock_and_check_sysrq(port);
1203
77285243
SAS		 1204 serial8250_rpm_put(up);
1205 return 1;
1206}
0a0661dd
SAS		 1207
1208static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1209{
1210 return false;
1211}
1212
1213#else
1214
33d9b8b2 1215static inline int omap_8250_rx_dma(struct uart_8250_port *p)
0a0661dd
SAS		 1216{
1217 return -EINVAL;
1218}
31a17132
SAS		 1219#endif
1220
9e91597f
SAS		 1221static int omap8250_no_handle_irq(struct uart_port *port)
1222{
1223 /* IRQ has not been requested but handling irq? */
1224 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1225 return 0;
1226}
1227
c26389f9
VR		 1228static struct omap8250_dma_params am654_dma = {
1229 .rx_size = SZ_2K,
1230 .rx_trigger = 1,
1231 .tx_trigger = TX_TRIGGER,
1232};
1233
7229b84c
VR		 1234static struct omap8250_dma_params am33xx_dma = {
1235 .rx_size = RX_TRIGGER,
1236 .rx_trigger = RX_TRIGGER,
1237 .tx_trigger = TX_TRIGGER,
1238};
1239
c26389f9
VR		 1240static struct omap8250_platdata am654_platdata = {
1241 .dma_params = &am654_dma,
b67e830d
VR		 1242 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS |
1243 UART_RX_TIMEOUT_QUIRK,
c26389f9
VR		 1244};
1245
7229b84c
VR		 1246static struct omap8250_platdata am33xx_platdata = {
1247 .dma_params = &am33xx_dma,
1248 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE,
1249};
1250
1251static struct omap8250_platdata omap4_platdata = {
1252 .dma_params = &am33xx_dma,
1253 .habit = UART_ERRATA_CLOCK_DISABLE,
1254};
4fcdff9b
SN		 1255
1256static const struct of_device_id omap8250_dt_ids[] = {
c26389f9 1257 { .compatible = "ti,am654-uart", .data = &am654_platdata, },
4fcdff9b
SN		 1258 { .compatible = "ti,omap2-uart" },
1259 { .compatible = "ti,omap3-uart" },
7229b84c
VR		 1260 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
1261 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
1262 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
1263 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
4fcdff9b
SN		 1264 {},
1265};
1266MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1267
61929cf0
SAS		 1268static int omap8250_probe(struct platform_device *pdev)
1269{
d6ce4ec0 1270 struct device_node *np = pdev->dev.of_node;
61929cf0 1271 struct omap8250_priv *priv;
7229b84c 1272 const struct omap8250_platdata *pdata;
61929cf0 1273 struct uart_8250_port up;
9167cc78 1274 struct resource *regs;
61929cf0 1275 void __iomem *membase;
9167cc78
AS		 1276 int irq, ret;
1277
1278 irq = platform_get_irq(pdev, 0);
1279 if (irq < 0)
1280 return irq;
61929cf0 1281
9167cc78
AS		 1282 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1283 if (!regs) {
1284 dev_err(&pdev->dev, "missing registers\n");
61929cf0
SAS		 1285 return -EINVAL;
1286 }
1287
1288 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1289 if (!priv)
1290 return -ENOMEM;
1291
4bdc0d67 1292 membase = devm_ioremap(&pdev->dev, regs->start,
61929cf0
SAS		 1293 resource_size(regs));
1294 if (!membase)
1295 return -ENODEV;
1296
1297 memset(&up, 0, sizeof(up));
1298 up.port.dev = &pdev->dev;
1299 up.port.mapbase = regs->start;
1300 up.port.membase = membase;
9167cc78 1301 up.port.irq = irq;
61929cf0
SAS		 1302 /*
1303 * It claims to be 16C750 compatible however it is a little different.
1304 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1305 * have) is enabled via EFR instead of MCR. The type is set here 8250
1306 * just to get things going. UNKNOWN does not work for a few reasons and
1307 * we don't need our own type since we don't use 8250's set_termios()
1308 * or pm callback.
1309 */
1310 up.port.type = PORT_8250;
1311 up.port.iotype = UPIO_MEM;
1312 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1313 UPF_HARD_FLOW;
1314 up.port.private_data = priv;
1315
1316 up.port.regshift = 2;
1317 up.port.fifosize = 64;
1318 up.tx_loadsz = 64;
1319 up.capabilities = UART_CAP_FIFO;
71504e51 1320#ifdef CONFIG_PM
61929cf0 1321 /*
71504e51 1322 * Runtime PM is mostly transparent. However to do it right we need to a
61929cf0 1323 * TX empty interrupt before we can put the device to auto idle. So if
71504e51
RW		 1324 * PM is not enabled we don't add that flag and can spare that one extra
1325 * interrupt in the TX path.
61929cf0
SAS		 1326 */
1327 up.capabilities |= UART_CAP_RPM;
1328#endif
1329 up.port.set_termios = omap_8250_set_termios;
4bf4ea9d 1330 up.port.set_mctrl = omap8250_set_mctrl;
61929cf0
SAS		 1331 up.port.pm = omap_8250_pm;
1332 up.port.startup = omap_8250_startup;
1333 up.port.shutdown = omap_8250_shutdown;
1334 up.port.throttle = omap_8250_throttle;
1335 up.port.unthrottle = omap_8250_unthrottle;
283e096f 1336 up.port.rs485_config = serial8250_em485_config;
058bc104
LW		 1337 up.rs485_start_tx = serial8250_em485_start_tx;
1338 up.rs485_stop_tx = serial8250_em485_stop_tx;
a4424b90 1339 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
61929cf0 1340
d6ce4ec0 1341 ret = of_alias_get_id(np, "serial");
54178fe6 1342 if (ret < 0) {
d6ce4ec0 1343 dev_err(&pdev->dev, "failed to get alias\n");
54178fe6 1344 return ret;
61929cf0 1345 }
54178fe6
SAS		 1346 up.port.line = ret;
1347
7d470ebf
V		 1348 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1349 struct clk *clk;
1350
1351 clk = devm_clk_get(&pdev->dev, NULL);
1352 if (IS_ERR(clk)) {
1353 if (PTR_ERR(clk) == -EPROBE_DEFER)
1354 return -EPROBE_DEFER;
1355 } else {
1356 up.port.uartclk = clk_get_rate(clk);
1357 }
1358 }
1359
1fe0e1fa
TL		 1360 if (of_property_read_u32(np, "overrun-throttle-ms",
1361 &up.overrun_backoff_time_ms) != 0)
1362 up.overrun_backoff_time_ms = 0;
1363
d6ce4ec0
V		 1364 priv->wakeirq = irq_of_parse_and_map(np, 1);
1365
7229b84c
VR		 1366 pdata = of_device_get_match_data(&pdev->dev);
1367 if (pdata)
1368 priv->habit |= pdata->habit;
d6ce4ec0 1369
61929cf0
SAS		 1370 if (!up.port.uartclk) {
1371 up.port.uartclk = DEFAULT_CLK_SPEED;
1372 dev_warn(&pdev->dev,
1373 "No clock speed specified: using default: %d\n",
1374 DEFAULT_CLK_SPEED);
1375 }
1376
2552d352
RW		 1377 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1378 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
01d2b189 1379 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency);
61929cf0
SAS		 1380 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1381
eda0cd35
JO		 1382 spin_lock_init(&priv->rx_dma_lock);
1383
61929cf0 1384 device_init_wakeup(&pdev->dev, true);
4ce35a36 1385 pm_runtime_enable(&pdev->dev);
61929cf0 1386 pm_runtime_use_autosuspend(&pdev->dev);
627a545c
TL		 1387
1388 /*
1389 * Disable runtime PM until autosuspend delay unless specifically
1390 * enabled by the user via sysfs. This is the historic way to
1391 * prevent an unsafe default policy with lossy characters on wake-up.
1392 * For serdev devices this is not needed, the policy can be managed by
1393 * the serdev driver.
1394 */
1395 if (!of_get_available_child_count(pdev->dev.of_node))
1396 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
61929cf0
SAS		 1397
1398 pm_runtime_irq_safe(&pdev->dev);
61929cf0
SAS		 1399
1400 pm_runtime_get_sync(&pdev->dev);
1401
1402 omap_serial_fill_features_erratas(&up, priv);
9e91597f 1403 up.port.handle_irq = omap8250_no_handle_irq;
7229b84c
VR		 1404 priv->rx_trigger = RX_TRIGGER;
1405 priv->tx_trigger = TX_TRIGGER;
0a0661dd 1406#ifdef CONFIG_SERIAL_8250_DMA
d6ce4ec0
V		 1407 /*
1408 * Oh DMA support. If there are no DMA properties in the DT then
1409 * we will fall back to a generic DMA channel which does not
1410 * really work here. To ensure that we do not get a generic DMA
1411 * channel assigned, we have the the_no_dma_filter_fn() here.
1412 * To avoid "failed to request DMA" messages we check for DMA
1413 * properties in DT.
1414 */
1415 ret = of_property_count_strings(np, "dma-names");
1416 if (ret == 2) {
7229b84c
VR		 1417 struct omap8250_dma_params *dma_params = NULL;
1418
d6ce4ec0 1419 up.dma = &priv->omap8250_dma;
7229b84c
VR		 1420 up.dma->fn = the_no_dma_filter_fn;
1421 up.dma->tx_dma = omap_8250_tx_dma;
1422 up.dma->rx_dma = omap_8250_rx_dma;
1423 if (pdata)
1424 dma_params = pdata->dma_params;
1425
1426 if (dma_params) {
1427 up.dma->rx_size = dma_params->rx_size;
1428 up.dma->rxconf.src_maxburst = dma_params->rx_trigger;
1429 up.dma->txconf.dst_maxburst = dma_params->tx_trigger;
1430 priv->rx_trigger = dma_params->rx_trigger;
1431 priv->tx_trigger = dma_params->tx_trigger;
1432 } else {
1433 up.dma->rx_size = RX_TRIGGER;
1434 up.dma->rxconf.src_maxburst = RX_TRIGGER;
1435 up.dma->txconf.dst_maxburst = TX_TRIGGER;
1436 }
0a0661dd
SAS		 1437 }
1438#endif
61929cf0
SAS		 1439 ret = serial8250_register_8250_port(&up);
1440 if (ret < 0) {
1441 dev_err(&pdev->dev, "unable to register 8250 port\n");
1442 goto err;
1443 }
1444 priv->line = ret;
1445 platform_set_drvdata(pdev, priv);
1446 pm_runtime_mark_last_busy(&pdev->dev);
1447 pm_runtime_put_autosuspend(&pdev->dev);
1448 return 0;
1449err:
4e0f5cc6
TL		 1450 pm_runtime_dont_use_autosuspend(&pdev->dev);
1451 pm_runtime_put_sync(&pdev->dev);
61929cf0
SAS		 1452 pm_runtime_disable(&pdev->dev);
1453 return ret;
1454}
1455
1456static int omap8250_remove(struct platform_device *pdev)
1457{
1458 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1459
4e0f5cc6 1460 pm_runtime_dont_use_autosuspend(&pdev->dev);
61929cf0
SAS		 1461 pm_runtime_put_sync(&pdev->dev);
1462 pm_runtime_disable(&pdev->dev);
1463 serial8250_unregister_port(priv->line);
01d2b189 1464 cpu_latency_qos_remove_request(&priv->pm_qos_request);
61929cf0
SAS		 1465 device_init_wakeup(&pdev->dev, false);
1466 return 0;
1467}
1468
61929cf0
SAS		 1469#ifdef CONFIG_PM_SLEEP
1470static int omap8250_prepare(struct device *dev)
1471{
1472 struct omap8250_priv *priv = dev_get_drvdata(dev);
1473
1474 if (!priv)
1475 return 0;
1476 priv->is_suspending = true;
1477 return 0;
1478}
1479
1480static void omap8250_complete(struct device *dev)
1481{
1482 struct omap8250_priv *priv = dev_get_drvdata(dev);
1483
1484 if (!priv)
1485 return;
1486 priv->is_suspending = false;
1487}
1488
1489static int omap8250_suspend(struct device *dev)
1490{
1491 struct omap8250_priv *priv = dev_get_drvdata(dev);
09d8b2bd 1492 struct uart_8250_port *up = serial8250_get_port(priv->line);
61929cf0
SAS		 1493
1494 serial8250_suspend_port(priv->line);
09d8b2bd
V		 1495
1496 pm_runtime_get_sync(dev);
1497 if (!device_may_wakeup(dev))
1498 priv->wer = 0;
1499 serial_out(up, UART_OMAP_WER, priv->wer);
1500 pm_runtime_mark_last_busy(dev);
1501 pm_runtime_put_autosuspend(dev);
1502
61929cf0 1503 flush_work(&priv->qos_work);
61929cf0
SAS		 1504 return 0;
1505}
1506
1507static int omap8250_resume(struct device *dev)
1508{
1509 struct omap8250_priv *priv = dev_get_drvdata(dev);
1510
61929cf0
SAS		 1511 serial8250_resume_port(priv->line);
1512 return 0;
1513}
1514#else
1515#define omap8250_prepare NULL
1516#define omap8250_complete NULL
1517#endif
1518
71504e51 1519#ifdef CONFIG_PM
61929cf0
SAS		 1520static int omap8250_lost_context(struct uart_8250_port *up)
1521{
1522 u32 val;
1523
cdb929e4 1524 val = serial_in(up, UART_OMAP_SCR);
61929cf0 1525 /*
cdb929e4
SN		 1526 * If we lose context, then SCR is set to its reset value of zero.
1527 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1528 * among other bits, to never set the register back to zero again.
61929cf0 1529 */
cdb929e4 1530 if (!val)
61929cf0
SAS		 1531 return 1;
1532 return 0;
1533}
1534
cdb929e4
SN		 1535/* TODO: in future, this should happen via API in drivers/reset/ */
1536static int omap8250_soft_reset(struct device *dev)
1537{
1538 struct omap8250_priv *priv = dev_get_drvdata(dev);
1539 struct uart_8250_port *up = serial8250_get_port(priv->line);
1540 int timeout = 100;
1541 int sysc;
1542 int syss;
1543
13dc04d0
TL		 1544 /*
1545 * At least on omap4, unused uarts may not idle after reset without
1546 * a basic scr dma configuration even with no dma in use. The
1547 * module clkctrl status bits will be 1 instead of 3 blocking idle
1548 * for the whole clockdomain. The softreset below will clear scr,
1549 * and we restore it on resume so this is safe to do on all SoCs
1550 * needing omap8250_soft_reset() quirk. Do it in two writes as
1551 * recommended in the comment for omap8250_update_scr().
1552 */
1553 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1554 serial_out(up, UART_OMAP_SCR,
1555 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1556
cdb929e4
SN		 1557 sysc = serial_in(up, UART_OMAP_SYSC);
1558
1559 /* softreset the UART */
1560 sysc |= OMAP_UART_SYSC_SOFTRESET;
1561 serial_out(up, UART_OMAP_SYSC, sysc);
1562
1563 /* By experiments, 1us enough for reset complete on AM335x */
1564 do {
1565 udelay(1);
1566 syss = serial_in(up, UART_OMAP_SYSS);
1567 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1568
1569 if (!timeout) {
1570 dev_err(dev, "timed out waiting for reset done\n");
1571 return -ETIMEDOUT;
1572 }
1573
1574 return 0;
1575}
1576
61929cf0
SAS		 1577static int omap8250_runtime_suspend(struct device *dev)
1578{
1579 struct omap8250_priv *priv = dev_get_drvdata(dev);
1580 struct uart_8250_port *up;
1581
4e0f5cc6
TL		 1582 /* In case runtime-pm tries this before we are setup */
1583 if (!priv)
1584 return 0;
1585
61929cf0
SAS		 1586 up = serial8250_get_port(priv->line);
1587 /*
1588 * When using 'no_console_suspend', the console UART must not be
1589 * suspended. Since driver suspend is managed by runtime suspend,
1590 * preventing runtime suspend (by returning error) will keep device
1591 * active during suspend.
1592 */
1593 if (priv->is_suspending && !console_suspend_enabled) {
1594 if (uart_console(&up->port))
1595 return -EBUSY;
1596 }
1597
cdb929e4
SN		 1598 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1599 int ret;
1600
1601 ret = omap8250_soft_reset(dev);
1602 if (ret)
1603 return ret;
1604
1605 /* Restore to UART mode after reset (for wakeup) */
1606 omap8250_update_mdr1(up, priv);
09d8b2bd
V		 1607 /* Restore wakeup enable register */
1608 serial_out(up, UART_OMAP_WER, priv->wer);
cdb929e4
SN		 1609 }
1610
727fd8ab 1611 if (up->dma && up->dma->rxchan)
33d9b8b2 1612 omap_8250_rx_dma_flush(up);
61929cf0 1613
2552d352 1614 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
61929cf0
SAS		 1615 schedule_work(&priv->qos_work);
1616
1617 return 0;
1618}
1619
1620static int omap8250_runtime_resume(struct device *dev)
1621{
1622 struct omap8250_priv *priv = dev_get_drvdata(dev);
1623 struct uart_8250_port *up;
61929cf0
SAS		 1624
1625 /* In case runtime-pm tries this before we are setup */
1626 if (!priv)
1627 return 0;
1628
1629 up = serial8250_get_port(priv->line);
61929cf0 1630
f56f0a54 1631 if (omap8250_lost_context(up))
61929cf0
SAS		 1632 omap8250_restore_regs(up);
1633
c26389f9 1634 if (up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2))
33d9b8b2 1635 omap_8250_rx_dma(up);
0a0661dd 1636
61929cf0
SAS		 1637 priv->latency = priv->calc_latency;
1638 schedule_work(&priv->qos_work);
1639 return 0;
1640}
1641#endif
1642
00648d02
SAS		 1643#ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1644static int __init omap8250_console_fixup(void)
1645{
1646 char *omap_str;
1647 char *options;
1648 u8 idx;
1649
1650 if (strstr(boot_command_line, "console=ttyS"))
1651 /* user set a ttyS based name for the console */
1652 return 0;
1653
1654 omap_str = strstr(boot_command_line, "console=ttyO");
1655 if (!omap_str)
1656 /* user did not set ttyO based console, so we don't care */
1657 return 0;
1658
1659 omap_str += 12;
1660 if ('0' <= *omap_str && *omap_str <= '9')
1661 idx = *omap_str - '0';
1662 else
1663 return 0;
1664
1665 omap_str++;
1666 if (omap_str[0] == ',') {
1667 omap_str++;
1668 options = omap_str;
1669 } else {
1670 options = NULL;
1671 }
1672
1673 add_preferred_console("ttyS", idx, options);
1674 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1675 idx, idx);
1676 pr_err("This ensures that you still see kernel messages. Please\n");
1677 pr_err("update your kernel commandline.\n");
1678 return 0;
1679}
1680console_initcall(omap8250_console_fixup);
1681#endif
1682
61929cf0
SAS		 1683static const struct dev_pm_ops omap8250_dev_pm_ops = {
1684 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1685 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1686 omap8250_runtime_resume, NULL)
1687 .prepare = omap8250_prepare,
1688 .complete = omap8250_complete,
1689};
1690
61929cf0
SAS		 1691static struct platform_driver omap8250_platform_driver = {
1692 .driver = {
1693 .name = "omap8250",
1694 .pm = &omap8250_dev_pm_ops,
1695 .of_match_table = omap8250_dt_ids,
61929cf0
SAS		 1696 },
1697 .probe = omap8250_probe,
1698 .remove = omap8250_remove,
1699};
1700module_platform_driver(omap8250_platform_driver);
1701
1702MODULE_AUTHOR("Sebastian Andrzej Siewior");
1703MODULE_DESCRIPTION("OMAP 8250 Driver");
1704MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)