Commit | Line | Data |
---|---|---|
e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
61929cf0 SAS |
2 | /* |
3 | * 8250-core based driver for the OMAP internal UART | |
4 | * | |
5 | * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. | |
6 | * | |
7 | * Copyright (C) 2014 Sebastian Andrzej Siewior | |
8 | * | |
9 | */ | |
10 | ||
8700a7ea | 11 | #include <linux/atomic.h> |
7d470ebf | 12 | #include <linux/clk.h> |
61929cf0 SAS |
13 | #include <linux/device.h> |
14 | #include <linux/io.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/serial_8250.h> | |
61929cf0 | 17 | #include <linux/serial_reg.h> |
77285243 | 18 | #include <linux/tty_flip.h> |
61929cf0 SAS |
19 | #include <linux/platform_device.h> |
20 | #include <linux/slab.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_gpio.h> | |
23 | #include <linux/of_irq.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/pm_runtime.h> | |
26 | #include <linux/console.h> | |
27 | #include <linux/pm_qos.h> | |
a3e362f1 | 28 | #include <linux/pm_wakeirq.h> |
31a17132 | 29 | #include <linux/dma-mapping.h> |
439c7183 | 30 | #include <linux/sys_soc.h> |
68e6939e | 31 | #include <linux/pm_domain.h> |
61929cf0 SAS |
32 | |
33 | #include "8250.h" | |
34 | ||
35 | #define DEFAULT_CLK_SPEED 48000000 | |
398cecc2 | 36 | #define OMAP_UART_REGSHIFT 2 |
61929cf0 SAS |
37 | |
38 | #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) | |
39 | #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) | |
31a17132 | 40 | #define OMAP_DMA_TX_KICK (1 << 2) |
cdb929e4 SN |
41 | /* |
42 | * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. | |
43 | * The same errata is applicable to AM335x and DRA7x processors too. | |
44 | */ | |
45 | #define UART_ERRATA_CLOCK_DISABLE (1 << 3) | |
c26389f9 | 46 | #define UART_HAS_EFR2 BIT(4) |
439c7183 | 47 | #define UART_HAS_RHR_IT_DIS BIT(5) |
b67e830d | 48 | #define UART_RX_TIMEOUT_QUIRK BIT(6) |
801954d1 | 49 | #define UART_HAS_NATIVE_RS485 BIT(7) |
61929cf0 SAS |
50 | |
51 | #define OMAP_UART_FCR_RX_TRIG 6 | |
52 | #define OMAP_UART_FCR_TX_TRIG 4 | |
53 | ||
54 | /* SCR register bitmasks */ | |
55 | #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) | |
56 | #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) | |
57 | #define OMAP_UART_SCR_TX_EMPTY (1 << 3) | |
58 | #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) | |
59 | #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) | |
60 | #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) | |
61 | ||
62 | /* MVR register bitmasks */ | |
63 | #define OMAP_UART_MVR_SCHEME_SHIFT 30 | |
64 | #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 | |
65 | #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 | |
66 | #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f | |
67 | #define OMAP_UART_MVR_MAJ_MASK 0x700 | |
68 | #define OMAP_UART_MVR_MAJ_SHIFT 8 | |
69 | #define OMAP_UART_MVR_MIN_MASK 0x3f | |
70 | ||
cdb929e4 SN |
71 | /* SYSC register bitmasks */ |
72 | #define OMAP_UART_SYSC_SOFTRESET (1 << 1) | |
73 | ||
74 | /* SYSS register bitmasks */ | |
75 | #define OMAP_UART_SYSS_RESETDONE (1 << 0) | |
76 | ||
61929cf0 SAS |
77 | #define UART_TI752_TLR_TX 0 |
78 | #define UART_TI752_TLR_RX 4 | |
79 | ||
80 | #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) | |
81 | #define TRIGGER_FCR_MASK(x) (x & 3) | |
82 | ||
83 | /* Enable XON/XOFF flow control on output */ | |
84 | #define OMAP_UART_SW_TX 0x08 | |
85 | /* Enable XON/XOFF flow control on input */ | |
86 | #define OMAP_UART_SW_RX 0x02 | |
87 | ||
88 | #define OMAP_UART_WER_MOD_WKUP 0x7f | |
89 | #define OMAP_UART_TX_WAKEUP_EN (1 << 7) | |
90 | ||
91 | #define TX_TRIGGER 1 | |
92 | #define RX_TRIGGER 48 | |
93 | ||
94 | #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) | |
95 | #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) | |
96 | ||
97 | #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) | |
98 | ||
99 | #define OMAP_UART_REV_46 0x0406 | |
100 | #define OMAP_UART_REV_52 0x0502 | |
101 | #define OMAP_UART_REV_63 0x0603 | |
102 | ||
439c7183 VR |
103 | /* Interrupt Enable Register 2 */ |
104 | #define UART_OMAP_IER2 0x1B | |
105 | #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) | |
106 | ||
801954d1 LW |
107 | /* Mode Definition Register 3 */ |
108 | #define UART_OMAP_MDR3 0x20 | |
109 | #define UART_OMAP_MDR3_DIR_POL BIT(3) | |
110 | #define UART_OMAP_MDR3_DIR_EN BIT(4) | |
111 | ||
c26389f9 VR |
112 | /* Enhanced features register 2 */ |
113 | #define UART_OMAP_EFR2 0x23 | |
114 | #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) | |
115 | ||
b67e830d | 116 | /* RX FIFO occupancy indicator */ |
79e9e30a | 117 | #define UART_OMAP_RX_LVL 0x19 |
b67e830d | 118 | |
68e6939e TR |
119 | /* |
120 | * Copy of the genpd flags for the console. | |
121 | * Only used if console suspend is disabled | |
122 | */ | |
123 | static unsigned int genpd_flags_console; | |
124 | ||
61929cf0 | 125 | struct omap8250_priv { |
398cecc2 | 126 | void __iomem *membase; |
61929cf0 SAS |
127 | int line; |
128 | u8 habit; | |
129 | u8 mdr1; | |
801954d1 | 130 | u8 mdr3; |
61929cf0 SAS |
131 | u8 efr; |
132 | u8 scr; | |
133 | u8 wer; | |
134 | u8 xon; | |
135 | u8 xoff; | |
0a0661dd | 136 | u8 delayed_restore; |
61929cf0 SAS |
137 | u16 quot; |
138 | ||
7229b84c VR |
139 | u8 tx_trigger; |
140 | u8 rx_trigger; | |
8700a7ea | 141 | atomic_t active; |
61929cf0 SAS |
142 | bool is_suspending; |
143 | int wakeirq; | |
144 | int wakeups_enabled; | |
145 | u32 latency; | |
146 | u32 calc_latency; | |
147 | struct pm_qos_request pm_qos_request; | |
148 | struct work_struct qos_work; | |
149 | struct uart_8250_dma omap8250_dma; | |
eda0cd35 | 150 | spinlock_t rx_dma_lock; |
830acf9e | 151 | bool rx_dma_broken; |
08fb00c6 | 152 | bool throttled; |
61929cf0 SAS |
153 | }; |
154 | ||
7229b84c VR |
155 | struct omap8250_dma_params { |
156 | u32 rx_size; | |
157 | u8 rx_trigger; | |
158 | u8 tx_trigger; | |
159 | }; | |
160 | ||
161 | struct omap8250_platdata { | |
162 | struct omap8250_dma_params *dma_params; | |
163 | u8 habit; | |
164 | }; | |
165 | ||
33d9b8b2 PH |
166 | #ifdef CONFIG_SERIAL_8250_DMA |
167 | static void omap_8250_rx_dma_flush(struct uart_8250_port *p); | |
168 | #else | |
169 | static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } | |
170 | #endif | |
171 | ||
398cecc2 | 172 | static u32 uart_read(struct omap8250_priv *priv, u32 reg) |
61929cf0 | 173 | { |
398cecc2 TL |
174 | return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); |
175 | } | |
176 | ||
93810191 TL |
177 | /* |
178 | * Called on runtime PM resume path from omap8250_restore_regs(), and | |
179 | * omap8250_set_mctrl(). | |
180 | */ | |
181 | static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
4bf4ea9d PH |
182 | { |
183 | struct uart_8250_port *up = up_to_u8250p(port); | |
184 | struct omap8250_priv *priv = up->port.private_data; | |
185 | u8 lcr; | |
186 | ||
187 | serial8250_do_set_mctrl(port, mctrl); | |
188 | ||
fc64f7ab | 189 | if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { |
4a96895f YY |
190 | /* |
191 | * Turn off autoRTS if RTS is lowered and restore autoRTS | |
192 | * setting if RTS is raised | |
193 | */ | |
194 | lcr = serial_in(up, UART_LCR); | |
195 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
196 | if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) | |
197 | priv->efr |= UART_EFR_RTS; | |
198 | else | |
199 | priv->efr &= ~UART_EFR_RTS; | |
200 | serial_out(up, UART_EFR, priv->efr); | |
201 | serial_out(up, UART_LCR, lcr); | |
202 | } | |
4bf4ea9d PH |
203 | } |
204 | ||
93810191 TL |
205 | static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) |
206 | { | |
207 | int err; | |
208 | ||
209 | err = pm_runtime_resume_and_get(port->dev); | |
210 | if (err) | |
211 | return; | |
212 | ||
213 | __omap8250_set_mctrl(port, mctrl); | |
214 | ||
215 | pm_runtime_mark_last_busy(port->dev); | |
216 | pm_runtime_put_autosuspend(port->dev); | |
217 | } | |
218 | ||
61929cf0 SAS |
219 | /* |
220 | * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) | |
221 | * The access to uart register after MDR1 Access | |
222 | * causes UART to corrupt data. | |
223 | * | |
224 | * Need a delay = | |
225 | * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) | |
226 | * give 10 times as much | |
227 | */ | |
228 | static void omap_8250_mdr1_errataset(struct uart_8250_port *up, | |
229 | struct omap8250_priv *priv) | |
230 | { | |
61929cf0 SAS |
231 | serial_out(up, UART_OMAP_MDR1, priv->mdr1); |
232 | udelay(2); | |
233 | serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | | |
234 | UART_FCR_CLEAR_RCVR); | |
61929cf0 SAS |
235 | } |
236 | ||
237 | static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, | |
238 | struct omap8250_priv *priv) | |
239 | { | |
240 | unsigned int uartclk = port->uartclk; | |
241 | unsigned int div_13, div_16; | |
242 | unsigned int abs_d13, abs_d16; | |
243 | ||
244 | /* | |
245 | * Old custom speed handling. | |
246 | */ | |
247 | if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { | |
6263368c | 248 | priv->quot = port->custom_divisor & UART_DIV_MAX; |
61929cf0 SAS |
249 | /* |
250 | * I assume that nobody is using this. But hey, if somebody | |
251 | * would like to specify the divisor _and_ the mode then the | |
252 | * driver is ready and waiting for it. | |
253 | */ | |
254 | if (port->custom_divisor & (1 << 16)) | |
255 | priv->mdr1 = UART_OMAP_MDR1_13X_MODE; | |
256 | else | |
257 | priv->mdr1 = UART_OMAP_MDR1_16X_MODE; | |
258 | return; | |
259 | } | |
260 | div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); | |
261 | div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); | |
262 | ||
263 | if (!div_13) | |
264 | div_13 = 1; | |
265 | if (!div_16) | |
266 | div_16 = 1; | |
267 | ||
268 | abs_d13 = abs(baud - uartclk / 13 / div_13); | |
269 | abs_d16 = abs(baud - uartclk / 16 / div_16); | |
270 | ||
271 | if (abs_d13 >= abs_d16) { | |
272 | priv->mdr1 = UART_OMAP_MDR1_16X_MODE; | |
273 | priv->quot = div_16; | |
274 | } else { | |
275 | priv->mdr1 = UART_OMAP_MDR1_13X_MODE; | |
276 | priv->quot = div_13; | |
277 | } | |
278 | } | |
279 | ||
280 | static void omap8250_update_scr(struct uart_8250_port *up, | |
281 | struct omap8250_priv *priv) | |
282 | { | |
283 | u8 old_scr; | |
284 | ||
285 | old_scr = serial_in(up, UART_OMAP_SCR); | |
286 | if (old_scr == priv->scr) | |
287 | return; | |
288 | ||
289 | /* | |
290 | * The manual recommends not to enable the DMA mode selector in the SCR | |
291 | * (instead of the FCR) register _and_ selecting the DMA mode as one | |
292 | * register write because this may lead to malfunction. | |
293 | */ | |
294 | if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) | |
295 | serial_out(up, UART_OMAP_SCR, | |
296 | priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); | |
297 | serial_out(up, UART_OMAP_SCR, priv->scr); | |
298 | } | |
299 | ||
6f03541f SN |
300 | static void omap8250_update_mdr1(struct uart_8250_port *up, |
301 | struct omap8250_priv *priv) | |
302 | { | |
303 | if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) | |
304 | omap_8250_mdr1_errataset(up, priv); | |
305 | else | |
306 | serial_out(up, UART_OMAP_MDR1, priv->mdr1); | |
307 | } | |
308 | ||
61929cf0 SAS |
309 | static void omap8250_restore_regs(struct uart_8250_port *up) |
310 | { | |
311 | struct omap8250_priv *priv = up->port.private_data; | |
0a0661dd | 312 | struct uart_8250_dma *dma = up->dma; |
038ee49f | 313 | u8 mcr = serial8250_in_MCR(up); |
0a0661dd | 314 | |
8b455037 JO |
315 | /* Port locked to synchronize UART_IER access against the console. */ |
316 | lockdep_assert_held_once(&up->port.lock); | |
317 | ||
0a0661dd SAS |
318 | if (dma && dma->tx_running) { |
319 | /* | |
320 | * TCSANOW requests the change to occur immediately however if | |
321 | * we have a TX-DMA operation in progress then it has been | |
322 | * observed that it might stall and never complete. Therefore we | |
323 | * delay DMA completes to prevent this hang from happen. | |
324 | */ | |
325 | priv->delayed_restore = 1; | |
326 | return; | |
327 | } | |
61929cf0 SAS |
328 | |
329 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
330 | serial_out(up, UART_EFR, UART_EFR_ECB); | |
331 | ||
332 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
038ee49f | 333 | serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); |
61929cf0 SAS |
334 | serial_out(up, UART_FCR, up->fcr); |
335 | ||
336 | omap8250_update_scr(up, priv); | |
337 | ||
338 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
339 | ||
340 | serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | | |
341 | OMAP_UART_TCR_HALT(52)); | |
342 | serial_out(up, UART_TI752_TLR, | |
7229b84c VR |
343 | TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | |
344 | TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); | |
61929cf0 SAS |
345 | |
346 | serial_out(up, UART_LCR, 0); | |
347 | ||
348 | /* drop TCR + TLR access, we setup XON/XOFF later */ | |
038ee49f LW |
349 | serial8250_out_MCR(up, mcr); |
350 | ||
61929cf0 SAS |
351 | serial_out(up, UART_IER, up->ier); |
352 | ||
353 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
354 | serial_dl_write(up, priv->quot); | |
355 | ||
9719acce | 356 | serial_out(up, UART_EFR, priv->efr); |
61929cf0 SAS |
357 | |
358 | /* Configure flow control */ | |
359 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
360 | serial_out(up, UART_XON1, priv->xon); | |
361 | serial_out(up, UART_XOFF1, priv->xoff); | |
362 | ||
363 | serial_out(up, UART_LCR, up->lcr); | |
6f03541f SN |
364 | |
365 | omap8250_update_mdr1(up, priv); | |
366 | ||
93810191 | 367 | __omap8250_set_mctrl(&up->port, up->port.mctrl); |
7c7f9bc9 | 368 | |
801954d1 LW |
369 | serial_out(up, UART_OMAP_MDR3, priv->mdr3); |
370 | ||
371 | if (up->port.rs485.flags & SER_RS485_ENABLED && | |
372 | up->port.rs485_config == serial8250_em485_config) | |
7c7f9bc9 | 373 | serial8250_em485_stop_tx(up); |
61929cf0 SAS |
374 | } |
375 | ||
376 | /* | |
377 | * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have | |
378 | * some differences in how we want to handle flow control. | |
379 | */ | |
380 | static void omap_8250_set_termios(struct uart_port *port, | |
381 | struct ktermios *termios, | |
bec5b814 | 382 | const struct ktermios *old) |
61929cf0 | 383 | { |
013e3586 | 384 | struct uart_8250_port *up = up_to_u8250p(port); |
61929cf0 SAS |
385 | struct omap8250_priv *priv = up->port.private_data; |
386 | unsigned char cval = 0; | |
387 | unsigned int baud; | |
388 | ||
988c5bbe | 389 | cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); |
61929cf0 SAS |
390 | |
391 | if (termios->c_cflag & CSTOPB) | |
392 | cval |= UART_LCR_STOP; | |
393 | if (termios->c_cflag & PARENB) | |
394 | cval |= UART_LCR_PARITY; | |
395 | if (!(termios->c_cflag & PARODD)) | |
396 | cval |= UART_LCR_EPAR; | |
397 | if (termios->c_cflag & CMSPAR) | |
398 | cval |= UART_LCR_SPAR; | |
399 | ||
400 | /* | |
401 | * Ask the core to calculate the divisor for us. | |
402 | */ | |
403 | baud = uart_get_baud_rate(port, termios, old, | |
6263368c | 404 | port->uartclk / 16 / UART_DIV_MAX, |
61929cf0 SAS |
405 | port->uartclk / 13); |
406 | omap_8250_get_divisor(port, baud, priv); | |
407 | ||
408 | /* | |
409 | * Ok, we're now changing the port state. Do it with | |
410 | * interrupts disabled. | |
411 | */ | |
412 | pm_runtime_get_sync(port->dev); | |
e4a13758 | 413 | uart_port_lock_irq(port); |
61929cf0 SAS |
414 | |
415 | /* | |
416 | * Update the per-port timeout. | |
417 | */ | |
418 | uart_update_timeout(port, termios->c_cflag, baud); | |
419 | ||
420 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
421 | if (termios->c_iflag & INPCK) | |
422 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
423 | if (termios->c_iflag & (IGNBRK | PARMRK)) | |
424 | up->port.read_status_mask |= UART_LSR_BI; | |
425 | ||
426 | /* | |
427 | * Characters to ignore | |
428 | */ | |
429 | up->port.ignore_status_mask = 0; | |
430 | if (termios->c_iflag & IGNPAR) | |
431 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
432 | if (termios->c_iflag & IGNBRK) { | |
433 | up->port.ignore_status_mask |= UART_LSR_BI; | |
434 | /* | |
435 | * If we're ignoring parity and break indicators, | |
436 | * ignore overruns too (for real raw support). | |
437 | */ | |
438 | if (termios->c_iflag & IGNPAR) | |
439 | up->port.ignore_status_mask |= UART_LSR_OE; | |
440 | } | |
441 | ||
442 | /* | |
443 | * ignore all characters if CREAD is not set | |
444 | */ | |
445 | if ((termios->c_cflag & CREAD) == 0) | |
446 | up->port.ignore_status_mask |= UART_LSR_DR; | |
447 | ||
448 | /* | |
449 | * Modem status interrupts | |
450 | */ | |
451 | up->ier &= ~UART_IER_MSI; | |
452 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
453 | up->ier |= UART_IER_MSI; | |
454 | ||
455 | up->lcr = cval; | |
456 | /* Up to here it was mostly serial8250_do_set_termios() */ | |
457 | ||
458 | /* | |
93ad8673 | 459 | * We enable TRIG_GRANU for RX and TX and additionally we set |
61929cf0 SAS |
460 | * SCR_TX_EMPTY bit. The result is the following: |
461 | * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. | |
462 | * - less than RX_TRIGGER number of bytes will also cause an interrupt | |
463 | * once the UART decides that there no new bytes arriving. | |
464 | * - Once THRE is enabled, the interrupt will be fired once the FIFO is | |
465 | * empty - the trigger level is ignored here. | |
466 | * | |
467 | * Once DMA is enabled: | |
468 | * - UART will assert the TX DMA line once there is room for TX_TRIGGER | |
469 | * bytes in the TX FIFO. On each assert the DMA engine will move | |
470 | * TX_TRIGGER bytes into the FIFO. | |
471 | * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in | |
472 | * the FIFO and move RX_TRIGGER bytes. | |
473 | * This is because threshold and trigger values are the same. | |
474 | */ | |
475 | up->fcr = UART_FCR_ENABLE_FIFO; | |
7229b84c VR |
476 | up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; |
477 | up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; | |
61929cf0 SAS |
478 | |
479 | priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | | |
480 | OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; | |
481 | ||
0a0661dd SAS |
482 | if (up->dma) |
483 | priv->scr |= OMAP_UART_SCR_DMAMODE_1 | | |
484 | OMAP_UART_SCR_DMAMODE_CTL; | |
485 | ||
61929cf0 SAS |
486 | priv->xon = termios->c_cc[VSTART]; |
487 | priv->xoff = termios->c_cc[VSTOP]; | |
488 | ||
489 | priv->efr = 0; | |
391f93f2 PH |
490 | up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); |
491 | ||
4a96895f | 492 | if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW && |
fc64f7ab AF |
493 | !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && |
494 | !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { | |
9719acce | 495 | /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ |
391f93f2 | 496 | up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; |
9719acce | 497 | priv->efr |= UART_EFR_CTS; |
61929cf0 SAS |
498 | } else if (up->port.flags & UPF_SOFT_FLOW) { |
499 | /* | |
5bac4b3d PH |
500 | * OMAP rx s/w flow control is borked; the transmitter remains |
501 | * stuck off even if rx flow control is subsequently disabled | |
61929cf0 | 502 | */ |
61929cf0 SAS |
503 | |
504 | /* | |
505 | * IXOFF Flag: | |
506 | * Enable XON/XOFF flow control on output. | |
507 | * Transmit XON1, XOFF1 | |
508 | */ | |
391f93f2 PH |
509 | if (termios->c_iflag & IXOFF) { |
510 | up->port.status |= UPSTAT_AUTOXOFF; | |
61929cf0 | 511 | priv->efr |= OMAP_UART_SW_TX; |
391f93f2 | 512 | } |
61929cf0 SAS |
513 | } |
514 | omap8250_restore_regs(up); | |
515 | ||
e4a13758 | 516 | uart_port_unlock_irq(&up->port); |
61929cf0 SAS |
517 | pm_runtime_mark_last_busy(port->dev); |
518 | pm_runtime_put_autosuspend(port->dev); | |
519 | ||
520 | /* calculate wakeup latency constraint */ | |
521 | priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; | |
522 | priv->latency = priv->calc_latency; | |
523 | ||
524 | schedule_work(&priv->qos_work); | |
525 | ||
526 | /* Don't rewrite B0 */ | |
527 | if (tty_termios_baud_rate(termios)) | |
528 | tty_termios_encode_baud_rate(termios, baud, baud); | |
529 | } | |
530 | ||
531 | /* same as 8250 except that we may have extra flow bits set in EFR */ | |
532 | static void omap_8250_pm(struct uart_port *port, unsigned int state, | |
533 | unsigned int oldstate) | |
534 | { | |
3e29af27 PH |
535 | struct uart_8250_port *up = up_to_u8250p(port); |
536 | u8 efr; | |
61929cf0 SAS |
537 | |
538 | pm_runtime_get_sync(port->dev); | |
d0b309a5 JO |
539 | |
540 | /* Synchronize UART_IER access against the console. */ | |
e4a13758 | 541 | uart_port_lock_irq(port); |
d0b309a5 | 542 | |
61929cf0 | 543 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
3e29af27 PH |
544 | efr = serial_in(up, UART_EFR); |
545 | serial_out(up, UART_EFR, efr | UART_EFR_ECB); | |
61929cf0 SAS |
546 | serial_out(up, UART_LCR, 0); |
547 | ||
548 | serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); | |
549 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
3e29af27 | 550 | serial_out(up, UART_EFR, efr); |
61929cf0 SAS |
551 | serial_out(up, UART_LCR, 0); |
552 | ||
e4a13758 | 553 | uart_port_unlock_irq(port); |
d0b309a5 | 554 | |
61929cf0 SAS |
555 | pm_runtime_mark_last_busy(port->dev); |
556 | pm_runtime_put_autosuspend(port->dev); | |
557 | } | |
558 | ||
559 | static void omap_serial_fill_features_erratas(struct uart_8250_port *up, | |
560 | struct omap8250_priv *priv) | |
561 | { | |
cb3ea80b | 562 | static const struct soc_device_attribute k3_soc_devices[] = { |
6f991850 VR |
563 | { .family = "AM65X", }, |
564 | { .family = "J721E", .revision = "SR1.0" }, | |
565 | { /* sentinel */ } | |
566 | }; | |
61929cf0 SAS |
567 | u32 mvr, scheme; |
568 | u16 revision, major, minor; | |
569 | ||
398cecc2 | 570 | mvr = uart_read(priv, UART_OMAP_MVER); |
61929cf0 SAS |
571 | |
572 | /* Check revision register scheme */ | |
573 | scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; | |
574 | ||
575 | switch (scheme) { | |
576 | case 0: /* Legacy Scheme: OMAP2/3 */ | |
577 | /* MINOR_REV[0:4], MAJOR_REV[4:7] */ | |
578 | major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> | |
579 | OMAP_UART_LEGACY_MVR_MAJ_SHIFT; | |
580 | minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); | |
581 | break; | |
582 | case 1: | |
583 | /* New Scheme: OMAP4+ */ | |
584 | /* MINOR_REV[0:5], MAJOR_REV[8:10] */ | |
585 | major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> | |
586 | OMAP_UART_MVR_MAJ_SHIFT; | |
587 | minor = (mvr & OMAP_UART_MVR_MIN_MASK); | |
588 | break; | |
589 | default: | |
590 | dev_warn(up->port.dev, | |
591 | "Unknown revision, defaulting to highest\n"); | |
592 | /* highest possible revision */ | |
593 | major = 0xff; | |
594 | minor = 0xff; | |
595 | } | |
596 | /* normalize revision for the driver */ | |
597 | revision = UART_BUILD_REVISION(major, minor); | |
598 | ||
599 | switch (revision) { | |
600 | case OMAP_UART_REV_46: | |
4fcdff9b | 601 | priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; |
61929cf0 SAS |
602 | break; |
603 | case OMAP_UART_REV_52: | |
4fcdff9b | 604 | priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | |
61929cf0 SAS |
605 | OMAP_UART_WER_HAS_TX_WAKEUP; |
606 | break; | |
607 | case OMAP_UART_REV_63: | |
4fcdff9b | 608 | priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | |
61929cf0 SAS |
609 | OMAP_UART_WER_HAS_TX_WAKEUP; |
610 | break; | |
611 | default: | |
612 | break; | |
613 | } | |
6f991850 VR |
614 | |
615 | /* | |
616 | * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't | |
617 | * don't have RHR_IT_DIS bit in IER2 register. So drop to flag | |
618 | * to enable errata workaround. | |
619 | */ | |
620 | if (soc_device_match(k3_soc_devices)) | |
621 | priv->habit &= ~UART_HAS_RHR_IT_DIS; | |
61929cf0 SAS |
622 | } |
623 | ||
624 | static void omap8250_uart_qos_work(struct work_struct *work) | |
625 | { | |
626 | struct omap8250_priv *priv; | |
627 | ||
628 | priv = container_of(work, struct omap8250_priv, qos_work); | |
01d2b189 | 629 | cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); |
61929cf0 SAS |
630 | } |
631 | ||
9e91597f SAS |
632 | #ifdef CONFIG_SERIAL_8250_DMA |
633 | static int omap_8250_dma_handle_irq(struct uart_port *port); | |
634 | #endif | |
635 | ||
636 | static irqreturn_t omap8250_irq(int irq, void *dev_id) | |
637 | { | |
fef4f600 TL |
638 | struct omap8250_priv *priv = dev_id; |
639 | struct uart_8250_port *up = serial8250_get_port(priv->line); | |
640 | struct uart_port *port = &up->port; | |
1fe0e1fa | 641 | unsigned int iir, lsr; |
9e91597f SAS |
642 | int ret; |
643 | ||
8700a7ea TL |
644 | pm_runtime_get_noresume(port->dev); |
645 | ||
646 | /* Shallow idle state wake-up to an IO interrupt? */ | |
647 | if (atomic_add_unless(&priv->active, 1, 1)) { | |
648 | priv->latency = priv->calc_latency; | |
649 | schedule_work(&priv->qos_work); | |
650 | } | |
651 | ||
9e91597f SAS |
652 | #ifdef CONFIG_SERIAL_8250_DMA |
653 | if (up->dma) { | |
654 | ret = omap_8250_dma_handle_irq(port); | |
8700a7ea TL |
655 | pm_runtime_mark_last_busy(port->dev); |
656 | pm_runtime_put(port->dev); | |
9e91597f SAS |
657 | return IRQ_RETVAL(ret); |
658 | } | |
659 | #endif | |
660 | ||
1fe0e1fa | 661 | lsr = serial_port_in(port, UART_LSR); |
9e91597f SAS |
662 | iir = serial_port_in(port, UART_IIR); |
663 | ret = serial8250_handle_irq(port, iir); | |
b67e830d VR |
664 | |
665 | /* | |
666 | * On K3 SoCs, it is observed that RX TIMEOUT is signalled after | |
667 | * FIFO has been drained, in which case a dummy read of RX FIFO | |
668 | * is required to clear RX TIMEOUT condition. | |
669 | */ | |
670 | if (priv->habit & UART_RX_TIMEOUT_QUIRK && | |
671 | (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && | |
672 | serial_port_in(port, UART_OMAP_RX_LVL) == 0) { | |
673 | serial_port_in(port, UART_RX); | |
674 | } | |
675 | ||
1fe0e1fa TL |
676 | /* Stop processing interrupts on input overrun */ |
677 | if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { | |
678 | unsigned long delay; | |
679 | ||
25614735 | 680 | /* Synchronize UART_IER access against the console. */ |
e4a13758 | 681 | uart_port_lock(port); |
1fe0e1fa TL |
682 | up->ier = port->serial_in(port, UART_IER); |
683 | if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { | |
684 | port->ops->stop_rx(port); | |
685 | } else { | |
686 | /* Keep restarting the timer until | |
687 | * the input overrun subsides. | |
688 | */ | |
689 | cancel_delayed_work(&up->overrun_backoff); | |
690 | } | |
e4a13758 | 691 | uart_port_unlock(port); |
1fe0e1fa TL |
692 | |
693 | delay = msecs_to_jiffies(up->overrun_backoff_time_ms); | |
694 | schedule_delayed_work(&up->overrun_backoff, delay); | |
695 | } | |
696 | ||
8700a7ea TL |
697 | pm_runtime_mark_last_busy(port->dev); |
698 | pm_runtime_put(port->dev); | |
9e91597f SAS |
699 | |
700 | return IRQ_RETVAL(ret); | |
701 | } | |
702 | ||
61929cf0 SAS |
703 | static int omap_8250_startup(struct uart_port *port) |
704 | { | |
9e91597f | 705 | struct uart_8250_port *up = up_to_u8250p(port); |
61929cf0 | 706 | struct omap8250_priv *priv = port->private_data; |
db86bb6e | 707 | struct uart_8250_dma *dma = &priv->omap8250_dma; |
61929cf0 SAS |
708 | int ret; |
709 | ||
710 | if (priv->wakeirq) { | |
a3e362f1 | 711 | ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); |
61929cf0 SAS |
712 | if (ret) |
713 | return ret; | |
61929cf0 SAS |
714 | } |
715 | ||
716 | pm_runtime_get_sync(port->dev); | |
717 | ||
9e91597f SAS |
718 | serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); |
719 | ||
720 | serial_out(up, UART_LCR, UART_LCR_WLEN8); | |
721 | ||
722 | up->lsr_saved_flags = 0; | |
723 | up->msr_saved_flags = 0; | |
724 | ||
84b40e3b | 725 | /* Disable DMA for console UART */ |
db86bb6e TL |
726 | if (dma->fn && !uart_console(port)) { |
727 | up->dma = &priv->omap8250_dma; | |
9e91597f SAS |
728 | ret = serial8250_request_dma(up); |
729 | if (ret) { | |
730 | dev_warn_ratelimited(port->dev, | |
731 | "failed to request DMA\n"); | |
732 | up->dma = NULL; | |
733 | } | |
db86bb6e TL |
734 | } else { |
735 | up->dma = NULL; | |
9e91597f SAS |
736 | } |
737 | ||
b1207d86 | 738 | /* Synchronize UART_IER access against the console. */ |
e4a13758 | 739 | uart_port_lock_irq(port); |
9e91597f SAS |
740 | up->ier = UART_IER_RLSI | UART_IER_RDI; |
741 | serial_out(up, UART_IER, up->ier); | |
e4a13758 | 742 | uart_port_unlock_irq(port); |
9e91597f | 743 | |
71504e51 | 744 | #ifdef CONFIG_PM |
61929cf0 SAS |
745 | up->capabilities |= UART_CAP_RPM; |
746 | #endif | |
747 | ||
748 | /* Enable module level wake up */ | |
749 | priv->wer = OMAP_UART_WER_MOD_WKUP; | |
750 | if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) | |
751 | priv->wer |= OMAP_UART_TX_WAKEUP_EN; | |
752 | serial_out(up, UART_OMAP_WER, priv->wer); | |
753 | ||
87660fb4 | 754 | if (up->dma && !(priv->habit & UART_HAS_EFR2)) { |
e4a13758 | 755 | uart_port_lock_irq(port); |
33d9b8b2 | 756 | up->dma->rx_dma(up); |
e4a13758 | 757 | uart_port_unlock_irq(port); |
87660fb4 | 758 | } |
0a0661dd | 759 | |
fef4f600 TL |
760 | enable_irq(up->port.irq); |
761 | ||
61929cf0 SAS |
762 | pm_runtime_mark_last_busy(port->dev); |
763 | pm_runtime_put_autosuspend(port->dev); | |
764 | return 0; | |
61929cf0 SAS |
765 | } |
766 | ||
767 | static void omap_8250_shutdown(struct uart_port *port) | |
768 | { | |
9e91597f | 769 | struct uart_8250_port *up = up_to_u8250p(port); |
61929cf0 SAS |
770 | struct omap8250_priv *priv = port->private_data; |
771 | ||
772 | flush_work(&priv->qos_work); | |
0a0661dd | 773 | if (up->dma) |
33d9b8b2 | 774 | omap_8250_rx_dma_flush(up); |
61929cf0 SAS |
775 | |
776 | pm_runtime_get_sync(port->dev); | |
777 | ||
778 | serial_out(up, UART_OMAP_WER, 0); | |
c26389f9 VR |
779 | if (priv->habit & UART_HAS_EFR2) |
780 | serial_out(up, UART_OMAP_EFR2, 0x0); | |
9e91597f | 781 | |
d0b309a5 | 782 | /* Synchronize UART_IER access against the console. */ |
e4a13758 | 783 | uart_port_lock_irq(port); |
9e91597f SAS |
784 | up->ier = 0; |
785 | serial_out(up, UART_IER, 0); | |
e4a13758 | 786 | uart_port_unlock_irq(port); |
fef4f600 TL |
787 | disable_irq_nosync(up->port.irq); |
788 | dev_pm_clear_wake_irq(port->dev); | |
9e91597f | 789 | |
db86bb6e TL |
790 | serial8250_release_dma(up); |
791 | up->dma = NULL; | |
9e91597f SAS |
792 | |
793 | /* | |
794 | * Disable break condition and FIFOs | |
795 | */ | |
796 | if (up->lcr & UART_LCR_SBC) | |
797 | serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); | |
798 | serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
61929cf0 SAS |
799 | |
800 | pm_runtime_mark_last_busy(port->dev); | |
801 | pm_runtime_put_autosuspend(port->dev); | |
61929cf0 SAS |
802 | } |
803 | ||
804 | static void omap_8250_throttle(struct uart_port *port) | |
805 | { | |
08fb00c6 | 806 | struct omap8250_priv *priv = port->private_data; |
61929cf0 | 807 | unsigned long flags; |
61929cf0 SAS |
808 | |
809 | pm_runtime_get_sync(port->dev); | |
810 | ||
e4a13758 | 811 | uart_port_lock_irqsave(port, &flags); |
f4b042a0 | 812 | port->ops->stop_rx(port); |
08fb00c6 | 813 | priv->throttled = true; |
e4a13758 | 814 | uart_port_unlock_irqrestore(port, flags); |
61929cf0 SAS |
815 | |
816 | pm_runtime_mark_last_busy(port->dev); | |
817 | pm_runtime_put_autosuspend(port->dev); | |
818 | } | |
819 | ||
820 | static void omap_8250_unthrottle(struct uart_port *port) | |
821 | { | |
08fb00c6 | 822 | struct omap8250_priv *priv = port->private_data; |
013e3586 | 823 | struct uart_8250_port *up = up_to_u8250p(port); |
61929cf0 | 824 | unsigned long flags; |
61929cf0 SAS |
825 | |
826 | pm_runtime_get_sync(port->dev); | |
827 | ||
d0b309a5 | 828 | /* Synchronize UART_IER access against the console. */ |
e4a13758 | 829 | uart_port_lock_irqsave(port, &flags); |
08fb00c6 V |
830 | priv->throttled = false; |
831 | if (up->dma) | |
832 | up->dma->rx_dma(up); | |
61929cf0 | 833 | up->ier |= UART_IER_RLSI | UART_IER_RDI; |
f4b042a0 | 834 | port->read_status_mask |= UART_LSR_DR; |
61929cf0 | 835 | serial_out(up, UART_IER, up->ier); |
e4a13758 | 836 | uart_port_unlock_irqrestore(port, flags); |
61929cf0 SAS |
837 | |
838 | pm_runtime_mark_last_busy(port->dev); | |
839 | pm_runtime_put_autosuspend(port->dev); | |
840 | } | |
841 | ||
801954d1 LW |
842 | static int omap8250_rs485_config(struct uart_port *port, |
843 | struct ktermios *termios, | |
844 | struct serial_rs485 *rs485) | |
845 | { | |
846 | struct omap8250_priv *priv = port->private_data; | |
847 | struct uart_8250_port *up = up_to_u8250p(port); | |
848 | u32 fixed_delay_rts_before_send = 0; | |
849 | u32 fixed_delay_rts_after_send = 0; | |
850 | unsigned int baud; | |
851 | ||
852 | /* | |
853 | * There is a fixed delay of 3 bit clock cycles after the TX shift | |
854 | * register is going empty to allow time for the stop bit to transition | |
855 | * through the transceiver before direction is changed to receive. | |
856 | * | |
857 | * Additionally there appears to be a 1 bit clock delay between writing | |
858 | * to the THR register and transmission of the start bit, per page 8783 | |
859 | * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf | |
860 | */ | |
861 | if (priv->quot) { | |
d85bf510 | 862 | if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) |
801954d1 LW |
863 | baud = port->uartclk / (16 * priv->quot); |
864 | else | |
865 | baud = port->uartclk / (13 * priv->quot); | |
866 | ||
867 | fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; | |
868 | fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; | |
869 | } | |
870 | ||
871 | /* | |
872 | * Fall back to RS485 software emulation if the UART is missing | |
873 | * hardware support, if the device tree specifies an mctrl_gpio | |
874 | * (indicates that RTS is unavailable due to a pinmux conflict) | |
875 | * or if the requested delays exceed the fixed hardware delays. | |
876 | */ | |
877 | if (!(priv->habit & UART_HAS_NATIVE_RS485) || | |
878 | mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || | |
879 | rs485->delay_rts_after_send > fixed_delay_rts_after_send || | |
880 | rs485->delay_rts_before_send > fixed_delay_rts_before_send) { | |
881 | priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; | |
882 | serial_out(up, UART_OMAP_MDR3, priv->mdr3); | |
883 | ||
884 | port->rs485_config = serial8250_em485_config; | |
885 | return serial8250_em485_config(port, termios, rs485); | |
886 | } | |
887 | ||
888 | rs485->delay_rts_after_send = fixed_delay_rts_after_send; | |
889 | rs485->delay_rts_before_send = fixed_delay_rts_before_send; | |
890 | ||
891 | if (rs485->flags & SER_RS485_ENABLED) | |
892 | priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; | |
893 | else | |
894 | priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; | |
895 | ||
896 | /* | |
897 | * Retain same polarity semantics as RS485 software emulation, | |
898 | * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. | |
899 | */ | |
900 | if (rs485->flags & SER_RS485_RTS_ON_SEND) | |
901 | priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; | |
902 | else | |
903 | priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; | |
904 | ||
905 | serial_out(up, UART_OMAP_MDR3, priv->mdr3); | |
906 | ||
907 | return 0; | |
908 | } | |
909 | ||
31a17132 | 910 | #ifdef CONFIG_SERIAL_8250_DMA |
33d9b8b2 | 911 | static int omap_8250_rx_dma(struct uart_8250_port *p); |
0e31c8d1 | 912 | |
78989841 | 913 | /* Must be called while priv->rx_dma_lock is held */ |
b74fdd23 | 914 | static void __dma_rx_do_complete(struct uart_8250_port *p) |
0e31c8d1 SAS |
915 | { |
916 | struct uart_8250_dma *dma = p->dma; | |
917 | struct tty_port *tty_port = &p->port.state->port; | |
439c7183 | 918 | struct omap8250_priv *priv = p->port.private_data; |
4bcf59a5 VR |
919 | struct dma_chan *rxchan = dma->rxchan; |
920 | dma_cookie_t cookie; | |
0e31c8d1 SAS |
921 | struct dma_tx_state state; |
922 | int count; | |
658e2ebc | 923 | int ret; |
439c7183 | 924 | u32 reg; |
0e31c8d1 | 925 | |
eda0cd35 | 926 | if (!dma->rx_running) |
78989841 | 927 | goto out; |
eda0cd35 | 928 | |
4bcf59a5 | 929 | cookie = dma->rx_cookie; |
0e31c8d1 | 930 | dma->rx_running = 0; |
439c7183 VR |
931 | |
932 | /* Re-enable RX FIFO interrupt now that transfer is complete */ | |
933 | if (priv->habit & UART_HAS_RHR_IT_DIS) { | |
934 | reg = serial_in(p, UART_OMAP_IER2); | |
935 | reg &= ~UART_OMAP_IER2_RHR_IT_DIS; | |
8973ab7a | 936 | serial_out(p, UART_OMAP_IER2, reg); |
439c7183 VR |
937 | } |
938 | ||
4bcf59a5 | 939 | dmaengine_tx_status(rxchan, cookie, &state); |
0e31c8d1 | 940 | |
4bcf59a5 VR |
941 | count = dma->rx_size - state.residue + state.in_flight_bytes; |
942 | if (count < dma->rx_size) { | |
943 | dmaengine_terminate_async(rxchan); | |
944 | ||
945 | /* | |
946 | * Poll for teardown to complete which guarantees in | |
947 | * flight data is drained. | |
948 | */ | |
949 | if (state.in_flight_bytes) { | |
950 | int poll_count = 25; | |
0e31c8d1 | 951 | |
4bcf59a5 VR |
952 | while (dmaengine_tx_status(rxchan, cookie, NULL) && |
953 | poll_count--) | |
954 | cpu_relax(); | |
0e31c8d1 | 955 | |
d7e325aa | 956 | if (poll_count == -1) |
4bcf59a5 VR |
957 | dev_err(p->port.dev, "teardown incomplete\n"); |
958 | } | |
959 | } | |
7cf4df30 | 960 | if (!count) |
78989841 | 961 | goto out; |
658e2ebc SAS |
962 | ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); |
963 | ||
964 | p->port.icount.rx += ret; | |
965 | p->port.icount.buf_overrun += count - ret; | |
78989841 | 966 | out: |
eda0cd35 | 967 | |
0e31c8d1 SAS |
968 | tty_flip_buffer_push(tty_port); |
969 | } | |
970 | ||
971 | static void __dma_rx_complete(void *param) | |
972 | { | |
a1bfb6eb | 973 | struct uart_8250_port *p = param; |
08fb00c6 | 974 | struct omap8250_priv *priv = p->port.private_data; |
a1bfb6eb V |
975 | struct uart_8250_dma *dma = p->dma; |
976 | struct dma_tx_state state; | |
977 | unsigned long flags; | |
978 | ||
d0b309a5 | 979 | /* Synchronize UART_IER access against the console. */ |
e4a13758 | 980 | uart_port_lock_irqsave(&p->port, &flags); |
a1bfb6eb V |
981 | |
982 | /* | |
983 | * If the tx status is not DMA_COMPLETE, then this is a delayed | |
984 | * completion callback. A previous RX timeout flush would have | |
985 | * already pushed the data, so exit. | |
986 | */ | |
987 | if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != | |
988 | DMA_COMPLETE) { | |
e4a13758 | 989 | uart_port_unlock_irqrestore(&p->port, flags); |
a1bfb6eb V |
990 | return; |
991 | } | |
992 | __dma_rx_do_complete(p); | |
c26389f9 VR |
993 | if (!priv->throttled) { |
994 | p->ier |= UART_IER_RLSI | UART_IER_RDI; | |
995 | serial_out(p, UART_IER, p->ier); | |
996 | if (!(priv->habit & UART_HAS_EFR2)) | |
997 | omap_8250_rx_dma(p); | |
998 | } | |
a1bfb6eb | 999 | |
e4a13758 | 1000 | uart_port_unlock_irqrestore(&p->port, flags); |
0e31c8d1 SAS |
1001 | } |
1002 | ||
eda0cd35 JO |
1003 | static void omap_8250_rx_dma_flush(struct uart_8250_port *p) |
1004 | { | |
1005 | struct omap8250_priv *priv = p->port.private_data; | |
1006 | struct uart_8250_dma *dma = p->dma; | |
75f54acc | 1007 | struct dma_tx_state state; |
eda0cd35 | 1008 | unsigned long flags; |
830acf9e | 1009 | int ret; |
eda0cd35 JO |
1010 | |
1011 | spin_lock_irqsave(&priv->rx_dma_lock, flags); | |
1012 | ||
1013 | if (!dma->rx_running) { | |
1014 | spin_unlock_irqrestore(&priv->rx_dma_lock, flags); | |
1015 | return; | |
1016 | } | |
1017 | ||
75f54acc V |
1018 | ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); |
1019 | if (ret == DMA_IN_PROGRESS) { | |
1020 | ret = dmaengine_pause(dma->rxchan); | |
1021 | if (WARN_ON_ONCE(ret)) | |
1022 | priv->rx_dma_broken = true; | |
1023 | } | |
b74fdd23 | 1024 | __dma_rx_do_complete(p); |
78989841 | 1025 | spin_unlock_irqrestore(&priv->rx_dma_lock, flags); |
eda0cd35 JO |
1026 | } |
1027 | ||
33d9b8b2 | 1028 | static int omap_8250_rx_dma(struct uart_8250_port *p) |
0e31c8d1 | 1029 | { |
eda0cd35 | 1030 | struct omap8250_priv *priv = p->port.private_data; |
0e31c8d1 | 1031 | struct uart_8250_dma *dma = p->dma; |
eda0cd35 | 1032 | int err = 0; |
0e31c8d1 | 1033 | struct dma_async_tx_descriptor *desc; |
eda0cd35 | 1034 | unsigned long flags; |
439c7183 | 1035 | u32 reg; |
0e31c8d1 | 1036 | |
87660fb4 JO |
1037 | /* Port locked to synchronize UART_IER access against the console. */ |
1038 | lockdep_assert_held_once(&p->port.lock); | |
1039 | ||
830acf9e SAS |
1040 | if (priv->rx_dma_broken) |
1041 | return -EINVAL; | |
1042 | ||
eda0cd35 JO |
1043 | spin_lock_irqsave(&priv->rx_dma_lock, flags); |
1044 | ||
c26389f9 VR |
1045 | if (dma->rx_running) { |
1046 | enum dma_status state; | |
1047 | ||
1048 | state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); | |
1049 | if (state == DMA_COMPLETE) { | |
1050 | /* | |
1051 | * Disable RX interrupts to allow RX DMA completion | |
1052 | * callback to run. | |
1053 | */ | |
1054 | p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); | |
1055 | serial_out(p, UART_IER, p->ier); | |
1056 | } | |
eda0cd35 | 1057 | goto out; |
c26389f9 | 1058 | } |
0e31c8d1 SAS |
1059 | |
1060 | desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, | |
1061 | dma->rx_size, DMA_DEV_TO_MEM, | |
1062 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
eda0cd35 JO |
1063 | if (!desc) { |
1064 | err = -EBUSY; | |
1065 | goto out; | |
1066 | } | |
0e31c8d1 SAS |
1067 | |
1068 | dma->rx_running = 1; | |
1069 | desc->callback = __dma_rx_complete; | |
1070 | desc->callback_param = p; | |
1071 | ||
1072 | dma->rx_cookie = dmaengine_submit(desc); | |
1073 | ||
439c7183 VR |
1074 | /* |
1075 | * Disable RX FIFO interrupt while RX DMA is enabled, else | |
1076 | * spurious interrupt may be raised when data is in the RX FIFO | |
1077 | * but is yet to be drained by DMA. | |
1078 | */ | |
1079 | if (priv->habit & UART_HAS_RHR_IT_DIS) { | |
1080 | reg = serial_in(p, UART_OMAP_IER2); | |
1081 | reg |= UART_OMAP_IER2_RHR_IT_DIS; | |
8973ab7a | 1082 | serial_out(p, UART_OMAP_IER2, reg); |
439c7183 VR |
1083 | } |
1084 | ||
0e31c8d1 | 1085 | dma_async_issue_pending(dma->rxchan); |
eda0cd35 JO |
1086 | out: |
1087 | spin_unlock_irqrestore(&priv->rx_dma_lock, flags); | |
1088 | return err; | |
0e31c8d1 SAS |
1089 | } |
1090 | ||
31a17132 SAS |
1091 | static int omap_8250_tx_dma(struct uart_8250_port *p); |
1092 | ||
1093 | static void omap_8250_dma_tx_complete(void *param) | |
1094 | { | |
1095 | struct uart_8250_port *p = param; | |
1096 | struct uart_8250_dma *dma = p->dma; | |
1788cf6a | 1097 | struct tty_port *tport = &p->port.state->port; |
31a17132 SAS |
1098 | unsigned long flags; |
1099 | bool en_thri = false; | |
0a0661dd | 1100 | struct omap8250_priv *priv = p->port.private_data; |
31a17132 SAS |
1101 | |
1102 | dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, | |
1103 | UART_XMIT_SIZE, DMA_TO_DEVICE); | |
1104 | ||
e4a13758 | 1105 | uart_port_lock_irqsave(&p->port, &flags); |
31a17132 SAS |
1106 | |
1107 | dma->tx_running = 0; | |
1108 | ||
77b2d268 | 1109 | uart_xmit_advance(&p->port, dma->tx_size); |
31a17132 | 1110 | |
0a0661dd SAS |
1111 | if (priv->delayed_restore) { |
1112 | priv->delayed_restore = 0; | |
1113 | omap8250_restore_regs(p); | |
1114 | } | |
1115 | ||
1788cf6a | 1116 | if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) |
31a17132 SAS |
1117 | uart_write_wakeup(&p->port); |
1118 | ||
1788cf6a | 1119 | if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(&p->port)) { |
31a17132 SAS |
1120 | int ret; |
1121 | ||
1122 | ret = omap_8250_tx_dma(p); | |
1123 | if (ret) | |
1124 | en_thri = true; | |
31a17132 SAS |
1125 | } else if (p->capabilities & UART_CAP_RPM) { |
1126 | en_thri = true; | |
1127 | } | |
1128 | ||
1129 | if (en_thri) { | |
1130 | dma->tx_err = 1; | |
7e267b29 | 1131 | serial8250_set_THRI(p); |
31a17132 SAS |
1132 | } |
1133 | ||
e4a13758 | 1134 | uart_port_unlock_irqrestore(&p->port, flags); |
31a17132 SAS |
1135 | } |
1136 | ||
1137 | static int omap_8250_tx_dma(struct uart_8250_port *p) | |
1138 | { | |
1139 | struct uart_8250_dma *dma = p->dma; | |
1140 | struct omap8250_priv *priv = p->port.private_data; | |
1788cf6a | 1141 | struct tty_port *tport = &p->port.state->port; |
31a17132 | 1142 | struct dma_async_tx_descriptor *desc; |
9054605a | 1143 | struct scatterlist sg; |
1788cf6a | 1144 | int skip_byte = -1; |
31a17132 SAS |
1145 | int ret; |
1146 | ||
1147 | if (dma->tx_running) | |
1148 | return 0; | |
1788cf6a | 1149 | if (uart_tx_stopped(&p->port) || kfifo_is_empty(&tport->xmit_fifo)) { |
31a17132 SAS |
1150 | |
1151 | /* | |
1152 | * Even if no data, we need to return an error for the two cases | |
1153 | * below so serial8250_tx_chars() is invoked and properly clears | |
1154 | * THRI and/or runtime suspend. | |
1155 | */ | |
1156 | if (dma->tx_err || p->capabilities & UART_CAP_RPM) { | |
1157 | ret = -EBUSY; | |
1158 | goto err; | |
1159 | } | |
7e267b29 | 1160 | serial8250_clear_THRI(p); |
31a17132 SAS |
1161 | return 0; |
1162 | } | |
1163 | ||
1788cf6a JSS |
1164 | sg_init_table(&sg, 1); |
1165 | ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, | |
1166 | UART_XMIT_SIZE, dma->tx_addr); | |
1167 | if (ret != 1) { | |
1168 | serial8250_clear_THRI(p); | |
1169 | return 0; | |
1170 | } | |
1171 | ||
1172 | dma->tx_size = sg_dma_len(&sg); | |
1173 | ||
31a17132 | 1174 | if (priv->habit & OMAP_DMA_TX_KICK) { |
1788cf6a | 1175 | unsigned char c; |
31a17132 SAS |
1176 | u8 tx_lvl; |
1177 | ||
1178 | /* | |
1179 | * We need to put the first byte into the FIFO in order to start | |
1180 | * the DMA transfer. For transfers smaller than four bytes we | |
1181 | * don't bother doing DMA at all. It seem not matter if there | |
1182 | * are still bytes in the FIFO from the last transfer (in case | |
1183 | * we got here directly from omap_8250_dma_tx_complete()). Bytes | |
1184 | * leaving the FIFO seem not to trigger the DMA transfer. It is | |
1185 | * really the byte that we put into the FIFO. | |
1186 | * If the FIFO is already full then we most likely got here from | |
1187 | * omap_8250_dma_tx_complete(). And this means the DMA engine | |
1188 | * just completed its work. We don't have to wait the complete | |
1189 | * 86us at 115200,8n1 but around 60us (not to mention lower | |
1190 | * baudrates). So in that case we take the interrupt and try | |
1191 | * again with an empty FIFO. | |
1192 | */ | |
1193 | tx_lvl = serial_in(p, UART_OMAP_TX_LVL); | |
1194 | if (tx_lvl == p->tx_loadsz) { | |
1195 | ret = -EBUSY; | |
1196 | goto err; | |
1197 | } | |
1198 | if (dma->tx_size < 4) { | |
1199 | ret = -EINVAL; | |
1200 | goto err; | |
1201 | } | |
1788cf6a JSS |
1202 | if (!kfifo_get(&tport->xmit_fifo, &c)) { |
1203 | ret = -EINVAL; | |
1204 | goto err; | |
1205 | } | |
1206 | skip_byte = c; | |
1207 | /* now we need to recompute due to kfifo_get */ | |
1208 | kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, | |
1209 | UART_XMIT_SIZE, dma->tx_addr); | |
31a17132 SAS |
1210 | } |
1211 | ||
9054605a | 1212 | desc = dmaengine_prep_slave_sg(dma->txchan, &sg, 1, DMA_MEM_TO_DEV, |
31a17132 SAS |
1213 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1214 | if (!desc) { | |
1215 | ret = -EBUSY; | |
1216 | goto err; | |
1217 | } | |
1218 | ||
1219 | dma->tx_running = 1; | |
1220 | ||
1221 | desc->callback = omap_8250_dma_tx_complete; | |
1222 | desc->callback_param = p; | |
1223 | ||
1224 | dma->tx_cookie = dmaengine_submit(desc); | |
1225 | ||
1226 | dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, | |
1227 | UART_XMIT_SIZE, DMA_TO_DEVICE); | |
1228 | ||
1229 | dma_async_issue_pending(dma->txchan); | |
1230 | if (dma->tx_err) | |
1231 | dma->tx_err = 0; | |
1232 | ||
7e267b29 | 1233 | serial8250_clear_THRI(p); |
1788cf6a JSS |
1234 | ret = 0; |
1235 | goto out_skip; | |
31a17132 SAS |
1236 | err: |
1237 | dma->tx_err = 1; | |
1788cf6a JSS |
1238 | out_skip: |
1239 | if (skip_byte >= 0) | |
1240 | serial_out(p, UART_TX, skip_byte); | |
31a17132 SAS |
1241 | return ret; |
1242 | } | |
1243 | ||
33d9b8b2 PH |
1244 | static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) |
1245 | { | |
1246 | switch (iir & 0x3f) { | |
1247 | case UART_IIR_RLSI: | |
1248 | case UART_IIR_RX_TIMEOUT: | |
1249 | case UART_IIR_RDI: | |
1250 | omap_8250_rx_dma_flush(up); | |
1251 | return true; | |
1252 | } | |
1253 | return omap_8250_rx_dma(up); | |
1254 | } | |
1255 | ||
f8ba5680 | 1256 | static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) |
c26389f9 VR |
1257 | { |
1258 | if ((status & (UART_LSR_DR | UART_LSR_BI)) && | |
1259 | (iir & UART_IIR_RDI)) { | |
1260 | if (handle_rx_dma(up, iir)) { | |
1261 | status = serial8250_rx_chars(up, status); | |
1262 | omap_8250_rx_dma(up); | |
1263 | } | |
1264 | } | |
1265 | ||
1266 | return status; | |
1267 | } | |
1268 | ||
1269 | static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, | |
f8ba5680 | 1270 | u16 status) |
c26389f9 | 1271 | { |
d0b309a5 JO |
1272 | /* Port locked to synchronize UART_IER access against the console. */ |
1273 | lockdep_assert_held_once(&up->port.lock); | |
1274 | ||
c26389f9 VR |
1275 | /* |
1276 | * Queue a new transfer if FIFO has data. | |
1277 | */ | |
1278 | if ((status & (UART_LSR_DR | UART_LSR_BI)) && | |
1279 | (up->ier & UART_IER_RDI)) { | |
1280 | omap_8250_rx_dma(up); | |
1281 | serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); | |
1282 | } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { | |
1283 | /* | |
1284 | * Disable RX timeout, read IIR to clear | |
1285 | * current timeout condition, clear EFR2 to | |
1286 | * periodic timeouts, re-enable interrupts. | |
1287 | */ | |
1288 | up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); | |
1289 | serial_out(up, UART_IER, up->ier); | |
1290 | omap_8250_rx_dma_flush(up); | |
1291 | serial_in(up, UART_IIR); | |
1292 | serial_out(up, UART_OMAP_EFR2, 0x0); | |
1293 | up->ier |= UART_IER_RLSI | UART_IER_RDI; | |
1294 | serial_out(up, UART_IER, up->ier); | |
1295 | } | |
1296 | } | |
1297 | ||
77285243 SAS |
1298 | /* |
1299 | * This is mostly serial8250_handle_irq(). We have a slightly different DMA | |
1300 | * hoook for RX/TX and need different logic for them in the ISR. Therefore we | |
1301 | * use the default routine in the non-DMA case and this one for with DMA. | |
1302 | */ | |
1303 | static int omap_8250_dma_handle_irq(struct uart_port *port) | |
1304 | { | |
1305 | struct uart_8250_port *up = up_to_u8250p(port); | |
c26389f9 | 1306 | struct omap8250_priv *priv = up->port.private_data; |
f8ba5680 | 1307 | u16 status; |
77285243 | 1308 | u8 iir; |
77285243 | 1309 | |
77285243 SAS |
1310 | iir = serial_port_in(port, UART_IIR); |
1311 | if (iir & UART_IIR_NO_INT) { | |
c6689dfd | 1312 | return IRQ_HANDLED; |
77285243 SAS |
1313 | } |
1314 | ||
e4a13758 | 1315 | uart_port_lock(port); |
77285243 SAS |
1316 | |
1317 | status = serial_port_in(port, UART_LSR); | |
1318 | ||
c6bb0574 RW |
1319 | if ((iir & 0x3f) != UART_IIR_THRI) { |
1320 | if (priv->habit & UART_HAS_EFR2) | |
1321 | am654_8250_handle_rx_dma(up, iir, status); | |
1322 | else | |
1323 | status = omap_8250_handle_rx_dma(up, iir, status); | |
1324 | } | |
c26389f9 | 1325 | |
77285243 SAS |
1326 | serial8250_modem_status(up); |
1327 | if (status & UART_LSR_THRE && up->dma->tx_err) { | |
1328 | if (uart_tx_stopped(&up->port) || | |
1788cf6a | 1329 | kfifo_is_empty(&up->port.state->port.xmit_fifo)) { |
77285243 SAS |
1330 | up->dma->tx_err = 0; |
1331 | serial8250_tx_chars(up); | |
1332 | } else { | |
1333 | /* | |
1334 | * try again due to an earlier failer which | |
1335 | * might have been resolved by now. | |
1336 | */ | |
a86f50ed | 1337 | if (omap_8250_tx_dma(up)) |
77285243 SAS |
1338 | serial8250_tx_chars(up); |
1339 | } | |
1340 | } | |
1341 | ||
75f4e830 JH |
1342 | uart_unlock_and_check_sysrq(port); |
1343 | ||
77285243 SAS |
1344 | return 1; |
1345 | } | |
0a0661dd SAS |
1346 | |
1347 | static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) | |
1348 | { | |
1349 | return false; | |
1350 | } | |
1351 | ||
1352 | #else | |
1353 | ||
33d9b8b2 | 1354 | static inline int omap_8250_rx_dma(struct uart_8250_port *p) |
0a0661dd SAS |
1355 | { |
1356 | return -EINVAL; | |
1357 | } | |
31a17132 SAS |
1358 | #endif |
1359 | ||
9e91597f SAS |
1360 | static int omap8250_no_handle_irq(struct uart_port *port) |
1361 | { | |
1362 | /* IRQ has not been requested but handling irq? */ | |
1363 | WARN_ONCE(1, "Unexpected irq handling before port startup\n"); | |
1364 | return 0; | |
1365 | } | |
1366 | ||
c26389f9 VR |
1367 | static struct omap8250_dma_params am654_dma = { |
1368 | .rx_size = SZ_2K, | |
1369 | .rx_trigger = 1, | |
1370 | .tx_trigger = TX_TRIGGER, | |
1371 | }; | |
1372 | ||
7229b84c VR |
1373 | static struct omap8250_dma_params am33xx_dma = { |
1374 | .rx_size = RX_TRIGGER, | |
1375 | .rx_trigger = RX_TRIGGER, | |
1376 | .tx_trigger = TX_TRIGGER, | |
1377 | }; | |
1378 | ||
c26389f9 VR |
1379 | static struct omap8250_platdata am654_platdata = { |
1380 | .dma_params = &am654_dma, | |
b67e830d | 1381 | .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | |
801954d1 | 1382 | UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, |
c26389f9 VR |
1383 | }; |
1384 | ||
7229b84c VR |
1385 | static struct omap8250_platdata am33xx_platdata = { |
1386 | .dma_params = &am33xx_dma, | |
1387 | .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, | |
1388 | }; | |
1389 | ||
1390 | static struct omap8250_platdata omap4_platdata = { | |
1391 | .dma_params = &am33xx_dma, | |
1392 | .habit = UART_ERRATA_CLOCK_DISABLE, | |
1393 | }; | |
4fcdff9b SN |
1394 | |
1395 | static const struct of_device_id omap8250_dt_ids[] = { | |
c26389f9 | 1396 | { .compatible = "ti,am654-uart", .data = &am654_platdata, }, |
4fcdff9b SN |
1397 | { .compatible = "ti,omap2-uart" }, |
1398 | { .compatible = "ti,omap3-uart" }, | |
7229b84c VR |
1399 | { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, |
1400 | { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, | |
1401 | { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, | |
1402 | { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, | |
4fcdff9b SN |
1403 | {}, |
1404 | }; | |
1405 | MODULE_DEVICE_TABLE(of, omap8250_dt_ids); | |
1406 | ||
61929cf0 SAS |
1407 | static int omap8250_probe(struct platform_device *pdev) |
1408 | { | |
d6ce4ec0 | 1409 | struct device_node *np = pdev->dev.of_node; |
61929cf0 | 1410 | struct omap8250_priv *priv; |
7229b84c | 1411 | const struct omap8250_platdata *pdata; |
61929cf0 | 1412 | struct uart_8250_port up; |
9167cc78 | 1413 | struct resource *regs; |
61929cf0 | 1414 | void __iomem *membase; |
664f5d03 | 1415 | int ret; |
61929cf0 | 1416 | |
9167cc78 AS |
1417 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1418 | if (!regs) { | |
1419 | dev_err(&pdev->dev, "missing registers\n"); | |
61929cf0 SAS |
1420 | return -EINVAL; |
1421 | } | |
1422 | ||
1423 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); | |
1424 | if (!priv) | |
1425 | return -ENOMEM; | |
1426 | ||
4bdc0d67 | 1427 | membase = devm_ioremap(&pdev->dev, regs->start, |
61929cf0 SAS |
1428 | resource_size(regs)); |
1429 | if (!membase) | |
1430 | return -ENODEV; | |
1431 | ||
1432 | memset(&up, 0, sizeof(up)); | |
1433 | up.port.dev = &pdev->dev; | |
1434 | up.port.mapbase = regs->start; | |
1435 | up.port.membase = membase; | |
61929cf0 SAS |
1436 | /* |
1437 | * It claims to be 16C750 compatible however it is a little different. | |
1438 | * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to | |
1439 | * have) is enabled via EFR instead of MCR. The type is set here 8250 | |
1440 | * just to get things going. UNKNOWN does not work for a few reasons and | |
1441 | * we don't need our own type since we don't use 8250's set_termios() | |
1442 | * or pm callback. | |
1443 | */ | |
1444 | up.port.type = PORT_8250; | |
664f5d03 | 1445 | up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | UPF_HARD_FLOW; |
61929cf0 SAS |
1446 | up.port.private_data = priv; |
1447 | ||
61929cf0 SAS |
1448 | up.tx_loadsz = 64; |
1449 | up.capabilities = UART_CAP_FIFO; | |
71504e51 | 1450 | #ifdef CONFIG_PM |
61929cf0 | 1451 | /* |
71504e51 | 1452 | * Runtime PM is mostly transparent. However to do it right we need to a |
61929cf0 | 1453 | * TX empty interrupt before we can put the device to auto idle. So if |
71504e51 RW |
1454 | * PM is not enabled we don't add that flag and can spare that one extra |
1455 | * interrupt in the TX path. | |
61929cf0 SAS |
1456 | */ |
1457 | up.capabilities |= UART_CAP_RPM; | |
1458 | #endif | |
1459 | up.port.set_termios = omap_8250_set_termios; | |
4bf4ea9d | 1460 | up.port.set_mctrl = omap8250_set_mctrl; |
61929cf0 SAS |
1461 | up.port.pm = omap_8250_pm; |
1462 | up.port.startup = omap_8250_startup; | |
1463 | up.port.shutdown = omap_8250_shutdown; | |
1464 | up.port.throttle = omap_8250_throttle; | |
1465 | up.port.unthrottle = omap_8250_unthrottle; | |
801954d1 LW |
1466 | up.port.rs485_config = omap8250_rs485_config; |
1467 | /* same rs485_supported for software emulation and native RS485 */ | |
1e005bfa | 1468 | up.port.rs485_supported = serial8250_em485_supported; |
058bc104 LW |
1469 | up.rs485_start_tx = serial8250_em485_start_tx; |
1470 | up.rs485_stop_tx = serial8250_em485_stop_tx; | |
a4424b90 | 1471 | up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); |
61929cf0 | 1472 | |
664f5d03 AS |
1473 | ret = uart_read_port_properties(&up.port); |
1474 | if (ret) | |
54178fe6 | 1475 | return ret; |
54178fe6 | 1476 | |
664f5d03 AS |
1477 | up.port.regshift = OMAP_UART_REGSHIFT; |
1478 | up.port.fifosize = 64; | |
1479 | ||
1480 | if (!up.port.uartclk) { | |
7d470ebf V |
1481 | struct clk *clk; |
1482 | ||
1483 | clk = devm_clk_get(&pdev->dev, NULL); | |
1484 | if (IS_ERR(clk)) { | |
1485 | if (PTR_ERR(clk) == -EPROBE_DEFER) | |
1486 | return -EPROBE_DEFER; | |
1487 | } else { | |
1488 | up.port.uartclk = clk_get_rate(clk); | |
1489 | } | |
1490 | } | |
1491 | ||
1fe0e1fa TL |
1492 | if (of_property_read_u32(np, "overrun-throttle-ms", |
1493 | &up.overrun_backoff_time_ms) != 0) | |
1494 | up.overrun_backoff_time_ms = 0; | |
1495 | ||
7229b84c VR |
1496 | pdata = of_device_get_match_data(&pdev->dev); |
1497 | if (pdata) | |
1498 | priv->habit |= pdata->habit; | |
d6ce4ec0 | 1499 | |
61929cf0 SAS |
1500 | if (!up.port.uartclk) { |
1501 | up.port.uartclk = DEFAULT_CLK_SPEED; | |
1502 | dev_warn(&pdev->dev, | |
1503 | "No clock speed specified: using default: %d\n", | |
1504 | DEFAULT_CLK_SPEED); | |
1505 | } | |
1506 | ||
398cecc2 TL |
1507 | priv->membase = membase; |
1508 | priv->line = -ENODEV; | |
2552d352 RW |
1509 | priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; |
1510 | priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; | |
01d2b189 | 1511 | cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); |
61929cf0 SAS |
1512 | INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); |
1513 | ||
eda0cd35 JO |
1514 | spin_lock_init(&priv->rx_dma_lock); |
1515 | ||
398cecc2 TL |
1516 | platform_set_drvdata(pdev, priv); |
1517 | ||
61929cf0 | 1518 | device_init_wakeup(&pdev->dev, true); |
4ce35a36 | 1519 | pm_runtime_enable(&pdev->dev); |
61929cf0 | 1520 | pm_runtime_use_autosuspend(&pdev->dev); |
627a545c TL |
1521 | |
1522 | /* | |
1523 | * Disable runtime PM until autosuspend delay unless specifically | |
1524 | * enabled by the user via sysfs. This is the historic way to | |
1525 | * prevent an unsafe default policy with lossy characters on wake-up. | |
1526 | * For serdev devices this is not needed, the policy can be managed by | |
1527 | * the serdev driver. | |
1528 | */ | |
1529 | if (!of_get_available_child_count(pdev->dev.of_node)) | |
1530 | pm_runtime_set_autosuspend_delay(&pdev->dev, -1); | |
61929cf0 | 1531 | |
61929cf0 SAS |
1532 | pm_runtime_get_sync(&pdev->dev); |
1533 | ||
1534 | omap_serial_fill_features_erratas(&up, priv); | |
9e91597f | 1535 | up.port.handle_irq = omap8250_no_handle_irq; |
7229b84c VR |
1536 | priv->rx_trigger = RX_TRIGGER; |
1537 | priv->tx_trigger = TX_TRIGGER; | |
0a0661dd | 1538 | #ifdef CONFIG_SERIAL_8250_DMA |
d6ce4ec0 V |
1539 | /* |
1540 | * Oh DMA support. If there are no DMA properties in the DT then | |
1541 | * we will fall back to a generic DMA channel which does not | |
1542 | * really work here. To ensure that we do not get a generic DMA | |
1543 | * channel assigned, we have the the_no_dma_filter_fn() here. | |
1544 | * To avoid "failed to request DMA" messages we check for DMA | |
1545 | * properties in DT. | |
1546 | */ | |
1547 | ret = of_property_count_strings(np, "dma-names"); | |
1548 | if (ret == 2) { | |
7229b84c | 1549 | struct omap8250_dma_params *dma_params = NULL; |
db86bb6e | 1550 | struct uart_8250_dma *dma = &priv->omap8250_dma; |
7229b84c | 1551 | |
db86bb6e TL |
1552 | dma->fn = the_no_dma_filter_fn; |
1553 | dma->tx_dma = omap_8250_tx_dma; | |
1554 | dma->rx_dma = omap_8250_rx_dma; | |
7229b84c VR |
1555 | if (pdata) |
1556 | dma_params = pdata->dma_params; | |
1557 | ||
1558 | if (dma_params) { | |
db86bb6e TL |
1559 | dma->rx_size = dma_params->rx_size; |
1560 | dma->rxconf.src_maxburst = dma_params->rx_trigger; | |
1561 | dma->txconf.dst_maxburst = dma_params->tx_trigger; | |
7229b84c VR |
1562 | priv->rx_trigger = dma_params->rx_trigger; |
1563 | priv->tx_trigger = dma_params->tx_trigger; | |
1564 | } else { | |
db86bb6e TL |
1565 | dma->rx_size = RX_TRIGGER; |
1566 | dma->rxconf.src_maxburst = RX_TRIGGER; | |
1567 | dma->txconf.dst_maxburst = TX_TRIGGER; | |
7229b84c | 1568 | } |
0a0661dd SAS |
1569 | } |
1570 | #endif | |
fef4f600 | 1571 | |
664f5d03 AS |
1572 | irq_set_status_flags(up.port.irq, IRQ_NOAUTOEN); |
1573 | ret = devm_request_irq(&pdev->dev, up.port.irq, omap8250_irq, 0, | |
fef4f600 TL |
1574 | dev_name(&pdev->dev), priv); |
1575 | if (ret < 0) | |
1576 | return ret; | |
1577 | ||
1578 | priv->wakeirq = irq_of_parse_and_map(np, 1); | |
1579 | ||
61929cf0 SAS |
1580 | ret = serial8250_register_8250_port(&up); |
1581 | if (ret < 0) { | |
1582 | dev_err(&pdev->dev, "unable to register 8250 port\n"); | |
1583 | goto err; | |
1584 | } | |
1585 | priv->line = ret; | |
61929cf0 SAS |
1586 | pm_runtime_mark_last_busy(&pdev->dev); |
1587 | pm_runtime_put_autosuspend(&pdev->dev); | |
1588 | return 0; | |
1589 | err: | |
4e0f5cc6 TL |
1590 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
1591 | pm_runtime_put_sync(&pdev->dev); | |
b9ab22c2 | 1592 | flush_work(&priv->qos_work); |
61929cf0 | 1593 | pm_runtime_disable(&pdev->dev); |
b9ab22c2 | 1594 | cpu_latency_qos_remove_request(&priv->pm_qos_request); |
61929cf0 SAS |
1595 | return ret; |
1596 | } | |
1597 | ||
7e1efdf8 | 1598 | static void omap8250_remove(struct platform_device *pdev) |
61929cf0 SAS |
1599 | { |
1600 | struct omap8250_priv *priv = platform_get_drvdata(pdev); | |
db86bb6e | 1601 | struct uart_8250_port *up; |
e3f0c638 TL |
1602 | int err; |
1603 | ||
1604 | err = pm_runtime_resume_and_get(&pdev->dev); | |
1605 | if (err) | |
ad90d035 | 1606 | dev_err(&pdev->dev, "Failed to resume hardware\n"); |
61929cf0 | 1607 | |
db86bb6e TL |
1608 | up = serial8250_get_port(priv->line); |
1609 | omap_8250_shutdown(&up->port); | |
398cecc2 TL |
1610 | serial8250_unregister_port(priv->line); |
1611 | priv->line = -ENODEV; | |
4e0f5cc6 | 1612 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
61929cf0 | 1613 | pm_runtime_put_sync(&pdev->dev); |
d0b68629 | 1614 | flush_work(&priv->qos_work); |
61929cf0 | 1615 | pm_runtime_disable(&pdev->dev); |
01d2b189 | 1616 | cpu_latency_qos_remove_request(&priv->pm_qos_request); |
61929cf0 | 1617 | device_init_wakeup(&pdev->dev, false); |
61929cf0 SAS |
1618 | } |
1619 | ||
61929cf0 SAS |
1620 | static int omap8250_prepare(struct device *dev) |
1621 | { | |
1622 | struct omap8250_priv *priv = dev_get_drvdata(dev); | |
1623 | ||
1624 | if (!priv) | |
1625 | return 0; | |
1626 | priv->is_suspending = true; | |
1627 | return 0; | |
1628 | } | |
1629 | ||
1630 | static void omap8250_complete(struct device *dev) | |
1631 | { | |
1632 | struct omap8250_priv *priv = dev_get_drvdata(dev); | |
1633 | ||
1634 | if (!priv) | |
1635 | return; | |
1636 | priv->is_suspending = false; | |
1637 | } | |
1638 | ||
1639 | static int omap8250_suspend(struct device *dev) | |
1640 | { | |
1641 | struct omap8250_priv *priv = dev_get_drvdata(dev); | |
09d8b2bd | 1642 | struct uart_8250_port *up = serial8250_get_port(priv->line); |
68e6939e | 1643 | struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain); |
560706ef | 1644 | int err = 0; |
61929cf0 SAS |
1645 | |
1646 | serial8250_suspend_port(priv->line); | |
09d8b2bd | 1647 | |
20a41a62 TL |
1648 | err = pm_runtime_resume_and_get(dev); |
1649 | if (err) | |
1650 | return err; | |
09d8b2bd V |
1651 | if (!device_may_wakeup(dev)) |
1652 | priv->wer = 0; | |
1653 | serial_out(up, UART_OMAP_WER, priv->wer); | |
68e6939e TR |
1654 | if (uart_console(&up->port)) { |
1655 | if (console_suspend_enabled) | |
1656 | err = pm_runtime_force_suspend(dev); | |
1657 | else { | |
1658 | /* | |
1659 | * The pd shall not be powered-off (no console suspend). | |
1660 | * Make copy of genpd flags before to set it always on. | |
1661 | * The original value is restored during the resume. | |
1662 | */ | |
1663 | genpd_flags_console = genpd->flags; | |
1664 | genpd->flags |= GENPD_FLAG_ALWAYS_ON; | |
1665 | } | |
1666 | } | |
61929cf0 | 1667 | flush_work(&priv->qos_work); |
20a41a62 TL |
1668 | |
1669 | return err; | |
61929cf0 SAS |
1670 | } |
1671 | ||
1672 | static int omap8250_resume(struct device *dev) | |
1673 | { | |
1674 | struct omap8250_priv *priv = dev_get_drvdata(dev); | |
560706ef | 1675 | struct uart_8250_port *up = serial8250_get_port(priv->line); |
68e6939e | 1676 | struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain); |
20a41a62 | 1677 | int err; |
61929cf0 | 1678 | |
560706ef | 1679 | if (uart_console(&up->port) && console_suspend_enabled) { |
68e6939e TR |
1680 | if (console_suspend_enabled) { |
1681 | err = pm_runtime_force_resume(dev); | |
1682 | if (err) | |
1683 | return err; | |
1684 | } else | |
1685 | genpd->flags = genpd_flags_console; | |
560706ef TL |
1686 | } |
1687 | ||
61929cf0 | 1688 | serial8250_resume_port(priv->line); |
20a41a62 TL |
1689 | /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ |
1690 | pm_runtime_mark_last_busy(dev); | |
1691 | pm_runtime_put_autosuspend(dev); | |
1692 | ||
61929cf0 SAS |
1693 | return 0; |
1694 | } | |
61929cf0 | 1695 | |
61929cf0 SAS |
1696 | static int omap8250_lost_context(struct uart_8250_port *up) |
1697 | { | |
1698 | u32 val; | |
1699 | ||
cdb929e4 | 1700 | val = serial_in(up, UART_OMAP_SCR); |
61929cf0 | 1701 | /* |
cdb929e4 SN |
1702 | * If we lose context, then SCR is set to its reset value of zero. |
1703 | * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, | |
1704 | * among other bits, to never set the register back to zero again. | |
61929cf0 | 1705 | */ |
cdb929e4 | 1706 | if (!val) |
61929cf0 SAS |
1707 | return 1; |
1708 | return 0; | |
1709 | } | |
1710 | ||
c53aab20 GU |
1711 | static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) |
1712 | { | |
1713 | writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); | |
1714 | } | |
1715 | ||
cdb929e4 SN |
1716 | /* TODO: in future, this should happen via API in drivers/reset/ */ |
1717 | static int omap8250_soft_reset(struct device *dev) | |
1718 | { | |
1719 | struct omap8250_priv *priv = dev_get_drvdata(dev); | |
cdb929e4 SN |
1720 | int timeout = 100; |
1721 | int sysc; | |
1722 | int syss; | |
1723 | ||
13dc04d0 TL |
1724 | /* |
1725 | * At least on omap4, unused uarts may not idle after reset without | |
1726 | * a basic scr dma configuration even with no dma in use. The | |
1727 | * module clkctrl status bits will be 1 instead of 3 blocking idle | |
1728 | * for the whole clockdomain. The softreset below will clear scr, | |
1729 | * and we restore it on resume so this is safe to do on all SoCs | |
1730 | * needing omap8250_soft_reset() quirk. Do it in two writes as | |
1731 | * recommended in the comment for omap8250_update_scr(). | |
1732 | */ | |
398cecc2 TL |
1733 | uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); |
1734 | uart_write(priv, UART_OMAP_SCR, | |
13dc04d0 TL |
1735 | OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); |
1736 | ||
398cecc2 | 1737 | sysc = uart_read(priv, UART_OMAP_SYSC); |
cdb929e4 SN |
1738 | |
1739 | /* softreset the UART */ | |
1740 | sysc |= OMAP_UART_SYSC_SOFTRESET; | |
398cecc2 | 1741 | uart_write(priv, UART_OMAP_SYSC, sysc); |
cdb929e4 SN |
1742 | |
1743 | /* By experiments, 1us enough for reset complete on AM335x */ | |
1744 | do { | |
1745 | udelay(1); | |
398cecc2 | 1746 | syss = uart_read(priv, UART_OMAP_SYSS); |
cdb929e4 SN |
1747 | } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); |
1748 | ||
1749 | if (!timeout) { | |
1750 | dev_err(dev, "timed out waiting for reset done\n"); | |
1751 | return -ETIMEDOUT; | |
1752 | } | |
1753 | ||
1754 | return 0; | |
1755 | } | |
1756 | ||
61929cf0 SAS |
1757 | static int omap8250_runtime_suspend(struct device *dev) |
1758 | { | |
1759 | struct omap8250_priv *priv = dev_get_drvdata(dev); | |
398cecc2 | 1760 | struct uart_8250_port *up = NULL; |
4e0f5cc6 | 1761 | |
398cecc2 TL |
1762 | if (priv->line >= 0) |
1763 | up = serial8250_get_port(priv->line); | |
61929cf0 | 1764 | |
cdb929e4 SN |
1765 | if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { |
1766 | int ret; | |
1767 | ||
1768 | ret = omap8250_soft_reset(dev); | |
1769 | if (ret) | |
1770 | return ret; | |
1771 | ||
398cecc2 TL |
1772 | if (up) { |
1773 | /* Restore to UART mode after reset (for wakeup) */ | |
1774 | omap8250_update_mdr1(up, priv); | |
1775 | /* Restore wakeup enable register */ | |
1776 | serial_out(up, UART_OMAP_WER, priv->wer); | |
1777 | } | |
cdb929e4 SN |
1778 | } |
1779 | ||
398cecc2 | 1780 | if (up && up->dma && up->dma->rxchan) |
33d9b8b2 | 1781 | omap_8250_rx_dma_flush(up); |
61929cf0 | 1782 | |
2552d352 | 1783 | priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; |
61929cf0 | 1784 | schedule_work(&priv->qos_work); |
8700a7ea | 1785 | atomic_set(&priv->active, 0); |
61929cf0 SAS |
1786 | |
1787 | return 0; | |
1788 | } | |
1789 | ||
1790 | static int omap8250_runtime_resume(struct device *dev) | |
1791 | { | |
1792 | struct omap8250_priv *priv = dev_get_drvdata(dev); | |
398cecc2 | 1793 | struct uart_8250_port *up = NULL; |
61929cf0 | 1794 | |
8700a7ea TL |
1795 | /* Did the hardware wake to a device IO interrupt before a wakeirq? */ |
1796 | if (atomic_read(&priv->active)) | |
1797 | return 0; | |
1798 | ||
398cecc2 TL |
1799 | if (priv->line >= 0) |
1800 | up = serial8250_get_port(priv->line); | |
61929cf0 | 1801 | |
8b455037 | 1802 | if (up && omap8250_lost_context(up)) { |
e4a13758 | 1803 | uart_port_lock_irq(&up->port); |
61929cf0 | 1804 | omap8250_restore_regs(up); |
e4a13758 | 1805 | uart_port_unlock_irq(&up->port); |
8b455037 | 1806 | } |
61929cf0 | 1807 | |
87660fb4 | 1808 | if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { |
e4a13758 | 1809 | uart_port_lock_irq(&up->port); |
33d9b8b2 | 1810 | omap_8250_rx_dma(up); |
e4a13758 | 1811 | uart_port_unlock_irq(&up->port); |
87660fb4 | 1812 | } |
0a0661dd | 1813 | |
8700a7ea | 1814 | atomic_set(&priv->active, 1); |
61929cf0 SAS |
1815 | priv->latency = priv->calc_latency; |
1816 | schedule_work(&priv->qos_work); | |
8700a7ea | 1817 | |
61929cf0 SAS |
1818 | return 0; |
1819 | } | |
61929cf0 | 1820 | |
00648d02 SAS |
1821 | #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP |
1822 | static int __init omap8250_console_fixup(void) | |
1823 | { | |
1824 | char *omap_str; | |
1825 | char *options; | |
1826 | u8 idx; | |
1827 | ||
1828 | if (strstr(boot_command_line, "console=ttyS")) | |
1829 | /* user set a ttyS based name for the console */ | |
1830 | return 0; | |
1831 | ||
1832 | omap_str = strstr(boot_command_line, "console=ttyO"); | |
1833 | if (!omap_str) | |
1834 | /* user did not set ttyO based console, so we don't care */ | |
1835 | return 0; | |
1836 | ||
1837 | omap_str += 12; | |
1838 | if ('0' <= *omap_str && *omap_str <= '9') | |
1839 | idx = *omap_str - '0'; | |
1840 | else | |
1841 | return 0; | |
1842 | ||
1843 | omap_str++; | |
1844 | if (omap_str[0] == ',') { | |
1845 | omap_str++; | |
1846 | options = omap_str; | |
1847 | } else { | |
1848 | options = NULL; | |
1849 | } | |
1850 | ||
1851 | add_preferred_console("ttyS", idx, options); | |
1852 | pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", | |
1853 | idx, idx); | |
1854 | pr_err("This ensures that you still see kernel messages. Please\n"); | |
1855 | pr_err("update your kernel commandline.\n"); | |
1856 | return 0; | |
1857 | } | |
1858 | console_initcall(omap8250_console_fixup); | |
1859 | #endif | |
1860 | ||
61929cf0 | 1861 | static const struct dev_pm_ops omap8250_dev_pm_ops = { |
ae62c49c AB |
1862 | SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) |
1863 | RUNTIME_PM_OPS(omap8250_runtime_suspend, | |
61929cf0 | 1864 | omap8250_runtime_resume, NULL) |
ae62c49c AB |
1865 | .prepare = pm_sleep_ptr(omap8250_prepare), |
1866 | .complete = pm_sleep_ptr(omap8250_complete), | |
61929cf0 SAS |
1867 | }; |
1868 | ||
61929cf0 SAS |
1869 | static struct platform_driver omap8250_platform_driver = { |
1870 | .driver = { | |
1871 | .name = "omap8250", | |
ae62c49c | 1872 | .pm = pm_ptr(&omap8250_dev_pm_ops), |
61929cf0 | 1873 | .of_match_table = omap8250_dt_ids, |
61929cf0 SAS |
1874 | }, |
1875 | .probe = omap8250_probe, | |
7e1efdf8 | 1876 | .remove_new = omap8250_remove, |
61929cf0 SAS |
1877 | }; |
1878 | module_platform_driver(omap8250_platform_driver); | |
1879 | ||
1880 | MODULE_AUTHOR("Sebastian Andrzej Siewior"); | |
1881 | MODULE_DESCRIPTION("OMAP 8250 Driver"); | |
1882 | MODULE_LICENSE("GPL v2"); |