[linux-2.6-block.git] / drivers / tty / serial / 21285.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for the serial port on the 21285 StrongArm-110 core logic chip.
 *
 * Based on drivers/char/serial.c
 */
#include <linux/module.h>
#include <linux/tty.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/device.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/io.h>

#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/system_info.h>
#include <asm/hardware/dec21285.h>
#include <mach/hardware.h>

#define BAUD_BASE		(mem_fclk_21285/64)

#define SERIAL_21285_NAME	"ttyFB"
#define SERIAL_21285_MAJOR	204
#define SERIAL_21285_MINOR	4

#define RXSTAT_DUMMY_READ	0x80000000
#define RXSTAT_FRAME		(1 << 0)
#define RXSTAT_PARITY		(1 << 1)
#define RXSTAT_OVERRUN		(1 << 2)
#define RXSTAT_ANYERR		(RXSTAT_FRAME|RXSTAT_PARITY|RXSTAT_OVERRUN)

#define H_UBRLCR_BREAK		(1 << 0)
#define H_UBRLCR_PARENB		(1 << 1)
#define H_UBRLCR_PAREVN		(1 << 2)
#define H_UBRLCR_STOPB		(1 << 3)
#define H_UBRLCR_FIFO		(1 << 4)

static const char serial21285_name[] = "Footbridge UART";

/*
 * We only need 2 bits of data, so instead of creating a whole structure for
 * this, use bits of the private_data pointer of the uart port structure.
 */
#define tx_enabled_bit	0
#define rx_enabled_bit	1

static bool is_enabled(struct uart_port *port, int bit)
{
	unsigned long *private_data = (unsigned long *)&port->private_data;

	if (test_bit(bit, private_data))
		return true;
	return false;
}

static void enable(struct uart_port *port, int bit)
{
	unsigned long *private_data = (unsigned long *)&port->private_data;

	set_bit(bit, private_data);
}

static void disable(struct uart_port *port, int bit)
{
	unsigned long *private_data = (unsigned long *)&port->private_data;

	clear_bit(bit, private_data);
}

#define is_tx_enabled(port)	is_enabled(port, tx_enabled_bit)
#define tx_enable(port)		enable(port, tx_enabled_bit)
#define tx_disable(port)	disable(port, tx_enabled_bit)

#define is_rx_enabled(port)	is_enabled(port, rx_enabled_bit)
#define rx_enable(port)		enable(port, rx_enabled_bit)
#define rx_disable(port)	disable(port, rx_enabled_bit)

/*
 * The documented expression for selecting the divisor is:
 *  BAUD_BASE / baud - 1
 * However, typically BAUD_BASE is not divisible by baud, so
 * we want to select the divisor that gives us the minimum
 * error.  Therefore, we want:
 *  int(BAUD_BASE / baud - 0.5) ->
 *  int(BAUD_BASE / baud - (baud >> 1) / baud) ->
 *  int((BAUD_BASE - (baud >> 1)) / baud)
 */

static void serial21285_stop_tx(struct uart_port *port)
{
	if (is_tx_enabled(port)) {
		disable_irq_nosync(IRQ_CONTX);
		tx_disable(port);
	}
}

static void serial21285_start_tx(struct uart_port *port)
{
	if (!is_tx_enabled(port)) {
		enable_irq(IRQ_CONTX);
		tx_enable(port);
	}
}

static void serial21285_stop_rx(struct uart_port *port)
{
	if (is_rx_enabled(port)) {
		disable_irq_nosync(IRQ_CONRX);
		rx_disable(port);
	}
}

static irqreturn_t serial21285_rx_chars(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	unsigned int status, ch, flag, rxs, max_count = 256;

	status = *CSR_UARTFLG;
	while (!(status & 0x10) && max_count--) {
		ch = *CSR_UARTDR;
		flag = TTY_NORMAL;
		port->icount.rx++;

		rxs = *CSR_RXSTAT | RXSTAT_DUMMY_READ;
		if (unlikely(rxs & RXSTAT_ANYERR)) {
			if (rxs & RXSTAT_PARITY)
				port->icount.parity++;
			else if (rxs & RXSTAT_FRAME)
				port->icount.frame++;
			if (rxs & RXSTAT_OVERRUN)
				port->icount.overrun++;

			rxs &= port->read_status_mask;

			if (rxs & RXSTAT_PARITY)
				flag = TTY_PARITY;
			else if (rxs & RXSTAT_FRAME)
				flag = TTY_FRAME;
		}

		uart_insert_char(port, rxs, RXSTAT_OVERRUN, ch, flag);

		status = *CSR_UARTFLG;
	}
	tty_flip_buffer_push(&port->state->port);

	return IRQ_HANDLED;
}

static irqreturn_t serial21285_tx_chars(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	struct circ_buf *xmit = &port->state->xmit;
	int count = 256;

	if (port->x_char) {
		*CSR_UARTDR = port->x_char;
		port->icount.tx++;
		port->x_char = 0;
		goto out;
	}
	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
		serial21285_stop_tx(port);
		goto out;
	}

	do {
		*CSR_UARTDR = xmit->buf[xmit->tail];
		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
		port->icount.tx++;
		if (uart_circ_empty(xmit))
			break;
	} while (--count > 0 && !(*CSR_UARTFLG & 0x20));

	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);

	if (uart_circ_empty(xmit))
		serial21285_stop_tx(port);

 out:
	return IRQ_HANDLED;
}

static unsigned int serial21285_tx_empty(struct uart_port *port)
{
	return (*CSR_UARTFLG & 8) ? 0 : TIOCSER_TEMT;
}

/* no modem control lines */
static unsigned int serial21285_get_mctrl(struct uart_port *port)
{
	return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
}

static void serial21285_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
}

static void serial21285_break_ctl(struct uart_port *port, int break_state)
{
	unsigned long flags;
	unsigned int h_lcr;

	spin_lock_irqsave(&port->lock, flags);
	h_lcr = *CSR_H_UBRLCR;
	if (break_state)
		h_lcr |= H_UBRLCR_BREAK;
	else
		h_lcr &= ~H_UBRLCR_BREAK;
	*CSR_H_UBRLCR = h_lcr;
	spin_unlock_irqrestore(&port->lock, flags);
}

static int serial21285_startup(struct uart_port *port)
{
	int ret;

	tx_enable(port);
	rx_enable(port);

	ret = request_irq(IRQ_CONRX, serial21285_rx_chars, 0,
			  serial21285_name, port);
	if (ret == 0) {
		ret = request_irq(IRQ_CONTX, serial21285_tx_chars, 0,
				  serial21285_name, port);
		if (ret)
			free_irq(IRQ_CONRX, port);
	}

	return ret;
}

static void serial21285_shutdown(struct uart_port *port)
{
	free_irq(IRQ_CONTX, port);
	free_irq(IRQ_CONRX, port);
}

static void
serial21285_set_termios(struct uart_port *port, struct ktermios *termios,
			const struct ktermios *old)
{
	unsigned long flags;
	unsigned int baud, quot, h_lcr, b;

	/*
	 * We don't support modem control lines.
	 */
	termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
	termios->c_cflag |= CLOCAL;

	/*
	 * We don't support BREAK character recognition.
	 */
	termios->c_iflag &= ~(IGNBRK | BRKINT);

	/*
	 * Ask the core to calculate the divisor for us.
	 */
	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 
	quot = uart_get_divisor(port, baud);
	b = port->uartclk / (16 * quot);
	tty_termios_encode_baud_rate(termios, b, b);

	switch (termios->c_cflag & CSIZE) {
	case CS5:
		h_lcr = 0x00;
		break;
	case CS6:
		h_lcr = 0x20;
		break;
	case CS7:
		h_lcr = 0x40;
		break;
	default: /* CS8 */
		h_lcr = 0x60;
		break;
	}

	if (termios->c_cflag & CSTOPB)
		h_lcr |= H_UBRLCR_STOPB;
	if (termios->c_cflag & PARENB) {
		h_lcr |= H_UBRLCR_PARENB;
		if (!(termios->c_cflag & PARODD))
			h_lcr |= H_UBRLCR_PAREVN;
	}

	if (port->fifosize)
		h_lcr |= H_UBRLCR_FIFO;

	spin_lock_irqsave(&port->lock, flags);

	/*
	 * Update the per-port timeout.
	 */
	uart_update_timeout(port, termios->c_cflag, baud);

	/*
	 * Which character status flags are we interested in?
	 */
	port->read_status_mask = RXSTAT_OVERRUN;
	if (termios->c_iflag & INPCK)
		port->read_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;

	/*
	 * Which character status flags should we ignore?
	 */
	port->ignore_status_mask = 0;
	if (termios->c_iflag & IGNPAR)
		port->ignore_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
	if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
		port->ignore_status_mask |= RXSTAT_OVERRUN;

	/*
	 * Ignore all characters if CREAD is not set.
	 */
	if ((termios->c_cflag & CREAD) == 0)
		port->ignore_status_mask |= RXSTAT_DUMMY_READ;

	quot -= 1;

	*CSR_UARTCON = 0;
	*CSR_L_UBRLCR = quot & 0xff;
	*CSR_M_UBRLCR = (quot >> 8) & 0x0f;
	*CSR_H_UBRLCR = h_lcr;
	*CSR_UARTCON = 1;

	spin_unlock_irqrestore(&port->lock, flags);
}

static const char *serial21285_type(struct uart_port *port)
{
	return port->type == PORT_21285 ? "DC21285" : NULL;
}

static void serial21285_release_port(struct uart_port *port)
{
	release_mem_region(port->mapbase, 32);
}

static int serial21285_request_port(struct uart_port *port)
{
	return request_mem_region(port->mapbase, 32, serial21285_name)
			 != NULL ? 0 : -EBUSY;
}

static void serial21285_config_port(struct uart_port *port, int flags)
{
	if (flags & UART_CONFIG_TYPE && serial21285_request_port(port) == 0)
		port->type = PORT_21285;
}

/*
 * verify the new serial_struct (for TIOCSSERIAL).
 */
static int serial21285_verify_port(struct uart_port *port, struct serial_struct *ser)
{
	int ret = 0;
	if (ser->type != PORT_UNKNOWN && ser->type != PORT_21285)
		ret = -EINVAL;
	if (ser->irq <= 0)
		ret = -EINVAL;
	if (ser->baud_base != port->uartclk / 16)
		ret = -EINVAL;
	return ret;
}

static const struct uart_ops serial21285_ops = {
	.tx_empty	= serial21285_tx_empty,
	.get_mctrl	= serial21285_get_mctrl,
	.set_mctrl	= serial21285_set_mctrl,
	.stop_tx	= serial21285_stop_tx,
	.start_tx	= serial21285_start_tx,
	.stop_rx	= serial21285_stop_rx,
	.break_ctl	= serial21285_break_ctl,
	.startup	= serial21285_startup,
	.shutdown	= serial21285_shutdown,
	.set_termios	= serial21285_set_termios,
	.type		= serial21285_type,
	.release_port	= serial21285_release_port,
	.request_port	= serial21285_request_port,
	.config_port	= serial21285_config_port,
	.verify_port	= serial21285_verify_port,
};

static struct uart_port serial21285_port = {
	.mapbase	= 0x42000160,
	.iotype		= UPIO_MEM,
	.irq		= 0,
	.fifosize	= 16,
	.ops		= &serial21285_ops,
	.flags		= UPF_BOOT_AUTOCONF,
};

static void serial21285_setup_ports(void)
{
	serial21285_port.uartclk = mem_fclk_21285 / 4;
}

#ifdef CONFIG_SERIAL_21285_CONSOLE
static void serial21285_console_putchar(struct uart_port *port, unsigned char ch)
{
	while (*CSR_UARTFLG & 0x20)
		barrier();
	*CSR_UARTDR = ch;
}

static void
serial21285_console_write(struct console *co, const char *s,
			  unsigned int count)
{
	uart_console_write(&serial21285_port, s, count, serial21285_console_putchar);
}

static void __init
serial21285_get_options(struct uart_port *port, int *baud,
			int *parity, int *bits)
{
	if (*CSR_UARTCON == 1) {
		unsigned int tmp;

		tmp = *CSR_H_UBRLCR;
		switch (tmp & 0x60) {
		case 0x00:
			*bits = 5;
			break;
		case 0x20:
			*bits = 6;
			break;
		case 0x40:
			*bits = 7;
			break;
		default:
		case 0x60:
			*bits = 8;
			break;
		}

		if (tmp & H_UBRLCR_PARENB) {
			*parity = 'o';
			if (tmp & H_UBRLCR_PAREVN)
				*parity = 'e';
		}

		tmp = *CSR_L_UBRLCR | (*CSR_M_UBRLCR << 8);

		*baud = port->uartclk / (16 * (tmp + 1));
	}
}

static int __init serial21285_console_setup(struct console *co, char *options)
{
	struct uart_port *port = &serial21285_port;
	int baud = 9600;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';

	/*
	 * Check whether an invalid uart number has been specified, and
	 * if so, search for the first available port that does have
	 * console support.
	 */
	if (options)
		uart_parse_options(options, &baud, &parity, &bits, &flow);
	else
		serial21285_get_options(port, &baud, &parity, &bits);

	return uart_set_options(port, co, baud, parity, bits, flow);
}

static struct uart_driver serial21285_reg;

static struct console serial21285_console =
{
	.name		= SERIAL_21285_NAME,
	.write		= serial21285_console_write,
	.device		= uart_console_device,
	.setup		= serial21285_console_setup,
	.flags		= CON_PRINTBUFFER,
	.index		= -1,
	.data		= &serial21285_reg,
};

static int __init rs285_console_init(void)
{
	serial21285_setup_ports();
	register_console(&serial21285_console);
	return 0;
}
console_initcall(rs285_console_init);

#define SERIAL_21285_CONSOLE	&serial21285_console
#else
#define SERIAL_21285_CONSOLE	NULL
#endif

static struct uart_driver serial21285_reg = {
	.owner			= THIS_MODULE,
	.driver_name		= "ttyFB",
	.dev_name		= "ttyFB",
	.major			= SERIAL_21285_MAJOR,
	.minor			= SERIAL_21285_MINOR,
	.nr			= 1,
	.cons			= SERIAL_21285_CONSOLE,
};

static int __init serial21285_init(void)
{
	int ret;

	printk(KERN_INFO "Serial: 21285 driver\n");

	serial21285_setup_ports();

	ret = uart_register_driver(&serial21285_reg);
	if (ret == 0)
		uart_add_one_port(&serial21285_reg, &serial21285_port);

	return ret;
}

static void __exit serial21285_exit(void)
{
	uart_remove_one_port(&serial21285_reg, &serial21285_port);
	uart_unregister_driver(&serial21285_reg);
}

module_init(serial21285_init);
module_exit(serial21285_exit);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Intel Footbridge (21285) serial driver");
MODULE_ALIAS_CHARDEV(SERIAL_21285_MAJOR, SERIAL_21285_MINOR);
Commit	Line	Data
e3b3d0f5	1	// SPDX-License-Identifier: GPL-2.0
1da177e4	2	/*
1da177e4 LT	3	* Driver for the serial port on the 21285 StrongArm-110 core logic chip.
	4	*
	5	* Based on drivers/char/serial.c
1da177e4	6	*/
1da177e4 LT	7	#include <linux/module.h>
	8	#include <linux/tty.h>
	9	#include <linux/ioport.h>
	10	#include <linux/init.h>
	11	#include <linux/console.h>
	12	#include <linux/device.h>
	13	#include <linux/tty_flip.h>
	14	#include <linux/serial_core.h>
	15	#include <linux/serial.h>
99730225	16	#include <linux/io.h>
1da177e4	17
1da177e4 LT	18	#include <asm/irq.h>
1da177e4 LT	19	#include <asm/mach-types.h>
9f97da78	20	#include <asm/system_info.h>
1da177e4	21	#include <asm/hardware/dec21285.h>
a09e64fb	22	#include <mach/hardware.h>
1da177e4 LT	23
	24	#define BAUD_BASE (mem_fclk_21285/64)
	25
	26	#define SERIAL_21285_NAME "ttyFB"
	27	#define SERIAL_21285_MAJOR 204
	28	#define SERIAL_21285_MINOR 4
	29
	30	#define RXSTAT_DUMMY_READ 0x80000000
	31	#define RXSTAT_FRAME (1 << 0)
	32	#define RXSTAT_PARITY (1 << 1)
	33	#define RXSTAT_OVERRUN (1 << 2)
	34	#define RXSTAT_ANYERR (RXSTAT_FRAME\|RXSTAT_PARITY\|RXSTAT_OVERRUN)
	35
	36	#define H_UBRLCR_BREAK (1 << 0)
	37	#define H_UBRLCR_PARENB (1 << 1)
	38	#define H_UBRLCR_PAREVN (1 << 2)
	39	#define H_UBRLCR_STOPB (1 << 3)
	40	#define H_UBRLCR_FIFO (1 << 4)
	41
	42	static const char serial21285_name[] = "Footbridge UART";
	43
293f8995 GKH	44	/*
	45	* We only need 2 bits of data, so instead of creating a whole structure for
	46	* this, use bits of the private_data pointer of the uart port structure.
	47	*/
	48	#define tx_enabled_bit 0
	49	#define rx_enabled_bit 1
	50
	51	static bool is_enabled(struct uart_port *port, int bit)
	52	{
82776f6c	53	unsigned long private_data = (unsigned long )&port->private_data;
293f8995	54
82776f6c	55	if (test_bit(bit, private_data))
293f8995 GKH	56	return true;
	57	return false;
	58	}
	59
	60	static void enable(struct uart_port *port, int bit)
	61	{
82776f6c	62	unsigned long private_data = (unsigned long )&port->private_data;
293f8995	63
82776f6c	64	set_bit(bit, private_data);
293f8995 GKH	65	}
	66
	67	static void disable(struct uart_port *port, int bit)
	68	{
82776f6c	69	unsigned long private_data = (unsigned long )&port->private_data;
293f8995	70
82776f6c	71	clear_bit(bit, private_data);
293f8995 GKH	72	}
	73
	74	#define is_tx_enabled(port) is_enabled(port, tx_enabled_bit)
	75	#define tx_enable(port) enable(port, tx_enabled_bit)
	76	#define tx_disable(port) disable(port, tx_enabled_bit)
	77
	78	#define is_rx_enabled(port) is_enabled(port, rx_enabled_bit)
	79	#define rx_enable(port) enable(port, rx_enabled_bit)
	80	#define rx_disable(port) disable(port, rx_enabled_bit)
1da177e4 LT	81
	82	/*
	83	* The documented expression for selecting the divisor is:
	84	* BAUD_BASE / baud - 1
	85	* However, typically BAUD_BASE is not divisible by baud, so
	86	* we want to select the divisor that gives us the minimum
	87	* error. Therefore, we want:
	88	* int(BAUD_BASE / baud - 0.5) ->
	89	* int(BAUD_BASE / baud - (baud >> 1) / baud) ->
	90	* int((BAUD_BASE - (baud >> 1)) / baud)
	91	*/
	92
b129a8cc	93	static void serial21285_stop_tx(struct uart_port *port)
1da177e4	94	{
293f8995	95	if (is_tx_enabled(port)) {
cc20b900	96	disable_irq_nosync(IRQ_CONTX);
293f8995	97	tx_disable(port);
1da177e4 LT	98	}
	99	}
	100
b129a8cc	101	static void serial21285_start_tx(struct uart_port *port)
1da177e4	102	{
293f8995	103	if (!is_tx_enabled(port)) {
1da177e4	104	enable_irq(IRQ_CONTX);
293f8995	105	tx_enable(port);
1da177e4 LT	106	}
	107	}
	108
	109	static void serial21285_stop_rx(struct uart_port *port)
	110	{
293f8995	111	if (is_rx_enabled(port)) {
cc20b900	112	disable_irq_nosync(IRQ_CONRX);
293f8995	113	rx_disable(port);
1da177e4 LT	114	}
	115	}
	116
7d12e780	117	static irqreturn_t serial21285_rx_chars(int irq, void *dev_id)
1da177e4 LT	118	{
1da177e4 LT	119	struct uart_port *port = dev_id;
1da177e4 LT	120	unsigned int status, ch, flag, rxs, max_count = 256;
	121
	122	status = *CSR_UARTFLG;
	123	while (!(status & 0x10) && max_count--) {
1da177e4 LT	124	ch = *CSR_UARTDR;
	125	flag = TTY_NORMAL;
	126	port->icount.rx++;
	127
	128	rxs = *CSR_RXSTAT \| RXSTAT_DUMMY_READ;
45849282	129	if (unlikely(rxs & RXSTAT_ANYERR)) {
1da177e4 LT	130	if (rxs & RXSTAT_PARITY)
	131	port->icount.parity++;
	132	else if (rxs & RXSTAT_FRAME)
	133	port->icount.frame++;
	134	if (rxs & RXSTAT_OVERRUN)
	135	port->icount.overrun++;
	136
	137	rxs &= port->read_status_mask;
	138
	139	if (rxs & RXSTAT_PARITY)
	140	flag = TTY_PARITY;
	141	else if (rxs & RXSTAT_FRAME)
	142	flag = TTY_FRAME;
	143	}
	144
05ab3014 RK	145	uart_insert_char(port, rxs, RXSTAT_OVERRUN, ch, flag);
05ab3014 RK	146
1da177e4 LT	147	status = *CSR_UARTFLG;
1da177e4 LT	148	}
2e124b4a	149	tty_flip_buffer_push(&port->state->port);
1da177e4 LT	150
	151	return IRQ_HANDLED;
	152	}
	153
7d12e780	154	static irqreturn_t serial21285_tx_chars(int irq, void *dev_id)
1da177e4 LT	155	{
1da177e4 LT	156	struct uart_port *port = dev_id;
ebd2c8f6	157	struct circ_buf *xmit = &port->state->xmit;
1da177e4 LT	158	int count = 256;
	159
	160	if (port->x_char) {
	161	*CSR_UARTDR = port->x_char;
	162	port->icount.tx++;
	163	port->x_char = 0;
	164	goto out;
	165	}
	166	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port)) {
b129a8cc	167	serial21285_stop_tx(port);
1da177e4 LT	168	goto out;
	169	}
	170
	171	do {
	172	*CSR_UARTDR = xmit->buf[xmit->tail];
	173	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
	174	port->icount.tx++;
	175	if (uart_circ_empty(xmit))
	176	break;
	177	} while (--count > 0 && !(*CSR_UARTFLG & 0x20));
	178
	179	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
	180	uart_write_wakeup(port);
	181
	182	if (uart_circ_empty(xmit))
b129a8cc	183	serial21285_stop_tx(port);
1da177e4 LT	184
	185	out:
	186	return IRQ_HANDLED;
	187	}
	188
	189	static unsigned int serial21285_tx_empty(struct uart_port *port)
	190	{
	191	return (*CSR_UARTFLG & 8) ? 0 : TIOCSER_TEMT;
	192	}
	193
	194	/* no modem control lines */
	195	static unsigned int serial21285_get_mctrl(struct uart_port *port)
	196	{
	197	return TIOCM_CAR \| TIOCM_DSR \| TIOCM_CTS;
	198	}
	199
	200	static void serial21285_set_mctrl(struct uart_port *port, unsigned int mctrl)
	201	{
	202	}
	203
	204	static void serial21285_break_ctl(struct uart_port *port, int break_state)
	205	{
	206	unsigned long flags;
	207	unsigned int h_lcr;
	208
	209	spin_lock_irqsave(&port->lock, flags);
	210	h_lcr = *CSR_H_UBRLCR;
	211	if (break_state)
	212	h_lcr \|= H_UBRLCR_BREAK;
	213	else
	214	h_lcr &= ~H_UBRLCR_BREAK;
	215	*CSR_H_UBRLCR = h_lcr;
	216	spin_unlock_irqrestore(&port->lock, flags);
	217	}
	218
	219	static int serial21285_startup(struct uart_port *port)
	220	{
	221	int ret;
	222
293f8995 GKH	223	tx_enable(port);
293f8995 GKH	224	rx_enable(port);
1da177e4 LT	225
	226	ret = request_irq(IRQ_CONRX, serial21285_rx_chars, 0,
	227	serial21285_name, port);
	228	if (ret == 0) {
	229	ret = request_irq(IRQ_CONTX, serial21285_tx_chars, 0,
	230	serial21285_name, port);
	231	if (ret)
	232	free_irq(IRQ_CONRX, port);
	233	}
	234
	235	return ret;
	236	}
	237
	238	static void serial21285_shutdown(struct uart_port *port)
	239	{
	240	free_irq(IRQ_CONTX, port);
	241	free_irq(IRQ_CONRX, port);
	242	}
	243
	244	static void
606d099c	245	serial21285_set_termios(struct uart_port port, struct ktermios termios,
bec5b814	246	const struct ktermios *old)
1da177e4 LT	247	{
1da177e4 LT	248	unsigned long flags;
eab4f5af	249	unsigned int baud, quot, h_lcr, b;
1da177e4 LT	250
	251	/*
	252	* We don't support modem control lines.
	253	*/
	254	termios->c_cflag &= ~(HUPCL \| CRTSCTS \| CMSPAR);
	255	termios->c_cflag \|= CLOCAL;
	256
	257	/*
	258	* We don't support BREAK character recognition.
	259	*/
	260	termios->c_iflag &= ~(IGNBRK \| BRKINT);
	261
	262	/*
	263	* Ask the core to calculate the divisor for us.
	264	*/
	265	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
	266	quot = uart_get_divisor(port, baud);
eab4f5af AC	267	b = port->uartclk / (16 * quot);
eab4f5af AC	268	tty_termios_encode_baud_rate(termios, b, b);
2f65baff	269
1da177e4 LT	270	switch (termios->c_cflag & CSIZE) {
	271	case CS5:
	272	h_lcr = 0x00;
	273	break;
	274	case CS6:
	275	h_lcr = 0x20;
	276	break;
	277	case CS7:
	278	h_lcr = 0x40;
	279	break;
	280	default: /* CS8 */
	281	h_lcr = 0x60;
	282	break;
	283	}
	284
	285	if (termios->c_cflag & CSTOPB)
	286	h_lcr \|= H_UBRLCR_STOPB;
	287	if (termios->c_cflag & PARENB) {
	288	h_lcr \|= H_UBRLCR_PARENB;
	289	if (!(termios->c_cflag & PARODD))
	290	h_lcr \|= H_UBRLCR_PAREVN;
	291	}
	292
	293	if (port->fifosize)
	294	h_lcr \|= H_UBRLCR_FIFO;
	295
	296	spin_lock_irqsave(&port->lock, flags);
	297
	298	/*
	299	* Update the per-port timeout.
	300	*/
	301	uart_update_timeout(port, termios->c_cflag, baud);
	302
	303	/*
	304	* Which character status flags are we interested in?
	305	*/
	306	port->read_status_mask = RXSTAT_OVERRUN;
	307	if (termios->c_iflag & INPCK)
	308	port->read_status_mask \|= RXSTAT_FRAME \| RXSTAT_PARITY;
	309
	310	/*
	311	* Which character status flags should we ignore?
	312	*/
	313	port->ignore_status_mask = 0;
	314	if (termios->c_iflag & IGNPAR)
	315	port->ignore_status_mask \|= RXSTAT_FRAME \| RXSTAT_PARITY;
	316	if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
	317	port->ignore_status_mask \|= RXSTAT_OVERRUN;
	318
	319	/*
	320	* Ignore all characters if CREAD is not set.
	321	*/
	322	if ((termios->c_cflag & CREAD) == 0)
	323	port->ignore_status_mask \|= RXSTAT_DUMMY_READ;
	324
	325	quot -= 1;
	326
	327	*CSR_UARTCON = 0;
	328	*CSR_L_UBRLCR = quot & 0xff;
	329	*CSR_M_UBRLCR = (quot >> 8) & 0x0f;
	330	*CSR_H_UBRLCR = h_lcr;
	331	*CSR_UARTCON = 1;
	332
	333	spin_unlock_irqrestore(&port->lock, flags);
334	}
335
336	static const char serial21285_type(struct uart_port port)
337	{
338	return port->type == PORT_21285 ? "DC21285" : NULL;
339	}
340
341	static void serial21285_release_port(struct uart_port *port)
342	{
343	release_mem_region(port->mapbase, 32);
344	}
345
346	static int serial21285_request_port(struct uart_port *port)
347	{
348	return request_mem_region(port->mapbase, 32, serial21285_name)
349	!= NULL ? 0 : -EBUSY;
350	}
351
352	static void serial21285_config_port(struct uart_port *port, int flags)
353	{
354	if (flags & UART_CONFIG_TYPE && serial21285_request_port(port) == 0)
355	port->type = PORT_21285;
356	}
357
358	/*
359	* verify the new serial_struct (for TIOCSSERIAL).
360	*/
361	static int serial21285_verify_port(struct uart_port port, struct serial_struct ser)
362	{
363	int ret = 0;
364	if (ser->type != PORT_UNKNOWN && ser->type != PORT_21285)
365	ret = -EINVAL;
d4e33fac	366	if (ser->irq <= 0)
1da177e4 LT	367	ret = -EINVAL;
	368	if (ser->baud_base != port->uartclk / 16)
	369	ret = -EINVAL;
	370	return ret;
	371	}
	372
ccb47a33	373	static const struct uart_ops serial21285_ops = {
1da177e4 LT	374	.tx_empty = serial21285_tx_empty,
	375	.get_mctrl = serial21285_get_mctrl,
	376	.set_mctrl = serial21285_set_mctrl,
	377	.stop_tx = serial21285_stop_tx,
	378	.start_tx = serial21285_start_tx,
	379	.stop_rx = serial21285_stop_rx,
1da177e4 LT	380	.break_ctl = serial21285_break_ctl,
	381	.startup = serial21285_startup,
	382	.shutdown = serial21285_shutdown,
	383	.set_termios = serial21285_set_termios,
	384	.type = serial21285_type,
	385	.release_port = serial21285_release_port,
	386	.request_port = serial21285_request_port,
	387	.config_port = serial21285_config_port,
	388	.verify_port = serial21285_verify_port,
	389	};
	390
	391	static struct uart_port serial21285_port = {
	392	.mapbase = 0x42000160,
9b4a1617	393	.iotype = UPIO_MEM,
d4e33fac	394	.irq = 0,
1da177e4 LT	395	.fifosize = 16,
1da177e4 LT	396	.ops = &serial21285_ops,
ce8337cb	397	.flags = UPF_BOOT_AUTOCONF,
1da177e4 LT	398	};
	399
	400	static void serial21285_setup_ports(void)
	401	{
	402	serial21285_port.uartclk = mem_fclk_21285 / 4;
	403	}
	404
	405	#ifdef CONFIG_SERIAL_21285_CONSOLE
3f8bab17	406	static void serial21285_console_putchar(struct uart_port *port, unsigned char ch)
d358788f RK	407	{
	408	while (*CSR_UARTFLG & 0x20)
	409	barrier();
	410	*CSR_UARTDR = ch;
	411	}
1da177e4 LT	412
	413	static void
	414	serial21285_console_write(struct console co, const char s,
	415	unsigned int count)
	416	{
d358788f	417	uart_console_write(&serial21285_port, s, count, serial21285_console_putchar);
1da177e4 LT	418	}
	419
	420	static void __init
	421	serial21285_get_options(struct uart_port port, int baud,
	422	int parity, int bits)
	423	{
	424	if (*CSR_UARTCON == 1) {
	425	unsigned int tmp;
	426
	427	tmp = *CSR_H_UBRLCR;
	428	switch (tmp & 0x60) {
	429	case 0x00:
	430	*bits = 5;
	431	break;
	432	case 0x20:
	433	*bits = 6;
	434	break;
	435	case 0x40:
	436	*bits = 7;
	437	break;
	438	default:
	439	case 0x60:
	440	*bits = 8;
	441	break;
	442	}
	443
	444	if (tmp & H_UBRLCR_PARENB) {
	445	*parity = 'o';
	446	if (tmp & H_UBRLCR_PAREVN)
	447	*parity = 'e';
	448	}
	449
	450	tmp = CSR_L_UBRLCR \| (CSR_M_UBRLCR << 8);
	451
	452	baud = port->uartclk / (16 (tmp + 1));
	453	}
	454	}
	455
	456	static int __init serial21285_console_setup(struct console co, char options)
	457	{
	458	struct uart_port *port = &serial21285_port;
	459	int baud = 9600;
	460	int bits = 8;
	461	int parity = 'n';
	462	int flow = 'n';
	463
1da177e4 LT	464	/*
	465	* Check whether an invalid uart number has been specified, and
	466	* if so, search for the first available port that does have
	467	* console support.
	468	*/
	469	if (options)
	470	uart_parse_options(options, &baud, &parity, &bits, &flow);
	471	else
	472	serial21285_get_options(port, &baud, &parity, &bits);
	473
	474	return uart_set_options(port, co, baud, parity, bits, flow);
	475	}
	476
2d93486c	477	static struct uart_driver serial21285_reg;
1da177e4 LT	478
	479	static struct console serial21285_console =
	480	{
	481	.name = SERIAL_21285_NAME,
	482	.write = serial21285_console_write,
	483	.device = uart_console_device,
	484	.setup = serial21285_console_setup,
	485	.flags = CON_PRINTBUFFER,
	486	.index = -1,
	487	.data = &serial21285_reg,
	488	};
	489
	490	static int __init rs285_console_init(void)
	491	{
	492	serial21285_setup_ports();
	493	register_console(&serial21285_console);
	494	return 0;
	495	}
	496	console_initcall(rs285_console_init);
	497
	498	#define SERIAL_21285_CONSOLE &serial21285_console
	499	#else
	500	#define SERIAL_21285_CONSOLE NULL
	501	#endif
	502
	503	static struct uart_driver serial21285_reg = {
	504	.owner = THIS_MODULE,
	505	.driver_name = "ttyFB",
	506	.dev_name = "ttyFB",
1da177e4 LT	507	.major = SERIAL_21285_MAJOR,
	508	.minor = SERIAL_21285_MINOR,
	509	.nr = 1,
	510	.cons = SERIAL_21285_CONSOLE,
	511	};
	512
	513	static int __init serial21285_init(void)
	514	{
	515	int ret;
	516
d87a6d95	517	printk(KERN_INFO "Serial: 21285 driver\n");
1da177e4 LT	518
	519	serial21285_setup_ports();
	520
	521	ret = uart_register_driver(&serial21285_reg);
	522	if (ret == 0)
	523	uart_add_one_port(&serial21285_reg, &serial21285_port);
	524
	525	return ret;
	526	}
	527
	528	static void __exit serial21285_exit(void)
	529	{
	530	uart_remove_one_port(&serial21285_reg, &serial21285_port);
	531	uart_unregister_driver(&serial21285_reg);
	532	}
	533
	534	module_init(serial21285_init);
	535	module_exit(serial21285_exit);
	536
	537	MODULE_LICENSE("GPL");
d87a6d95	538	MODULE_DESCRIPTION("Intel Footbridge (21285) serial driver");
1da177e4	539	MODULE_ALIAS_CHARDEV(SERIAL_21285_MAJOR, SERIAL_21285_MINOR);