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net/mlx4_core: Reduce harmless SRIOV error message to debug level
[linux-2.6-block.git] / drivers / tty / rocket.c
CommitLineData
1da177e4
LT		 1/*
2 * RocketPort device driver for Linux
3 *
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Kernel Synchronization:
25 *
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
28 * are not used.
29 *
30 * Critical data:
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
37 *
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
40 */
41
42/****** Defines ******/
1da177e4
LT		 43#define ROCKET_PARANOIA_CHECK
44#define ROCKET_DISABLE_SIMUSAGE
45
46#undef ROCKET_SOFT_FLOW
47#undef ROCKET_DEBUG_OPEN
48#undef ROCKET_DEBUG_INTR
49#undef ROCKET_DEBUG_WRITE
50#undef ROCKET_DEBUG_FLOW
51#undef ROCKET_DEBUG_THROTTLE
52#undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53#undef ROCKET_DEBUG_RECEIVE
54#undef ROCKET_DEBUG_HANGUP
55#undef REV_PCI_ORDER
56#undef ROCKET_DEBUG_IO
57
37c44b52 58#define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
1da177e4
LT		 59
60/****** Kernel includes ******/
61
1da177e4
LT		 62#include <linux/module.h>
63#include <linux/errno.h>
64#include <linux/major.h>
65#include <linux/kernel.h>
66#include <linux/signal.h>
67#include <linux/slab.h>
68#include <linux/mm.h>
69#include <linux/sched.h>
70#include <linux/timer.h>
71#include <linux/interrupt.h>
72#include <linux/tty.h>
73#include <linux/tty_driver.h>
74#include <linux/tty_flip.h>
44b7d1b3 75#include <linux/serial.h>
1da177e4
LT		 76#include <linux/string.h>
77#include <linux/fcntl.h>
78#include <linux/ptrace.h>
69f545ea 79#include <linux/mutex.h>
1da177e4
LT		 80#include <linux/ioport.h>
81#include <linux/delay.h>
8cf5a8c5 82#include <linux/completion.h>
1da177e4
LT		 83#include <linux/wait.h>
84#include <linux/pci.h>
44b7d1b3 85#include <linux/uaccess.h>
60063497 86#include <linux/atomic.h>
457fb605 87#include <asm/unaligned.h>
1da177e4
LT		 88#include <linux/bitops.h>
89#include <linux/spinlock.h>
1da177e4
LT		 90#include <linux/init.h>
91
92/****** RocketPort includes ******/
93
94#include "rocket_int.h"
95#include "rocket.h"
96
97#define ROCKET_VERSION "2.09"
98#define ROCKET_DATE "12-June-2003"
99
100/****** RocketPort Local Variables ******/
101
40565f19
JS		 102static void rp_do_poll(unsigned long dummy);
103
1da177e4
LT		 104static struct tty_driver *rocket_driver;
105
106static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
108};
109
110static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113static atomic_t rp_num_ports_open; /* Number of serial ports open */
40565f19 114static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
1da177e4
LT		 115
116static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117static unsigned long board2;
118static unsigned long board3;
119static unsigned long board4;
120static unsigned long controller;
90ab5ee9 121static bool support_low_speed;
1da177e4
LT		 122static unsigned long modem1;
123static unsigned long modem2;
124static unsigned long modem3;
125static unsigned long modem4;
126static unsigned long pc104_1[8];
127static unsigned long pc104_2[8];
128static unsigned long pc104_3[8];
129static unsigned long pc104_4[8];
130static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
131
132static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133static unsigned long rcktpt_io_addr[NUM_BOARDS];
134static int rcktpt_type[NUM_BOARDS];
135static int is_PCI[NUM_BOARDS];
136static rocketModel_t rocketModel[NUM_BOARDS];
137static int max_board;
31f35939 138static const struct tty_port_operations rocket_port_ops;
1da177e4
LT		 139
140/*
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
144 */
145
146static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
147 AIOP_INTR_BIT_0,
148 AIOP_INTR_BIT_1,
149 AIOP_INTR_BIT_2,
150 AIOP_INTR_BIT_3
151};
152
416187ca 153#ifdef CONFIG_PCI
1da177e4
LT		 154static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
155 UPCI_AIOP_INTR_BIT_0,
156 UPCI_AIOP_INTR_BIT_1,
157 UPCI_AIOP_INTR_BIT_2,
158 UPCI_AIOP_INTR_BIT_3
159};
416187ca 160#endif
1da177e4 161
f15313bf
AB		 162static Byte_t RData[RDATASIZE] = {
163 0x00, 0x09, 0xf6, 0x82,
164 0x02, 0x09, 0x86, 0xfb,
165 0x04, 0x09, 0x00, 0x0a,
166 0x06, 0x09, 0x01, 0x0a,
167 0x08, 0x09, 0x8a, 0x13,
168 0x0a, 0x09, 0xc5, 0x11,
169 0x0c, 0x09, 0x86, 0x85,
170 0x0e, 0x09, 0x20, 0x0a,
171 0x10, 0x09, 0x21, 0x0a,
172 0x12, 0x09, 0x41, 0xff,
173 0x14, 0x09, 0x82, 0x00,
174 0x16, 0x09, 0x82, 0x7b,
175 0x18, 0x09, 0x8a, 0x7d,
176 0x1a, 0x09, 0x88, 0x81,
177 0x1c, 0x09, 0x86, 0x7a,
178 0x1e, 0x09, 0x84, 0x81,
179 0x20, 0x09, 0x82, 0x7c,
180 0x22, 0x09, 0x0a, 0x0a
181};
182
183static Byte_t RRegData[RREGDATASIZE] = {
184 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
185 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
186 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
187 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
188 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
189 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
190 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
191 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
192 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
193 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
194 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
195 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
196 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
197};
198
199static CONTROLLER_T sController[CTL_SIZE] = {
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
206 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
207 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
208};
209
210static Byte_t sBitMapClrTbl[8] = {
211 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
212};
213
214static Byte_t sBitMapSetTbl[8] = {
215 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
216};
217
218static int sClockPrescale = 0x14;
219
1da177e4
LT		 220/*
221 * Line number is the ttySIx number (x), the Minor number. We
222 * assign them sequentially, starting at zero. The following
223 * array keeps track of the line number assigned to a given board/aiop/channel.
224 */
225static unsigned char lineNumbers[MAX_RP_PORTS];
226static unsigned long nextLineNumber;
227
228/***** RocketPort Static Prototypes *********/
229static int __init init_ISA(int i);
230static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
231static void rp_flush_buffer(struct tty_struct *tty);
1da177e4
LT		 232static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
233static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
234static void rp_start(struct tty_struct *tty);
f15313bf
AB		 235static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
236 int ChanNum);
237static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
238static void sFlushRxFIFO(CHANNEL_T * ChP);
239static void sFlushTxFIFO(CHANNEL_T * ChP);
240static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
241static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
242static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
243static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
244static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
f15313bf
AB		 245static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
246 ByteIO_t * AiopIOList, int AiopIOListSize,
247 int IRQNum, Byte_t Frequency, int PeriodicOnly);
248static int sReadAiopID(ByteIO_t io);
249static int sReadAiopNumChan(WordIO_t io);
1da177e4 250
1da177e4
LT		 251MODULE_AUTHOR("Theodore Ts'o");
252MODULE_DESCRIPTION("Comtrol RocketPort driver");
253module_param(board1, ulong, 0);
254MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
255module_param(board2, ulong, 0);
256MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
257module_param(board3, ulong, 0);
258MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
259module_param(board4, ulong, 0);
260MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
261module_param(controller, ulong, 0);
262MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
263module_param(support_low_speed, bool, 0);
264MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
265module_param(modem1, ulong, 0);
266MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
267module_param(modem2, ulong, 0);
268MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
269module_param(modem3, ulong, 0);
270MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
271module_param(modem4, ulong, 0);
272MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
273module_param_array(pc104_1, ulong, NULL, 0);
274MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
275module_param_array(pc104_2, ulong, NULL, 0);
276MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
277module_param_array(pc104_3, ulong, NULL, 0);
278MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
279module_param_array(pc104_4, ulong, NULL, 0);
280MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
281
d269cdd0 282static int rp_init(void);
1da177e4
LT		 283static void rp_cleanup_module(void);
284
285module_init(rp_init);
286module_exit(rp_cleanup_module);
287
1da177e4 288
1da177e4 289MODULE_LICENSE("Dual BSD/GPL");
1da177e4
LT		 290
291/*************************************************************************/
292/* Module code starts here */
293
294static inline int rocket_paranoia_check(struct r_port *info,
295 const char *routine)
296{
297#ifdef ROCKET_PARANOIA_CHECK
298 if (!info)
299 return 1;
300 if (info->magic != RPORT_MAGIC) {
68562b79
JS		 301 printk(KERN_WARNING "Warning: bad magic number for rocketport "
302 "struct in %s\n", routine);
1da177e4
LT		 303 return 1;
304 }
305#endif
306 return 0;
307}
308
309
310/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
311 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
312 * tty layer.
313 */
2e124b4a
JS		 314static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
315 unsigned int ChanStatus)
1da177e4
LT		 316{
317 unsigned int CharNStat;
cc44a817
PF		 318 int ToRecv, wRecv, space;
319 unsigned char *cbuf;
1da177e4
LT		 320
321 ToRecv = sGetRxCnt(cp);
1da177e4 322#ifdef ROCKET_DEBUG_INTR
68562b79 323 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
1da177e4 324#endif
cc44a817
PF		 325 if (ToRecv == 0)
326 return;
33f0f88f 327
1da177e4
LT		 328 /*
329 * if status indicates there are errored characters in the
330 * FIFO, then enter status mode (a word in FIFO holds
331 * character and status).
332 */
333 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
334 if (!(ChanStatus & STATMODE)) {
335#ifdef ROCKET_DEBUG_RECEIVE
68562b79 336 printk(KERN_INFO "Entering STATMODE...\n");
1da177e4
LT		 337#endif
338 ChanStatus |= STATMODE;
339 sEnRxStatusMode(cp);
340 }
341 }
342
343 /*
344 * if we previously entered status mode, then read down the
345 * FIFO one word at a time, pulling apart the character and
346 * the status. Update error counters depending on status
347 */
348 if (ChanStatus & STATMODE) {
349#ifdef ROCKET_DEBUG_RECEIVE
68562b79
JS		 350 printk(KERN_INFO "Ignore %x, read %x...\n",
351 info->ignore_status_mask, info->read_status_mask);
1da177e4
LT		 352#endif
353 while (ToRecv) {
cc44a817
PF		 354 char flag;
355
1da177e4
LT		 356 CharNStat = sInW(sGetTxRxDataIO(cp));
357#ifdef ROCKET_DEBUG_RECEIVE
68562b79 358 printk(KERN_INFO "%x...\n", CharNStat);
1da177e4
LT		 359#endif
360 if (CharNStat & STMBREAKH)
361 CharNStat &= ~(STMFRAMEH | STMPARITYH);
362 if (CharNStat & info->ignore_status_mask) {
363 ToRecv--;
364 continue;
365 }
366 CharNStat &= info->read_status_mask;
367 if (CharNStat & STMBREAKH)
cc44a817 368 flag = TTY_BREAK;
1da177e4 369 else if (CharNStat & STMPARITYH)
cc44a817 370 flag = TTY_PARITY;
1da177e4 371 else if (CharNStat & STMFRAMEH)
cc44a817 372 flag = TTY_FRAME;
1da177e4 373 else if (CharNStat & STMRCVROVRH)
cc44a817 374 flag = TTY_OVERRUN;
1da177e4 375 else
cc44a817 376 flag = TTY_NORMAL;
92a19f9c
JS		 377 tty_insert_flip_char(&info->port, CharNStat & 0xff,
378 flag);
1da177e4
LT		 379 ToRecv--;
380 }
381
382 /*
383 * after we've emptied the FIFO in status mode, turn
384 * status mode back off
385 */
386 if (sGetRxCnt(cp) == 0) {
387#ifdef ROCKET_DEBUG_RECEIVE
388 printk(KERN_INFO "Status mode off.\n");
389#endif
390 sDisRxStatusMode(cp);
391 }
392 } else {
393 /*
394 * we aren't in status mode, so read down the FIFO two
395 * characters at time by doing repeated word IO
396 * transfer.
397 */
2f693357 398 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
cc44a817
PF		 399 if (space < ToRecv) {
400#ifdef ROCKET_DEBUG_RECEIVE
401 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
402#endif
403 if (space <= 0)
404 return;
405 ToRecv = space;
406 }
1da177e4
LT		 407 wRecv = ToRecv >> 1;
408 if (wRecv)
409 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
410 if (ToRecv & 1)
411 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
1da177e4
LT		 412 }
413 /* Push the data up to the tty layer */
2e124b4a 414 tty_flip_buffer_push(&info->port);
1da177e4
LT		 415}
416
417/*
418 * Serial port transmit data function. Called from the timer polling loop as a
419 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
420 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
421 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
422 */
423static void rp_do_transmit(struct r_port *info)
424{
425 int c;
426 CHANNEL_t *cp = &info->channel;
427 struct tty_struct *tty;
428 unsigned long flags;
429
430#ifdef ROCKET_DEBUG_INTR
68562b79 431 printk(KERN_DEBUG "%s\n", __func__);
1da177e4
LT		 432#endif
433 if (!info)
434 return;
47b01b3a
AC		 435 tty = tty_port_tty_get(&info->port);
436
437 if (tty == NULL) {
438 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
1da177e4
LT		 439 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
440 return;
441 }
442
443 spin_lock_irqsave(&info->slock, flags);
1da177e4
LT		 444 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
445
446 /* Loop sending data to FIFO until done or FIFO full */
447 while (1) {
ee797069 448 if (tty->stopped)
1da177e4 449 break;
709107fc
HH		 450 c = min(info->xmit_fifo_room, info->xmit_cnt);
451 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
1da177e4
LT		 452 if (c <= 0 || info->xmit_fifo_room <= 0)
453 break;
454 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
455 if (c & 1)
456 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
457 info->xmit_tail += c;
458 info->xmit_tail &= XMIT_BUF_SIZE - 1;
459 info->xmit_cnt -= c;
460 info->xmit_fifo_room -= c;
461#ifdef ROCKET_DEBUG_INTR
68562b79 462 printk(KERN_INFO "tx %d chars...\n", c);
1da177e4
LT		 463#endif
464 }
465
466 if (info->xmit_cnt == 0)
467 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
468
469 if (info->xmit_cnt < WAKEUP_CHARS) {
470 tty_wakeup(tty);
1da177e4
LT		 471#ifdef ROCKETPORT_HAVE_POLL_WAIT
472 wake_up_interruptible(&tty->poll_wait);
473#endif
474 }
475
476 spin_unlock_irqrestore(&info->slock, flags);
47b01b3a 477 tty_kref_put(tty);
1da177e4
LT		 478
479#ifdef ROCKET_DEBUG_INTR
68562b79 480 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
1da177e4
LT		 481 info->xmit_tail, info->xmit_fifo_room);
482#endif
483}
484
485/*
486 * Called when a serial port signals it has read data in it's RX FIFO.
487 * It checks what interrupts are pending and services them, including
488 * receiving serial data.
489 */
490static void rp_handle_port(struct r_port *info)
491{
492 CHANNEL_t *cp;
1da177e4
LT		 493 unsigned int IntMask, ChanStatus;
494
495 if (!info)
496 return;
497
d41861ca 498 if (!tty_port_initialized(&info->port)) {
68562b79
JS		 499 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
500 "info->flags & NOT_INIT\n");
1da177e4
LT		 501 return;
502 }
2e124b4a 503
1da177e4 504 cp = &info->channel;
1da177e4
LT		 505
506 IntMask = sGetChanIntID(cp) & info->intmask;
507#ifdef ROCKET_DEBUG_INTR
68562b79 508 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
1da177e4
LT		 509#endif
510 ChanStatus = sGetChanStatus(cp);
511 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
2e124b4a 512 rp_do_receive(info, cp, ChanStatus);
1da177e4
LT		 513 }
514 if (IntMask & DELTA_CD) { /* CD change */
515#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
68562b79 516 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
1da177e4
LT		 517 (ChanStatus & CD_ACT) ? "on" : "off");
518#endif
519 if (!(ChanStatus & CD_ACT) && info->cd_status) {
520#ifdef ROCKET_DEBUG_HANGUP
521 printk(KERN_INFO "CD drop, calling hangup.\n");
522#endif
aa27a094 523 tty_port_tty_hangup(&info->port, false);
1da177e4
LT		 524 }
525 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
e60a1084 526 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 527 }
528#ifdef ROCKET_DEBUG_INTR
529 if (IntMask & DELTA_CTS) { /* CTS change */
530 printk(KERN_INFO "CTS change...\n");
531 }
532 if (IntMask & DELTA_DSR) { /* DSR change */
533 printk(KERN_INFO "DSR change...\n");
534 }
535#endif
536}
537
538/*
539 * The top level polling routine. Repeats every 1/100 HZ (10ms).
540 */
541static void rp_do_poll(unsigned long dummy)
542{
543 CONTROLLER_t *ctlp;
6c0286b1
JS		 544 int ctrl, aiop, ch, line;
545 unsigned int xmitmask, i;
1da177e4
LT		 546 unsigned int CtlMask;
547 unsigned char AiopMask;
548 Word_t bit;
549
550 /* Walk through all the boards (ctrl's) */
551 for (ctrl = 0; ctrl < max_board; ctrl++) {
552 if (rcktpt_io_addr[ctrl] <= 0)
553 continue;
554
555 /* Get a ptr to the board's control struct */
556 ctlp = sCtlNumToCtlPtr(ctrl);
557
3a4fa0a2 558 /* Get the interrupt status from the board */
1da177e4
LT		 559#ifdef CONFIG_PCI
560 if (ctlp->BusType == isPCI)
561 CtlMask = sPCIGetControllerIntStatus(ctlp);
562 else
563#endif
564 CtlMask = sGetControllerIntStatus(ctlp);
565
566 /* Check if any AIOP read bits are set */
567 for (aiop = 0; CtlMask; aiop++) {
568 bit = ctlp->AiopIntrBits[aiop];
569 if (CtlMask & bit) {
570 CtlMask &= ~bit;
571 AiopMask = sGetAiopIntStatus(ctlp, aiop);
572
573 /* Check if any port read bits are set */
574 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
575 if (AiopMask & 1) {
576
577 /* Get the line number (/dev/ttyRx number). */
578 /* Read the data from the port. */
579 line = GetLineNumber(ctrl, aiop, ch);
580 rp_handle_port(rp_table[line]);
581 }
582 }
583 }
584 }
585
586 xmitmask = xmit_flags[ctrl];
587
588 /*
589 * xmit_flags contains bit-significant flags, indicating there is data
590 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
591 * 1, ... (32 total possible). The variable i has the aiop and ch
592 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
593 */
594 if (xmitmask) {
595 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
596 if (xmitmask & (1 << i)) {
597 aiop = (i & 0x18) >> 3;
598 ch = i & 0x07;
599 line = GetLineNumber(ctrl, aiop, ch);
600 rp_do_transmit(rp_table[line]);
601 }
602 }
603 }
604 }
605
606 /*
607 * Reset the timer so we get called at the next clock tick (10ms).
608 */
609 if (atomic_read(&rp_num_ports_open))
610 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
611}
612
613/*
614 * Initializes the r_port structure for a port, as well as enabling the port on
615 * the board.
616 * Inputs: board, aiop, chan numbers
617 */
06ed48b7
JL		 618static void __init
619init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
1da177e4
LT		 620{
621 unsigned rocketMode;
622 struct r_port *info;
623 int line;
624 CONTROLLER_T *ctlp;
625
626 /* Get the next available line number */
627 line = SetLineNumber(board, aiop, chan);
628
629 ctlp = sCtlNumToCtlPtr(board);
630
631 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
dd00cc48 632 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
1da177e4 633 if (!info) {
68562b79
JS		 634 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
635 line);
1da177e4
LT		 636 return;
637 }
1da177e4
LT		 638
639 info->magic = RPORT_MAGIC;
640 info->line = line;
641 info->ctlp = ctlp;
642 info->board = board;
643 info->aiop = aiop;
644 info->chan = chan;
31f35939
AC		 645 tty_port_init(&info->port);
646 info->port.ops = &rocket_port_ops;
1da177e4
LT		 647 info->flags &= ~ROCKET_MODE_MASK;
648 switch (pc104[board][line]) {
649 case 422:
650 info->flags |= ROCKET_MODE_RS422;
651 break;
652 case 485:
653 info->flags |= ROCKET_MODE_RS485;
654 break;
655 case 232:
656 default:
657 info->flags |= ROCKET_MODE_RS232;
658 break;
659 }
660
661 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
662 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
68562b79
JS		 663 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
664 board, aiop, chan);
191c5f10 665 tty_port_destroy(&info->port);
1da177e4
LT		 666 kfree(info);
667 return;
668 }
669
670 rocketMode = info->flags & ROCKET_MODE_MASK;
671
672 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
673 sEnRTSToggle(&info->channel);
674 else
675 sDisRTSToggle(&info->channel);
676
677 if (ctlp->boardType == ROCKET_TYPE_PC104) {
678 switch (rocketMode) {
679 case ROCKET_MODE_RS485:
680 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
681 break;
682 case ROCKET_MODE_RS422:
683 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
684 break;
685 case ROCKET_MODE_RS232:
686 default:
687 if (info->flags & ROCKET_RTS_TOGGLE)
688 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
689 else
690 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
691 break;
692 }
693 }
694 spin_lock_init(&info->slock);
69f545ea 695 mutex_init(&info->write_mtx);
1da177e4 696 rp_table[line] = info;
734cc178
JS		 697 tty_port_register_device(&info->port, rocket_driver, line,
698 pci_dev ? &pci_dev->dev : NULL);
1da177e4
LT		 699}
700
701/*
702 * Configures a rocketport port according to its termio settings. Called from
703 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
704 */
47b01b3a 705static void configure_r_port(struct tty_struct *tty, struct r_port *info,
606d099c 706 struct ktermios *old_termios)
1da177e4
LT		 707{
708 unsigned cflag;
709 unsigned long flags;
710 unsigned rocketMode;
711 int bits, baud, divisor;
712 CHANNEL_t *cp;
adc8d746 713 struct ktermios *t = &tty->termios;
1da177e4 714
1da177e4 715 cp = &info->channel;
6df3526b 716 cflag = t->c_cflag;
1da177e4
LT		 717
718 /* Byte size and parity */
719 if ((cflag & CSIZE) == CS8) {
720 sSetData8(cp);
721 bits = 10;
722 } else {
723 sSetData7(cp);
724 bits = 9;
725 }
726 if (cflag & CSTOPB) {
727 sSetStop2(cp);
728 bits++;
729 } else {
730 sSetStop1(cp);
731 }
732
733 if (cflag & PARENB) {
734 sEnParity(cp);
735 bits++;
736 if (cflag & PARODD) {
737 sSetOddParity(cp);
738 } else {
739 sSetEvenParity(cp);
740 }
741 } else {
742 sDisParity(cp);
743 }
744
745 /* baud rate */
47b01b3a 746 baud = tty_get_baud_rate(tty);
1da177e4
LT		 747 if (!baud)
748 baud = 9600;
749 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
750 if ((divisor >= 8192 || divisor < 0) && old_termios) {
6df3526b 751 baud = tty_termios_baud_rate(old_termios);
1da177e4
LT		 752 if (!baud)
753 baud = 9600;
754 divisor = (rp_baud_base[info->board] / baud) - 1;
755 }
756 if (divisor >= 8192 || divisor < 0) {
757 baud = 9600;
758 divisor = (rp_baud_base[info->board] / baud) - 1;
759 }
760 info->cps = baud / bits;
761 sSetBaud(cp, divisor);
762
6df3526b 763 /* FIXME: Should really back compute a baud rate from the divisor */
47b01b3a 764 tty_encode_baud_rate(tty, baud, baud);
6df3526b 765
1da177e4
LT		 766 if (cflag & CRTSCTS) {
767 info->intmask |= DELTA_CTS;
768 sEnCTSFlowCtl(cp);
769 } else {
770 info->intmask &= ~DELTA_CTS;
771 sDisCTSFlowCtl(cp);
772 }
773 if (cflag & CLOCAL) {
774 info->intmask &= ~DELTA_CD;
775 } else {
776 spin_lock_irqsave(&info->slock, flags);
777 if (sGetChanStatus(cp) & CD_ACT)
778 info->cd_status = 1;
779 else
780 info->cd_status = 0;
781 info->intmask |= DELTA_CD;
782 spin_unlock_irqrestore(&info->slock, flags);
783 }
784
785 /*
786 * Handle software flow control in the board
787 */
788#ifdef ROCKET_SOFT_FLOW
47b01b3a 789 if (I_IXON(tty)) {
1da177e4 790 sEnTxSoftFlowCtl(cp);
47b01b3a 791 if (I_IXANY(tty)) {
1da177e4
LT		 792 sEnIXANY(cp);
793 } else {
794 sDisIXANY(cp);
795 }
47b01b3a
AC		 796 sSetTxXONChar(cp, START_CHAR(tty));
797 sSetTxXOFFChar(cp, STOP_CHAR(tty));
1da177e4
LT		 798 } else {
799 sDisTxSoftFlowCtl(cp);
800 sDisIXANY(cp);
801 sClrTxXOFF(cp);
802 }
803#endif
804
805 /*
806 * Set up ignore/read mask words
807 */
808 info->read_status_mask = STMRCVROVRH | 0xFF;
47b01b3a 809 if (I_INPCK(tty))
1da177e4 810 info->read_status_mask |= STMFRAMEH | STMPARITYH;
47b01b3a 811 if (I_BRKINT(tty) || I_PARMRK(tty))
1da177e4
LT		 812 info->read_status_mask |= STMBREAKH;
813
814 /*
815 * Characters to ignore
816 */
817 info->ignore_status_mask = 0;
47b01b3a 818 if (I_IGNPAR(tty))
1da177e4 819 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
47b01b3a 820 if (I_IGNBRK(tty)) {
1da177e4
LT		 821 info->ignore_status_mask |= STMBREAKH;
822 /*
823 * If we're ignoring parity and break indicators,
824 * ignore overruns too. (For real raw support).
825 */
47b01b3a 826 if (I_IGNPAR(tty))
1da177e4
LT		 827 info->ignore_status_mask |= STMRCVROVRH;
828 }
829
830 rocketMode = info->flags & ROCKET_MODE_MASK;
831
832 if ((info->flags & ROCKET_RTS_TOGGLE)
833 || (rocketMode == ROCKET_MODE_RS485))
834 sEnRTSToggle(cp);
835 else
836 sDisRTSToggle(cp);
837
838 sSetRTS(&info->channel);
839
840 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
841 switch (rocketMode) {
842 case ROCKET_MODE_RS485:
843 sSetInterfaceMode(cp, InterfaceModeRS485);
844 break;
845 case ROCKET_MODE_RS422:
846 sSetInterfaceMode(cp, InterfaceModeRS422);
847 break;
848 case ROCKET_MODE_RS232:
849 default:
850 if (info->flags & ROCKET_RTS_TOGGLE)
851 sSetInterfaceMode(cp, InterfaceModeRS232T);
852 else
853 sSetInterfaceMode(cp, InterfaceModeRS232);
854 break;
855 }
856 }
857}
858
31f35939
AC		 859static int carrier_raised(struct tty_port *port)
860{
861 struct r_port *info = container_of(port, struct r_port, port);
862 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
863}
864
fcc8ac18 865static void dtr_rts(struct tty_port *port, int on)
5d951fb4
AC		 866{
867 struct r_port *info = container_of(port, struct r_port, port);
fcc8ac18
AC		 868 if (on) {
869 sSetDTR(&info->channel);
870 sSetRTS(&info->channel);
871 } else {
872 sClrDTR(&info->channel);
873 sClrRTS(&info->channel);
874 }
5d951fb4
AC		 875}
876
1da177e4
LT		 877/*
878 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
879 * port's r_port struct. Initializes the port hardware.
880 */
881static int rp_open(struct tty_struct *tty, struct file *filp)
882{
883 struct r_port *info;
fba85e01 884 struct tty_port *port;
410235fd 885 int retval;
1da177e4
LT		 886 CHANNEL_t *cp;
887 unsigned long page;
888
410235fd
JS		 889 info = rp_table[tty->index];
890 if (info == NULL)
1da177e4 891 return -ENXIO;
fba85e01
AC		 892 port = &info->port;
893
1da177e4
LT		 894 page = __get_free_page(GFP_KERNEL);
895 if (!page)
896 return -ENOMEM;
897
1da177e4
LT		 898 /*
899 * We must not sleep from here until the port is marked fully in use.
900 */
901 if (info->xmit_buf)
902 free_page(page);
903 else
904 info->xmit_buf = (unsigned char *) page;
905
906 tty->driver_data = info;
fba85e01 907 tty_port_tty_set(port, tty);
1da177e4 908
fba85e01 909 if (port->count++ == 0) {
1da177e4
LT		 910 atomic_inc(&rp_num_ports_open);
911
912#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 913 printk(KERN_INFO "rocket mod++ = %d...\n",
914 atomic_read(&rp_num_ports_open));
1da177e4
LT		 915#endif
916 }
917#ifdef ROCKET_DEBUG_OPEN
e60a1084 918 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
1da177e4
LT		 919#endif
920
921 /*
922 * Info->count is now 1; so it's safe to sleep now.
923 */
d41861ca 924 if (!tty_port_initialized(port)) {
1da177e4
LT		 925 cp = &info->channel;
926 sSetRxTrigger(cp, TRIG_1);
927 if (sGetChanStatus(cp) & CD_ACT)
928 info->cd_status = 1;
929 else
930 info->cd_status = 0;
931 sDisRxStatusMode(cp);
932 sFlushRxFIFO(cp);
933 sFlushTxFIFO(cp);
934
935 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
936 sSetRxTrigger(cp, TRIG_1);
937
938 sGetChanStatus(cp);
939 sDisRxStatusMode(cp);
940 sClrTxXOFF(cp);
941
942 sDisCTSFlowCtl(cp);
943 sDisTxSoftFlowCtl(cp);
944
945 sEnRxFIFO(cp);
946 sEnTransmit(cp);
947
d41861ca 948 tty_port_set_initialized(&info->port, 1);
1da177e4
LT		 949
950 /*
951 * Set up the tty->alt_speed kludge
952 */
953 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
47b01b3a 954 tty->alt_speed = 57600;
1da177e4 955 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
47b01b3a 956 tty->alt_speed = 115200;
1da177e4 957 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
47b01b3a 958 tty->alt_speed = 230400;
1da177e4 959 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
47b01b3a 960 tty->alt_speed = 460800;
1da177e4 961
47b01b3a 962 configure_r_port(tty, info, NULL);
9db276f8 963 if (C_BAUD(tty)) {
1da177e4
LT		 964 sSetDTR(cp);
965 sSetRTS(cp);
966 }
967 }
968 /* Starts (or resets) the maint polling loop */
969 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
970
fba85e01 971 retval = tty_port_block_til_ready(port, tty, filp);
1da177e4
LT		 972 if (retval) {
973#ifdef ROCKET_DEBUG_OPEN
974 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
975#endif
976 return retval;
977 }
978 return 0;
979}
980
981/*
e60a1084 982 * Exception handler that closes a serial port. info->port.count is considered critical.
1da177e4
LT		 983 */
984static void rp_close(struct tty_struct *tty, struct file *filp)
985{
c9f19e96 986 struct r_port *info = tty->driver_data;
c1314a49 987 struct tty_port *port = &info->port;
1da177e4
LT		 988 int timeout;
989 CHANNEL_t *cp;
990
991 if (rocket_paranoia_check(info, "rp_close"))
992 return;
993
994#ifdef ROCKET_DEBUG_OPEN
e60a1084 995 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1da177e4
LT		 996#endif
997
fba85e01 998 if (tty_port_close_start(port, tty, filp) == 0)
1da177e4 999 return;
1da177e4 1000
417b6e0e 1001 mutex_lock(&port->mutex);
1da177e4 1002 cp = &info->channel;
1da177e4
LT		 1003 /*
1004 * Before we drop DTR, make sure the UART transmitter
1005 * has completely drained; this is especially
1006 * important if there is a transmit FIFO!
1007 */
1008 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1009 if (timeout == 0)
1010 timeout = 1;
1011 rp_wait_until_sent(tty, timeout);
1012 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1013
1014 sDisTransmit(cp);
1015 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1016 sDisCTSFlowCtl(cp);
1017 sDisTxSoftFlowCtl(cp);
1018 sClrTxXOFF(cp);
1019 sFlushRxFIFO(cp);
1020 sFlushTxFIFO(cp);
1021 sClrRTS(cp);
1022 if (C_HUPCL(tty))
1023 sClrDTR(cp);
1024
f6de0c98 1025 rp_flush_buffer(tty);
1da177e4
LT		 1026
1027 tty_ldisc_flush(tty);
1028
1029 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1030
fba85e01
AC		 1031 /* We can't yet use tty_port_close_end as the buffer handling in this
1032 driver is a bit different to the usual */
1033
c1314a49
AC		 1034 if (port->blocked_open) {
1035 if (port->close_delay) {
1036 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1da177e4 1037 }
c1314a49 1038 wake_up_interruptible(&port->open_wait);
1da177e4
LT		 1039 } else {
1040 if (info->xmit_buf) {
1041 free_page((unsigned long) info->xmit_buf);
1042 info->xmit_buf = NULL;
1043 }
1044 }
417b6e0e 1045 spin_lock_irq(&port->lock);
1da177e4 1046 tty->closing = 0;
417b6e0e 1047 spin_unlock_irq(&port->lock);
d41861ca 1048 tty_port_set_initialized(port, 0);
807c8d81 1049 tty_port_set_active(port, 0);
417b6e0e 1050 mutex_unlock(&port->mutex);
fba85e01 1051 tty_port_tty_set(port, NULL);
417b6e0e 1052
1da177e4
LT		 1053 atomic_dec(&rp_num_ports_open);
1054
1055#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 1056 printk(KERN_INFO "rocket mod-- = %d...\n",
1057 atomic_read(&rp_num_ports_open));
1da177e4
LT		 1058 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1059#endif
1060
1061}
1062
1063static void rp_set_termios(struct tty_struct *tty,
606d099c 1064 struct ktermios *old_termios)
1da177e4 1065{
c9f19e96 1066 struct r_port *info = tty->driver_data;
1da177e4
LT		 1067 CHANNEL_t *cp;
1068 unsigned cflag;
1069
1070 if (rocket_paranoia_check(info, "rp_set_termios"))
1071 return;
1072
adc8d746 1073 cflag = tty->termios.c_cflag;
1da177e4 1074
1da177e4
LT		 1075 /*
1076 * This driver doesn't support CS5 or CS6
1077 */
1078 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
adc8d746 1079 tty->termios.c_cflag =
1da177e4 1080 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
6df3526b 1081 /* Or CMSPAR */
adc8d746 1082 tty->termios.c_cflag &= ~CMSPAR;
1da177e4 1083
47b01b3a 1084 configure_r_port(tty, info, old_termios);
1da177e4
LT		 1085
1086 cp = &info->channel;
1087
1088 /* Handle transition to B0 status */
9db276f8 1089 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
1da177e4
LT		 1090 sClrDTR(cp);
1091 sClrRTS(cp);
1092 }
1093
1094 /* Handle transition away from B0 status */
9db276f8 1095 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
ee797069 1096 sSetRTS(cp);
1da177e4
LT		 1097 sSetDTR(cp);
1098 }
1099
9db276f8 1100 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty))
1da177e4 1101 rp_start(tty);
1da177e4
LT		 1102}
1103
9e98966c 1104static int rp_break(struct tty_struct *tty, int break_state)
1da177e4 1105{
c9f19e96 1106 struct r_port *info = tty->driver_data;
1da177e4
LT		 1107 unsigned long flags;
1108
1109 if (rocket_paranoia_check(info, "rp_break"))
9e98966c 1110 return -EINVAL;
1da177e4
LT		 1111
1112 spin_lock_irqsave(&info->slock, flags);
1113 if (break_state == -1)
1114 sSendBreak(&info->channel);
1115 else
1116 sClrBreak(&info->channel);
1117 spin_unlock_irqrestore(&info->slock, flags);
9e98966c 1118 return 0;
1da177e4
LT		 1119}
1120
1121/*
1122 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1123 * the UPCI boards was added, it was decided to make this a function because
1124 * the macro was getting too complicated. All cases except the first one
1125 * (UPCIRingInd) are taken directly from the original macro.
1126 */
1127static int sGetChanRI(CHANNEL_T * ChP)
1128{
1129 CONTROLLER_t *CtlP = ChP->CtlP;
1130 int ChanNum = ChP->ChanNum;
1131 int RingInd = 0;
1132
1133 if (CtlP->UPCIRingInd)
1134 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1135 else if (CtlP->AltChanRingIndicator)
1136 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1137 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1138 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1139
1140 return RingInd;
1141}
1142
1143/********************************************************************************************/
1144/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1145
1146/*
1147 * Returns the state of the serial modem control lines. These next 2 functions
1148 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1149 */
60b33c13 1150static int rp_tiocmget(struct tty_struct *tty)
1da177e4 1151{
c9f19e96 1152 struct r_port *info = tty->driver_data;
1da177e4
LT		 1153 unsigned int control, result, ChanStatus;
1154
1155 ChanStatus = sGetChanStatusLo(&info->channel);
1156 control = info->channel.TxControl[3];
1157 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1158 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1159 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1160 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1161 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1162 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1163
1164 return result;
1165}
1166
1167/*
1168 * Sets the modem control lines
1169 */
20b9d177
AC		 1170static int rp_tiocmset(struct tty_struct *tty,
1171 unsigned int set, unsigned int clear)
1da177e4 1172{
c9f19e96 1173 struct r_port *info = tty->driver_data;
1da177e4
LT		 1174
1175 if (set & TIOCM_RTS)
1176 info->channel.TxControl[3] |= SET_RTS;
1177 if (set & TIOCM_DTR)
1178 info->channel.TxControl[3] |= SET_DTR;
1179 if (clear & TIOCM_RTS)
1180 info->channel.TxControl[3] &= ~SET_RTS;
1181 if (clear & TIOCM_DTR)
1182 info->channel.TxControl[3] &= ~SET_DTR;
1183
457fb605 1184 out32(info->channel.IndexAddr, info->channel.TxControl);
1da177e4
LT		 1185 return 0;
1186}
1187
1188static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1189{
1190 struct rocket_config tmp;
1191
1da177e4 1192 memset(&tmp, 0, sizeof (tmp));
417b6e0e 1193 mutex_lock(&info->port.mutex);
1da177e4
LT		 1194 tmp.line = info->line;
1195 tmp.flags = info->flags;
44b7d1b3
AC		 1196 tmp.close_delay = info->port.close_delay;
1197 tmp.closing_wait = info->port.closing_wait;
1da177e4 1198 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
417b6e0e 1199 mutex_unlock(&info->port.mutex);
1da177e4
LT		 1200
1201 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1202 return -EFAULT;
1203 return 0;
1204}
1205
47b01b3a
AC		 1206static int set_config(struct tty_struct *tty, struct r_port *info,
1207 struct rocket_config __user *new_info)
1da177e4
LT		 1208{
1209 struct rocket_config new_serial;
1210
1211 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1212 return -EFAULT;
1213
417b6e0e 1214 mutex_lock(&info->port.mutex);
1da177e4
LT		 1215 if (!capable(CAP_SYS_ADMIN))
1216 {
417b6e0e
AC		 1217 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1218 mutex_unlock(&info->port.mutex);
1da177e4 1219 return -EPERM;
417b6e0e 1220 }
1da177e4 1221 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
47b01b3a 1222 configure_r_port(tty, info, NULL);
49bf7eaf 1223 mutex_unlock(&info->port.mutex);
1da177e4
LT		 1224 return 0;
1225 }
1226
1227 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
44b7d1b3
AC		 1228 info->port.close_delay = new_serial.close_delay;
1229 info->port.closing_wait = new_serial.closing_wait;
1da177e4
LT		 1230
1231 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
47b01b3a 1232 tty->alt_speed = 57600;
1da177e4 1233 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
47b01b3a 1234 tty->alt_speed = 115200;
1da177e4 1235 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
47b01b3a 1236 tty->alt_speed = 230400;
1da177e4 1237 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
47b01b3a 1238 tty->alt_speed = 460800;
417b6e0e 1239 mutex_unlock(&info->port.mutex);
1da177e4 1240
47b01b3a 1241 configure_r_port(tty, info, NULL);
1da177e4
LT		 1242 return 0;
1243}
1244
1245/*
1246 * This function fills in a rocket_ports struct with information
1247 * about what boards/ports are in the system. This info is passed
1248 * to user space. See setrocket.c where the info is used to create
1249 * the /dev/ttyRx ports.
1250 */
1251static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1252{
1253 struct rocket_ports tmp;
1254 int board;
1255
1da177e4
LT		 1256 memset(&tmp, 0, sizeof (tmp));
1257 tmp.tty_major = rocket_driver->major;
1258
1259 for (board = 0; board < 4; board++) {
1260 tmp.rocketModel[board].model = rocketModel[board].model;
1261 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1262 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1263 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1264 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1265 }
1266 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1267 return -EFAULT;
1268 return 0;
1269}
1270
1271static int reset_rm2(struct r_port *info, void __user *arg)
1272{
1273 int reset;
1274
4129a645
AC		 1275 if (!capable(CAP_SYS_ADMIN))
1276 return -EPERM;
1277
1da177e4
LT		 1278 if (copy_from_user(&reset, arg, sizeof (int)))
1279 return -EFAULT;
1280 if (reset)
1281 reset = 1;
1282
1283 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1284 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1285 return -EINVAL;
1286
1287 if (info->ctlp->BusType == isISA)
1288 sModemReset(info->ctlp, info->chan, reset);
1289 else
1290 sPCIModemReset(info->ctlp, info->chan, reset);
1291
1292 return 0;
1293}
1294
1295static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1296{
1297 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1298 return -EFAULT;
1299 return 0;
1300}
1301
1302/* IOCTL call handler into the driver */
6caa76b7 1303static int rp_ioctl(struct tty_struct *tty,
1da177e4
LT		 1304 unsigned int cmd, unsigned long arg)
1305{
c9f19e96 1306 struct r_port *info = tty->driver_data;
1da177e4 1307 void __user *argp = (void __user *)arg;
bdf183aa 1308 int ret = 0;
1da177e4
LT		 1309
1310 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1311 return -ENXIO;
1312
1313 switch (cmd) {
1314 case RCKP_GET_STRUCT:
1315 if (copy_to_user(argp, info, sizeof (struct r_port)))
bdf183aa
AC		 1316 ret = -EFAULT;
1317 break;
1da177e4 1318 case RCKP_GET_CONFIG:
bdf183aa
AC		 1319 ret = get_config(info, argp);
1320 break;
1da177e4 1321 case RCKP_SET_CONFIG:
47b01b3a 1322 ret = set_config(tty, info, argp);
bdf183aa 1323 break;
1da177e4 1324 case RCKP_GET_PORTS:
bdf183aa
AC		 1325 ret = get_ports(info, argp);
1326 break;
1da177e4 1327 case RCKP_RESET_RM2:
bdf183aa
AC		 1328 ret = reset_rm2(info, argp);
1329 break;
1da177e4 1330 case RCKP_GET_VERSION:
bdf183aa
AC		 1331 ret = get_version(info, argp);
1332 break;
1da177e4 1333 default:
bdf183aa 1334 ret = -ENOIOCTLCMD;
1da177e4 1335 }
bdf183aa 1336 return ret;
1da177e4
LT		 1337}
1338
1339static void rp_send_xchar(struct tty_struct *tty, char ch)
1340{
c9f19e96 1341 struct r_port *info = tty->driver_data;
1da177e4
LT		 1342 CHANNEL_t *cp;
1343
1344 if (rocket_paranoia_check(info, "rp_send_xchar"))
1345 return;
1346
1347 cp = &info->channel;
1348 if (sGetTxCnt(cp))
1349 sWriteTxPrioByte(cp, ch);
1350 else
1351 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1352}
1353
1354static void rp_throttle(struct tty_struct *tty)
1355{
c9f19e96 1356 struct r_port *info = tty->driver_data;
1da177e4
LT		 1357
1358#ifdef ROCKET_DEBUG_THROTTLE
fdfb719e 1359 printk(KERN_INFO "throttle %s ....\n", tty->name);
1da177e4
LT		 1360#endif
1361
1362 if (rocket_paranoia_check(info, "rp_throttle"))
1363 return;
1364
1da177e4
LT		 1365 if (I_IXOFF(tty))
1366 rp_send_xchar(tty, STOP_CHAR(tty));
1367
1368 sClrRTS(&info->channel);
1369}
1370
1371static void rp_unthrottle(struct tty_struct *tty)
1372{
c9f19e96 1373 struct r_port *info = tty->driver_data;
1da177e4 1374#ifdef ROCKET_DEBUG_THROTTLE
fdfb719e 1375 printk(KERN_INFO "unthrottle %s ....\n", tty->name);
1da177e4
LT		 1376#endif
1377
e5f50fbe 1378 if (rocket_paranoia_check(info, "rp_unthrottle"))
1da177e4
LT		 1379 return;
1380
1da177e4
LT		 1381 if (I_IXOFF(tty))
1382 rp_send_xchar(tty, START_CHAR(tty));
1383
1384 sSetRTS(&info->channel);
1385}
1386
1387/*
1388 * ------------------------------------------------------------
1389 * rp_stop() and rp_start()
1390 *
1391 * This routines are called before setting or resetting tty->stopped.
1392 * They enable or disable transmitter interrupts, as necessary.
1393 * ------------------------------------------------------------
1394 */
1395static void rp_stop(struct tty_struct *tty)
1396{
c9f19e96 1397 struct r_port *info = tty->driver_data;
1da177e4
LT		 1398
1399#ifdef ROCKET_DEBUG_FLOW
1400 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1401 info->xmit_cnt, info->xmit_fifo_room);
1402#endif
1403
1404 if (rocket_paranoia_check(info, "rp_stop"))
1405 return;
1406
1407 if (sGetTxCnt(&info->channel))
1408 sDisTransmit(&info->channel);
1409}
1410
1411static void rp_start(struct tty_struct *tty)
1412{
c9f19e96 1413 struct r_port *info = tty->driver_data;
1da177e4
LT		 1414
1415#ifdef ROCKET_DEBUG_FLOW
1416 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1417 info->xmit_cnt, info->xmit_fifo_room);
1418#endif
1419
1420 if (rocket_paranoia_check(info, "rp_stop"))
1421 return;
1422
1423 sEnTransmit(&info->channel);
1424 set_bit((info->aiop * 8) + info->chan,
1425 (void *) &xmit_flags[info->board]);
1426}
1427
1428/*
1429 * rp_wait_until_sent() --- wait until the transmitter is empty
1430 */
1431static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1432{
c9f19e96 1433 struct r_port *info = tty->driver_data;
1da177e4
LT		 1434 CHANNEL_t *cp;
1435 unsigned long orig_jiffies;
1436 int check_time, exit_time;
1437 int txcnt;
1438
1439 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1440 return;
1441
1442 cp = &info->channel;
1443
1444 orig_jiffies = jiffies;
1445#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
e5f50fbe 1446 printk(KERN_INFO "In %s(%d) (jiff=%lu)...\n", __func__, timeout,
1da177e4 1447 jiffies);
68562b79 1448 printk(KERN_INFO "cps=%d...\n", info->cps);
1da177e4
LT		 1449#endif
1450 while (1) {
1451 txcnt = sGetTxCnt(cp);
1452 if (!txcnt) {
1453 if (sGetChanStatusLo(cp) & TXSHRMT)
1454 break;
1455 check_time = (HZ / info->cps) / 5;
1456 } else {
1457 check_time = HZ * txcnt / info->cps;
1458 }
1459 if (timeout) {
1460 exit_time = orig_jiffies + timeout - jiffies;
1461 if (exit_time <= 0)
1462 break;
1463 if (exit_time < check_time)
1464 check_time = exit_time;
1465 }
1466 if (check_time == 0)
1467 check_time = 1;
1468#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
68562b79
JS		 1469 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1470 jiffies, check_time);
1da177e4
LT		 1471#endif
1472 msleep_interruptible(jiffies_to_msecs(check_time));
1473 if (signal_pending(current))
1474 break;
1475 }
cc0a8fbb 1476 __set_current_state(TASK_RUNNING);
1da177e4
LT		 1477#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1478 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1479#endif
1480}
1481
1482/*
1483 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1484 */
1485static void rp_hangup(struct tty_struct *tty)
1486{
1487 CHANNEL_t *cp;
c9f19e96 1488 struct r_port *info = tty->driver_data;
417b6e0e 1489 unsigned long flags;
1da177e4
LT		 1490
1491 if (rocket_paranoia_check(info, "rp_hangup"))
1492 return;
1493
1494#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
68562b79 1495 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1da177e4
LT		 1496#endif
1497 rp_flush_buffer(tty);
417b6e0e 1498 spin_lock_irqsave(&info->port.lock, flags);
e60a1084 1499 if (info->port.count)
1da177e4
LT		 1500 atomic_dec(&rp_num_ports_open);
1501 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
417b6e0e 1502 spin_unlock_irqrestore(&info->port.lock, flags);
1da177e4 1503
fba85e01 1504 tty_port_hangup(&info->port);
1da177e4
LT		 1505
1506 cp = &info->channel;
1507 sDisRxFIFO(cp);
1508 sDisTransmit(cp);
1509 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1510 sDisCTSFlowCtl(cp);
1511 sDisTxSoftFlowCtl(cp);
1512 sClrTxXOFF(cp);
d41861ca 1513 tty_port_set_initialized(&info->port, 0);
1da177e4 1514
e60a1084 1515 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1516}
1517
1518/*
1519 * Exception handler - write char routine. The RocketPort driver uses a
1520 * double-buffering strategy, with the twist that if the in-memory CPU
1521 * buffer is empty, and there's space in the transmit FIFO, the
1522 * writing routines will write directly to transmit FIFO.
1523 * Write buffer and counters protected by spinlocks
1524 */
bbbbb96f 1525static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 1526{
c9f19e96 1527 struct r_port *info = tty->driver_data;
1da177e4
LT		 1528 CHANNEL_t *cp;
1529 unsigned long flags;
1530
1531 if (rocket_paranoia_check(info, "rp_put_char"))
bbbbb96f 1532 return 0;
1da177e4 1533
69f545ea
MK		 1534 /*
1535 * Grab the port write mutex, locking out other processes that try to
1536 * write to this port
1537 */
1538 mutex_lock(&info->write_mtx);
1da177e4
LT		 1539
1540#ifdef ROCKET_DEBUG_WRITE
68562b79 1541 printk(KERN_INFO "rp_put_char %c...\n", ch);
1da177e4
LT		 1542#endif
1543
1544 spin_lock_irqsave(&info->slock, flags);
1545 cp = &info->channel;
1546
ee797069 1547 if (!tty->stopped && info->xmit_fifo_room == 0)
1da177e4
LT		 1548 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1549
ee797069 1550 if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1da177e4
LT		 1551 info->xmit_buf[info->xmit_head++] = ch;
1552 info->xmit_head &= XMIT_BUF_SIZE - 1;
1553 info->xmit_cnt++;
1554 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1555 } else {
1556 sOutB(sGetTxRxDataIO(cp), ch);
1557 info->xmit_fifo_room--;
1558 }
1559 spin_unlock_irqrestore(&info->slock, flags);
69f545ea 1560 mutex_unlock(&info->write_mtx);
bbbbb96f 1561 return 1;
1da177e4
LT		 1562}
1563
1564/*
1565 * Exception handler - write routine, called when user app writes to the device.
69f545ea 1566 * A per port write mutex is used to protect from another process writing to
1da177e4
LT		 1567 * this port at the same time. This other process could be running on the other CPU
1568 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1569 * Spinlocks protect the info xmit members.
1570 */
1571static int rp_write(struct tty_struct *tty,
1572 const unsigned char *buf, int count)
1573{
c9f19e96 1574 struct r_port *info = tty->driver_data;
1da177e4
LT		 1575 CHANNEL_t *cp;
1576 const unsigned char *b;
1577 int c, retval = 0;
1578 unsigned long flags;
1579
1580 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1581 return 0;
1582
1e3e8d91
SS		 1583 if (mutex_lock_interruptible(&info->write_mtx))
1584 return -ERESTARTSYS;
1da177e4
LT		 1585
1586#ifdef ROCKET_DEBUG_WRITE
68562b79 1587 printk(KERN_INFO "rp_write %d chars...\n", count);
1da177e4
LT		 1588#endif
1589 cp = &info->channel;
1590
ee797069 1591 if (!tty->stopped && info->xmit_fifo_room < count)
1da177e4
LT		 1592 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1593
1594 /*
1595 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1596 * into FIFO. Use the write queue for temp storage.
1597 */
ee797069 1598 if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1da177e4
LT		 1599 c = min(count, info->xmit_fifo_room);
1600 b = buf;
1601
1602 /* Push data into FIFO, 2 bytes at a time */
1603 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1604
1605 /* If there is a byte remaining, write it */
1606 if (c & 1)
1607 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1608
1609 retval += c;
1610 buf += c;
1611 count -= c;
1612
1613 spin_lock_irqsave(&info->slock, flags);
1614 info->xmit_fifo_room -= c;
1615 spin_unlock_irqrestore(&info->slock, flags);
1616 }
1617
1618 /* If count is zero, we wrote it all and are done */
1619 if (!count)
1620 goto end;
1621
1622 /* Write remaining data into the port's xmit_buf */
1623 while (1) {
47b01b3a 1624 /* Hung up ? */
807c8d81 1625 if (!tty_port_active(&info->port))
1da177e4 1626 goto end;
709107fc
HH		 1627 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1628 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1da177e4
LT		 1629 if (c <= 0)
1630 break;
1631
1632 b = buf;
1633 memcpy(info->xmit_buf + info->xmit_head, b, c);
1634
1635 spin_lock_irqsave(&info->slock, flags);
1636 info->xmit_head =
1637 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1638 info->xmit_cnt += c;
1639 spin_unlock_irqrestore(&info->slock, flags);
1640
1641 buf += c;
1642 count -= c;
1643 retval += c;
1644 }
1645
ee797069 1646 if ((retval > 0) && !tty->stopped)
1da177e4
LT		 1647 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1648
1649end:
1650 if (info->xmit_cnt < WAKEUP_CHARS) {
1651 tty_wakeup(tty);
1da177e4
LT		 1652#ifdef ROCKETPORT_HAVE_POLL_WAIT
1653 wake_up_interruptible(&tty->poll_wait);
1654#endif
1655 }
69f545ea 1656 mutex_unlock(&info->write_mtx);
1da177e4
LT		 1657 return retval;
1658}
1659
1660/*
1661 * Return the number of characters that can be sent. We estimate
1662 * only using the in-memory transmit buffer only, and ignore the
1663 * potential space in the transmit FIFO.
1664 */
1665static int rp_write_room(struct tty_struct *tty)
1666{
c9f19e96 1667 struct r_port *info = tty->driver_data;
1da177e4
LT		 1668 int ret;
1669
1670 if (rocket_paranoia_check(info, "rp_write_room"))
1671 return 0;
1672
1673 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1674 if (ret < 0)
1675 ret = 0;
1676#ifdef ROCKET_DEBUG_WRITE
68562b79 1677 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1da177e4
LT		 1678#endif
1679 return ret;
1680}
1681
1682/*
1683 * Return the number of characters in the buffer. Again, this only
1684 * counts those characters in the in-memory transmit buffer.
1685 */
1686static int rp_chars_in_buffer(struct tty_struct *tty)
1687{
c9f19e96 1688 struct r_port *info = tty->driver_data;
1da177e4
LT		 1689
1690 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1691 return 0;
1692
1da177e4 1693#ifdef ROCKET_DEBUG_WRITE
68562b79 1694 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1da177e4
LT		 1695#endif
1696 return info->xmit_cnt;
1697}
1698
1699/*
1700 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1701 * r_port struct for the port. Note that spinlock are used to protect info members,
1702 * do not call this function if the spinlock is already held.
1703 */
1704static void rp_flush_buffer(struct tty_struct *tty)
1705{
c9f19e96 1706 struct r_port *info = tty->driver_data;
1da177e4
LT		 1707 CHANNEL_t *cp;
1708 unsigned long flags;
1709
1710 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1711 return;
1712
1713 spin_lock_irqsave(&info->slock, flags);
1714 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1715 spin_unlock_irqrestore(&info->slock, flags);
1716
1da177e4
LT		 1717#ifdef ROCKETPORT_HAVE_POLL_WAIT
1718 wake_up_interruptible(&tty->poll_wait);
1719#endif
1720 tty_wakeup(tty);
1721
1722 cp = &info->channel;
1723 sFlushTxFIFO(cp);
1724}
1725
1726#ifdef CONFIG_PCI
1727
311df74a 1728static const struct pci_device_id rocket_pci_ids[] = {
b9d42395
KC		 1729 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1730 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1731 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1732 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1733 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1734 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1735 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1736 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1737 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1738 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1739 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1740 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1741 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1742 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1743 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1744 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1745 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1746 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1747 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1748 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1749 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1750 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
8d5916d3
JS		 1751 { }
1752};
1753MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1754
416187ca
JS		 1755/* Resets the speaker controller on RocketModem II and III devices */
1756static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
1757{
1758 ByteIO_t addr;
1759
1760 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
1761 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
1762 addr = CtlP->AiopIO[0] + 0x4F;
1763 sOutB(addr, 0);
1764 }
1765
1766 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
1767 if ((model == MODEL_UPCI_RM3_8PORT)
1768 || (model == MODEL_UPCI_RM3_4PORT)) {
1769 addr = CtlP->AiopIO[0] + 0x88;
1770 sOutB(addr, 0);
1771 }
1772}
1773
1774/***************************************************************************
1775Function: sPCIInitController
1776Purpose: Initialization of controller global registers and controller
1777 structure.
1778Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
1779 IRQNum,Frequency,PeriodicOnly)
1780 CONTROLLER_T *CtlP; Ptr to controller structure
1781 int CtlNum; Controller number
1782 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
1783 This list must be in the order the AIOPs will be found on the
1784 controller. Once an AIOP in the list is not found, it is
1785 assumed that there are no more AIOPs on the controller.
1786 int AiopIOListSize; Number of addresses in AiopIOList
1787 int IRQNum; Interrupt Request number. Can be any of the following:
1788 0: Disable global interrupts
1789 3: IRQ 3
1790 4: IRQ 4
1791 5: IRQ 5
1792 9: IRQ 9
1793 10: IRQ 10
1794 11: IRQ 11
1795 12: IRQ 12
1796 15: IRQ 15
1797 Byte_t Frequency: A flag identifying the frequency
1798 of the periodic interrupt, can be any one of the following:
1799 FREQ_DIS - periodic interrupt disabled
1800 FREQ_137HZ - 137 Hertz
1801 FREQ_69HZ - 69 Hertz
1802 FREQ_34HZ - 34 Hertz
1803 FREQ_17HZ - 17 Hertz
1804 FREQ_9HZ - 9 Hertz
1805 FREQ_4HZ - 4 Hertz
1806 If IRQNum is set to 0 the Frequency parameter is
1807 overidden, it is forced to a value of FREQ_DIS.
1808 int PeriodicOnly: 1 if all interrupts except the periodic
1809 interrupt are to be blocked.
1810 0 is both the periodic interrupt and
1811 other channel interrupts are allowed.
1812 If IRQNum is set to 0 the PeriodicOnly parameter is
1813 overidden, it is forced to a value of 0.
1814Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
1815 initialization failed.
1816
1817Comments:
1818 If periodic interrupts are to be disabled but AIOP interrupts
1819 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1820
1821 If interrupts are to be completely disabled set IRQNum to 0.
1822
1823 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1824 invalid combination.
1825
1826 This function performs initialization of global interrupt modes,
1827 but it does not actually enable global interrupts. To enable
1828 and disable global interrupts use functions sEnGlobalInt() and
1829 sDisGlobalInt(). Enabling of global interrupts is normally not
1830 done until all other initializations are complete.
1831
1832 Even if interrupts are globally enabled, they must also be
1833 individually enabled for each channel that is to generate
1834 interrupts.
1835
1836Warnings: No range checking on any of the parameters is done.
1837
1838 No context switches are allowed while executing this function.
1839
1840 After this function all AIOPs on the controller are disabled,
1841 they can be enabled with sEnAiop().
1842*/
1843static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
1844 ByteIO_t * AiopIOList, int AiopIOListSize,
1845 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
1846 int PeriodicOnly, int altChanRingIndicator,
1847 int UPCIRingInd)
1848{
1849 int i;
1850 ByteIO_t io;
1851
1852 CtlP->AltChanRingIndicator = altChanRingIndicator;
1853 CtlP->UPCIRingInd = UPCIRingInd;
1854 CtlP->CtlNum = CtlNum;
1855 CtlP->CtlID = CTLID_0001; /* controller release 1 */
1856 CtlP->BusType = isPCI; /* controller release 1 */
1857
1858 if (ConfigIO) {
1859 CtlP->isUPCI = 1;
1860 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
1861 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
1862 CtlP->AiopIntrBits = upci_aiop_intr_bits;
1863 } else {
1864 CtlP->isUPCI = 0;
1865 CtlP->PCIIO =
1866 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
1867 CtlP->AiopIntrBits = aiop_intr_bits;
1868 }
1869
1870 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
1871 /* Init AIOPs */
1872 CtlP->NumAiop = 0;
1873 for (i = 0; i < AiopIOListSize; i++) {
1874 io = AiopIOList[i];
1875 CtlP->AiopIO[i] = (WordIO_t) io;
1876 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
1877
1878 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
1879 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
1880 break; /* done looking for AIOPs */
1881
1882 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
1883 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
1884 sOutB(io + _INDX_DATA, sClockPrescale);
1885 CtlP->NumAiop++; /* bump count of AIOPs */
1886 }
1887
1888 if (CtlP->NumAiop == 0)
1889 return (-1);
1890 else
1891 return (CtlP->NumAiop);
1892}
1893
1da177e4
LT		 1894/*
1895 * Called when a PCI card is found. Retrieves and stores model information,
1896 * init's aiopic and serial port hardware.
1897 * Inputs: i is the board number (0-n)
1898 */
f15313bf 1899static __init int register_PCI(int i, struct pci_dev *dev)
1da177e4
LT		 1900{
1901 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1902 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1da177e4
LT		 1903 CONTROLLER_t *ctlp;
1904
1905 int fast_clock = 0;
1906 int altChanRingIndicator = 0;
1907 int ports_per_aiop = 8;
1da177e4
LT		 1908 WordIO_t ConfigIO = 0;
1909 ByteIO_t UPCIRingInd = 0;
1910
b9d42395
KC		 1911 if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
1912 pci_enable_device(dev))
1da177e4
LT		 1913 return 0;
1914
1915 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1da177e4
LT		 1916
1917 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1918 rocketModel[i].loadrm2 = 0;
1919 rocketModel[i].startingPortNumber = nextLineNumber;
1920
1921 /* Depending on the model, set up some config variables */
1922 switch (dev->device) {
1923 case PCI_DEVICE_ID_RP4QUAD:
1da177e4
LT		 1924 max_num_aiops = 1;
1925 ports_per_aiop = 4;
1926 rocketModel[i].model = MODEL_RP4QUAD;
1927 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1928 rocketModel[i].numPorts = 4;
1929 break;
1930 case PCI_DEVICE_ID_RP8OCTA:
1da177e4
LT		 1931 max_num_aiops = 1;
1932 rocketModel[i].model = MODEL_RP8OCTA;
1933 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1934 rocketModel[i].numPorts = 8;
1935 break;
1936 case PCI_DEVICE_ID_URP8OCTA:
1da177e4
LT		 1937 max_num_aiops = 1;
1938 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1939 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1940 rocketModel[i].numPorts = 8;
1941 break;
1942 case PCI_DEVICE_ID_RP8INTF:
1da177e4
LT		 1943 max_num_aiops = 1;
1944 rocketModel[i].model = MODEL_RP8INTF;
1945 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1946 rocketModel[i].numPorts = 8;
1947 break;
1948 case PCI_DEVICE_ID_URP8INTF:
1da177e4
LT		 1949 max_num_aiops = 1;
1950 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1951 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1952 rocketModel[i].numPorts = 8;
1953 break;
1954 case PCI_DEVICE_ID_RP8J:
1da177e4
LT		 1955 max_num_aiops = 1;
1956 rocketModel[i].model = MODEL_RP8J;
1957 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1958 rocketModel[i].numPorts = 8;
1959 break;
1960 case PCI_DEVICE_ID_RP4J:
1da177e4
LT		 1961 max_num_aiops = 1;
1962 ports_per_aiop = 4;
1963 rocketModel[i].model = MODEL_RP4J;
1964 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1965 rocketModel[i].numPorts = 4;
1966 break;
1967 case PCI_DEVICE_ID_RP8SNI:
1da177e4
LT		 1968 max_num_aiops = 1;
1969 rocketModel[i].model = MODEL_RP8SNI;
1970 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1971 rocketModel[i].numPorts = 8;
1972 break;
1973 case PCI_DEVICE_ID_RP16SNI:
1da177e4
LT		 1974 max_num_aiops = 2;
1975 rocketModel[i].model = MODEL_RP16SNI;
1976 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1977 rocketModel[i].numPorts = 16;
1978 break;
1979 case PCI_DEVICE_ID_RP16INTF:
1da177e4
LT		 1980 max_num_aiops = 2;
1981 rocketModel[i].model = MODEL_RP16INTF;
1982 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1983 rocketModel[i].numPorts = 16;
1984 break;
1985 case PCI_DEVICE_ID_URP16INTF:
1da177e4
LT		 1986 max_num_aiops = 2;
1987 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1988 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1989 rocketModel[i].numPorts = 16;
1990 break;
1991 case PCI_DEVICE_ID_CRP16INTF:
1da177e4
LT		 1992 max_num_aiops = 2;
1993 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1994 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1995 rocketModel[i].numPorts = 16;
1996 break;
1997 case PCI_DEVICE_ID_RP32INTF:
1da177e4
LT		 1998 max_num_aiops = 4;
1999 rocketModel[i].model = MODEL_RP32INTF;
2000 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
2001 rocketModel[i].numPorts = 32;
2002 break;
2003 case PCI_DEVICE_ID_URP32INTF:
1da177e4
LT		 2004 max_num_aiops = 4;
2005 rocketModel[i].model = MODEL_UPCI_RP32INTF;
2006 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
2007 rocketModel[i].numPorts = 32;
2008 break;
2009 case PCI_DEVICE_ID_RPP4:
1da177e4
LT		 2010 max_num_aiops = 1;
2011 ports_per_aiop = 4;
2012 altChanRingIndicator++;
2013 fast_clock++;
2014 rocketModel[i].model = MODEL_RPP4;
2015 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2016 rocketModel[i].numPorts = 4;
2017 break;
2018 case PCI_DEVICE_ID_RPP8:
1da177e4
LT		 2019 max_num_aiops = 2;
2020 ports_per_aiop = 4;
2021 altChanRingIndicator++;
2022 fast_clock++;
2023 rocketModel[i].model = MODEL_RPP8;
2024 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2025 rocketModel[i].numPorts = 8;
2026 break;
2027 case PCI_DEVICE_ID_RP2_232:
1da177e4
LT		 2028 max_num_aiops = 1;
2029 ports_per_aiop = 2;
2030 altChanRingIndicator++;
2031 fast_clock++;
2032 rocketModel[i].model = MODEL_RP2_232;
2033 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2034 rocketModel[i].numPorts = 2;
2035 break;
2036 case PCI_DEVICE_ID_RP2_422:
1da177e4
LT		 2037 max_num_aiops = 1;
2038 ports_per_aiop = 2;
2039 altChanRingIndicator++;
2040 fast_clock++;
2041 rocketModel[i].model = MODEL_RP2_422;
2042 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2043 rocketModel[i].numPorts = 2;
2044 break;
2045 case PCI_DEVICE_ID_RP6M:
2046
2047 max_num_aiops = 1;
2048 ports_per_aiop = 6;
1da177e4 2049
57fedc7a
JS		 2050 /* If revision is 1, the rocketmodem flash must be loaded.
2051 * If it is 2 it is a "socketed" version. */
2052 if (dev->revision == 1) {
1da177e4
LT		 2053 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2054 rocketModel[i].loadrm2 = 1;
2055 } else {
2056 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2057 }
2058
2059 rocketModel[i].model = MODEL_RP6M;
2060 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2061 rocketModel[i].numPorts = 6;
2062 break;
2063 case PCI_DEVICE_ID_RP4M:
2064 max_num_aiops = 1;
2065 ports_per_aiop = 4;
57fedc7a 2066 if (dev->revision == 1) {
1da177e4
LT		 2067 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2068 rocketModel[i].loadrm2 = 1;
2069 } else {
2070 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2071 }
2072
2073 rocketModel[i].model = MODEL_RP4M;
2074 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2075 rocketModel[i].numPorts = 4;
2076 break;
2077 default:
1da177e4
LT		 2078 max_num_aiops = 0;
2079 break;
2080 }
2081
2082 /*
2083 * Check for UPCI boards.
2084 */
2085
2086 switch (dev->device) {
2087 case PCI_DEVICE_ID_URP32INTF:
2088 case PCI_DEVICE_ID_URP8INTF:
2089 case PCI_DEVICE_ID_URP16INTF:
2090 case PCI_DEVICE_ID_CRP16INTF:
2091 case PCI_DEVICE_ID_URP8OCTA:
2092 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2093 ConfigIO = pci_resource_start(dev, 1);
2094 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2095 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2096
2097 /*
2098 * Check for octa or quad cable.
2099 */
2100 if (!
2101 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2102 PCI_GPIO_CTRL_8PORT)) {
1da177e4
LT		 2103 ports_per_aiop = 4;
2104 rocketModel[i].numPorts = 4;
2105 }
2106 }
2107 break;
2108 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
1da177e4
LT		 2109 max_num_aiops = 1;
2110 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2111 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2112 rocketModel[i].numPorts = 8;
2113 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2114 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2115 ConfigIO = pci_resource_start(dev, 1);
2116 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2117 break;
2118 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
1da177e4
LT		 2119 max_num_aiops = 1;
2120 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2121 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2122 rocketModel[i].numPorts = 4;
2123 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2124 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2125 ConfigIO = pci_resource_start(dev, 1);
2126 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2127 break;
2128 default:
2129 break;
2130 }
2131
1da177e4
LT		 2132 if (fast_clock) {
2133 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2134 rp_baud_base[i] = 921600;
2135 } else {
2136 /*
2137 * If support_low_speed is set, use the slow clock
2138 * prescale, which supports 50 bps
2139 */
2140 if (support_low_speed) {
2141 /* mod 9 (divide by 10) prescale */
2142 sClockPrescale = 0x19;
2143 rp_baud_base[i] = 230400;
2144 } else {
25985edc 2145 /* mod 4 (divide by 5) prescale */
1da177e4
LT		 2146 sClockPrescale = 0x14;
2147 rp_baud_base[i] = 460800;
2148 }
2149 }
2150
2151 for (aiop = 0; aiop < max_num_aiops; aiop++)
2152 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2153 ctlp = sCtlNumToCtlPtr(i);
2154 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2155 for (aiop = 0; aiop < max_num_aiops; aiop++)
2156 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2157
68562b79
JS		 2158 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2159 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2160 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2161 rocketModel[i].startingPortNumber,
2162 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
1da177e4
LT		 2163
2164 if (num_aiops <= 0) {
2165 rcktpt_io_addr[i] = 0;
2166 return (0);
2167 }
2168 is_PCI[i] = 1;
2169
2170 /* Reset the AIOPIC, init the serial ports */
2171 for (aiop = 0; aiop < num_aiops; aiop++) {
2172 sResetAiopByNum(ctlp, aiop);
2173 num_chan = ports_per_aiop;
2174 for (chan = 0; chan < num_chan; chan++)
2175 init_r_port(i, aiop, chan, dev);
2176 }
2177
2178 /* Rocket modems must be reset */
2179 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2180 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2181 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2182 num_chan = ports_per_aiop;
2183 for (chan = 0; chan < num_chan; chan++)
2184 sPCIModemReset(ctlp, chan, 1);
48a67f5d 2185 msleep(500);
1da177e4
LT		 2186 for (chan = 0; chan < num_chan; chan++)
2187 sPCIModemReset(ctlp, chan, 0);
48a67f5d 2188 msleep(500);
1da177e4
LT		 2189 rmSpeakerReset(ctlp, rocketModel[i].model);
2190 }
2191 return (1);
2192}
2193
2194/*
2195 * Probes for PCI cards, inits them if found
2196 * Input: board_found = number of ISA boards already found, or the
2197 * starting board number
2198 * Returns: Number of PCI boards found
2199 */
2200static int __init init_PCI(int boards_found)
2201{
2202 struct pci_dev *dev = NULL;
2203 int count = 0;
2204
2205 /* Work through the PCI device list, pulling out ours */
606d099c 2206 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
1da177e4
LT		 2207 if (register_PCI(count + boards_found, dev))
2208 count++;
2209 }
2210 return (count);
2211}
2212
2213#endif /* CONFIG_PCI */
2214
2215/*
2216 * Probes for ISA cards
2217 * Input: i = the board number to look for
2218 * Returns: 1 if board found, 0 else
2219 */
2220static int __init init_ISA(int i)
2221{
2222 int num_aiops, num_chan = 0, total_num_chan = 0;
2223 int aiop, chan;
2224 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2225 CONTROLLER_t *ctlp;
2226 char *type_string;
2227
2228 /* If io_addr is zero, no board configured */
2229 if (rcktpt_io_addr[i] == 0)
2230 return (0);
2231
2232 /* Reserve the IO region */
2233 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
68562b79
JS		 2234 printk(KERN_ERR "Unable to reserve IO region for configured "
2235 "ISA RocketPort at address 0x%lx, board not "
2236 "installed...\n", rcktpt_io_addr[i]);
1da177e4
LT		 2237 rcktpt_io_addr[i] = 0;
2238 return (0);
2239 }
2240
2241 ctlp = sCtlNumToCtlPtr(i);
2242
2243 ctlp->boardType = rcktpt_type[i];
2244
2245 switch (rcktpt_type[i]) {
2246 case ROCKET_TYPE_PC104:
2247 type_string = "(PC104)";
2248 break;
2249 case ROCKET_TYPE_MODEM:
2250 type_string = "(RocketModem)";
2251 break;
2252 case ROCKET_TYPE_MODEMII:
2253 type_string = "(RocketModem II)";
2254 break;
2255 default:
2256 type_string = "";
2257 break;
2258 }
2259
2260 /*
2261 * If support_low_speed is set, use the slow clock prescale,
2262 * which supports 50 bps
2263 */
2264 if (support_low_speed) {
2265 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2266 rp_baud_base[i] = 230400;
2267 } else {
25985edc 2268 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
1da177e4
LT		 2269 rp_baud_base[i] = 460800;
2270 }
2271
2272 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2273 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2274
2275 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2276
2277 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2278 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2279 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2280 }
2281
2282 /* If something went wrong initing the AIOP's release the ISA IO memory */
2283 if (num_aiops <= 0) {
2284 release_region(rcktpt_io_addr[i], 64);
2285 rcktpt_io_addr[i] = 0;
2286 return (0);
2287 }
2288
2289 rocketModel[i].startingPortNumber = nextLineNumber;
2290
2291 for (aiop = 0; aiop < num_aiops; aiop++) {
2292 sResetAiopByNum(ctlp, aiop);
2293 sEnAiop(ctlp, aiop);
2294 num_chan = sGetAiopNumChan(ctlp, aiop);
2295 total_num_chan += num_chan;
2296 for (chan = 0; chan < num_chan; chan++)
2297 init_r_port(i, aiop, chan, NULL);
2298 }
2299 is_PCI[i] = 0;
2300 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2301 num_chan = sGetAiopNumChan(ctlp, 0);
2302 total_num_chan = num_chan;
2303 for (chan = 0; chan < num_chan; chan++)
2304 sModemReset(ctlp, chan, 1);
48a67f5d 2305 msleep(500);
1da177e4
LT		 2306 for (chan = 0; chan < num_chan; chan++)
2307 sModemReset(ctlp, chan, 0);
48a67f5d 2308 msleep(500);
1da177e4
LT		 2309 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2310 } else {
2311 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2312 }
2313 rocketModel[i].numPorts = total_num_chan;
2314 rocketModel[i].model = MODEL_ISA;
2315
2316 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2317 i, rcktpt_io_addr[i], num_aiops, type_string);
2318
2319 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2320 rocketModel[i].modelString,
2321 rocketModel[i].startingPortNumber,
2322 rocketModel[i].startingPortNumber +
2323 rocketModel[i].numPorts - 1);
2324
2325 return (1);
2326}
2327
b68e31d0 2328static const struct tty_operations rocket_ops = {
1da177e4
LT		 2329 .open = rp_open,
2330 .close = rp_close,
2331 .write = rp_write,
2332 .put_char = rp_put_char,
2333 .write_room = rp_write_room,
2334 .chars_in_buffer = rp_chars_in_buffer,
2335 .flush_buffer = rp_flush_buffer,
2336 .ioctl = rp_ioctl,
2337 .throttle = rp_throttle,
2338 .unthrottle = rp_unthrottle,
2339 .set_termios = rp_set_termios,
2340 .stop = rp_stop,
2341 .start = rp_start,
2342 .hangup = rp_hangup,
2343 .break_ctl = rp_break,
2344 .send_xchar = rp_send_xchar,
2345 .wait_until_sent = rp_wait_until_sent,
2346 .tiocmget = rp_tiocmget,
2347 .tiocmset = rp_tiocmset,
2348};
2349
31f35939
AC		 2350static const struct tty_port_operations rocket_port_ops = {
2351 .carrier_raised = carrier_raised,
fcc8ac18 2352 .dtr_rts = dtr_rts,
31f35939
AC		 2353};
2354
1da177e4
LT		 2355/*
2356 * The module "startup" routine; it's run when the module is loaded.
2357 */
d269cdd0 2358static int __init rp_init(void)
1da177e4 2359{
4384a3fa 2360 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
1da177e4
LT		 2361
2362 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2363 ROCKET_VERSION, ROCKET_DATE);
2364
2365 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2366 if (!rocket_driver)
4384a3fa 2367 goto err;
1da177e4 2368
1da177e4
LT		 2369 /*
2370 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2371 * zero, use the default controller IO address of board1 + 0x40.
2372 */
2373 if (board1) {
2374 if (controller == 0)
2375 controller = board1 + 0x40;
2376 } else {
2377 controller = 0; /* Used as a flag, meaning no ISA boards */
2378 }
2379
2380 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2381 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
4384a3fa
JS		 2382 printk(KERN_ERR "Unable to reserve IO region for first "
2383 "configured ISA RocketPort controller 0x%lx. "
2384 "Driver exiting\n", controller);
2385 ret = -EBUSY;
2386 goto err_tty;
1da177e4
LT		 2387 }
2388
2389 /* Store ISA variable retrieved from command line or .conf file. */
2390 rcktpt_io_addr[0] = board1;
2391 rcktpt_io_addr[1] = board2;
2392 rcktpt_io_addr[2] = board3;
2393 rcktpt_io_addr[3] = board4;
2394
2395 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2396 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2397 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2398 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2399 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2400 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2401 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2402 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2403
2404 /*
2405 * Set up the tty driver structure and then register this
2406 * driver with the tty layer.
2407 */
2408
331b8319 2409 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
1da177e4
LT		 2410 rocket_driver->name = "ttyR";
2411 rocket_driver->driver_name = "Comtrol RocketPort";
2412 rocket_driver->major = TTY_ROCKET_MAJOR;
2413 rocket_driver->minor_start = 0;
2414 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2415 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2416 rocket_driver->init_termios = tty_std_termios;
2417 rocket_driver->init_termios.c_cflag =
2418 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 2419 rocket_driver->init_termios.c_ispeed = 9600;
2420 rocket_driver->init_termios.c_ospeed = 9600;
1da177e4 2421#ifdef ROCKET_SOFT_FLOW
ac6aec2f 2422 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
1da177e4
LT		 2423#endif
2424 tty_set_operations(rocket_driver, &rocket_ops);
2425
4384a3fa
JS		 2426 ret = tty_register_driver(rocket_driver);
2427 if (ret < 0) {
2428 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
713efa9a 2429 goto err_controller;
1da177e4
LT		 2430 }
2431
2432#ifdef ROCKET_DEBUG_OPEN
2433 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2434#endif
2435
2436 /*
2437 * OK, let's probe each of the controllers looking for boards. Any boards found
2438 * will be initialized here.
2439 */
2440 isa_boards_found = 0;
2441 pci_boards_found = 0;
2442
2443 for (i = 0; i < NUM_BOARDS; i++) {
2444 if (init_ISA(i))
2445 isa_boards_found++;
2446 }
2447
2448#ifdef CONFIG_PCI
2449 if (isa_boards_found < NUM_BOARDS)
2450 pci_boards_found = init_PCI(isa_boards_found);
2451#endif
2452
2453 max_board = pci_boards_found + isa_boards_found;
2454
2455 if (max_board == 0) {
4384a3fa
JS		 2456 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2457 ret = -ENXIO;
2458 goto err_ttyu;
1da177e4
LT		 2459 }
2460
2461 return 0;
4384a3fa
JS		 2462err_ttyu:
2463 tty_unregister_driver(rocket_driver);
713efa9a
DC		 2464err_controller:
2465 if (controller)
2466 release_region(controller, 4);
4384a3fa
JS		 2467err_tty:
2468 put_tty_driver(rocket_driver);
2469err:
2470 return ret;
1da177e4
LT		 2471}
2472
1da177e4
LT		 2473
2474static void rp_cleanup_module(void)
2475{
2476 int retval;
2477 int i;
2478
2479 del_timer_sync(&rocket_timer);
2480
2481 retval = tty_unregister_driver(rocket_driver);
2482 if (retval)
68562b79 2483 printk(KERN_ERR "Error %d while trying to unregister "
1da177e4 2484 "rocketport driver\n", -retval);
1da177e4 2485
735d5661 2486 for (i = 0; i < MAX_RP_PORTS; i++)
ac6aec2f
JS		 2487 if (rp_table[i]) {
2488 tty_unregister_device(rocket_driver, i);
191c5f10 2489 tty_port_destroy(&rp_table[i]->port);
ac6aec2f
JS		 2490 kfree(rp_table[i]);
2491 }
2492
2493 put_tty_driver(rocket_driver);
1da177e4
LT		 2494
2495 for (i = 0; i < NUM_BOARDS; i++) {
2496 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2497 continue;
2498 release_region(rcktpt_io_addr[i], 64);
2499 }
2500 if (controller)
2501 release_region(controller, 4);
2502}
1da177e4 2503
1da177e4
LT		 2504/***************************************************************************
2505Function: sInitController
2506Purpose: Initialization of controller global registers and controller
2507 structure.
2508Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2509 IRQNum,Frequency,PeriodicOnly)
2510 CONTROLLER_T *CtlP; Ptr to controller structure
2511 int CtlNum; Controller number
2512 ByteIO_t MudbacIO; Mudbac base I/O address.
2513 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2514 This list must be in the order the AIOPs will be found on the
2515 controller. Once an AIOP in the list is not found, it is
2516 assumed that there are no more AIOPs on the controller.
2517 int AiopIOListSize; Number of addresses in AiopIOList
2518 int IRQNum; Interrupt Request number. Can be any of the following:
2519 0: Disable global interrupts
2520 3: IRQ 3
2521 4: IRQ 4
2522 5: IRQ 5
2523 9: IRQ 9
2524 10: IRQ 10
2525 11: IRQ 11
2526 12: IRQ 12
2527 15: IRQ 15
2528 Byte_t Frequency: A flag identifying the frequency
2529 of the periodic interrupt, can be any one of the following:
2530 FREQ_DIS - periodic interrupt disabled
2531 FREQ_137HZ - 137 Hertz
2532 FREQ_69HZ - 69 Hertz
2533 FREQ_34HZ - 34 Hertz
2534 FREQ_17HZ - 17 Hertz
2535 FREQ_9HZ - 9 Hertz
2536 FREQ_4HZ - 4 Hertz
2537 If IRQNum is set to 0 the Frequency parameter is
2538 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2539 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2540 interrupt are to be blocked.
f15313bf 2541 0 is both the periodic interrupt and
1da177e4
LT		 2542 other channel interrupts are allowed.
2543 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2544 overidden, it is forced to a value of 0.
1da177e4
LT		 2545Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2546 initialization failed.
2547
2548Comments:
2549 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2550 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2551
2552 If interrupts are to be completely disabled set IRQNum to 0.
2553
f15313bf 2554 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2555 invalid combination.
2556
2557 This function performs initialization of global interrupt modes,
2558 but it does not actually enable global interrupts. To enable
2559 and disable global interrupts use functions sEnGlobalInt() and
2560 sDisGlobalInt(). Enabling of global interrupts is normally not
2561 done until all other initializations are complete.
2562
2563 Even if interrupts are globally enabled, they must also be
2564 individually enabled for each channel that is to generate
2565 interrupts.
2566
2567Warnings: No range checking on any of the parameters is done.
2568
2569 No context switches are allowed while executing this function.
2570
2571 After this function all AIOPs on the controller are disabled,
2572 they can be enabled with sEnAiop().
2573*/
f15313bf
AB		 2574static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2575 ByteIO_t * AiopIOList, int AiopIOListSize,
2576 int IRQNum, Byte_t Frequency, int PeriodicOnly)
1da177e4
LT		 2577{
2578 int i;
2579 ByteIO_t io;
2580 int done;
2581
2582 CtlP->AiopIntrBits = aiop_intr_bits;
2583 CtlP->AltChanRingIndicator = 0;
2584 CtlP->CtlNum = CtlNum;
2585 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2586 CtlP->BusType = isISA;
2587 CtlP->MBaseIO = MudbacIO;
2588 CtlP->MReg1IO = MudbacIO + 1;
2589 CtlP->MReg2IO = MudbacIO + 2;
2590 CtlP->MReg3IO = MudbacIO + 3;
2591#if 1
2592 CtlP->MReg2 = 0; /* interrupt disable */
2593 CtlP->MReg3 = 0; /* no periodic interrupts */
2594#else
2595 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2596 CtlP->MReg2 = 0; /* interrupt disable */
2597 CtlP->MReg3 = 0; /* no periodic interrupts */
2598 } else {
2599 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2600 CtlP->MReg3 = Frequency; /* set frequency */
2601 if (PeriodicOnly) { /* periodic interrupt only */
2602 CtlP->MReg3 |= PERIODIC_ONLY;
2603 }
2604 }
2605#endif
2606 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2607 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2608 sControllerEOI(CtlP); /* clear EOI if warm init */
2609 /* Init AIOPs */
2610 CtlP->NumAiop = 0;
2611 for (i = done = 0; i < AiopIOListSize; i++) {
2612 io = AiopIOList[i];
2613 CtlP->AiopIO[i] = (WordIO_t) io;
2614 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2615 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2616 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2617 if (done)
2618 continue;
2619 sEnAiop(CtlP, i); /* enable the AIOP */
2620 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2621 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2622 done = 1; /* done looking for AIOPs */
2623 else {
2624 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2625 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2626 sOutB(io + _INDX_DATA, sClockPrescale);
2627 CtlP->NumAiop++; /* bump count of AIOPs */
2628 }
2629 sDisAiop(CtlP, i); /* disable AIOP */
2630 }
2631
2632 if (CtlP->NumAiop == 0)
2633 return (-1);
2634 else
2635 return (CtlP->NumAiop);
2636}
2637
1da177e4
LT		 2638/***************************************************************************
2639Function: sReadAiopID
2640Purpose: Read the AIOP idenfication number directly from an AIOP.
2641Call: sReadAiopID(io)
2642 ByteIO_t io: AIOP base I/O address
2643Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2644 is replace by an identifying number.
2645 Flag AIOPID_NULL if no valid AIOP is found
2646Warnings: No context switches are allowed while executing this function.
2647
2648*/
f15313bf 2649static int sReadAiopID(ByteIO_t io)
1da177e4
LT		 2650{
2651 Byte_t AiopID; /* ID byte from AIOP */
2652
2653 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2654 sOutB(io + _CMD_REG, 0x0);
2655 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2656 if (AiopID == 0x06)
2657 return (1);
2658 else /* AIOP does not exist */
2659 return (-1);
2660}
2661
2662/***************************************************************************
2663Function: sReadAiopNumChan
2664Purpose: Read the number of channels available in an AIOP directly from
2665 an AIOP.
2666Call: sReadAiopNumChan(io)
2667 WordIO_t io: AIOP base I/O address
2668Return: int: The number of channels available
2669Comments: The number of channels is determined by write/reads from identical
2670 offsets within the SRAM address spaces for channels 0 and 4.
2671 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2672 AIOP, otherwise it is an 8 channel.
2673Warnings: No context switches are allowed while executing this function.
2674*/
f15313bf 2675static int sReadAiopNumChan(WordIO_t io)
1da177e4
LT		 2676{
2677 Word_t x;
2678 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2679
2680 /* write to chan 0 SRAM */
457fb605 2681 out32((DWordIO_t) io + _INDX_ADDR, R);
1da177e4
LT		 2682 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2683 x = sInW(io + _INDX_DATA);
2684 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2685 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2686 return (8);
2687 else
2688 return (4);
2689}
2690
2691/***************************************************************************
2692Function: sInitChan
2693Purpose: Initialization of a channel and channel structure
2694Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2695 CONTROLLER_T *CtlP; Ptr to controller structure
2696 CHANNEL_T *ChP; Ptr to channel structure
2697 int AiopNum; AIOP number within controller
2698 int ChanNum; Channel number within AIOP
f15313bf 2699Return: int: 1 if initialization succeeded, 0 if it fails because channel
1da177e4
LT		 2700 number exceeds number of channels available in AIOP.
2701Comments: This function must be called before a channel can be used.
2702Warnings: No range checking on any of the parameters is done.
2703
2704 No context switches are allowed while executing this function.
2705*/
f15313bf
AB		 2706static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2707 int ChanNum)
1da177e4
LT		 2708{
2709 int i;
2710 WordIO_t AiopIO;
2711 WordIO_t ChIOOff;
2712 Byte_t *ChR;
2713 Word_t ChOff;
2714 static Byte_t R[4];
2715 int brd9600;
2716
2717 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
f15313bf 2718 return 0; /* exceeds num chans in AIOP */
1da177e4
LT		 2719
2720 /* Channel, AIOP, and controller identifiers */
2721 ChP->CtlP = CtlP;
2722 ChP->ChanID = CtlP->AiopID[AiopNum];
2723 ChP->AiopNum = AiopNum;
2724 ChP->ChanNum = ChanNum;
2725
2726 /* Global direct addresses */
2727 AiopIO = CtlP->AiopIO[AiopNum];
2728 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2729 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2730 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2731 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2732 ChP->IndexData = AiopIO + _INDX_DATA;
2733
2734 /* Channel direct addresses */
2735 ChIOOff = AiopIO + ChP->ChanNum * 2;
2736 ChP->TxRxData = ChIOOff + _TD0;
2737 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2738 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2739 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2740
2741 /* Initialize the channel from the RData array */
2742 for (i = 0; i < RDATASIZE; i += 4) {
2743 R[0] = RData[i];
2744 R[1] = RData[i + 1] + 0x10 * ChanNum;
2745 R[2] = RData[i + 2];
2746 R[3] = RData[i + 3];
457fb605 2747 out32(ChP->IndexAddr, R);
1da177e4
LT		 2748 }
2749
2750 ChR = ChP->R;
2751 for (i = 0; i < RREGDATASIZE; i += 4) {
2752 ChR[i] = RRegData[i];
2753 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2754 ChR[i + 2] = RRegData[i + 2];
2755 ChR[i + 3] = RRegData[i + 3];
2756 }
2757
2758 /* Indexed registers */
2759 ChOff = (Word_t) ChanNum *0x1000;
2760
2761 if (sClockPrescale == 0x14)
2762 brd9600 = 47;
2763 else
2764 brd9600 = 23;
2765
2766 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2767 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2768 ChP->BaudDiv[2] = (Byte_t) brd9600;
2769 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
457fb605 2770 out32(ChP->IndexAddr, ChP->BaudDiv);
1da177e4
LT		 2771
2772 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2773 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2774 ChP->TxControl[2] = 0;
2775 ChP->TxControl[3] = 0;
457fb605 2776 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 2777
2778 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2779 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2780 ChP->RxControl[2] = 0;
2781 ChP->RxControl[3] = 0;
457fb605 2782 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 2783
2784 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2785 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2786 ChP->TxEnables[2] = 0;
2787 ChP->TxEnables[3] = 0;
457fb605 2788 out32(ChP->IndexAddr, ChP->TxEnables);
1da177e4
LT		 2789
2790 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2791 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2792 ChP->TxCompare[2] = 0;
2793 ChP->TxCompare[3] = 0;
457fb605 2794 out32(ChP->IndexAddr, ChP->TxCompare);
1da177e4
LT		 2795
2796 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2797 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2798 ChP->TxReplace1[2] = 0;
2799 ChP->TxReplace1[3] = 0;
457fb605 2800 out32(ChP->IndexAddr, ChP->TxReplace1);
1da177e4
LT		 2801
2802 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2803 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2804 ChP->TxReplace2[2] = 0;
2805 ChP->TxReplace2[3] = 0;
457fb605 2806 out32(ChP->IndexAddr, ChP->TxReplace2);
1da177e4
LT		 2807
2808 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2809 ChP->TxFIFO = ChOff + _TX_FIFO;
2810
2811 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2812 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2813 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2814 sOutW(ChP->IndexData, 0);
2815 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2816 ChP->RxFIFO = ChOff + _RX_FIFO;
2817
2818 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2819 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2820 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2821 sOutW(ChP->IndexData, 0);
2822 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2823 sOutW(ChP->IndexData, 0);
2824 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2825 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2826 sOutB(ChP->IndexData, 0);
2827 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2828 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2829 sOutB(ChP->IndexData, 0);
2830 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2831 sEnRxProcessor(ChP); /* start the Rx processor */
2832
f15313bf 2833 return 1;
1da177e4
LT		 2834}
2835
2836/***************************************************************************
2837Function: sStopRxProcessor
2838Purpose: Stop the receive processor from processing a channel.
2839Call: sStopRxProcessor(ChP)
2840 CHANNEL_T *ChP; Ptr to channel structure
2841
2842Comments: The receive processor can be started again with sStartRxProcessor().
2843 This function causes the receive processor to skip over the
2844 stopped channel. It does not stop it from processing other channels.
2845
2846Warnings: No context switches are allowed while executing this function.
2847
2848 Do not leave the receive processor stopped for more than one
2849 character time.
2850
2851 After calling this function a delay of 4 uS is required to ensure
2852 that the receive processor is no longer processing this channel.
2853*/
f15313bf 2854static void sStopRxProcessor(CHANNEL_T * ChP)
1da177e4
LT		 2855{
2856 Byte_t R[4];
2857
2858 R[0] = ChP->R[0];
2859 R[1] = ChP->R[1];
2860 R[2] = 0x0a;
2861 R[3] = ChP->R[3];
457fb605 2862 out32(ChP->IndexAddr, R);
1da177e4
LT		 2863}
2864
2865/***************************************************************************
2866Function: sFlushRxFIFO
2867Purpose: Flush the Rx FIFO
2868Call: sFlushRxFIFO(ChP)
2869 CHANNEL_T *ChP; Ptr to channel structure
2870Return: void
2871Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2872 while it is being flushed the receive processor is stopped
2873 and the transmitter is disabled. After these operations a
2874 4 uS delay is done before clearing the pointers to allow
2875 the receive processor to stop. These items are handled inside
2876 this function.
2877Warnings: No context switches are allowed while executing this function.
2878*/
f15313bf 2879static void sFlushRxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 2880{
2881 int i;
2882 Byte_t Ch; /* channel number within AIOP */
f15313bf 2883 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
1da177e4
LT		 2884
2885 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2886 return; /* don't need to flush */
2887
f15313bf 2888 RxFIFOEnabled = 0;
1da177e4 2889 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
f15313bf 2890 RxFIFOEnabled = 1;
1da177e4
LT		 2891 sDisRxFIFO(ChP); /* disable it */
2892 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2893 sInB(ChP->IntChan); /* depends on bus i/o timing */
2894 }
2895 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2896 Ch = (Byte_t) sGetChanNum(ChP);
2897 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2898 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2899 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2900 sOutW(ChP->IndexData, 0);
2901 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2902 sOutW(ChP->IndexData, 0);
2903 if (RxFIFOEnabled)
2904 sEnRxFIFO(ChP); /* enable Rx FIFO */
2905}
2906
2907/***************************************************************************
2908Function: sFlushTxFIFO
2909Purpose: Flush the Tx FIFO
2910Call: sFlushTxFIFO(ChP)
2911 CHANNEL_T *ChP; Ptr to channel structure
2912Return: void
2913Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2914 while it is being flushed the receive processor is stopped
2915 and the transmitter is disabled. After these operations a
2916 4 uS delay is done before clearing the pointers to allow
2917 the receive processor to stop. These items are handled inside
2918 this function.
2919Warnings: No context switches are allowed while executing this function.
2920*/
f15313bf 2921static void sFlushTxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 2922{
2923 int i;
2924 Byte_t Ch; /* channel number within AIOP */
f15313bf 2925 int TxEnabled; /* 1 if transmitter enabled */
1da177e4
LT		 2926
2927 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2928 return; /* don't need to flush */
2929
f15313bf 2930 TxEnabled = 0;
1da177e4 2931 if (ChP->TxControl[3] & TX_ENABLE) {
f15313bf 2932 TxEnabled = 1;
1da177e4
LT		 2933 sDisTransmit(ChP); /* disable transmitter */
2934 }
2935 sStopRxProcessor(ChP); /* stop Rx processor */
2936 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2937 sInB(ChP->IntChan); /* depends on bus i/o timing */
2938 Ch = (Byte_t) sGetChanNum(ChP);
2939 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2940 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2941 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2942 sOutW(ChP->IndexData, 0);
2943 if (TxEnabled)
2944 sEnTransmit(ChP); /* enable transmitter */
2945 sStartRxProcessor(ChP); /* restart Rx processor */
2946}
2947
2948/***************************************************************************
2949Function: sWriteTxPrioByte
2950Purpose: Write a byte of priority transmit data to a channel
2951Call: sWriteTxPrioByte(ChP,Data)
2952 CHANNEL_T *ChP; Ptr to channel structure
2953 Byte_t Data; The transmit data byte
2954
2955Return: int: 1 if the bytes is successfully written, otherwise 0.
2956
2957Comments: The priority byte is transmitted before any data in the Tx FIFO.
2958
2959Warnings: No context switches are allowed while executing this function.
2960*/
f15313bf 2961static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
1da177e4
LT		 2962{
2963 Byte_t DWBuf[4]; /* buffer for double word writes */
2964 Word_t *WordPtr; /* must be far because Win SS != DS */
2965 register DWordIO_t IndexAddr;
2966
2967 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2968 IndexAddr = ChP->IndexAddr;
2969 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2970 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2971 return (0); /* nothing sent */
2972
2973 WordPtr = (Word_t *) (&DWBuf[0]);
2974 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2975
2976 DWBuf[2] = Data; /* data byte value */
457fb605 2977 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 2978
2979 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2980
2981 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
2982 DWBuf[3] = 0; /* priority buffer pointer */
457fb605 2983 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 2984 } else { /* write it to Tx FIFO */
2985
2986 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2987 }
2988 return (1); /* 1 byte sent */
2989}
2990
2991/***************************************************************************
2992Function: sEnInterrupts
2993Purpose: Enable one or more interrupts for a channel
2994Call: sEnInterrupts(ChP,Flags)
2995 CHANNEL_T *ChP; Ptr to channel structure
2996 Word_t Flags: Interrupt enable flags, can be any combination
2997 of the following flags:
2998 TXINT_EN: Interrupt on Tx FIFO empty
2999 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3000 sSetRxTrigger())
3001 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3002 MCINT_EN: Interrupt on modem input change
3003 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3004 Interrupt Channel Register.
3005Return: void
3006Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3007 enabled. If an interrupt enable flag is not set in Flags, that
3008 interrupt will not be changed. Interrupts can be disabled with
3009 function sDisInterrupts().
3010
3011 This function sets the appropriate bit for the channel in the AIOP's
3012 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3013 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3014
3015 Interrupts must also be globally enabled before channel interrupts
3016 will be passed on to the host. This is done with function
3017 sEnGlobalInt().
3018
3019 In some cases it may be desirable to disable interrupts globally but
3020 enable channel interrupts. This would allow the global interrupt
3021 status register to be used to determine which AIOPs need service.
3022*/
f15313bf 3023static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3024{
3025 Byte_t Mask; /* Interrupt Mask Register */
3026
3027 ChP->RxControl[2] |=
3028 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3029
457fb605 3030 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 3031
3032 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3033
457fb605 3034 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3035
3036 if (Flags & CHANINT_EN) {
3037 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3038 sOutB(ChP->IntMask, Mask);
3039 }
3040}
3041
3042/***************************************************************************
3043Function: sDisInterrupts
3044Purpose: Disable one or more interrupts for a channel
3045Call: sDisInterrupts(ChP,Flags)
3046 CHANNEL_T *ChP; Ptr to channel structure
3047 Word_t Flags: Interrupt flags, can be any combination
3048 of the following flags:
3049 TXINT_EN: Interrupt on Tx FIFO empty
3050 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3051 sSetRxTrigger())
3052 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3053 MCINT_EN: Interrupt on modem input change
3054 CHANINT_EN: Disable channel interrupt signal to the
3055 AIOP's Interrupt Channel Register.
3056Return: void
3057Comments: If an interrupt flag is set in Flags, that interrupt will be
3058 disabled. If an interrupt flag is not set in Flags, that
3059 interrupt will not be changed. Interrupts can be enabled with
3060 function sEnInterrupts().
3061
3062 This function clears the appropriate bit for the channel in the AIOP's
3063 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3064 this channel's bit from being set in the AIOP's Interrupt Channel
3065 Register.
3066*/
f15313bf 3067static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3068{
3069 Byte_t Mask; /* Interrupt Mask Register */
3070
3071 ChP->RxControl[2] &=
3072 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
457fb605 3073 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4 3074 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
457fb605 3075 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3076
3077 if (Flags & CHANINT_EN) {
3078 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3079 sOutB(ChP->IntMask, Mask);
3080 }
3081}
3082
f15313bf 3083static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
1da177e4
LT		 3084{
3085 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3086}
3087
3088/*
3089 * Not an official SSCI function, but how to reset RocketModems.
3090 * ISA bus version
3091 */
f15313bf 3092static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3093{
3094 ByteIO_t addr;
3095 Byte_t val;
3096
3097 addr = CtlP->AiopIO[0] + 0x400;
3098 val = sInB(CtlP->MReg3IO);
3099 /* if AIOP[1] is not enabled, enable it */
3100 if ((val & 2) == 0) {
3101 val = sInB(CtlP->MReg2IO);
3102 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3103 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3104 }
3105
3106 sEnAiop(CtlP, 1);
3107 if (!on)
3108 addr += 8;
3109 sOutB(addr + chan, 0); /* apply or remove reset */
3110 sDisAiop(CtlP, 1);
3111}
3112
3113/*
3114 * Not an official SSCI function, but how to reset RocketModems.
3115 * PCI bus version
3116 */
f15313bf 3117static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3118{
3119 ByteIO_t addr;
3120
3121 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3122 if (!on)
3123 addr += 8;
3124 sOutB(addr + chan, 0); /* apply or remove reset */
3125}
3126
1da177e4
LT		 3127/* Returns the line number given the controller (board), aiop and channel number */
3128static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3129{
3130 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3131}
3132
3133/*
3134 * Stores the line number associated with a given controller (board), aiop
3135 * and channel number.
3136 * Returns: The line number assigned
3137 */
3138static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3139{
3140 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3141 return (nextLineNumber - 1);
3142}
Linux 6.x block layer and io_uring tree(s)