projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag '3.9-rc3-smp-6-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/sstabe...
[linux-2.6-block.git] / drivers / tty / rocket.c
CommitLineData
1da177e4
LT		 1/*
2 * RocketPort device driver for Linux
3 *
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Kernel Synchronization:
25 *
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
28 * are not used.
29 *
30 * Critical data:
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
37 *
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
40 */
41
42/****** Defines ******/
1da177e4
LT		 43#define ROCKET_PARANOIA_CHECK
44#define ROCKET_DISABLE_SIMUSAGE
45
46#undef ROCKET_SOFT_FLOW
47#undef ROCKET_DEBUG_OPEN
48#undef ROCKET_DEBUG_INTR
49#undef ROCKET_DEBUG_WRITE
50#undef ROCKET_DEBUG_FLOW
51#undef ROCKET_DEBUG_THROTTLE
52#undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53#undef ROCKET_DEBUG_RECEIVE
54#undef ROCKET_DEBUG_HANGUP
55#undef REV_PCI_ORDER
56#undef ROCKET_DEBUG_IO
57
37c44b52 58#define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
1da177e4
LT		 59
60/****** Kernel includes ******/
61
1da177e4
LT		 62#include <linux/module.h>
63#include <linux/errno.h>
64#include <linux/major.h>
65#include <linux/kernel.h>
66#include <linux/signal.h>
67#include <linux/slab.h>
68#include <linux/mm.h>
69#include <linux/sched.h>
70#include <linux/timer.h>
71#include <linux/interrupt.h>
72#include <linux/tty.h>
73#include <linux/tty_driver.h>
74#include <linux/tty_flip.h>
44b7d1b3 75#include <linux/serial.h>
1da177e4
LT		 76#include <linux/string.h>
77#include <linux/fcntl.h>
78#include <linux/ptrace.h>
69f545ea 79#include <linux/mutex.h>
1da177e4
LT		 80#include <linux/ioport.h>
81#include <linux/delay.h>
8cf5a8c5 82#include <linux/completion.h>
1da177e4
LT		 83#include <linux/wait.h>
84#include <linux/pci.h>
44b7d1b3 85#include <linux/uaccess.h>
60063497 86#include <linux/atomic.h>
457fb605 87#include <asm/unaligned.h>
1da177e4
LT		 88#include <linux/bitops.h>
89#include <linux/spinlock.h>
1da177e4
LT		 90#include <linux/init.h>
91
92/****** RocketPort includes ******/
93
94#include "rocket_int.h"
95#include "rocket.h"
96
97#define ROCKET_VERSION "2.09"
98#define ROCKET_DATE "12-June-2003"
99
100/****** RocketPort Local Variables ******/
101
40565f19
JS		 102static void rp_do_poll(unsigned long dummy);
103
1da177e4
LT		 104static struct tty_driver *rocket_driver;
105
106static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
108};
109
110static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113static atomic_t rp_num_ports_open; /* Number of serial ports open */
40565f19 114static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
1da177e4
LT		 115
116static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117static unsigned long board2;
118static unsigned long board3;
119static unsigned long board4;
120static unsigned long controller;
90ab5ee9 121static bool support_low_speed;
1da177e4
LT		 122static unsigned long modem1;
123static unsigned long modem2;
124static unsigned long modem3;
125static unsigned long modem4;
126static unsigned long pc104_1[8];
127static unsigned long pc104_2[8];
128static unsigned long pc104_3[8];
129static unsigned long pc104_4[8];
130static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
131
132static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133static unsigned long rcktpt_io_addr[NUM_BOARDS];
134static int rcktpt_type[NUM_BOARDS];
135static int is_PCI[NUM_BOARDS];
136static rocketModel_t rocketModel[NUM_BOARDS];
137static int max_board;
31f35939 138static const struct tty_port_operations rocket_port_ops;
1da177e4
LT		 139
140/*
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
144 */
145
146static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
147 AIOP_INTR_BIT_0,
148 AIOP_INTR_BIT_1,
149 AIOP_INTR_BIT_2,
150 AIOP_INTR_BIT_3
151};
152
153static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
154 UPCI_AIOP_INTR_BIT_0,
155 UPCI_AIOP_INTR_BIT_1,
156 UPCI_AIOP_INTR_BIT_2,
157 UPCI_AIOP_INTR_BIT_3
158};
159
f15313bf
AB		 160static Byte_t RData[RDATASIZE] = {
161 0x00, 0x09, 0xf6, 0x82,
162 0x02, 0x09, 0x86, 0xfb,
163 0x04, 0x09, 0x00, 0x0a,
164 0x06, 0x09, 0x01, 0x0a,
165 0x08, 0x09, 0x8a, 0x13,
166 0x0a, 0x09, 0xc5, 0x11,
167 0x0c, 0x09, 0x86, 0x85,
168 0x0e, 0x09, 0x20, 0x0a,
169 0x10, 0x09, 0x21, 0x0a,
170 0x12, 0x09, 0x41, 0xff,
171 0x14, 0x09, 0x82, 0x00,
172 0x16, 0x09, 0x82, 0x7b,
173 0x18, 0x09, 0x8a, 0x7d,
174 0x1a, 0x09, 0x88, 0x81,
175 0x1c, 0x09, 0x86, 0x7a,
176 0x1e, 0x09, 0x84, 0x81,
177 0x20, 0x09, 0x82, 0x7c,
178 0x22, 0x09, 0x0a, 0x0a
179};
180
181static Byte_t RRegData[RREGDATASIZE] = {
182 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
183 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
184 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
185 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
186 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
187 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
188 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
189 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
190 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
191 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
192 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
193 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
194 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
195};
196
197static CONTROLLER_T sController[CTL_SIZE] = {
198 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
199 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
206};
207
208static Byte_t sBitMapClrTbl[8] = {
209 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
210};
211
212static Byte_t sBitMapSetTbl[8] = {
213 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
214};
215
216static int sClockPrescale = 0x14;
217
1da177e4
LT		 218/*
219 * Line number is the ttySIx number (x), the Minor number. We
220 * assign them sequentially, starting at zero. The following
221 * array keeps track of the line number assigned to a given board/aiop/channel.
222 */
223static unsigned char lineNumbers[MAX_RP_PORTS];
224static unsigned long nextLineNumber;
225
226/***** RocketPort Static Prototypes *********/
227static int __init init_ISA(int i);
228static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
229static void rp_flush_buffer(struct tty_struct *tty);
230static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
231static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
232static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
233static void rp_start(struct tty_struct *tty);
f15313bf
AB		 234static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
235 int ChanNum);
236static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
237static void sFlushRxFIFO(CHANNEL_T * ChP);
238static void sFlushTxFIFO(CHANNEL_T * ChP);
239static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
240static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
241static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
242static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
243static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
244static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
245 ByteIO_t * AiopIOList, int AiopIOListSize,
246 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
247 int PeriodicOnly, int altChanRingIndicator,
248 int UPCIRingInd);
249static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
250 ByteIO_t * AiopIOList, int AiopIOListSize,
251 int IRQNum, Byte_t Frequency, int PeriodicOnly);
252static int sReadAiopID(ByteIO_t io);
253static int sReadAiopNumChan(WordIO_t io);
1da177e4 254
1da177e4
LT		 255MODULE_AUTHOR("Theodore Ts'o");
256MODULE_DESCRIPTION("Comtrol RocketPort driver");
257module_param(board1, ulong, 0);
258MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
259module_param(board2, ulong, 0);
260MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
261module_param(board3, ulong, 0);
262MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
263module_param(board4, ulong, 0);
264MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
265module_param(controller, ulong, 0);
266MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
267module_param(support_low_speed, bool, 0);
268MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
269module_param(modem1, ulong, 0);
270MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
271module_param(modem2, ulong, 0);
272MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
273module_param(modem3, ulong, 0);
274MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
275module_param(modem4, ulong, 0);
276MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
277module_param_array(pc104_1, ulong, NULL, 0);
278MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
279module_param_array(pc104_2, ulong, NULL, 0);
280MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
281module_param_array(pc104_3, ulong, NULL, 0);
282MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
283module_param_array(pc104_4, ulong, NULL, 0);
284MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
285
d269cdd0 286static int rp_init(void);
1da177e4
LT		 287static void rp_cleanup_module(void);
288
289module_init(rp_init);
290module_exit(rp_cleanup_module);
291
1da177e4 292
1da177e4 293MODULE_LICENSE("Dual BSD/GPL");
1da177e4
LT		 294
295/*************************************************************************/
296/* Module code starts here */
297
298static inline int rocket_paranoia_check(struct r_port *info,
299 const char *routine)
300{
301#ifdef ROCKET_PARANOIA_CHECK
302 if (!info)
303 return 1;
304 if (info->magic != RPORT_MAGIC) {
68562b79
JS		 305 printk(KERN_WARNING "Warning: bad magic number for rocketport "
306 "struct in %s\n", routine);
1da177e4
LT		 307 return 1;
308 }
309#endif
310 return 0;
311}
312
313
314/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
315 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
316 * tty layer.
317 */
2e124b4a
JS		 318static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
319 unsigned int ChanStatus)
1da177e4
LT		 320{
321 unsigned int CharNStat;
cc44a817
PF		 322 int ToRecv, wRecv, space;
323 unsigned char *cbuf;
1da177e4
LT		 324
325 ToRecv = sGetRxCnt(cp);
1da177e4 326#ifdef ROCKET_DEBUG_INTR
68562b79 327 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
1da177e4 328#endif
cc44a817
PF		 329 if (ToRecv == 0)
330 return;
33f0f88f 331
1da177e4
LT		 332 /*
333 * if status indicates there are errored characters in the
334 * FIFO, then enter status mode (a word in FIFO holds
335 * character and status).
336 */
337 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
338 if (!(ChanStatus & STATMODE)) {
339#ifdef ROCKET_DEBUG_RECEIVE
68562b79 340 printk(KERN_INFO "Entering STATMODE...\n");
1da177e4
LT		 341#endif
342 ChanStatus |= STATMODE;
343 sEnRxStatusMode(cp);
344 }
345 }
346
347 /*
348 * if we previously entered status mode, then read down the
349 * FIFO one word at a time, pulling apart the character and
350 * the status. Update error counters depending on status
351 */
352 if (ChanStatus & STATMODE) {
353#ifdef ROCKET_DEBUG_RECEIVE
68562b79
JS		 354 printk(KERN_INFO "Ignore %x, read %x...\n",
355 info->ignore_status_mask, info->read_status_mask);
1da177e4
LT		 356#endif
357 while (ToRecv) {
cc44a817
PF		 358 char flag;
359
1da177e4
LT		 360 CharNStat = sInW(sGetTxRxDataIO(cp));
361#ifdef ROCKET_DEBUG_RECEIVE
68562b79 362 printk(KERN_INFO "%x...\n", CharNStat);
1da177e4
LT		 363#endif
364 if (CharNStat & STMBREAKH)
365 CharNStat &= ~(STMFRAMEH | STMPARITYH);
366 if (CharNStat & info->ignore_status_mask) {
367 ToRecv--;
368 continue;
369 }
370 CharNStat &= info->read_status_mask;
371 if (CharNStat & STMBREAKH)
cc44a817 372 flag = TTY_BREAK;
1da177e4 373 else if (CharNStat & STMPARITYH)
cc44a817 374 flag = TTY_PARITY;
1da177e4 375 else if (CharNStat & STMFRAMEH)
cc44a817 376 flag = TTY_FRAME;
1da177e4 377 else if (CharNStat & STMRCVROVRH)
cc44a817 378 flag = TTY_OVERRUN;
1da177e4 379 else
cc44a817 380 flag = TTY_NORMAL;
92a19f9c
JS		 381 tty_insert_flip_char(&info->port, CharNStat & 0xff,
382 flag);
1da177e4
LT		 383 ToRecv--;
384 }
385
386 /*
387 * after we've emptied the FIFO in status mode, turn
388 * status mode back off
389 */
390 if (sGetRxCnt(cp) == 0) {
391#ifdef ROCKET_DEBUG_RECEIVE
392 printk(KERN_INFO "Status mode off.\n");
393#endif
394 sDisRxStatusMode(cp);
395 }
396 } else {
397 /*
398 * we aren't in status mode, so read down the FIFO two
399 * characters at time by doing repeated word IO
400 * transfer.
401 */
2f693357 402 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
cc44a817
PF		 403 if (space < ToRecv) {
404#ifdef ROCKET_DEBUG_RECEIVE
405 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
406#endif
407 if (space <= 0)
408 return;
409 ToRecv = space;
410 }
1da177e4
LT		 411 wRecv = ToRecv >> 1;
412 if (wRecv)
413 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
414 if (ToRecv & 1)
415 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
1da177e4
LT		 416 }
417 /* Push the data up to the tty layer */
2e124b4a 418 tty_flip_buffer_push(&info->port);
1da177e4
LT		 419}
420
421/*
422 * Serial port transmit data function. Called from the timer polling loop as a
423 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
424 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
425 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
426 */
427static void rp_do_transmit(struct r_port *info)
428{
429 int c;
430 CHANNEL_t *cp = &info->channel;
431 struct tty_struct *tty;
432 unsigned long flags;
433
434#ifdef ROCKET_DEBUG_INTR
68562b79 435 printk(KERN_DEBUG "%s\n", __func__);
1da177e4
LT		 436#endif
437 if (!info)
438 return;
47b01b3a
AC		 439 tty = tty_port_tty_get(&info->port);
440
441 if (tty == NULL) {
442 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
1da177e4
LT		 443 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
444 return;
445 }
446
447 spin_lock_irqsave(&info->slock, flags);
1da177e4
LT		 448 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
449
450 /* Loop sending data to FIFO until done or FIFO full */
451 while (1) {
ee797069 452 if (tty->stopped)
1da177e4 453 break;
709107fc
HH		 454 c = min(info->xmit_fifo_room, info->xmit_cnt);
455 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
1da177e4
LT		 456 if (c <= 0 || info->xmit_fifo_room <= 0)
457 break;
458 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
459 if (c & 1)
460 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
461 info->xmit_tail += c;
462 info->xmit_tail &= XMIT_BUF_SIZE - 1;
463 info->xmit_cnt -= c;
464 info->xmit_fifo_room -= c;
465#ifdef ROCKET_DEBUG_INTR
68562b79 466 printk(KERN_INFO "tx %d chars...\n", c);
1da177e4
LT		 467#endif
468 }
469
470 if (info->xmit_cnt == 0)
471 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
472
473 if (info->xmit_cnt < WAKEUP_CHARS) {
474 tty_wakeup(tty);
1da177e4
LT		 475#ifdef ROCKETPORT_HAVE_POLL_WAIT
476 wake_up_interruptible(&tty->poll_wait);
477#endif
478 }
479
480 spin_unlock_irqrestore(&info->slock, flags);
47b01b3a 481 tty_kref_put(tty);
1da177e4
LT		 482
483#ifdef ROCKET_DEBUG_INTR
68562b79 484 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
1da177e4
LT		 485 info->xmit_tail, info->xmit_fifo_room);
486#endif
487}
488
489/*
490 * Called when a serial port signals it has read data in it's RX FIFO.
491 * It checks what interrupts are pending and services them, including
492 * receiving serial data.
493 */
494static void rp_handle_port(struct r_port *info)
495{
496 CHANNEL_t *cp;
1da177e4
LT		 497 unsigned int IntMask, ChanStatus;
498
499 if (!info)
500 return;
501
21bed701 502 if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
68562b79
JS		 503 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
504 "info->flags & NOT_INIT\n");
1da177e4
LT		 505 return;
506 }
2e124b4a 507
1da177e4 508 cp = &info->channel;
1da177e4
LT		 509
510 IntMask = sGetChanIntID(cp) & info->intmask;
511#ifdef ROCKET_DEBUG_INTR
68562b79 512 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
1da177e4
LT		 513#endif
514 ChanStatus = sGetChanStatus(cp);
515 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
2e124b4a 516 rp_do_receive(info, cp, ChanStatus);
1da177e4
LT		 517 }
518 if (IntMask & DELTA_CD) { /* CD change */
519#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
68562b79 520 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
1da177e4
LT		 521 (ChanStatus & CD_ACT) ? "on" : "off");
522#endif
523 if (!(ChanStatus & CD_ACT) && info->cd_status) {
524#ifdef ROCKET_DEBUG_HANGUP
525 printk(KERN_INFO "CD drop, calling hangup.\n");
526#endif
aa27a094 527 tty_port_tty_hangup(&info->port, false);
1da177e4
LT		 528 }
529 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
e60a1084 530 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 531 }
532#ifdef ROCKET_DEBUG_INTR
533 if (IntMask & DELTA_CTS) { /* CTS change */
534 printk(KERN_INFO "CTS change...\n");
535 }
536 if (IntMask & DELTA_DSR) { /* DSR change */
537 printk(KERN_INFO "DSR change...\n");
538 }
539#endif
540}
541
542/*
543 * The top level polling routine. Repeats every 1/100 HZ (10ms).
544 */
545static void rp_do_poll(unsigned long dummy)
546{
547 CONTROLLER_t *ctlp;
6c0286b1
JS		 548 int ctrl, aiop, ch, line;
549 unsigned int xmitmask, i;
1da177e4
LT		 550 unsigned int CtlMask;
551 unsigned char AiopMask;
552 Word_t bit;
553
554 /* Walk through all the boards (ctrl's) */
555 for (ctrl = 0; ctrl < max_board; ctrl++) {
556 if (rcktpt_io_addr[ctrl] <= 0)
557 continue;
558
559 /* Get a ptr to the board's control struct */
560 ctlp = sCtlNumToCtlPtr(ctrl);
561
3a4fa0a2 562 /* Get the interrupt status from the board */
1da177e4
LT		 563#ifdef CONFIG_PCI
564 if (ctlp->BusType == isPCI)
565 CtlMask = sPCIGetControllerIntStatus(ctlp);
566 else
567#endif
568 CtlMask = sGetControllerIntStatus(ctlp);
569
570 /* Check if any AIOP read bits are set */
571 for (aiop = 0; CtlMask; aiop++) {
572 bit = ctlp->AiopIntrBits[aiop];
573 if (CtlMask & bit) {
574 CtlMask &= ~bit;
575 AiopMask = sGetAiopIntStatus(ctlp, aiop);
576
577 /* Check if any port read bits are set */
578 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
579 if (AiopMask & 1) {
580
581 /* Get the line number (/dev/ttyRx number). */
582 /* Read the data from the port. */
583 line = GetLineNumber(ctrl, aiop, ch);
584 rp_handle_port(rp_table[line]);
585 }
586 }
587 }
588 }
589
590 xmitmask = xmit_flags[ctrl];
591
592 /*
593 * xmit_flags contains bit-significant flags, indicating there is data
594 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
595 * 1, ... (32 total possible). The variable i has the aiop and ch
596 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
597 */
598 if (xmitmask) {
599 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
600 if (xmitmask & (1 << i)) {
601 aiop = (i & 0x18) >> 3;
602 ch = i & 0x07;
603 line = GetLineNumber(ctrl, aiop, ch);
604 rp_do_transmit(rp_table[line]);
605 }
606 }
607 }
608 }
609
610 /*
611 * Reset the timer so we get called at the next clock tick (10ms).
612 */
613 if (atomic_read(&rp_num_ports_open))
614 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
615}
616
617/*
618 * Initializes the r_port structure for a port, as well as enabling the port on
619 * the board.
620 * Inputs: board, aiop, chan numbers
621 */
622static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
623{
624 unsigned rocketMode;
625 struct r_port *info;
626 int line;
627 CONTROLLER_T *ctlp;
628
629 /* Get the next available line number */
630 line = SetLineNumber(board, aiop, chan);
631
632 ctlp = sCtlNumToCtlPtr(board);
633
634 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
dd00cc48 635 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
1da177e4 636 if (!info) {
68562b79
JS		 637 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
638 line);
1da177e4
LT		 639 return;
640 }
1da177e4
LT		 641
642 info->magic = RPORT_MAGIC;
643 info->line = line;
644 info->ctlp = ctlp;
645 info->board = board;
646 info->aiop = aiop;
647 info->chan = chan;
31f35939
AC		 648 tty_port_init(&info->port);
649 info->port.ops = &rocket_port_ops;
8cf5a8c5 650 init_completion(&info->close_wait);
1da177e4
LT		 651 info->flags &= ~ROCKET_MODE_MASK;
652 switch (pc104[board][line]) {
653 case 422:
654 info->flags |= ROCKET_MODE_RS422;
655 break;
656 case 485:
657 info->flags |= ROCKET_MODE_RS485;
658 break;
659 case 232:
660 default:
661 info->flags |= ROCKET_MODE_RS232;
662 break;
663 }
664
665 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
666 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
68562b79
JS		 667 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
668 board, aiop, chan);
191c5f10 669 tty_port_destroy(&info->port);
1da177e4
LT		 670 kfree(info);
671 return;
672 }
673
674 rocketMode = info->flags & ROCKET_MODE_MASK;
675
676 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
677 sEnRTSToggle(&info->channel);
678 else
679 sDisRTSToggle(&info->channel);
680
681 if (ctlp->boardType == ROCKET_TYPE_PC104) {
682 switch (rocketMode) {
683 case ROCKET_MODE_RS485:
684 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
685 break;
686 case ROCKET_MODE_RS422:
687 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
688 break;
689 case ROCKET_MODE_RS232:
690 default:
691 if (info->flags & ROCKET_RTS_TOGGLE)
692 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
693 else
694 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
695 break;
696 }
697 }
698 spin_lock_init(&info->slock);
69f545ea 699 mutex_init(&info->write_mtx);
1da177e4 700 rp_table[line] = info;
734cc178
JS		 701 tty_port_register_device(&info->port, rocket_driver, line,
702 pci_dev ? &pci_dev->dev : NULL);
1da177e4
LT		 703}
704
705/*
706 * Configures a rocketport port according to its termio settings. Called from
707 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
708 */
47b01b3a 709static void configure_r_port(struct tty_struct *tty, struct r_port *info,
606d099c 710 struct ktermios *old_termios)
1da177e4
LT		 711{
712 unsigned cflag;
713 unsigned long flags;
714 unsigned rocketMode;
715 int bits, baud, divisor;
716 CHANNEL_t *cp;
adc8d746 717 struct ktermios *t = &tty->termios;
1da177e4 718
1da177e4 719 cp = &info->channel;
6df3526b 720 cflag = t->c_cflag;
1da177e4
LT		 721
722 /* Byte size and parity */
723 if ((cflag & CSIZE) == CS8) {
724 sSetData8(cp);
725 bits = 10;
726 } else {
727 sSetData7(cp);
728 bits = 9;
729 }
730 if (cflag & CSTOPB) {
731 sSetStop2(cp);
732 bits++;
733 } else {
734 sSetStop1(cp);
735 }
736
737 if (cflag & PARENB) {
738 sEnParity(cp);
739 bits++;
740 if (cflag & PARODD) {
741 sSetOddParity(cp);
742 } else {
743 sSetEvenParity(cp);
744 }
745 } else {
746 sDisParity(cp);
747 }
748
749 /* baud rate */
47b01b3a 750 baud = tty_get_baud_rate(tty);
1da177e4
LT		 751 if (!baud)
752 baud = 9600;
753 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
754 if ((divisor >= 8192 || divisor < 0) && old_termios) {
6df3526b 755 baud = tty_termios_baud_rate(old_termios);
1da177e4
LT		 756 if (!baud)
757 baud = 9600;
758 divisor = (rp_baud_base[info->board] / baud) - 1;
759 }
760 if (divisor >= 8192 || divisor < 0) {
761 baud = 9600;
762 divisor = (rp_baud_base[info->board] / baud) - 1;
763 }
764 info->cps = baud / bits;
765 sSetBaud(cp, divisor);
766
6df3526b 767 /* FIXME: Should really back compute a baud rate from the divisor */
47b01b3a 768 tty_encode_baud_rate(tty, baud, baud);
6df3526b 769
1da177e4
LT		 770 if (cflag & CRTSCTS) {
771 info->intmask |= DELTA_CTS;
772 sEnCTSFlowCtl(cp);
773 } else {
774 info->intmask &= ~DELTA_CTS;
775 sDisCTSFlowCtl(cp);
776 }
777 if (cflag & CLOCAL) {
778 info->intmask &= ~DELTA_CD;
779 } else {
780 spin_lock_irqsave(&info->slock, flags);
781 if (sGetChanStatus(cp) & CD_ACT)
782 info->cd_status = 1;
783 else
784 info->cd_status = 0;
785 info->intmask |= DELTA_CD;
786 spin_unlock_irqrestore(&info->slock, flags);
787 }
788
789 /*
790 * Handle software flow control in the board
791 */
792#ifdef ROCKET_SOFT_FLOW
47b01b3a 793 if (I_IXON(tty)) {
1da177e4 794 sEnTxSoftFlowCtl(cp);
47b01b3a 795 if (I_IXANY(tty)) {
1da177e4
LT		 796 sEnIXANY(cp);
797 } else {
798 sDisIXANY(cp);
799 }
47b01b3a
AC		 800 sSetTxXONChar(cp, START_CHAR(tty));
801 sSetTxXOFFChar(cp, STOP_CHAR(tty));
1da177e4
LT		 802 } else {
803 sDisTxSoftFlowCtl(cp);
804 sDisIXANY(cp);
805 sClrTxXOFF(cp);
806 }
807#endif
808
809 /*
810 * Set up ignore/read mask words
811 */
812 info->read_status_mask = STMRCVROVRH | 0xFF;
47b01b3a 813 if (I_INPCK(tty))
1da177e4 814 info->read_status_mask |= STMFRAMEH | STMPARITYH;
47b01b3a 815 if (I_BRKINT(tty) || I_PARMRK(tty))
1da177e4
LT		 816 info->read_status_mask |= STMBREAKH;
817
818 /*
819 * Characters to ignore
820 */
821 info->ignore_status_mask = 0;
47b01b3a 822 if (I_IGNPAR(tty))
1da177e4 823 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
47b01b3a 824 if (I_IGNBRK(tty)) {
1da177e4
LT		 825 info->ignore_status_mask |= STMBREAKH;
826 /*
827 * If we're ignoring parity and break indicators,
828 * ignore overruns too. (For real raw support).
829 */
47b01b3a 830 if (I_IGNPAR(tty))
1da177e4
LT		 831 info->ignore_status_mask |= STMRCVROVRH;
832 }
833
834 rocketMode = info->flags & ROCKET_MODE_MASK;
835
836 if ((info->flags & ROCKET_RTS_TOGGLE)
837 || (rocketMode == ROCKET_MODE_RS485))
838 sEnRTSToggle(cp);
839 else
840 sDisRTSToggle(cp);
841
842 sSetRTS(&info->channel);
843
844 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
845 switch (rocketMode) {
846 case ROCKET_MODE_RS485:
847 sSetInterfaceMode(cp, InterfaceModeRS485);
848 break;
849 case ROCKET_MODE_RS422:
850 sSetInterfaceMode(cp, InterfaceModeRS422);
851 break;
852 case ROCKET_MODE_RS232:
853 default:
854 if (info->flags & ROCKET_RTS_TOGGLE)
855 sSetInterfaceMode(cp, InterfaceModeRS232T);
856 else
857 sSetInterfaceMode(cp, InterfaceModeRS232);
858 break;
859 }
860 }
861}
862
31f35939
AC		 863static int carrier_raised(struct tty_port *port)
864{
865 struct r_port *info = container_of(port, struct r_port, port);
866 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
867}
868
fcc8ac18 869static void dtr_rts(struct tty_port *port, int on)
5d951fb4
AC		 870{
871 struct r_port *info = container_of(port, struct r_port, port);
fcc8ac18
AC		 872 if (on) {
873 sSetDTR(&info->channel);
874 sSetRTS(&info->channel);
875 } else {
876 sClrDTR(&info->channel);
877 sClrRTS(&info->channel);
878 }
5d951fb4
AC		 879}
880
1da177e4
LT		 881/*
882 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
883 * port's r_port struct. Initializes the port hardware.
884 */
885static int rp_open(struct tty_struct *tty, struct file *filp)
886{
887 struct r_port *info;
fba85e01 888 struct tty_port *port;
410235fd 889 int retval;
1da177e4
LT		 890 CHANNEL_t *cp;
891 unsigned long page;
892
410235fd
JS		 893 info = rp_table[tty->index];
894 if (info == NULL)
1da177e4 895 return -ENXIO;
fba85e01
AC		 896 port = &info->port;
897
1da177e4
LT		 898 page = __get_free_page(GFP_KERNEL);
899 if (!page)
900 return -ENOMEM;
901
fba85e01 902 if (port->flags & ASYNC_CLOSING) {
8cf5a8c5 903 retval = wait_for_completion_interruptible(&info->close_wait);
1da177e4 904 free_page(page);
8cf5a8c5
JS		 905 if (retval)
906 return retval;
fba85e01 907 return ((port->flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
1da177e4
LT		 908 }
909
910 /*
911 * We must not sleep from here until the port is marked fully in use.
912 */
913 if (info->xmit_buf)
914 free_page(page);
915 else
916 info->xmit_buf = (unsigned char *) page;
917
918 tty->driver_data = info;
fba85e01 919 tty_port_tty_set(port, tty);
1da177e4 920
fba85e01 921 if (port->count++ == 0) {
1da177e4
LT		 922 atomic_inc(&rp_num_ports_open);
923
924#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 925 printk(KERN_INFO "rocket mod++ = %d...\n",
926 atomic_read(&rp_num_ports_open));
1da177e4
LT		 927#endif
928 }
929#ifdef ROCKET_DEBUG_OPEN
e60a1084 930 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
1da177e4
LT		 931#endif
932
933 /*
934 * Info->count is now 1; so it's safe to sleep now.
935 */
a391ad0f 936 if (!test_bit(ASYNCB_INITIALIZED, &port->flags)) {
1da177e4
LT		 937 cp = &info->channel;
938 sSetRxTrigger(cp, TRIG_1);
939 if (sGetChanStatus(cp) & CD_ACT)
940 info->cd_status = 1;
941 else
942 info->cd_status = 0;
943 sDisRxStatusMode(cp);
944 sFlushRxFIFO(cp);
945 sFlushTxFIFO(cp);
946
947 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
948 sSetRxTrigger(cp, TRIG_1);
949
950 sGetChanStatus(cp);
951 sDisRxStatusMode(cp);
952 sClrTxXOFF(cp);
953
954 sDisCTSFlowCtl(cp);
955 sDisTxSoftFlowCtl(cp);
956
957 sEnRxFIFO(cp);
958 sEnTransmit(cp);
959
a391ad0f 960 set_bit(ASYNCB_INITIALIZED, &info->port.flags);
1da177e4
LT		 961
962 /*
963 * Set up the tty->alt_speed kludge
964 */
965 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
47b01b3a 966 tty->alt_speed = 57600;
1da177e4 967 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
47b01b3a 968 tty->alt_speed = 115200;
1da177e4 969 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
47b01b3a 970 tty->alt_speed = 230400;
1da177e4 971 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
47b01b3a 972 tty->alt_speed = 460800;
1da177e4 973
47b01b3a 974 configure_r_port(tty, info, NULL);
adc8d746 975 if (tty->termios.c_cflag & CBAUD) {
1da177e4
LT		 976 sSetDTR(cp);
977 sSetRTS(cp);
978 }
979 }
980 /* Starts (or resets) the maint polling loop */
981 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
982
fba85e01 983 retval = tty_port_block_til_ready(port, tty, filp);
1da177e4
LT		 984 if (retval) {
985#ifdef ROCKET_DEBUG_OPEN
986 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
987#endif
988 return retval;
989 }
990 return 0;
991}
992
993/*
e60a1084 994 * Exception handler that closes a serial port. info->port.count is considered critical.
1da177e4
LT		 995 */
996static void rp_close(struct tty_struct *tty, struct file *filp)
997{
c9f19e96 998 struct r_port *info = tty->driver_data;
c1314a49 999 struct tty_port *port = &info->port;
1da177e4
LT		 1000 int timeout;
1001 CHANNEL_t *cp;
1002
1003 if (rocket_paranoia_check(info, "rp_close"))
1004 return;
1005
1006#ifdef ROCKET_DEBUG_OPEN
e60a1084 1007 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1da177e4
LT		 1008#endif
1009
fba85e01 1010 if (tty_port_close_start(port, tty, filp) == 0)
1da177e4 1011 return;
1da177e4 1012
417b6e0e 1013 mutex_lock(&port->mutex);
1da177e4 1014 cp = &info->channel;
1da177e4
LT		 1015 /*
1016 * Before we drop DTR, make sure the UART transmitter
1017 * has completely drained; this is especially
1018 * important if there is a transmit FIFO!
1019 */
1020 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1021 if (timeout == 0)
1022 timeout = 1;
1023 rp_wait_until_sent(tty, timeout);
1024 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1025
1026 sDisTransmit(cp);
1027 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1028 sDisCTSFlowCtl(cp);
1029 sDisTxSoftFlowCtl(cp);
1030 sClrTxXOFF(cp);
1031 sFlushRxFIFO(cp);
1032 sFlushTxFIFO(cp);
1033 sClrRTS(cp);
1034 if (C_HUPCL(tty))
1035 sClrDTR(cp);
1036
f6de0c98 1037 rp_flush_buffer(tty);
1da177e4
LT		 1038
1039 tty_ldisc_flush(tty);
1040
1041 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1042
fba85e01
AC		 1043 /* We can't yet use tty_port_close_end as the buffer handling in this
1044 driver is a bit different to the usual */
1045
c1314a49
AC		 1046 if (port->blocked_open) {
1047 if (port->close_delay) {
1048 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1da177e4 1049 }
c1314a49 1050 wake_up_interruptible(&port->open_wait);
1da177e4
LT		 1051 } else {
1052 if (info->xmit_buf) {
1053 free_page((unsigned long) info->xmit_buf);
1054 info->xmit_buf = NULL;
1055 }
1056 }
417b6e0e 1057 spin_lock_irq(&port->lock);
21bed701 1058 info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1da177e4 1059 tty->closing = 0;
417b6e0e
AC		 1060 spin_unlock_irq(&port->lock);
1061 mutex_unlock(&port->mutex);
fba85e01 1062 tty_port_tty_set(port, NULL);
417b6e0e 1063
fba85e01 1064 wake_up_interruptible(&port->close_wait);
8cf5a8c5 1065 complete_all(&info->close_wait);
1da177e4
LT		 1066 atomic_dec(&rp_num_ports_open);
1067
1068#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 1069 printk(KERN_INFO "rocket mod-- = %d...\n",
1070 atomic_read(&rp_num_ports_open));
1da177e4
LT		 1071 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1072#endif
1073
1074}
1075
1076static void rp_set_termios(struct tty_struct *tty,
606d099c 1077 struct ktermios *old_termios)
1da177e4 1078{
c9f19e96 1079 struct r_port *info = tty->driver_data;
1da177e4
LT		 1080 CHANNEL_t *cp;
1081 unsigned cflag;
1082
1083 if (rocket_paranoia_check(info, "rp_set_termios"))
1084 return;
1085
adc8d746 1086 cflag = tty->termios.c_cflag;
1da177e4 1087
1da177e4
LT		 1088 /*
1089 * This driver doesn't support CS5 or CS6
1090 */
1091 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
adc8d746 1092 tty->termios.c_cflag =
1da177e4 1093 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
6df3526b 1094 /* Or CMSPAR */
adc8d746 1095 tty->termios.c_cflag &= ~CMSPAR;
1da177e4 1096
47b01b3a 1097 configure_r_port(tty, info, old_termios);
1da177e4
LT		 1098
1099 cp = &info->channel;
1100
1101 /* Handle transition to B0 status */
adc8d746 1102 if ((old_termios->c_cflag & CBAUD) && !(tty->termios.c_cflag & CBAUD)) {
1da177e4
LT		 1103 sClrDTR(cp);
1104 sClrRTS(cp);
1105 }
1106
1107 /* Handle transition away from B0 status */
adc8d746 1108 if (!(old_termios->c_cflag & CBAUD) && (tty->termios.c_cflag & CBAUD)) {
ee797069 1109 sSetRTS(cp);
1da177e4
LT		 1110 sSetDTR(cp);
1111 }
1112
ee797069 1113 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios.c_cflag & CRTSCTS))
1da177e4 1114 rp_start(tty);
1da177e4
LT		 1115}
1116
9e98966c 1117static int rp_break(struct tty_struct *tty, int break_state)
1da177e4 1118{
c9f19e96 1119 struct r_port *info = tty->driver_data;
1da177e4
LT		 1120 unsigned long flags;
1121
1122 if (rocket_paranoia_check(info, "rp_break"))
9e98966c 1123 return -EINVAL;
1da177e4
LT		 1124
1125 spin_lock_irqsave(&info->slock, flags);
1126 if (break_state == -1)
1127 sSendBreak(&info->channel);
1128 else
1129 sClrBreak(&info->channel);
1130 spin_unlock_irqrestore(&info->slock, flags);
9e98966c 1131 return 0;
1da177e4
LT		 1132}
1133
1134/*
1135 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1136 * the UPCI boards was added, it was decided to make this a function because
1137 * the macro was getting too complicated. All cases except the first one
1138 * (UPCIRingInd) are taken directly from the original macro.
1139 */
1140static int sGetChanRI(CHANNEL_T * ChP)
1141{
1142 CONTROLLER_t *CtlP = ChP->CtlP;
1143 int ChanNum = ChP->ChanNum;
1144 int RingInd = 0;
1145
1146 if (CtlP->UPCIRingInd)
1147 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1148 else if (CtlP->AltChanRingIndicator)
1149 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1150 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1151 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1152
1153 return RingInd;
1154}
1155
1156/********************************************************************************************/
1157/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1158
1159/*
1160 * Returns the state of the serial modem control lines. These next 2 functions
1161 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1162 */
60b33c13 1163static int rp_tiocmget(struct tty_struct *tty)
1da177e4 1164{
c9f19e96 1165 struct r_port *info = tty->driver_data;
1da177e4
LT		 1166 unsigned int control, result, ChanStatus;
1167
1168 ChanStatus = sGetChanStatusLo(&info->channel);
1169 control = info->channel.TxControl[3];
1170 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1171 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1172 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1173 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1174 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1175 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1176
1177 return result;
1178}
1179
1180/*
1181 * Sets the modem control lines
1182 */
20b9d177
AC		 1183static int rp_tiocmset(struct tty_struct *tty,
1184 unsigned int set, unsigned int clear)
1da177e4 1185{
c9f19e96 1186 struct r_port *info = tty->driver_data;
1da177e4
LT		 1187
1188 if (set & TIOCM_RTS)
1189 info->channel.TxControl[3] |= SET_RTS;
1190 if (set & TIOCM_DTR)
1191 info->channel.TxControl[3] |= SET_DTR;
1192 if (clear & TIOCM_RTS)
1193 info->channel.TxControl[3] &= ~SET_RTS;
1194 if (clear & TIOCM_DTR)
1195 info->channel.TxControl[3] &= ~SET_DTR;
1196
457fb605 1197 out32(info->channel.IndexAddr, info->channel.TxControl);
1da177e4
LT		 1198 return 0;
1199}
1200
1201static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1202{
1203 struct rocket_config tmp;
1204
1205 if (!retinfo)
1206 return -EFAULT;
1207 memset(&tmp, 0, sizeof (tmp));
417b6e0e 1208 mutex_lock(&info->port.mutex);
1da177e4
LT		 1209 tmp.line = info->line;
1210 tmp.flags = info->flags;
44b7d1b3
AC		 1211 tmp.close_delay = info->port.close_delay;
1212 tmp.closing_wait = info->port.closing_wait;
1da177e4 1213 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
417b6e0e 1214 mutex_unlock(&info->port.mutex);
1da177e4
LT		 1215
1216 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1217 return -EFAULT;
1218 return 0;
1219}
1220
47b01b3a
AC		 1221static int set_config(struct tty_struct *tty, struct r_port *info,
1222 struct rocket_config __user *new_info)
1da177e4
LT		 1223{
1224 struct rocket_config new_serial;
1225
1226 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1227 return -EFAULT;
1228
417b6e0e 1229 mutex_lock(&info->port.mutex);
1da177e4
LT		 1230 if (!capable(CAP_SYS_ADMIN))
1231 {
417b6e0e
AC		 1232 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1233 mutex_unlock(&info->port.mutex);
1da177e4 1234 return -EPERM;
417b6e0e 1235 }
1da177e4 1236 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
47b01b3a 1237 configure_r_port(tty, info, NULL);
49bf7eaf 1238 mutex_unlock(&info->port.mutex);
1da177e4
LT		 1239 return 0;
1240 }
1241
1242 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
44b7d1b3
AC		 1243 info->port.close_delay = new_serial.close_delay;
1244 info->port.closing_wait = new_serial.closing_wait;
1da177e4
LT		 1245
1246 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
47b01b3a 1247 tty->alt_speed = 57600;
1da177e4 1248 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
47b01b3a 1249 tty->alt_speed = 115200;
1da177e4 1250 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
47b01b3a 1251 tty->alt_speed = 230400;
1da177e4 1252 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
47b01b3a 1253 tty->alt_speed = 460800;
417b6e0e 1254 mutex_unlock(&info->port.mutex);
1da177e4 1255
47b01b3a 1256 configure_r_port(tty, info, NULL);
1da177e4
LT		 1257 return 0;
1258}
1259
1260/*
1261 * This function fills in a rocket_ports struct with information
1262 * about what boards/ports are in the system. This info is passed
1263 * to user space. See setrocket.c where the info is used to create
1264 * the /dev/ttyRx ports.
1265 */
1266static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1267{
1268 struct rocket_ports tmp;
1269 int board;
1270
1271 if (!retports)
1272 return -EFAULT;
1273 memset(&tmp, 0, sizeof (tmp));
1274 tmp.tty_major = rocket_driver->major;
1275
1276 for (board = 0; board < 4; board++) {
1277 tmp.rocketModel[board].model = rocketModel[board].model;
1278 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1279 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1280 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1281 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1282 }
1283 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1284 return -EFAULT;
1285 return 0;
1286}
1287
1288static int reset_rm2(struct r_port *info, void __user *arg)
1289{
1290 int reset;
1291
4129a645
AC		 1292 if (!capable(CAP_SYS_ADMIN))
1293 return -EPERM;
1294
1da177e4
LT		 1295 if (copy_from_user(&reset, arg, sizeof (int)))
1296 return -EFAULT;
1297 if (reset)
1298 reset = 1;
1299
1300 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1301 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1302 return -EINVAL;
1303
1304 if (info->ctlp->BusType == isISA)
1305 sModemReset(info->ctlp, info->chan, reset);
1306 else
1307 sPCIModemReset(info->ctlp, info->chan, reset);
1308
1309 return 0;
1310}
1311
1312static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1313{
1314 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1315 return -EFAULT;
1316 return 0;
1317}
1318
1319/* IOCTL call handler into the driver */
6caa76b7 1320static int rp_ioctl(struct tty_struct *tty,
1da177e4
LT		 1321 unsigned int cmd, unsigned long arg)
1322{
c9f19e96 1323 struct r_port *info = tty->driver_data;
1da177e4 1324 void __user *argp = (void __user *)arg;
bdf183aa 1325 int ret = 0;
1da177e4
LT		 1326
1327 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1328 return -ENXIO;
1329
1330 switch (cmd) {
1331 case RCKP_GET_STRUCT:
1332 if (copy_to_user(argp, info, sizeof (struct r_port)))
bdf183aa
AC		 1333 ret = -EFAULT;
1334 break;
1da177e4 1335 case RCKP_GET_CONFIG:
bdf183aa
AC		 1336 ret = get_config(info, argp);
1337 break;
1da177e4 1338 case RCKP_SET_CONFIG:
47b01b3a 1339 ret = set_config(tty, info, argp);
bdf183aa 1340 break;
1da177e4 1341 case RCKP_GET_PORTS:
bdf183aa
AC		 1342 ret = get_ports(info, argp);
1343 break;
1da177e4 1344 case RCKP_RESET_RM2:
bdf183aa
AC		 1345 ret = reset_rm2(info, argp);
1346 break;
1da177e4 1347 case RCKP_GET_VERSION:
bdf183aa
AC		 1348 ret = get_version(info, argp);
1349 break;
1da177e4 1350 default:
bdf183aa 1351 ret = -ENOIOCTLCMD;
1da177e4 1352 }
bdf183aa 1353 return ret;
1da177e4
LT		 1354}
1355
1356static void rp_send_xchar(struct tty_struct *tty, char ch)
1357{
c9f19e96 1358 struct r_port *info = tty->driver_data;
1da177e4
LT		 1359 CHANNEL_t *cp;
1360
1361 if (rocket_paranoia_check(info, "rp_send_xchar"))
1362 return;
1363
1364 cp = &info->channel;
1365 if (sGetTxCnt(cp))
1366 sWriteTxPrioByte(cp, ch);
1367 else
1368 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1369}
1370
1371static void rp_throttle(struct tty_struct *tty)
1372{
c9f19e96 1373 struct r_port *info = tty->driver_data;
1da177e4
LT		 1374
1375#ifdef ROCKET_DEBUG_THROTTLE
1376 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1377 tty->ldisc.chars_in_buffer(tty));
1378#endif
1379
1380 if (rocket_paranoia_check(info, "rp_throttle"))
1381 return;
1382
1da177e4
LT		 1383 if (I_IXOFF(tty))
1384 rp_send_xchar(tty, STOP_CHAR(tty));
1385
1386 sClrRTS(&info->channel);
1387}
1388
1389static void rp_unthrottle(struct tty_struct *tty)
1390{
c9f19e96 1391 struct r_port *info = tty->driver_data;
1da177e4
LT		 1392#ifdef ROCKET_DEBUG_THROTTLE
1393 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1394 tty->ldisc.chars_in_buffer(tty));
1395#endif
1396
1397 if (rocket_paranoia_check(info, "rp_throttle"))
1398 return;
1399
1da177e4
LT		 1400 if (I_IXOFF(tty))
1401 rp_send_xchar(tty, START_CHAR(tty));
1402
1403 sSetRTS(&info->channel);
1404}
1405
1406/*
1407 * ------------------------------------------------------------
1408 * rp_stop() and rp_start()
1409 *
1410 * This routines are called before setting or resetting tty->stopped.
1411 * They enable or disable transmitter interrupts, as necessary.
1412 * ------------------------------------------------------------
1413 */
1414static void rp_stop(struct tty_struct *tty)
1415{
c9f19e96 1416 struct r_port *info = tty->driver_data;
1da177e4
LT		 1417
1418#ifdef ROCKET_DEBUG_FLOW
1419 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1420 info->xmit_cnt, info->xmit_fifo_room);
1421#endif
1422
1423 if (rocket_paranoia_check(info, "rp_stop"))
1424 return;
1425
1426 if (sGetTxCnt(&info->channel))
1427 sDisTransmit(&info->channel);
1428}
1429
1430static void rp_start(struct tty_struct *tty)
1431{
c9f19e96 1432 struct r_port *info = tty->driver_data;
1da177e4
LT		 1433
1434#ifdef ROCKET_DEBUG_FLOW
1435 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1436 info->xmit_cnt, info->xmit_fifo_room);
1437#endif
1438
1439 if (rocket_paranoia_check(info, "rp_stop"))
1440 return;
1441
1442 sEnTransmit(&info->channel);
1443 set_bit((info->aiop * 8) + info->chan,
1444 (void *) &xmit_flags[info->board]);
1445}
1446
1447/*
1448 * rp_wait_until_sent() --- wait until the transmitter is empty
1449 */
1450static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1451{
c9f19e96 1452 struct r_port *info = tty->driver_data;
1da177e4
LT		 1453 CHANNEL_t *cp;
1454 unsigned long orig_jiffies;
1455 int check_time, exit_time;
1456 int txcnt;
1457
1458 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1459 return;
1460
1461 cp = &info->channel;
1462
1463 orig_jiffies = jiffies;
1464#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
68562b79 1465 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1da177e4 1466 jiffies);
68562b79 1467 printk(KERN_INFO "cps=%d...\n", info->cps);
1da177e4
LT		 1468#endif
1469 while (1) {
1470 txcnt = sGetTxCnt(cp);
1471 if (!txcnt) {
1472 if (sGetChanStatusLo(cp) & TXSHRMT)
1473 break;
1474 check_time = (HZ / info->cps) / 5;
1475 } else {
1476 check_time = HZ * txcnt / info->cps;
1477 }
1478 if (timeout) {
1479 exit_time = orig_jiffies + timeout - jiffies;
1480 if (exit_time <= 0)
1481 break;
1482 if (exit_time < check_time)
1483 check_time = exit_time;
1484 }
1485 if (check_time == 0)
1486 check_time = 1;
1487#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
68562b79
JS		 1488 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1489 jiffies, check_time);
1da177e4
LT		 1490#endif
1491 msleep_interruptible(jiffies_to_msecs(check_time));
1492 if (signal_pending(current))
1493 break;
1494 }
cc0a8fbb 1495 __set_current_state(TASK_RUNNING);
1da177e4
LT		 1496#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1497 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1498#endif
1499}
1500
1501/*
1502 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1503 */
1504static void rp_hangup(struct tty_struct *tty)
1505{
1506 CHANNEL_t *cp;
c9f19e96 1507 struct r_port *info = tty->driver_data;
417b6e0e 1508 unsigned long flags;
1da177e4
LT		 1509
1510 if (rocket_paranoia_check(info, "rp_hangup"))
1511 return;
1512
1513#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
68562b79 1514 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1da177e4
LT		 1515#endif
1516 rp_flush_buffer(tty);
417b6e0e
AC		 1517 spin_lock_irqsave(&info->port.lock, flags);
1518 if (info->port.flags & ASYNC_CLOSING) {
1519 spin_unlock_irqrestore(&info->port.lock, flags);
1da177e4 1520 return;
417b6e0e 1521 }
e60a1084 1522 if (info->port.count)
1da177e4
LT		 1523 atomic_dec(&rp_num_ports_open);
1524 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
417b6e0e 1525 spin_unlock_irqrestore(&info->port.lock, flags);
1da177e4 1526
fba85e01 1527 tty_port_hangup(&info->port);
1da177e4
LT		 1528
1529 cp = &info->channel;
1530 sDisRxFIFO(cp);
1531 sDisTransmit(cp);
1532 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1533 sDisCTSFlowCtl(cp);
1534 sDisTxSoftFlowCtl(cp);
1535 sClrTxXOFF(cp);
417b6e0e 1536 clear_bit(ASYNCB_INITIALIZED, &info->port.flags);
1da177e4 1537
e60a1084 1538 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1539}
1540
1541/*
1542 * Exception handler - write char routine. The RocketPort driver uses a
1543 * double-buffering strategy, with the twist that if the in-memory CPU
1544 * buffer is empty, and there's space in the transmit FIFO, the
1545 * writing routines will write directly to transmit FIFO.
1546 * Write buffer and counters protected by spinlocks
1547 */
bbbbb96f 1548static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 1549{
c9f19e96 1550 struct r_port *info = tty->driver_data;
1da177e4
LT		 1551 CHANNEL_t *cp;
1552 unsigned long flags;
1553
1554 if (rocket_paranoia_check(info, "rp_put_char"))
bbbbb96f 1555 return 0;
1da177e4 1556
69f545ea
MK		 1557 /*
1558 * Grab the port write mutex, locking out other processes that try to
1559 * write to this port
1560 */
1561 mutex_lock(&info->write_mtx);
1da177e4
LT		 1562
1563#ifdef ROCKET_DEBUG_WRITE
68562b79 1564 printk(KERN_INFO "rp_put_char %c...\n", ch);
1da177e4
LT		 1565#endif
1566
1567 spin_lock_irqsave(&info->slock, flags);
1568 cp = &info->channel;
1569
ee797069 1570 if (!tty->stopped && info->xmit_fifo_room == 0)
1da177e4
LT		 1571 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1572
ee797069 1573 if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1da177e4
LT		 1574 info->xmit_buf[info->xmit_head++] = ch;
1575 info->xmit_head &= XMIT_BUF_SIZE - 1;
1576 info->xmit_cnt++;
1577 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1578 } else {
1579 sOutB(sGetTxRxDataIO(cp), ch);
1580 info->xmit_fifo_room--;
1581 }
1582 spin_unlock_irqrestore(&info->slock, flags);
69f545ea 1583 mutex_unlock(&info->write_mtx);
bbbbb96f 1584 return 1;
1da177e4
LT		 1585}
1586
1587/*
1588 * Exception handler - write routine, called when user app writes to the device.
69f545ea 1589 * A per port write mutex is used to protect from another process writing to
1da177e4
LT		 1590 * this port at the same time. This other process could be running on the other CPU
1591 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1592 * Spinlocks protect the info xmit members.
1593 */
1594static int rp_write(struct tty_struct *tty,
1595 const unsigned char *buf, int count)
1596{
c9f19e96 1597 struct r_port *info = tty->driver_data;
1da177e4
LT		 1598 CHANNEL_t *cp;
1599 const unsigned char *b;
1600 int c, retval = 0;
1601 unsigned long flags;
1602
1603 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1604 return 0;
1605
1e3e8d91
SS		 1606 if (mutex_lock_interruptible(&info->write_mtx))
1607 return -ERESTARTSYS;
1da177e4
LT		 1608
1609#ifdef ROCKET_DEBUG_WRITE
68562b79 1610 printk(KERN_INFO "rp_write %d chars...\n", count);
1da177e4
LT		 1611#endif
1612 cp = &info->channel;
1613
ee797069 1614 if (!tty->stopped && info->xmit_fifo_room < count)
1da177e4
LT		 1615 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1616
1617 /*
1618 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1619 * into FIFO. Use the write queue for temp storage.
1620 */
ee797069 1621 if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1da177e4
LT		 1622 c = min(count, info->xmit_fifo_room);
1623 b = buf;
1624
1625 /* Push data into FIFO, 2 bytes at a time */
1626 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1627
1628 /* If there is a byte remaining, write it */
1629 if (c & 1)
1630 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1631
1632 retval += c;
1633 buf += c;
1634 count -= c;
1635
1636 spin_lock_irqsave(&info->slock, flags);
1637 info->xmit_fifo_room -= c;
1638 spin_unlock_irqrestore(&info->slock, flags);
1639 }
1640
1641 /* If count is zero, we wrote it all and are done */
1642 if (!count)
1643 goto end;
1644
1645 /* Write remaining data into the port's xmit_buf */
1646 while (1) {
47b01b3a 1647 /* Hung up ? */
a391ad0f 1648 if (!test_bit(ASYNCB_NORMAL_ACTIVE, &info->port.flags))
1da177e4 1649 goto end;
709107fc
HH		 1650 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1651 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1da177e4
LT		 1652 if (c <= 0)
1653 break;
1654
1655 b = buf;
1656 memcpy(info->xmit_buf + info->xmit_head, b, c);
1657
1658 spin_lock_irqsave(&info->slock, flags);
1659 info->xmit_head =
1660 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1661 info->xmit_cnt += c;
1662 spin_unlock_irqrestore(&info->slock, flags);
1663
1664 buf += c;
1665 count -= c;
1666 retval += c;
1667 }
1668
ee797069 1669 if ((retval > 0) && !tty->stopped)
1da177e4
LT		 1670 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1671
1672end:
1673 if (info->xmit_cnt < WAKEUP_CHARS) {
1674 tty_wakeup(tty);
1da177e4
LT		 1675#ifdef ROCKETPORT_HAVE_POLL_WAIT
1676 wake_up_interruptible(&tty->poll_wait);
1677#endif
1678 }
69f545ea 1679 mutex_unlock(&info->write_mtx);
1da177e4
LT		 1680 return retval;
1681}
1682
1683/*
1684 * Return the number of characters that can be sent. We estimate
1685 * only using the in-memory transmit buffer only, and ignore the
1686 * potential space in the transmit FIFO.
1687 */
1688static int rp_write_room(struct tty_struct *tty)
1689{
c9f19e96 1690 struct r_port *info = tty->driver_data;
1da177e4
LT		 1691 int ret;
1692
1693 if (rocket_paranoia_check(info, "rp_write_room"))
1694 return 0;
1695
1696 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1697 if (ret < 0)
1698 ret = 0;
1699#ifdef ROCKET_DEBUG_WRITE
68562b79 1700 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1da177e4
LT		 1701#endif
1702 return ret;
1703}
1704
1705/*
1706 * Return the number of characters in the buffer. Again, this only
1707 * counts those characters in the in-memory transmit buffer.
1708 */
1709static int rp_chars_in_buffer(struct tty_struct *tty)
1710{
c9f19e96 1711 struct r_port *info = tty->driver_data;
1da177e4
LT		 1712
1713 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1714 return 0;
1715
1da177e4 1716#ifdef ROCKET_DEBUG_WRITE
68562b79 1717 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1da177e4
LT		 1718#endif
1719 return info->xmit_cnt;
1720}
1721
1722/*
1723 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1724 * r_port struct for the port. Note that spinlock are used to protect info members,
1725 * do not call this function if the spinlock is already held.
1726 */
1727static void rp_flush_buffer(struct tty_struct *tty)
1728{
c9f19e96 1729 struct r_port *info = tty->driver_data;
1da177e4
LT		 1730 CHANNEL_t *cp;
1731 unsigned long flags;
1732
1733 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1734 return;
1735
1736 spin_lock_irqsave(&info->slock, flags);
1737 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1738 spin_unlock_irqrestore(&info->slock, flags);
1739
1da177e4
LT		 1740#ifdef ROCKETPORT_HAVE_POLL_WAIT
1741 wake_up_interruptible(&tty->poll_wait);
1742#endif
1743 tty_wakeup(tty);
1744
1745 cp = &info->channel;
1746 sFlushTxFIFO(cp);
1747}
1748
1749#ifdef CONFIG_PCI
1750
b9d42395
KC		 1751static DEFINE_PCI_DEVICE_TABLE(rocket_pci_ids) = {
1752 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1753 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1754 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1755 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1756 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1757 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1758 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1759 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1760 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1761 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1762 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1763 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1764 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1765 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1766 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1767 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1768 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1769 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1770 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1771 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1772 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1773 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
8d5916d3
JS		 1774 { }
1775};
1776MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1777
1da177e4
LT		 1778/*
1779 * Called when a PCI card is found. Retrieves and stores model information,
1780 * init's aiopic and serial port hardware.
1781 * Inputs: i is the board number (0-n)
1782 */
f15313bf 1783static __init int register_PCI(int i, struct pci_dev *dev)
1da177e4
LT		 1784{
1785 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1786 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1da177e4
LT		 1787 CONTROLLER_t *ctlp;
1788
1789 int fast_clock = 0;
1790 int altChanRingIndicator = 0;
1791 int ports_per_aiop = 8;
1da177e4
LT		 1792 WordIO_t ConfigIO = 0;
1793 ByteIO_t UPCIRingInd = 0;
1794
b9d42395
KC		 1795 if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
1796 pci_enable_device(dev))
1da177e4
LT		 1797 return 0;
1798
1799 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1da177e4
LT		 1800
1801 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1802 rocketModel[i].loadrm2 = 0;
1803 rocketModel[i].startingPortNumber = nextLineNumber;
1804
1805 /* Depending on the model, set up some config variables */
1806 switch (dev->device) {
1807 case PCI_DEVICE_ID_RP4QUAD:
1da177e4
LT		 1808 max_num_aiops = 1;
1809 ports_per_aiop = 4;
1810 rocketModel[i].model = MODEL_RP4QUAD;
1811 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1812 rocketModel[i].numPorts = 4;
1813 break;
1814 case PCI_DEVICE_ID_RP8OCTA:
1da177e4
LT		 1815 max_num_aiops = 1;
1816 rocketModel[i].model = MODEL_RP8OCTA;
1817 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1818 rocketModel[i].numPorts = 8;
1819 break;
1820 case PCI_DEVICE_ID_URP8OCTA:
1da177e4
LT		 1821 max_num_aiops = 1;
1822 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1823 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1824 rocketModel[i].numPorts = 8;
1825 break;
1826 case PCI_DEVICE_ID_RP8INTF:
1da177e4
LT		 1827 max_num_aiops = 1;
1828 rocketModel[i].model = MODEL_RP8INTF;
1829 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1830 rocketModel[i].numPorts = 8;
1831 break;
1832 case PCI_DEVICE_ID_URP8INTF:
1da177e4
LT		 1833 max_num_aiops = 1;
1834 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1835 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1836 rocketModel[i].numPorts = 8;
1837 break;
1838 case PCI_DEVICE_ID_RP8J:
1da177e4
LT		 1839 max_num_aiops = 1;
1840 rocketModel[i].model = MODEL_RP8J;
1841 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1842 rocketModel[i].numPorts = 8;
1843 break;
1844 case PCI_DEVICE_ID_RP4J:
1da177e4
LT		 1845 max_num_aiops = 1;
1846 ports_per_aiop = 4;
1847 rocketModel[i].model = MODEL_RP4J;
1848 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1849 rocketModel[i].numPorts = 4;
1850 break;
1851 case PCI_DEVICE_ID_RP8SNI:
1da177e4
LT		 1852 max_num_aiops = 1;
1853 rocketModel[i].model = MODEL_RP8SNI;
1854 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1855 rocketModel[i].numPorts = 8;
1856 break;
1857 case PCI_DEVICE_ID_RP16SNI:
1da177e4
LT		 1858 max_num_aiops = 2;
1859 rocketModel[i].model = MODEL_RP16SNI;
1860 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1861 rocketModel[i].numPorts = 16;
1862 break;
1863 case PCI_DEVICE_ID_RP16INTF:
1da177e4
LT		 1864 max_num_aiops = 2;
1865 rocketModel[i].model = MODEL_RP16INTF;
1866 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1867 rocketModel[i].numPorts = 16;
1868 break;
1869 case PCI_DEVICE_ID_URP16INTF:
1da177e4
LT		 1870 max_num_aiops = 2;
1871 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1872 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1873 rocketModel[i].numPorts = 16;
1874 break;
1875 case PCI_DEVICE_ID_CRP16INTF:
1da177e4
LT		 1876 max_num_aiops = 2;
1877 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1878 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1879 rocketModel[i].numPorts = 16;
1880 break;
1881 case PCI_DEVICE_ID_RP32INTF:
1da177e4
LT		 1882 max_num_aiops = 4;
1883 rocketModel[i].model = MODEL_RP32INTF;
1884 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1885 rocketModel[i].numPorts = 32;
1886 break;
1887 case PCI_DEVICE_ID_URP32INTF:
1da177e4
LT		 1888 max_num_aiops = 4;
1889 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1890 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1891 rocketModel[i].numPorts = 32;
1892 break;
1893 case PCI_DEVICE_ID_RPP4:
1da177e4
LT		 1894 max_num_aiops = 1;
1895 ports_per_aiop = 4;
1896 altChanRingIndicator++;
1897 fast_clock++;
1898 rocketModel[i].model = MODEL_RPP4;
1899 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1900 rocketModel[i].numPorts = 4;
1901 break;
1902 case PCI_DEVICE_ID_RPP8:
1da177e4
LT		 1903 max_num_aiops = 2;
1904 ports_per_aiop = 4;
1905 altChanRingIndicator++;
1906 fast_clock++;
1907 rocketModel[i].model = MODEL_RPP8;
1908 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
1909 rocketModel[i].numPorts = 8;
1910 break;
1911 case PCI_DEVICE_ID_RP2_232:
1da177e4
LT		 1912 max_num_aiops = 1;
1913 ports_per_aiop = 2;
1914 altChanRingIndicator++;
1915 fast_clock++;
1916 rocketModel[i].model = MODEL_RP2_232;
1917 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
1918 rocketModel[i].numPorts = 2;
1919 break;
1920 case PCI_DEVICE_ID_RP2_422:
1da177e4
LT		 1921 max_num_aiops = 1;
1922 ports_per_aiop = 2;
1923 altChanRingIndicator++;
1924 fast_clock++;
1925 rocketModel[i].model = MODEL_RP2_422;
1926 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
1927 rocketModel[i].numPorts = 2;
1928 break;
1929 case PCI_DEVICE_ID_RP6M:
1930
1931 max_num_aiops = 1;
1932 ports_per_aiop = 6;
1da177e4 1933
57fedc7a
JS		 1934 /* If revision is 1, the rocketmodem flash must be loaded.
1935 * If it is 2 it is a "socketed" version. */
1936 if (dev->revision == 1) {
1da177e4
LT		 1937 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1938 rocketModel[i].loadrm2 = 1;
1939 } else {
1940 rcktpt_type[i] = ROCKET_TYPE_MODEM;
1941 }
1942
1943 rocketModel[i].model = MODEL_RP6M;
1944 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
1945 rocketModel[i].numPorts = 6;
1946 break;
1947 case PCI_DEVICE_ID_RP4M:
1948 max_num_aiops = 1;
1949 ports_per_aiop = 4;
57fedc7a 1950 if (dev->revision == 1) {
1da177e4
LT		 1951 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1952 rocketModel[i].loadrm2 = 1;
1953 } else {
1954 rcktpt_type[i] = ROCKET_TYPE_MODEM;
1955 }
1956
1957 rocketModel[i].model = MODEL_RP4M;
1958 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
1959 rocketModel[i].numPorts = 4;
1960 break;
1961 default:
1da177e4
LT		 1962 max_num_aiops = 0;
1963 break;
1964 }
1965
1966 /*
1967 * Check for UPCI boards.
1968 */
1969
1970 switch (dev->device) {
1971 case PCI_DEVICE_ID_URP32INTF:
1972 case PCI_DEVICE_ID_URP8INTF:
1973 case PCI_DEVICE_ID_URP16INTF:
1974 case PCI_DEVICE_ID_CRP16INTF:
1975 case PCI_DEVICE_ID_URP8OCTA:
1976 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1977 ConfigIO = pci_resource_start(dev, 1);
1978 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
1979 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1980
1981 /*
1982 * Check for octa or quad cable.
1983 */
1984 if (!
1985 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
1986 PCI_GPIO_CTRL_8PORT)) {
1da177e4
LT		 1987 ports_per_aiop = 4;
1988 rocketModel[i].numPorts = 4;
1989 }
1990 }
1991 break;
1992 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
1da177e4
LT		 1993 max_num_aiops = 1;
1994 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
1995 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
1996 rocketModel[i].numPorts = 8;
1997 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1998 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1999 ConfigIO = pci_resource_start(dev, 1);
2000 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2001 break;
2002 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
1da177e4
LT		 2003 max_num_aiops = 1;
2004 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2005 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2006 rocketModel[i].numPorts = 4;
2007 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2008 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2009 ConfigIO = pci_resource_start(dev, 1);
2010 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2011 break;
2012 default:
2013 break;
2014 }
2015
1da177e4
LT		 2016 if (fast_clock) {
2017 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2018 rp_baud_base[i] = 921600;
2019 } else {
2020 /*
2021 * If support_low_speed is set, use the slow clock
2022 * prescale, which supports 50 bps
2023 */
2024 if (support_low_speed) {
2025 /* mod 9 (divide by 10) prescale */
2026 sClockPrescale = 0x19;
2027 rp_baud_base[i] = 230400;
2028 } else {
25985edc 2029 /* mod 4 (divide by 5) prescale */
1da177e4
LT		 2030 sClockPrescale = 0x14;
2031 rp_baud_base[i] = 460800;
2032 }
2033 }
2034
2035 for (aiop = 0; aiop < max_num_aiops; aiop++)
2036 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2037 ctlp = sCtlNumToCtlPtr(i);
2038 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2039 for (aiop = 0; aiop < max_num_aiops; aiop++)
2040 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2041
68562b79
JS		 2042 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2043 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2044 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2045 rocketModel[i].startingPortNumber,
2046 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
1da177e4
LT		 2047
2048 if (num_aiops <= 0) {
2049 rcktpt_io_addr[i] = 0;
2050 return (0);
2051 }
2052 is_PCI[i] = 1;
2053
2054 /* Reset the AIOPIC, init the serial ports */
2055 for (aiop = 0; aiop < num_aiops; aiop++) {
2056 sResetAiopByNum(ctlp, aiop);
2057 num_chan = ports_per_aiop;
2058 for (chan = 0; chan < num_chan; chan++)
2059 init_r_port(i, aiop, chan, dev);
2060 }
2061
2062 /* Rocket modems must be reset */
2063 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2064 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2065 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2066 num_chan = ports_per_aiop;
2067 for (chan = 0; chan < num_chan; chan++)
2068 sPCIModemReset(ctlp, chan, 1);
48a67f5d 2069 msleep(500);
1da177e4
LT		 2070 for (chan = 0; chan < num_chan; chan++)
2071 sPCIModemReset(ctlp, chan, 0);
48a67f5d 2072 msleep(500);
1da177e4
LT		 2073 rmSpeakerReset(ctlp, rocketModel[i].model);
2074 }
2075 return (1);
2076}
2077
2078/*
2079 * Probes for PCI cards, inits them if found
2080 * Input: board_found = number of ISA boards already found, or the
2081 * starting board number
2082 * Returns: Number of PCI boards found
2083 */
2084static int __init init_PCI(int boards_found)
2085{
2086 struct pci_dev *dev = NULL;
2087 int count = 0;
2088
2089 /* Work through the PCI device list, pulling out ours */
606d099c 2090 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
1da177e4
LT		 2091 if (register_PCI(count + boards_found, dev))
2092 count++;
2093 }
2094 return (count);
2095}
2096
2097#endif /* CONFIG_PCI */
2098
2099/*
2100 * Probes for ISA cards
2101 * Input: i = the board number to look for
2102 * Returns: 1 if board found, 0 else
2103 */
2104static int __init init_ISA(int i)
2105{
2106 int num_aiops, num_chan = 0, total_num_chan = 0;
2107 int aiop, chan;
2108 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2109 CONTROLLER_t *ctlp;
2110 char *type_string;
2111
2112 /* If io_addr is zero, no board configured */
2113 if (rcktpt_io_addr[i] == 0)
2114 return (0);
2115
2116 /* Reserve the IO region */
2117 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
68562b79
JS		 2118 printk(KERN_ERR "Unable to reserve IO region for configured "
2119 "ISA RocketPort at address 0x%lx, board not "
2120 "installed...\n", rcktpt_io_addr[i]);
1da177e4
LT		 2121 rcktpt_io_addr[i] = 0;
2122 return (0);
2123 }
2124
2125 ctlp = sCtlNumToCtlPtr(i);
2126
2127 ctlp->boardType = rcktpt_type[i];
2128
2129 switch (rcktpt_type[i]) {
2130 case ROCKET_TYPE_PC104:
2131 type_string = "(PC104)";
2132 break;
2133 case ROCKET_TYPE_MODEM:
2134 type_string = "(RocketModem)";
2135 break;
2136 case ROCKET_TYPE_MODEMII:
2137 type_string = "(RocketModem II)";
2138 break;
2139 default:
2140 type_string = "";
2141 break;
2142 }
2143
2144 /*
2145 * If support_low_speed is set, use the slow clock prescale,
2146 * which supports 50 bps
2147 */
2148 if (support_low_speed) {
2149 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2150 rp_baud_base[i] = 230400;
2151 } else {
25985edc 2152 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
1da177e4
LT		 2153 rp_baud_base[i] = 460800;
2154 }
2155
2156 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2157 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2158
2159 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2160
2161 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2162 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2163 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2164 }
2165
2166 /* If something went wrong initing the AIOP's release the ISA IO memory */
2167 if (num_aiops <= 0) {
2168 release_region(rcktpt_io_addr[i], 64);
2169 rcktpt_io_addr[i] = 0;
2170 return (0);
2171 }
2172
2173 rocketModel[i].startingPortNumber = nextLineNumber;
2174
2175 for (aiop = 0; aiop < num_aiops; aiop++) {
2176 sResetAiopByNum(ctlp, aiop);
2177 sEnAiop(ctlp, aiop);
2178 num_chan = sGetAiopNumChan(ctlp, aiop);
2179 total_num_chan += num_chan;
2180 for (chan = 0; chan < num_chan; chan++)
2181 init_r_port(i, aiop, chan, NULL);
2182 }
2183 is_PCI[i] = 0;
2184 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2185 num_chan = sGetAiopNumChan(ctlp, 0);
2186 total_num_chan = num_chan;
2187 for (chan = 0; chan < num_chan; chan++)
2188 sModemReset(ctlp, chan, 1);
48a67f5d 2189 msleep(500);
1da177e4
LT		 2190 for (chan = 0; chan < num_chan; chan++)
2191 sModemReset(ctlp, chan, 0);
48a67f5d 2192 msleep(500);
1da177e4
LT		 2193 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2194 } else {
2195 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2196 }
2197 rocketModel[i].numPorts = total_num_chan;
2198 rocketModel[i].model = MODEL_ISA;
2199
2200 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2201 i, rcktpt_io_addr[i], num_aiops, type_string);
2202
2203 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2204 rocketModel[i].modelString,
2205 rocketModel[i].startingPortNumber,
2206 rocketModel[i].startingPortNumber +
2207 rocketModel[i].numPorts - 1);
2208
2209 return (1);
2210}
2211
b68e31d0 2212static const struct tty_operations rocket_ops = {
1da177e4
LT		 2213 .open = rp_open,
2214 .close = rp_close,
2215 .write = rp_write,
2216 .put_char = rp_put_char,
2217 .write_room = rp_write_room,
2218 .chars_in_buffer = rp_chars_in_buffer,
2219 .flush_buffer = rp_flush_buffer,
2220 .ioctl = rp_ioctl,
2221 .throttle = rp_throttle,
2222 .unthrottle = rp_unthrottle,
2223 .set_termios = rp_set_termios,
2224 .stop = rp_stop,
2225 .start = rp_start,
2226 .hangup = rp_hangup,
2227 .break_ctl = rp_break,
2228 .send_xchar = rp_send_xchar,
2229 .wait_until_sent = rp_wait_until_sent,
2230 .tiocmget = rp_tiocmget,
2231 .tiocmset = rp_tiocmset,
2232};
2233
31f35939
AC		 2234static const struct tty_port_operations rocket_port_ops = {
2235 .carrier_raised = carrier_raised,
fcc8ac18 2236 .dtr_rts = dtr_rts,
31f35939
AC		 2237};
2238
1da177e4
LT		 2239/*
2240 * The module "startup" routine; it's run when the module is loaded.
2241 */
d269cdd0 2242static int __init rp_init(void)
1da177e4 2243{
4384a3fa 2244 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
1da177e4
LT		 2245
2246 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2247 ROCKET_VERSION, ROCKET_DATE);
2248
2249 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2250 if (!rocket_driver)
4384a3fa 2251 goto err;
1da177e4 2252
1da177e4
LT		 2253 /*
2254 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2255 * zero, use the default controller IO address of board1 + 0x40.
2256 */
2257 if (board1) {
2258 if (controller == 0)
2259 controller = board1 + 0x40;
2260 } else {
2261 controller = 0; /* Used as a flag, meaning no ISA boards */
2262 }
2263
2264 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2265 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
4384a3fa
JS		 2266 printk(KERN_ERR "Unable to reserve IO region for first "
2267 "configured ISA RocketPort controller 0x%lx. "
2268 "Driver exiting\n", controller);
2269 ret = -EBUSY;
2270 goto err_tty;
1da177e4
LT		 2271 }
2272
2273 /* Store ISA variable retrieved from command line or .conf file. */
2274 rcktpt_io_addr[0] = board1;
2275 rcktpt_io_addr[1] = board2;
2276 rcktpt_io_addr[2] = board3;
2277 rcktpt_io_addr[3] = board4;
2278
2279 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2280 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2281 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2282 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2283 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2284 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2285 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2286 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2287
2288 /*
2289 * Set up the tty driver structure and then register this
2290 * driver with the tty layer.
2291 */
2292
331b8319 2293 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
1da177e4
LT		 2294 rocket_driver->name = "ttyR";
2295 rocket_driver->driver_name = "Comtrol RocketPort";
2296 rocket_driver->major = TTY_ROCKET_MAJOR;
2297 rocket_driver->minor_start = 0;
2298 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2299 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2300 rocket_driver->init_termios = tty_std_termios;
2301 rocket_driver->init_termios.c_cflag =
2302 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 2303 rocket_driver->init_termios.c_ispeed = 9600;
2304 rocket_driver->init_termios.c_ospeed = 9600;
1da177e4 2305#ifdef ROCKET_SOFT_FLOW
ac6aec2f 2306 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
1da177e4
LT		 2307#endif
2308 tty_set_operations(rocket_driver, &rocket_ops);
2309
4384a3fa
JS		 2310 ret = tty_register_driver(rocket_driver);
2311 if (ret < 0) {
2312 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
713efa9a 2313 goto err_controller;
1da177e4
LT		 2314 }
2315
2316#ifdef ROCKET_DEBUG_OPEN
2317 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2318#endif
2319
2320 /*
2321 * OK, let's probe each of the controllers looking for boards. Any boards found
2322 * will be initialized here.
2323 */
2324 isa_boards_found = 0;
2325 pci_boards_found = 0;
2326
2327 for (i = 0; i < NUM_BOARDS; i++) {
2328 if (init_ISA(i))
2329 isa_boards_found++;
2330 }
2331
2332#ifdef CONFIG_PCI
2333 if (isa_boards_found < NUM_BOARDS)
2334 pci_boards_found = init_PCI(isa_boards_found);
2335#endif
2336
2337 max_board = pci_boards_found + isa_boards_found;
2338
2339 if (max_board == 0) {
4384a3fa
JS		 2340 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2341 ret = -ENXIO;
2342 goto err_ttyu;
1da177e4
LT		 2343 }
2344
2345 return 0;
4384a3fa
JS		 2346err_ttyu:
2347 tty_unregister_driver(rocket_driver);
713efa9a
DC		 2348err_controller:
2349 if (controller)
2350 release_region(controller, 4);
4384a3fa
JS		 2351err_tty:
2352 put_tty_driver(rocket_driver);
2353err:
2354 return ret;
1da177e4
LT		 2355}
2356
1da177e4
LT		 2357
2358static void rp_cleanup_module(void)
2359{
2360 int retval;
2361 int i;
2362
2363 del_timer_sync(&rocket_timer);
2364
2365 retval = tty_unregister_driver(rocket_driver);
2366 if (retval)
68562b79 2367 printk(KERN_ERR "Error %d while trying to unregister "
1da177e4 2368 "rocketport driver\n", -retval);
1da177e4 2369
735d5661 2370 for (i = 0; i < MAX_RP_PORTS; i++)
ac6aec2f
JS		 2371 if (rp_table[i]) {
2372 tty_unregister_device(rocket_driver, i);
191c5f10 2373 tty_port_destroy(&rp_table[i]->port);
ac6aec2f
JS		 2374 kfree(rp_table[i]);
2375 }
2376
2377 put_tty_driver(rocket_driver);
1da177e4
LT		 2378
2379 for (i = 0; i < NUM_BOARDS; i++) {
2380 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2381 continue;
2382 release_region(rcktpt_io_addr[i], 64);
2383 }
2384 if (controller)
2385 release_region(controller, 4);
2386}
1da177e4 2387
1da177e4
LT		 2388/***************************************************************************
2389Function: sInitController
2390Purpose: Initialization of controller global registers and controller
2391 structure.
2392Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2393 IRQNum,Frequency,PeriodicOnly)
2394 CONTROLLER_T *CtlP; Ptr to controller structure
2395 int CtlNum; Controller number
2396 ByteIO_t MudbacIO; Mudbac base I/O address.
2397 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2398 This list must be in the order the AIOPs will be found on the
2399 controller. Once an AIOP in the list is not found, it is
2400 assumed that there are no more AIOPs on the controller.
2401 int AiopIOListSize; Number of addresses in AiopIOList
2402 int IRQNum; Interrupt Request number. Can be any of the following:
2403 0: Disable global interrupts
2404 3: IRQ 3
2405 4: IRQ 4
2406 5: IRQ 5
2407 9: IRQ 9
2408 10: IRQ 10
2409 11: IRQ 11
2410 12: IRQ 12
2411 15: IRQ 15
2412 Byte_t Frequency: A flag identifying the frequency
2413 of the periodic interrupt, can be any one of the following:
2414 FREQ_DIS - periodic interrupt disabled
2415 FREQ_137HZ - 137 Hertz
2416 FREQ_69HZ - 69 Hertz
2417 FREQ_34HZ - 34 Hertz
2418 FREQ_17HZ - 17 Hertz
2419 FREQ_9HZ - 9 Hertz
2420 FREQ_4HZ - 4 Hertz
2421 If IRQNum is set to 0 the Frequency parameter is
2422 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2423 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2424 interrupt are to be blocked.
f15313bf 2425 0 is both the periodic interrupt and
1da177e4
LT		 2426 other channel interrupts are allowed.
2427 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2428 overidden, it is forced to a value of 0.
1da177e4
LT		 2429Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2430 initialization failed.
2431
2432Comments:
2433 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2434 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2435
2436 If interrupts are to be completely disabled set IRQNum to 0.
2437
f15313bf 2438 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2439 invalid combination.
2440
2441 This function performs initialization of global interrupt modes,
2442 but it does not actually enable global interrupts. To enable
2443 and disable global interrupts use functions sEnGlobalInt() and
2444 sDisGlobalInt(). Enabling of global interrupts is normally not
2445 done until all other initializations are complete.
2446
2447 Even if interrupts are globally enabled, they must also be
2448 individually enabled for each channel that is to generate
2449 interrupts.
2450
2451Warnings: No range checking on any of the parameters is done.
2452
2453 No context switches are allowed while executing this function.
2454
2455 After this function all AIOPs on the controller are disabled,
2456 they can be enabled with sEnAiop().
2457*/
f15313bf
AB		 2458static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2459 ByteIO_t * AiopIOList, int AiopIOListSize,
2460 int IRQNum, Byte_t Frequency, int PeriodicOnly)
1da177e4
LT		 2461{
2462 int i;
2463 ByteIO_t io;
2464 int done;
2465
2466 CtlP->AiopIntrBits = aiop_intr_bits;
2467 CtlP->AltChanRingIndicator = 0;
2468 CtlP->CtlNum = CtlNum;
2469 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2470 CtlP->BusType = isISA;
2471 CtlP->MBaseIO = MudbacIO;
2472 CtlP->MReg1IO = MudbacIO + 1;
2473 CtlP->MReg2IO = MudbacIO + 2;
2474 CtlP->MReg3IO = MudbacIO + 3;
2475#if 1
2476 CtlP->MReg2 = 0; /* interrupt disable */
2477 CtlP->MReg3 = 0; /* no periodic interrupts */
2478#else
2479 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2480 CtlP->MReg2 = 0; /* interrupt disable */
2481 CtlP->MReg3 = 0; /* no periodic interrupts */
2482 } else {
2483 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2484 CtlP->MReg3 = Frequency; /* set frequency */
2485 if (PeriodicOnly) { /* periodic interrupt only */
2486 CtlP->MReg3 |= PERIODIC_ONLY;
2487 }
2488 }
2489#endif
2490 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2491 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2492 sControllerEOI(CtlP); /* clear EOI if warm init */
2493 /* Init AIOPs */
2494 CtlP->NumAiop = 0;
2495 for (i = done = 0; i < AiopIOListSize; i++) {
2496 io = AiopIOList[i];
2497 CtlP->AiopIO[i] = (WordIO_t) io;
2498 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2499 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2500 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2501 if (done)
2502 continue;
2503 sEnAiop(CtlP, i); /* enable the AIOP */
2504 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2505 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2506 done = 1; /* done looking for AIOPs */
2507 else {
2508 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2509 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2510 sOutB(io + _INDX_DATA, sClockPrescale);
2511 CtlP->NumAiop++; /* bump count of AIOPs */
2512 }
2513 sDisAiop(CtlP, i); /* disable AIOP */
2514 }
2515
2516 if (CtlP->NumAiop == 0)
2517 return (-1);
2518 else
2519 return (CtlP->NumAiop);
2520}
2521
f678c440 2522#ifdef CONFIG_PCI
1da177e4
LT		 2523/***************************************************************************
2524Function: sPCIInitController
2525Purpose: Initialization of controller global registers and controller
2526 structure.
2527Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2528 IRQNum,Frequency,PeriodicOnly)
2529 CONTROLLER_T *CtlP; Ptr to controller structure
2530 int CtlNum; Controller number
2531 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2532 This list must be in the order the AIOPs will be found on the
2533 controller. Once an AIOP in the list is not found, it is
2534 assumed that there are no more AIOPs on the controller.
2535 int AiopIOListSize; Number of addresses in AiopIOList
2536 int IRQNum; Interrupt Request number. Can be any of the following:
2537 0: Disable global interrupts
2538 3: IRQ 3
2539 4: IRQ 4
2540 5: IRQ 5
2541 9: IRQ 9
2542 10: IRQ 10
2543 11: IRQ 11
2544 12: IRQ 12
2545 15: IRQ 15
2546 Byte_t Frequency: A flag identifying the frequency
2547 of the periodic interrupt, can be any one of the following:
2548 FREQ_DIS - periodic interrupt disabled
2549 FREQ_137HZ - 137 Hertz
2550 FREQ_69HZ - 69 Hertz
2551 FREQ_34HZ - 34 Hertz
2552 FREQ_17HZ - 17 Hertz
2553 FREQ_9HZ - 9 Hertz
2554 FREQ_4HZ - 4 Hertz
2555 If IRQNum is set to 0 the Frequency parameter is
2556 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2557 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2558 interrupt are to be blocked.
f15313bf 2559 0 is both the periodic interrupt and
1da177e4
LT		 2560 other channel interrupts are allowed.
2561 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2562 overidden, it is forced to a value of 0.
1da177e4
LT		 2563Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2564 initialization failed.
2565
2566Comments:
2567 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2568 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2569
2570 If interrupts are to be completely disabled set IRQNum to 0.
2571
f15313bf 2572 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2573 invalid combination.
2574
2575 This function performs initialization of global interrupt modes,
2576 but it does not actually enable global interrupts. To enable
2577 and disable global interrupts use functions sEnGlobalInt() and
2578 sDisGlobalInt(). Enabling of global interrupts is normally not
2579 done until all other initializations are complete.
2580
2581 Even if interrupts are globally enabled, they must also be
2582 individually enabled for each channel that is to generate
2583 interrupts.
2584
2585Warnings: No range checking on any of the parameters is done.
2586
2587 No context switches are allowed while executing this function.
2588
2589 After this function all AIOPs on the controller are disabled,
2590 they can be enabled with sEnAiop().
2591*/
f15313bf
AB		 2592static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2593 ByteIO_t * AiopIOList, int AiopIOListSize,
2594 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2595 int PeriodicOnly, int altChanRingIndicator,
2596 int UPCIRingInd)
1da177e4
LT		 2597{
2598 int i;
2599 ByteIO_t io;
2600
2601 CtlP->AltChanRingIndicator = altChanRingIndicator;
2602 CtlP->UPCIRingInd = UPCIRingInd;
2603 CtlP->CtlNum = CtlNum;
2604 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2605 CtlP->BusType = isPCI; /* controller release 1 */
2606
2607 if (ConfigIO) {
2608 CtlP->isUPCI = 1;
2609 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2610 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2611 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2612 } else {
2613 CtlP->isUPCI = 0;
2614 CtlP->PCIIO =
2615 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2616 CtlP->AiopIntrBits = aiop_intr_bits;
2617 }
2618
2619 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2620 /* Init AIOPs */
2621 CtlP->NumAiop = 0;
2622 for (i = 0; i < AiopIOListSize; i++) {
2623 io = AiopIOList[i];
2624 CtlP->AiopIO[i] = (WordIO_t) io;
2625 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2626
2627 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2628 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2629 break; /* done looking for AIOPs */
2630
2631 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2632 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2633 sOutB(io + _INDX_DATA, sClockPrescale);
2634 CtlP->NumAiop++; /* bump count of AIOPs */
2635 }
2636
2637 if (CtlP->NumAiop == 0)
2638 return (-1);
2639 else
2640 return (CtlP->NumAiop);
2641}
2642
f678c440
JS		 2643/* Resets the speaker controller on RocketModem II and III devices */
2644static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
2645{
2646 ByteIO_t addr;
2647
2648 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
2649 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
2650 addr = CtlP->AiopIO[0] + 0x4F;
2651 sOutB(addr, 0);
2652 }
2653
2654 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
2655 if ((model == MODEL_UPCI_RM3_8PORT)
2656 || (model == MODEL_UPCI_RM3_4PORT)) {
2657 addr = CtlP->AiopIO[0] + 0x88;
2658 sOutB(addr, 0);
2659 }
2660}
2661#endif
2662
1da177e4
LT		 2663/***************************************************************************
2664Function: sReadAiopID
2665Purpose: Read the AIOP idenfication number directly from an AIOP.
2666Call: sReadAiopID(io)
2667 ByteIO_t io: AIOP base I/O address
2668Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2669 is replace by an identifying number.
2670 Flag AIOPID_NULL if no valid AIOP is found
2671Warnings: No context switches are allowed while executing this function.
2672
2673*/
f15313bf 2674static int sReadAiopID(ByteIO_t io)
1da177e4
LT		 2675{
2676 Byte_t AiopID; /* ID byte from AIOP */
2677
2678 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2679 sOutB(io + _CMD_REG, 0x0);
2680 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2681 if (AiopID == 0x06)
2682 return (1);
2683 else /* AIOP does not exist */
2684 return (-1);
2685}
2686
2687/***************************************************************************
2688Function: sReadAiopNumChan
2689Purpose: Read the number of channels available in an AIOP directly from
2690 an AIOP.
2691Call: sReadAiopNumChan(io)
2692 WordIO_t io: AIOP base I/O address
2693Return: int: The number of channels available
2694Comments: The number of channels is determined by write/reads from identical
2695 offsets within the SRAM address spaces for channels 0 and 4.
2696 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2697 AIOP, otherwise it is an 8 channel.
2698Warnings: No context switches are allowed while executing this function.
2699*/
f15313bf 2700static int sReadAiopNumChan(WordIO_t io)
1da177e4
LT		 2701{
2702 Word_t x;
2703 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2704
2705 /* write to chan 0 SRAM */
457fb605 2706 out32((DWordIO_t) io + _INDX_ADDR, R);
1da177e4
LT		 2707 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2708 x = sInW(io + _INDX_DATA);
2709 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2710 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2711 return (8);
2712 else
2713 return (4);
2714}
2715
2716/***************************************************************************
2717Function: sInitChan
2718Purpose: Initialization of a channel and channel structure
2719Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2720 CONTROLLER_T *CtlP; Ptr to controller structure
2721 CHANNEL_T *ChP; Ptr to channel structure
2722 int AiopNum; AIOP number within controller
2723 int ChanNum; Channel number within AIOP
f15313bf 2724Return: int: 1 if initialization succeeded, 0 if it fails because channel
1da177e4
LT		 2725 number exceeds number of channels available in AIOP.
2726Comments: This function must be called before a channel can be used.
2727Warnings: No range checking on any of the parameters is done.
2728
2729 No context switches are allowed while executing this function.
2730*/
f15313bf
AB		 2731static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2732 int ChanNum)
1da177e4
LT		 2733{
2734 int i;
2735 WordIO_t AiopIO;
2736 WordIO_t ChIOOff;
2737 Byte_t *ChR;
2738 Word_t ChOff;
2739 static Byte_t R[4];
2740 int brd9600;
2741
2742 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
f15313bf 2743 return 0; /* exceeds num chans in AIOP */
1da177e4
LT		 2744
2745 /* Channel, AIOP, and controller identifiers */
2746 ChP->CtlP = CtlP;
2747 ChP->ChanID = CtlP->AiopID[AiopNum];
2748 ChP->AiopNum = AiopNum;
2749 ChP->ChanNum = ChanNum;
2750
2751 /* Global direct addresses */
2752 AiopIO = CtlP->AiopIO[AiopNum];
2753 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2754 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2755 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2756 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2757 ChP->IndexData = AiopIO + _INDX_DATA;
2758
2759 /* Channel direct addresses */
2760 ChIOOff = AiopIO + ChP->ChanNum * 2;
2761 ChP->TxRxData = ChIOOff + _TD0;
2762 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2763 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2764 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2765
2766 /* Initialize the channel from the RData array */
2767 for (i = 0; i < RDATASIZE; i += 4) {
2768 R[0] = RData[i];
2769 R[1] = RData[i + 1] + 0x10 * ChanNum;
2770 R[2] = RData[i + 2];
2771 R[3] = RData[i + 3];
457fb605 2772 out32(ChP->IndexAddr, R);
1da177e4
LT		 2773 }
2774
2775 ChR = ChP->R;
2776 for (i = 0; i < RREGDATASIZE; i += 4) {
2777 ChR[i] = RRegData[i];
2778 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2779 ChR[i + 2] = RRegData[i + 2];
2780 ChR[i + 3] = RRegData[i + 3];
2781 }
2782
2783 /* Indexed registers */
2784 ChOff = (Word_t) ChanNum *0x1000;
2785
2786 if (sClockPrescale == 0x14)
2787 brd9600 = 47;
2788 else
2789 brd9600 = 23;
2790
2791 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2792 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2793 ChP->BaudDiv[2] = (Byte_t) brd9600;
2794 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
457fb605 2795 out32(ChP->IndexAddr, ChP->BaudDiv);
1da177e4
LT		 2796
2797 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2798 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2799 ChP->TxControl[2] = 0;
2800 ChP->TxControl[3] = 0;
457fb605 2801 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 2802
2803 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2804 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2805 ChP->RxControl[2] = 0;
2806 ChP->RxControl[3] = 0;
457fb605 2807 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 2808
2809 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2810 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2811 ChP->TxEnables[2] = 0;
2812 ChP->TxEnables[3] = 0;
457fb605 2813 out32(ChP->IndexAddr, ChP->TxEnables);
1da177e4
LT		 2814
2815 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2816 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2817 ChP->TxCompare[2] = 0;
2818 ChP->TxCompare[3] = 0;
457fb605 2819 out32(ChP->IndexAddr, ChP->TxCompare);
1da177e4
LT		 2820
2821 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2822 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2823 ChP->TxReplace1[2] = 0;
2824 ChP->TxReplace1[3] = 0;
457fb605 2825 out32(ChP->IndexAddr, ChP->TxReplace1);
1da177e4
LT		 2826
2827 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2828 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2829 ChP->TxReplace2[2] = 0;
2830 ChP->TxReplace2[3] = 0;
457fb605 2831 out32(ChP->IndexAddr, ChP->TxReplace2);
1da177e4
LT		 2832
2833 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2834 ChP->TxFIFO = ChOff + _TX_FIFO;
2835
2836 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2837 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2838 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2839 sOutW(ChP->IndexData, 0);
2840 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2841 ChP->RxFIFO = ChOff + _RX_FIFO;
2842
2843 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2844 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2845 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2846 sOutW(ChP->IndexData, 0);
2847 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2848 sOutW(ChP->IndexData, 0);
2849 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2850 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2851 sOutB(ChP->IndexData, 0);
2852 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2853 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2854 sOutB(ChP->IndexData, 0);
2855 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2856 sEnRxProcessor(ChP); /* start the Rx processor */
2857
f15313bf 2858 return 1;
1da177e4
LT		 2859}
2860
2861/***************************************************************************
2862Function: sStopRxProcessor
2863Purpose: Stop the receive processor from processing a channel.
2864Call: sStopRxProcessor(ChP)
2865 CHANNEL_T *ChP; Ptr to channel structure
2866
2867Comments: The receive processor can be started again with sStartRxProcessor().
2868 This function causes the receive processor to skip over the
2869 stopped channel. It does not stop it from processing other channels.
2870
2871Warnings: No context switches are allowed while executing this function.
2872
2873 Do not leave the receive processor stopped for more than one
2874 character time.
2875
2876 After calling this function a delay of 4 uS is required to ensure
2877 that the receive processor is no longer processing this channel.
2878*/
f15313bf 2879static void sStopRxProcessor(CHANNEL_T * ChP)
1da177e4
LT		 2880{
2881 Byte_t R[4];
2882
2883 R[0] = ChP->R[0];
2884 R[1] = ChP->R[1];
2885 R[2] = 0x0a;
2886 R[3] = ChP->R[3];
457fb605 2887 out32(ChP->IndexAddr, R);
1da177e4
LT		 2888}
2889
2890/***************************************************************************
2891Function: sFlushRxFIFO
2892Purpose: Flush the Rx FIFO
2893Call: sFlushRxFIFO(ChP)
2894 CHANNEL_T *ChP; Ptr to channel structure
2895Return: void
2896Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2897 while it is being flushed the receive processor is stopped
2898 and the transmitter is disabled. After these operations a
2899 4 uS delay is done before clearing the pointers to allow
2900 the receive processor to stop. These items are handled inside
2901 this function.
2902Warnings: No context switches are allowed while executing this function.
2903*/
f15313bf 2904static void sFlushRxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 2905{
2906 int i;
2907 Byte_t Ch; /* channel number within AIOP */
f15313bf 2908 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
1da177e4
LT		 2909
2910 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2911 return; /* don't need to flush */
2912
f15313bf 2913 RxFIFOEnabled = 0;
1da177e4 2914 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
f15313bf 2915 RxFIFOEnabled = 1;
1da177e4
LT		 2916 sDisRxFIFO(ChP); /* disable it */
2917 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2918 sInB(ChP->IntChan); /* depends on bus i/o timing */
2919 }
2920 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2921 Ch = (Byte_t) sGetChanNum(ChP);
2922 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2923 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2924 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2925 sOutW(ChP->IndexData, 0);
2926 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2927 sOutW(ChP->IndexData, 0);
2928 if (RxFIFOEnabled)
2929 sEnRxFIFO(ChP); /* enable Rx FIFO */
2930}
2931
2932/***************************************************************************
2933Function: sFlushTxFIFO
2934Purpose: Flush the Tx FIFO
2935Call: sFlushTxFIFO(ChP)
2936 CHANNEL_T *ChP; Ptr to channel structure
2937Return: void
2938Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2939 while it is being flushed the receive processor is stopped
2940 and the transmitter is disabled. After these operations a
2941 4 uS delay is done before clearing the pointers to allow
2942 the receive processor to stop. These items are handled inside
2943 this function.
2944Warnings: No context switches are allowed while executing this function.
2945*/
f15313bf 2946static void sFlushTxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 2947{
2948 int i;
2949 Byte_t Ch; /* channel number within AIOP */
f15313bf 2950 int TxEnabled; /* 1 if transmitter enabled */
1da177e4
LT		 2951
2952 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2953 return; /* don't need to flush */
2954
f15313bf 2955 TxEnabled = 0;
1da177e4 2956 if (ChP->TxControl[3] & TX_ENABLE) {
f15313bf 2957 TxEnabled = 1;
1da177e4
LT		 2958 sDisTransmit(ChP); /* disable transmitter */
2959 }
2960 sStopRxProcessor(ChP); /* stop Rx processor */
2961 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2962 sInB(ChP->IntChan); /* depends on bus i/o timing */
2963 Ch = (Byte_t) sGetChanNum(ChP);
2964 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2965 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2966 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2967 sOutW(ChP->IndexData, 0);
2968 if (TxEnabled)
2969 sEnTransmit(ChP); /* enable transmitter */
2970 sStartRxProcessor(ChP); /* restart Rx processor */
2971}
2972
2973/***************************************************************************
2974Function: sWriteTxPrioByte
2975Purpose: Write a byte of priority transmit data to a channel
2976Call: sWriteTxPrioByte(ChP,Data)
2977 CHANNEL_T *ChP; Ptr to channel structure
2978 Byte_t Data; The transmit data byte
2979
2980Return: int: 1 if the bytes is successfully written, otherwise 0.
2981
2982Comments: The priority byte is transmitted before any data in the Tx FIFO.
2983
2984Warnings: No context switches are allowed while executing this function.
2985*/
f15313bf 2986static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
1da177e4
LT		 2987{
2988 Byte_t DWBuf[4]; /* buffer for double word writes */
2989 Word_t *WordPtr; /* must be far because Win SS != DS */
2990 register DWordIO_t IndexAddr;
2991
2992 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2993 IndexAddr = ChP->IndexAddr;
2994 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2995 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2996 return (0); /* nothing sent */
2997
2998 WordPtr = (Word_t *) (&DWBuf[0]);
2999 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3000
3001 DWBuf[2] = Data; /* data byte value */
457fb605 3002 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 3003
3004 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3005
3006 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3007 DWBuf[3] = 0; /* priority buffer pointer */
457fb605 3008 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 3009 } else { /* write it to Tx FIFO */
3010
3011 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3012 }
3013 return (1); /* 1 byte sent */
3014}
3015
3016/***************************************************************************
3017Function: sEnInterrupts
3018Purpose: Enable one or more interrupts for a channel
3019Call: sEnInterrupts(ChP,Flags)
3020 CHANNEL_T *ChP; Ptr to channel structure
3021 Word_t Flags: Interrupt enable flags, can be any combination
3022 of the following flags:
3023 TXINT_EN: Interrupt on Tx FIFO empty
3024 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3025 sSetRxTrigger())
3026 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3027 MCINT_EN: Interrupt on modem input change
3028 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3029 Interrupt Channel Register.
3030Return: void
3031Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3032 enabled. If an interrupt enable flag is not set in Flags, that
3033 interrupt will not be changed. Interrupts can be disabled with
3034 function sDisInterrupts().
3035
3036 This function sets the appropriate bit for the channel in the AIOP's
3037 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3038 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3039
3040 Interrupts must also be globally enabled before channel interrupts
3041 will be passed on to the host. This is done with function
3042 sEnGlobalInt().
3043
3044 In some cases it may be desirable to disable interrupts globally but
3045 enable channel interrupts. This would allow the global interrupt
3046 status register to be used to determine which AIOPs need service.
3047*/
f15313bf 3048static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3049{
3050 Byte_t Mask; /* Interrupt Mask Register */
3051
3052 ChP->RxControl[2] |=
3053 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3054
457fb605 3055 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 3056
3057 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3058
457fb605 3059 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3060
3061 if (Flags & CHANINT_EN) {
3062 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3063 sOutB(ChP->IntMask, Mask);
3064 }
3065}
3066
3067/***************************************************************************
3068Function: sDisInterrupts
3069Purpose: Disable one or more interrupts for a channel
3070Call: sDisInterrupts(ChP,Flags)
3071 CHANNEL_T *ChP; Ptr to channel structure
3072 Word_t Flags: Interrupt flags, can be any combination
3073 of the following flags:
3074 TXINT_EN: Interrupt on Tx FIFO empty
3075 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3076 sSetRxTrigger())
3077 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3078 MCINT_EN: Interrupt on modem input change
3079 CHANINT_EN: Disable channel interrupt signal to the
3080 AIOP's Interrupt Channel Register.
3081Return: void
3082Comments: If an interrupt flag is set in Flags, that interrupt will be
3083 disabled. If an interrupt flag is not set in Flags, that
3084 interrupt will not be changed. Interrupts can be enabled with
3085 function sEnInterrupts().
3086
3087 This function clears the appropriate bit for the channel in the AIOP's
3088 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3089 this channel's bit from being set in the AIOP's Interrupt Channel
3090 Register.
3091*/
f15313bf 3092static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3093{
3094 Byte_t Mask; /* Interrupt Mask Register */
3095
3096 ChP->RxControl[2] &=
3097 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
457fb605 3098 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4 3099 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
457fb605 3100 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3101
3102 if (Flags & CHANINT_EN) {
3103 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3104 sOutB(ChP->IntMask, Mask);
3105 }
3106}
3107
f15313bf 3108static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
1da177e4
LT		 3109{
3110 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3111}
3112
3113/*
3114 * Not an official SSCI function, but how to reset RocketModems.
3115 * ISA bus version
3116 */
f15313bf 3117static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3118{
3119 ByteIO_t addr;
3120 Byte_t val;
3121
3122 addr = CtlP->AiopIO[0] + 0x400;
3123 val = sInB(CtlP->MReg3IO);
3124 /* if AIOP[1] is not enabled, enable it */
3125 if ((val & 2) == 0) {
3126 val = sInB(CtlP->MReg2IO);
3127 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3128 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3129 }
3130
3131 sEnAiop(CtlP, 1);
3132 if (!on)
3133 addr += 8;
3134 sOutB(addr + chan, 0); /* apply or remove reset */
3135 sDisAiop(CtlP, 1);
3136}
3137
3138/*
3139 * Not an official SSCI function, but how to reset RocketModems.
3140 * PCI bus version
3141 */
f15313bf 3142static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3143{
3144 ByteIO_t addr;
3145
3146 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3147 if (!on)
3148 addr += 8;
3149 sOutB(addr + chan, 0); /* apply or remove reset */
3150}
3151
1da177e4
LT		 3152/* Returns the line number given the controller (board), aiop and channel number */
3153static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3154{
3155 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3156}
3157
3158/*
3159 * Stores the line number associated with a given controller (board), aiop
3160 * and channel number.
3161 * Returns: The line number assigned
3162 */
3163static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3164{
3165 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3166 return (nextLineNumber - 1);
3167}
Linux 6.x block layer and io_uring tree(s)