Commit | Line | Data |
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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1da177e4 LT |
2 | /* |
3 | * mxser.c -- MOXA Smartio/Industio family multiport serial driver. | |
4 | * | |
80ff8a80 JS |
5 | * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com). |
6 | * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com> | |
1da177e4 | 7 | * |
1c45607a JS |
8 | * This code is loosely based on the 1.8 moxa driver which is based on |
9 | * Linux serial driver, written by Linus Torvalds, Theodore T'so and | |
10 | * others. | |
1da177e4 | 11 | * |
1da177e4 | 12 | * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox |
8eb04cf3 AC |
13 | * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on |
14 | * www.moxa.com. | |
1da177e4 | 15 | * - Fixed x86_64 cleanness |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 | 18 | #include <linux/module.h> |
1da177e4 LT |
19 | #include <linux/errno.h> |
20 | #include <linux/signal.h> | |
21 | #include <linux/sched.h> | |
22 | #include <linux/timer.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/tty.h> | |
25 | #include <linux/tty_flip.h> | |
26 | #include <linux/serial.h> | |
27 | #include <linux/serial_reg.h> | |
28 | #include <linux/major.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/fcntl.h> | |
31 | #include <linux/ptrace.h> | |
1da177e4 LT |
32 | #include <linux/ioport.h> |
33 | #include <linux/mm.h> | |
1da177e4 LT |
34 | #include <linux/delay.h> |
35 | #include <linux/pci.h> | |
1977f032 | 36 | #include <linux/bitops.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
5a3c6b25 | 38 | #include <linux/ratelimit.h> |
1da177e4 | 39 | |
1da177e4 LT |
40 | #include <asm/io.h> |
41 | #include <asm/irq.h> | |
7c0f6ba6 | 42 | #include <linux/uaccess.h> |
1da177e4 | 43 | |
4463cc5b JS |
44 | /* |
45 | * Semi-public control interfaces | |
46 | */ | |
47 | ||
48 | /* | |
49 | * MOXA ioctls | |
50 | */ | |
51 | ||
52 | #define MOXA 0x400 | |
4463cc5b JS |
53 | #define MOXA_SET_OP_MODE (MOXA + 66) |
54 | #define MOXA_GET_OP_MODE (MOXA + 67) | |
55 | ||
56 | #define RS232_MODE 0 | |
57 | #define RS485_2WIRE_MODE 1 | |
58 | #define RS422_MODE 2 | |
59 | #define RS485_4WIRE_MODE 3 | |
60 | #define OP_MODE_MASK 3 | |
61 | ||
4463cc5b JS |
62 | /* --------------------------------------------------- */ |
63 | ||
4463cc5b JS |
64 | /* |
65 | * Follow just what Moxa Must chip defines. | |
66 | * | |
67 | * When LCR register (offset 0x03) writes the following value, the Must chip | |
68 | * will enter enchance mode. And write value on EFR (offset 0x02) bit 6,7 to | |
69 | * change bank. | |
70 | */ | |
71 | #define MOXA_MUST_ENTER_ENCHANCE 0xBF | |
72 | ||
73 | /* when enhance mode enabled, access on general bank register */ | |
74 | #define MOXA_MUST_GDL_REGISTER 0x07 | |
75 | #define MOXA_MUST_GDL_MASK 0x7F | |
76 | #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80 | |
77 | ||
78 | #define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */ | |
79 | /* enchance register bank select and enchance mode setting register */ | |
80 | /* when LCR register equals to 0xBF */ | |
81 | #define MOXA_MUST_EFR_REGISTER 0x02 | |
82 | #define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enchance mode enable */ | |
83 | /* enchance register bank set 0, 1, 2 */ | |
84 | #define MOXA_MUST_EFR_BANK0 0x00 | |
85 | #define MOXA_MUST_EFR_BANK1 0x40 | |
86 | #define MOXA_MUST_EFR_BANK2 0x80 | |
87 | #define MOXA_MUST_EFR_BANK3 0xC0 | |
88 | #define MOXA_MUST_EFR_BANK_MASK 0xC0 | |
89 | ||
90 | /* set XON1 value register, when LCR=0xBF and change to bank0 */ | |
91 | #define MOXA_MUST_XON1_REGISTER 0x04 | |
92 | ||
93 | /* set XON2 value register, when LCR=0xBF and change to bank0 */ | |
94 | #define MOXA_MUST_XON2_REGISTER 0x05 | |
95 | ||
96 | /* set XOFF1 value register, when LCR=0xBF and change to bank0 */ | |
97 | #define MOXA_MUST_XOFF1_REGISTER 0x06 | |
98 | ||
99 | /* set XOFF2 value register, when LCR=0xBF and change to bank0 */ | |
100 | #define MOXA_MUST_XOFF2_REGISTER 0x07 | |
101 | ||
102 | #define MOXA_MUST_RBRTL_REGISTER 0x04 | |
103 | #define MOXA_MUST_RBRTH_REGISTER 0x05 | |
104 | #define MOXA_MUST_RBRTI_REGISTER 0x06 | |
105 | #define MOXA_MUST_THRTL_REGISTER 0x07 | |
106 | #define MOXA_MUST_ENUM_REGISTER 0x04 | |
107 | #define MOXA_MUST_HWID_REGISTER 0x05 | |
108 | #define MOXA_MUST_ECR_REGISTER 0x06 | |
109 | #define MOXA_MUST_CSR_REGISTER 0x07 | |
110 | ||
111 | #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */ | |
112 | #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */ | |
113 | ||
114 | #define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */ | |
115 | #define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */ | |
116 | #define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */ | |
117 | #define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */ | |
118 | ||
119 | #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI) | |
120 | ||
121 | /* GDA interrupt pending */ | |
122 | #define MOXA_MUST_IIR_GDA 0x1C | |
123 | #define MOXA_MUST_IIR_RDA 0x04 | |
124 | #define MOXA_MUST_IIR_RTO 0x0C | |
125 | #define MOXA_MUST_IIR_LSR 0x06 | |
126 | ||
127 | /* received Xon/Xoff or specical interrupt pending */ | |
128 | #define MOXA_MUST_IIR_XSC 0x10 | |
129 | ||
130 | /* RTS/CTS change state interrupt pending */ | |
131 | #define MOXA_MUST_IIR_RTSCTS 0x20 | |
132 | #define MOXA_MUST_IIR_MASK 0x3E | |
133 | ||
134 | #define MOXA_MUST_MCR_XON_FLAG 0x40 | |
135 | #define MOXA_MUST_MCR_XON_ANY 0x80 | |
136 | #define MOXA_MUST_MCR_TX_XON 0x08 | |
137 | ||
138 | #define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */ | |
139 | #define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */ | |
140 | #define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */ | |
141 | #define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */ | |
142 | #define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */ | |
143 | #define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */ | |
144 | #define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */ | |
145 | #define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */ | |
146 | #define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */ | |
147 | #define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */ | |
148 | #define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */ | |
1da177e4 | 149 | |
1da177e4 | 150 | #define MXSERMAJOR 174 |
1da177e4 | 151 | |
1da177e4 | 152 | #define MXSER_BOARDS 4 /* Max. boards */ |
1da177e4 | 153 | #define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */ |
1c45607a JS |
154 | #define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD) |
155 | #define MXSER_ISR_PASS_LIMIT 100 | |
1da177e4 | 156 | |
1da177e4 LT |
157 | #define WAKEUP_CHARS 256 |
158 | ||
a6970c39 | 159 | #define MXSER_BAUD_BASE 921600 |
d811b26b | 160 | #define MXSER_CUSTOM_DIVISOR (MXSER_BAUD_BASE * 16) |
a6970c39 | 161 | |
e129deff | 162 | #define PCI_DEVICE_ID_POS104UL 0x1044 |
1c45607a | 163 | #define PCI_DEVICE_ID_CB108 0x1080 |
e129deff | 164 | #define PCI_DEVICE_ID_CP102UF 0x1023 |
502f295f | 165 | #define PCI_DEVICE_ID_CP112UL 0x1120 |
1c45607a | 166 | #define PCI_DEVICE_ID_CB114 0x1142 |
80ff8a80 | 167 | #define PCI_DEVICE_ID_CP114UL 0x1143 |
1c45607a JS |
168 | #define PCI_DEVICE_ID_CB134I 0x1341 |
169 | #define PCI_DEVICE_ID_CP138U 0x1380 | |
1da177e4 | 170 | |
1c45607a | 171 | #define MXSER_HIGHBAUD 1 |
1da177e4 | 172 | |
e4558366 JS |
173 | enum mxser_must_hwid { |
174 | MOXA_OTHER_UART = 0x00, | |
175 | MOXA_MUST_MU150_HWID = 0x01, | |
176 | MOXA_MUST_MU860_HWID = 0x02, | |
177 | }; | |
178 | ||
1c45607a | 179 | static const struct { |
dc33f644 JS |
180 | u8 type; |
181 | u8 fifo_size; | |
182 | u8 rx_high_water; | |
183 | u8 rx_low_water; | |
184 | speed_t max_baud; | |
1c45607a | 185 | } Gpci_uart_info[] = { |
dc33f644 JS |
186 | { MOXA_OTHER_UART, 16, 14, 1, 921600 }, |
187 | { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 }, | |
188 | { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 } | |
1da177e4 | 189 | }; |
1c45607a | 190 | #define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info) |
1da177e4 | 191 | |
1c45607a JS |
192 | struct mxser_cardinfo { |
193 | char *name; | |
194 | unsigned int nports; | |
195 | unsigned int flags; | |
196 | }; | |
1da177e4 | 197 | |
1c45607a | 198 | static const struct mxser_cardinfo mxser_cards[] = { |
15254902 | 199 | /* 0*/ { "C168H/PCI series", 8, }, |
1c45607a | 200 | { "C104H/PCI series", 4, }, |
1c45607a JS |
201 | { "CP-132 series", 2, }, |
202 | { "CP-114 series", 4, }, | |
15254902 JS |
203 | { "CT-114 series", 4, }, |
204 | /* 5*/ { "CP-102 series", 2, MXSER_HIGHBAUD }, | |
1c45607a JS |
205 | { "CP-104U series", 4, }, |
206 | { "CP-168U series", 8, }, | |
207 | { "CP-132U series", 2, }, | |
15254902 JS |
208 | { "CP-134U series", 4, }, |
209 | /*10*/ { "CP-104JU series", 4, }, | |
1c45607a JS |
210 | { "Moxa UC7000 Serial", 8, }, /* RC7000 */ |
211 | { "CP-118U series", 8, }, | |
212 | { "CP-102UL series", 2, }, | |
15254902 JS |
213 | { "CP-102U series", 2, }, |
214 | /*15*/ { "CP-118EL series", 8, }, | |
1c45607a JS |
215 | { "CP-168EL series", 8, }, |
216 | { "CP-104EL series", 4, }, | |
217 | { "CB-108 series", 8, }, | |
15254902 JS |
218 | { "CB-114 series", 4, }, |
219 | /*20*/ { "CB-134I series", 4, }, | |
1c45607a | 220 | { "CP-138U series", 8, }, |
80ff8a80 | 221 | { "POS-104UL series", 4, }, |
e129deff | 222 | { "CP-114UL series", 4, }, |
15254902 JS |
223 | { "CP-102UF series", 2, }, |
224 | /*25*/ { "CP-112UL series", 2, }, | |
1c45607a | 225 | }; |
1da177e4 | 226 | |
1c45607a JS |
227 | /* driver_data correspond to the lines in the structure above |
228 | see also ISA probe function before you change something */ | |
3385ecf8 | 229 | static const struct pci_device_id mxser_pcibrds[] = { |
15254902 JS |
230 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 0 }, |
231 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 1 }, | |
232 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 2 }, | |
233 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 3 }, | |
234 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 4 }, | |
235 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 5 }, | |
236 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 6 }, | |
237 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 7 }, | |
238 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 8 }, | |
239 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 9 }, | |
240 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 10 }, | |
241 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 11 }, | |
242 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 12 }, | |
243 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 13 }, | |
244 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 14 }, | |
245 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 15 }, | |
246 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 16 }, | |
247 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 17 }, | |
248 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 18 }, | |
249 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 19 }, | |
250 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 20 }, | |
251 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 21 }, | |
252 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 22 }, | |
253 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL), .driver_data = 23 }, | |
254 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP102UF), .driver_data = 24 }, | |
255 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP112UL), .driver_data = 25 }, | |
1c45607a | 256 | { } |
1da177e4 | 257 | }; |
1da177e4 LT |
258 | MODULE_DEVICE_TABLE(pci, mxser_pcibrds); |
259 | ||
1da177e4 | 260 | static int ttymajor = MXSERMAJOR; |
1da177e4 LT |
261 | |
262 | /* Variables for insmod */ | |
263 | ||
264 | MODULE_AUTHOR("Casper Yang"); | |
265 | MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver"); | |
8d3b33f6 | 266 | module_param(ttymajor, int, 0); |
1da177e4 LT |
267 | MODULE_LICENSE("GPL"); |
268 | ||
1c45607a JS |
269 | struct mxser_board; |
270 | ||
271 | struct mxser_port { | |
0ad9e7d1 | 272 | struct tty_port port; |
1c45607a | 273 | struct mxser_board *board; |
1c45607a JS |
274 | |
275 | unsigned long ioaddr; | |
276 | unsigned long opmode_ioaddr; | |
1da177e4 | 277 | |
dc33f644 JS |
278 | u8 rx_high_water; |
279 | u8 rx_low_water; | |
1da177e4 | 280 | int type; /* UART type */ |
1c45607a | 281 | |
a93963e4 JS |
282 | unsigned char x_char; /* xon/xoff character */ |
283 | u8 IER; /* Interrupt Enable Register */ | |
284 | u8 MCR; /* Modem control register */ | |
1c45607a | 285 | |
1c45607a JS |
286 | unsigned char ldisc_stop_rx; |
287 | ||
1c45607a | 288 | struct async_icount icount; /* kernel counters for 4 input interrupts */ |
104583b5 | 289 | unsigned int timeout; |
1c45607a | 290 | |
a93963e4 JS |
291 | u8 read_status_mask; |
292 | u8 ignore_status_mask; | |
dc33f644 | 293 | u8 xmit_fifo_size; |
02e43144 JS |
294 | unsigned int xmit_head; |
295 | unsigned int xmit_tail; | |
296 | unsigned int xmit_cnt; | |
cd7b4b39 | 297 | int closing; |
1c45607a | 298 | |
1da177e4 | 299 | spinlock_t slock; |
1c45607a JS |
300 | }; |
301 | ||
302 | struct mxser_board { | |
303 | unsigned int idx; | |
304 | int irq; | |
305 | const struct mxser_cardinfo *info; | |
306 | unsigned long vector; | |
1c45607a | 307 | |
e4558366 | 308 | enum mxser_must_hwid must_hwid; |
928f9464 | 309 | speed_t max_baud; |
1c45607a JS |
310 | |
311 | struct mxser_port ports[MXSER_PORTS_PER_BOARD]; | |
1da177e4 LT |
312 | }; |
313 | ||
1c45607a | 314 | static struct mxser_board mxser_boards[MXSER_BOARDS]; |
1da177e4 | 315 | static struct tty_driver *mxvar_sdriver; |
1da177e4 | 316 | |
edb7d27c JS |
317 | static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set, |
318 | bool restore_LCR) | |
148ff86b | 319 | { |
edb7d27c | 320 | u8 oldlcr, efr; |
148ff86b CH |
321 | |
322 | oldlcr = inb(baseio + UART_LCR); | |
323 | outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); | |
324 | ||
325 | efr = inb(baseio + MOXA_MUST_EFR_REGISTER); | |
edb7d27c JS |
326 | efr &= ~clear; |
327 | efr |= set; | |
148ff86b CH |
328 | |
329 | outb(efr, baseio + MOXA_MUST_EFR_REGISTER); | |
148ff86b | 330 | |
edb7d27c JS |
331 | if (restore_LCR) |
332 | outb(oldlcr, baseio + UART_LCR); | |
148ff86b | 333 | |
edb7d27c | 334 | return oldlcr; |
148ff86b CH |
335 | } |
336 | ||
b286484b | 337 | static u8 mxser_must_select_bank(unsigned long baseio, u8 bank) |
148ff86b | 338 | { |
b286484b JS |
339 | return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank, |
340 | false); | |
341 | } | |
148ff86b | 342 | |
b286484b JS |
343 | static void mxser_set_must_xon1_value(unsigned long baseio, u8 value) |
344 | { | |
345 | u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); | |
148ff86b CH |
346 | outb(value, baseio + MOXA_MUST_XON1_REGISTER); |
347 | outb(oldlcr, baseio + UART_LCR); | |
348 | } | |
349 | ||
350 | static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value) | |
351 | { | |
b286484b | 352 | u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); |
148ff86b CH |
353 | outb(value, baseio + MOXA_MUST_XOFF1_REGISTER); |
354 | outb(oldlcr, baseio + UART_LCR); | |
355 | } | |
356 | ||
357 | static void mxser_set_must_fifo_value(struct mxser_port *info) | |
358 | { | |
b286484b | 359 | u8 oldlcr = mxser_must_select_bank(info->ioaddr, MOXA_MUST_EFR_BANK1); |
dc33f644 JS |
360 | outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER); |
361 | outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER); | |
362 | outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER); | |
148ff86b CH |
363 | outb(oldlcr, info->ioaddr + UART_LCR); |
364 | } | |
365 | ||
366 | static void mxser_set_must_enum_value(unsigned long baseio, u8 value) | |
367 | { | |
b286484b | 368 | u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); |
148ff86b CH |
369 | outb(value, baseio + MOXA_MUST_ENUM_REGISTER); |
370 | outb(oldlcr, baseio + UART_LCR); | |
371 | } | |
372 | ||
b286484b | 373 | static u8 mxser_get_must_hardware_id(unsigned long baseio) |
148ff86b | 374 | { |
b286484b JS |
375 | u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); |
376 | u8 id = inb(baseio + MOXA_MUST_HWID_REGISTER); | |
148ff86b | 377 | outb(oldlcr, baseio + UART_LCR); |
b286484b JS |
378 | |
379 | return id; | |
148ff86b CH |
380 | } |
381 | ||
edb7d27c JS |
382 | static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set) |
383 | { | |
384 | __mxser_must_set_EFR(baseio, clear, set, true); | |
385 | } | |
386 | ||
387 | static void mxser_must_set_enhance_mode(unsigned long baseio, bool enable) | |
388 | { | |
389 | mxser_must_set_EFR(baseio, | |
390 | enable ? 0 : MOXA_MUST_EFR_EFRB_ENABLE, | |
391 | enable ? MOXA_MUST_EFR_EFRB_ENABLE : 0); | |
392 | } | |
393 | ||
b441eb0f | 394 | static void mxser_must_no_sw_flow_control(unsigned long baseio) |
148ff86b | 395 | { |
b441eb0f | 396 | mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_MASK, 0); |
148ff86b CH |
397 | } |
398 | ||
b441eb0f | 399 | static void mxser_must_set_tx_sw_flow_control(unsigned long baseio, bool enable) |
148ff86b | 400 | { |
b441eb0f JS |
401 | mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_TX_MASK, |
402 | enable ? MOXA_MUST_EFR_SF_TX1 : 0); | |
148ff86b CH |
403 | } |
404 | ||
b441eb0f | 405 | static void mxser_must_set_rx_sw_flow_control(unsigned long baseio, bool enable) |
148ff86b | 406 | { |
b441eb0f JS |
407 | mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_RX_MASK, |
408 | enable ? MOXA_MUST_EFR_SF_RX1 : 0); | |
148ff86b CH |
409 | } |
410 | ||
e4558366 | 411 | static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io) |
1da177e4 LT |
412 | { |
413 | u8 oldmcr, hwid; | |
414 | int i; | |
415 | ||
416 | outb(0, io + UART_LCR); | |
edb7d27c | 417 | mxser_must_set_enhance_mode(io, false); |
1da177e4 LT |
418 | oldmcr = inb(io + UART_MCR); |
419 | outb(0, io + UART_MCR); | |
148ff86b | 420 | mxser_set_must_xon1_value(io, 0x11); |
1da177e4 LT |
421 | if ((hwid = inb(io + UART_MCR)) != 0) { |
422 | outb(oldmcr, io + UART_MCR); | |
8ea2c2ec | 423 | return MOXA_OTHER_UART; |
1da177e4 LT |
424 | } |
425 | ||
b286484b | 426 | hwid = mxser_get_must_hardware_id(io); |
e4558366 | 427 | for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */ |
1c45607a | 428 | if (hwid == Gpci_uart_info[i].type) |
e4558366 JS |
429 | return hwid; |
430 | ||
1da177e4 LT |
431 | return MOXA_OTHER_UART; |
432 | } | |
433 | ||
1c45607a | 434 | static void process_txrx_fifo(struct mxser_port *info) |
1da177e4 LT |
435 | { |
436 | int i; | |
437 | ||
438 | if ((info->type == PORT_16450) || (info->type == PORT_8250)) { | |
1da177e4 LT |
439 | info->rx_high_water = 1; |
440 | info->rx_low_water = 1; | |
441 | info->xmit_fifo_size = 1; | |
1c45607a JS |
442 | } else |
443 | for (i = 0; i < UART_INFO_NUM; i++) | |
292955a7 | 444 | if (info->board->must_hwid == Gpci_uart_info[i].type) { |
1da177e4 LT |
445 | info->rx_low_water = Gpci_uart_info[i].rx_low_water; |
446 | info->rx_high_water = Gpci_uart_info[i].rx_high_water; | |
dc33f644 | 447 | info->xmit_fifo_size = Gpci_uart_info[i].fifo_size; |
1da177e4 LT |
448 | break; |
449 | } | |
1da177e4 LT |
450 | } |
451 | ||
31f35939 AC |
452 | static int mxser_carrier_raised(struct tty_port *port) |
453 | { | |
454 | struct mxser_port *mp = container_of(port, struct mxser_port, port); | |
455 | return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0; | |
456 | } | |
457 | ||
fcc8ac18 | 458 | static void mxser_dtr_rts(struct tty_port *port, int on) |
5d951fb4 AC |
459 | { |
460 | struct mxser_port *mp = container_of(port, struct mxser_port, port); | |
461 | unsigned long flags; | |
462 | ||
463 | spin_lock_irqsave(&mp->slock, flags); | |
fcc8ac18 AC |
464 | if (on) |
465 | outb(inb(mp->ioaddr + UART_MCR) | | |
466 | UART_MCR_DTR | UART_MCR_RTS, mp->ioaddr + UART_MCR); | |
467 | else | |
468 | outb(inb(mp->ioaddr + UART_MCR)&~(UART_MCR_DTR | UART_MCR_RTS), | |
469 | mp->ioaddr + UART_MCR); | |
5d951fb4 AC |
470 | spin_unlock_irqrestore(&mp->slock, flags); |
471 | } | |
472 | ||
dc33f644 | 473 | static int mxser_set_baud(struct tty_struct *tty, speed_t newspd) |
1da177e4 | 474 | { |
216ba023 | 475 | struct mxser_port *info = tty->driver_data; |
104583b5 | 476 | unsigned int quot = 0, baud; |
1c45607a | 477 | unsigned char cval; |
104583b5 | 478 | u64 timeout; |
1da177e4 | 479 | |
216ba023 | 480 | if (!info->ioaddr) |
1c45607a | 481 | return -1; |
1da177e4 | 482 | |
928f9464 | 483 | if (newspd > info->board->max_baud) |
1c45607a | 484 | return -1; |
1da177e4 | 485 | |
1c45607a | 486 | if (newspd == 134) { |
a6970c39 | 487 | quot = 2 * MXSER_BAUD_BASE / 269; |
216ba023 | 488 | tty_encode_baud_rate(tty, 134, 134); |
1c45607a | 489 | } else if (newspd) { |
a6970c39 | 490 | quot = MXSER_BAUD_BASE / newspd; |
1c45607a JS |
491 | if (quot == 0) |
492 | quot = 1; | |
a6970c39 | 493 | baud = MXSER_BAUD_BASE / quot; |
216ba023 | 494 | tty_encode_baud_rate(tty, baud, baud); |
1c45607a JS |
495 | } else { |
496 | quot = 0; | |
497 | } | |
1da177e4 | 498 | |
104583b5 JS |
499 | /* |
500 | * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the | |
501 | * u64 domain | |
502 | */ | |
503 | timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot; | |
a6970c39 | 504 | do_div(timeout, MXSER_BAUD_BASE); |
104583b5 | 505 | info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */ |
1da177e4 | 506 | |
1c45607a JS |
507 | if (quot) { |
508 | info->MCR |= UART_MCR_DTR; | |
509 | outb(info->MCR, info->ioaddr + UART_MCR); | |
510 | } else { | |
511 | info->MCR &= ~UART_MCR_DTR; | |
512 | outb(info->MCR, info->ioaddr + UART_MCR); | |
513 | return 0; | |
514 | } | |
1da177e4 | 515 | |
1c45607a | 516 | cval = inb(info->ioaddr + UART_LCR); |
1da177e4 | 517 | |
1c45607a | 518 | outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */ |
1da177e4 | 519 | |
1c45607a JS |
520 | outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */ |
521 | outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */ | |
522 | outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */ | |
1da177e4 | 523 | |
1c45607a | 524 | #ifdef BOTHER |
216ba023 | 525 | if (C_BAUD(tty) == BOTHER) { |
a6970c39 | 526 | quot = MXSER_BAUD_BASE % newspd; |
1c45607a JS |
527 | quot *= 8; |
528 | if (quot % newspd > newspd / 2) { | |
529 | quot /= newspd; | |
530 | quot++; | |
531 | } else | |
532 | quot /= newspd; | |
533 | ||
148ff86b | 534 | mxser_set_must_enum_value(info->ioaddr, quot); |
1c45607a JS |
535 | } else |
536 | #endif | |
148ff86b | 537 | mxser_set_must_enum_value(info->ioaddr, 0); |
1da177e4 | 538 | |
8ea2c2ec | 539 | return 0; |
1da177e4 | 540 | } |
1da177e4 | 541 | |
1c45607a JS |
542 | /* |
543 | * This routine is called to set the UART divisor registers to match | |
544 | * the specified baud rate for a serial port. | |
545 | */ | |
beca62c4 | 546 | static void mxser_change_speed(struct tty_struct *tty) |
1da177e4 | 547 | { |
216ba023 | 548 | struct mxser_port *info = tty->driver_data; |
1c45607a | 549 | unsigned cflag, cval, fcr; |
1c45607a | 550 | unsigned char status; |
1da177e4 | 551 | |
adc8d746 | 552 | cflag = tty->termios.c_cflag; |
216ba023 | 553 | if (!info->ioaddr) |
beca62c4 | 554 | return; |
1da177e4 | 555 | |
ef3dff8a | 556 | mxser_set_baud(tty, tty_get_baud_rate(tty)); |
1da177e4 | 557 | |
1c45607a JS |
558 | /* byte size and parity */ |
559 | switch (cflag & CSIZE) { | |
2c21832b | 560 | default: |
1c45607a | 561 | case CS5: |
2c21832b | 562 | cval = UART_LCR_WLEN5; |
1c45607a JS |
563 | break; |
564 | case CS6: | |
2c21832b | 565 | cval = UART_LCR_WLEN6; |
1c45607a JS |
566 | break; |
567 | case CS7: | |
2c21832b | 568 | cval = UART_LCR_WLEN7; |
1c45607a JS |
569 | break; |
570 | case CS8: | |
2c21832b | 571 | cval = UART_LCR_WLEN8; |
1c45607a | 572 | break; |
1c45607a | 573 | } |
2c21832b | 574 | |
1c45607a | 575 | if (cflag & CSTOPB) |
2c21832b | 576 | cval |= UART_LCR_STOP; |
1c45607a JS |
577 | if (cflag & PARENB) |
578 | cval |= UART_LCR_PARITY; | |
579 | if (!(cflag & PARODD)) | |
580 | cval |= UART_LCR_EPAR; | |
581 | if (cflag & CMSPAR) | |
582 | cval |= UART_LCR_SPAR; | |
1da177e4 | 583 | |
1c45607a | 584 | if ((info->type == PORT_8250) || (info->type == PORT_16450)) { |
292955a7 | 585 | if (info->board->must_hwid) { |
1c45607a JS |
586 | fcr = UART_FCR_ENABLE_FIFO; |
587 | fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; | |
148ff86b | 588 | mxser_set_must_fifo_value(info); |
1c45607a JS |
589 | } else |
590 | fcr = 0; | |
591 | } else { | |
592 | fcr = UART_FCR_ENABLE_FIFO; | |
292955a7 | 593 | if (info->board->must_hwid) { |
1c45607a | 594 | fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; |
148ff86b | 595 | mxser_set_must_fifo_value(info); |
1c45607a | 596 | } else { |
dc33f644 | 597 | switch (info->rx_high_water) { |
1c45607a JS |
598 | case 1: |
599 | fcr |= UART_FCR_TRIGGER_1; | |
600 | break; | |
601 | case 4: | |
602 | fcr |= UART_FCR_TRIGGER_4; | |
603 | break; | |
604 | case 8: | |
605 | fcr |= UART_FCR_TRIGGER_8; | |
606 | break; | |
607 | default: | |
608 | fcr |= UART_FCR_TRIGGER_14; | |
609 | break; | |
610 | } | |
1da177e4 | 611 | } |
1da177e4 LT |
612 | } |
613 | ||
1c45607a JS |
614 | /* CTS flow control flag and modem status interrupts */ |
615 | info->IER &= ~UART_IER_MSI; | |
616 | info->MCR &= ~UART_MCR_AFE; | |
5604a98e | 617 | tty_port_set_cts_flow(&info->port, cflag & CRTSCTS); |
1c45607a | 618 | if (cflag & CRTSCTS) { |
1c45607a | 619 | info->IER |= UART_IER_MSI; |
292955a7 | 620 | if ((info->type == PORT_16550A) || (info->board->must_hwid)) { |
1c45607a JS |
621 | info->MCR |= UART_MCR_AFE; |
622 | } else { | |
623 | status = inb(info->ioaddr + UART_MSR); | |
216ba023 | 624 | if (tty->hw_stopped) { |
1c45607a | 625 | if (status & UART_MSR_CTS) { |
216ba023 | 626 | tty->hw_stopped = 0; |
1c45607a | 627 | if (info->type != PORT_16550A && |
292955a7 | 628 | !info->board->must_hwid) { |
1c45607a JS |
629 | outb(info->IER & ~UART_IER_THRI, |
630 | info->ioaddr + | |
631 | UART_IER); | |
632 | info->IER |= UART_IER_THRI; | |
633 | outb(info->IER, info->ioaddr + | |
634 | UART_IER); | |
635 | } | |
216ba023 | 636 | tty_wakeup(tty); |
1c45607a JS |
637 | } |
638 | } else { | |
639 | if (!(status & UART_MSR_CTS)) { | |
216ba023 | 640 | tty->hw_stopped = 1; |
1c45607a | 641 | if ((info->type != PORT_16550A) && |
292955a7 | 642 | (!info->board->must_hwid)) { |
1c45607a JS |
643 | info->IER &= ~UART_IER_THRI; |
644 | outb(info->IER, info->ioaddr + | |
645 | UART_IER); | |
646 | } | |
647 | } | |
648 | } | |
1da177e4 | 649 | } |
1c45607a JS |
650 | } |
651 | outb(info->MCR, info->ioaddr + UART_MCR); | |
2d68655d PH |
652 | tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL); |
653 | if (~cflag & CLOCAL) | |
1c45607a | 654 | info->IER |= UART_IER_MSI; |
1c45607a JS |
655 | outb(info->IER, info->ioaddr + UART_IER); |
656 | ||
657 | /* | |
658 | * Set up parity check flag | |
659 | */ | |
660 | info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
216ba023 | 661 | if (I_INPCK(tty)) |
1c45607a | 662 | info->read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
216ba023 | 663 | if (I_BRKINT(tty) || I_PARMRK(tty)) |
1c45607a | 664 | info->read_status_mask |= UART_LSR_BI; |
1da177e4 | 665 | |
1c45607a | 666 | info->ignore_status_mask = 0; |
1da177e4 | 667 | |
216ba023 | 668 | if (I_IGNBRK(tty)) { |
1c45607a JS |
669 | info->ignore_status_mask |= UART_LSR_BI; |
670 | info->read_status_mask |= UART_LSR_BI; | |
8ea2c2ec | 671 | /* |
1c45607a JS |
672 | * If we're ignore parity and break indicators, ignore |
673 | * overruns too. (For real raw support). | |
8ea2c2ec | 674 | */ |
216ba023 | 675 | if (I_IGNPAR(tty)) { |
1c45607a JS |
676 | info->ignore_status_mask |= |
677 | UART_LSR_OE | | |
678 | UART_LSR_PE | | |
679 | UART_LSR_FE; | |
680 | info->read_status_mask |= | |
681 | UART_LSR_OE | | |
682 | UART_LSR_PE | | |
683 | UART_LSR_FE; | |
684 | } | |
1da177e4 | 685 | } |
292955a7 | 686 | if (info->board->must_hwid) { |
216ba023 AC |
687 | mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty)); |
688 | mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty)); | |
b441eb0f JS |
689 | mxser_must_set_rx_sw_flow_control(info->ioaddr, I_IXON(tty)); |
690 | mxser_must_set_tx_sw_flow_control(info->ioaddr, I_IXOFF(tty)); | |
1da177e4 | 691 | } |
1da177e4 | 692 | |
1da177e4 | 693 | |
1c45607a JS |
694 | outb(fcr, info->ioaddr + UART_FCR); /* set fcr */ |
695 | outb(cval, info->ioaddr + UART_LCR); | |
1da177e4 LT |
696 | } |
697 | ||
216ba023 AC |
698 | static void mxser_check_modem_status(struct tty_struct *tty, |
699 | struct mxser_port *port, int status) | |
1da177e4 | 700 | { |
1c45607a JS |
701 | /* update input line counters */ |
702 | if (status & UART_MSR_TERI) | |
703 | port->icount.rng++; | |
704 | if (status & UART_MSR_DDSR) | |
705 | port->icount.dsr++; | |
706 | if (status & UART_MSR_DDCD) | |
707 | port->icount.dcd++; | |
708 | if (status & UART_MSR_DCTS) | |
709 | port->icount.cts++; | |
bdc04e31 | 710 | wake_up_interruptible(&port->port.delta_msr_wait); |
1da177e4 | 711 | |
2d68655d | 712 | if (tty_port_check_carrier(&port->port) && (status & UART_MSR_DDCD)) { |
1c45607a | 713 | if (status & UART_MSR_DCD) |
0ad9e7d1 | 714 | wake_up_interruptible(&port->port.open_wait); |
1c45607a | 715 | } |
1da177e4 | 716 | |
f21ec3d2 | 717 | if (tty_port_cts_enabled(&port->port)) { |
216ba023 | 718 | if (tty->hw_stopped) { |
1c45607a | 719 | if (status & UART_MSR_CTS) { |
216ba023 | 720 | tty->hw_stopped = 0; |
1c45607a JS |
721 | |
722 | if ((port->type != PORT_16550A) && | |
292955a7 | 723 | (!port->board->must_hwid)) { |
1c45607a JS |
724 | outb(port->IER & ~UART_IER_THRI, |
725 | port->ioaddr + UART_IER); | |
726 | port->IER |= UART_IER_THRI; | |
727 | outb(port->IER, port->ioaddr + | |
728 | UART_IER); | |
729 | } | |
216ba023 | 730 | tty_wakeup(tty); |
1c45607a JS |
731 | } |
732 | } else { | |
733 | if (!(status & UART_MSR_CTS)) { | |
216ba023 | 734 | tty->hw_stopped = 1; |
1c45607a | 735 | if (port->type != PORT_16550A && |
292955a7 | 736 | !port->board->must_hwid) { |
1c45607a JS |
737 | port->IER &= ~UART_IER_THRI; |
738 | outb(port->IER, port->ioaddr + | |
739 | UART_IER); | |
740 | } | |
741 | } | |
742 | } | |
1da177e4 LT |
743 | } |
744 | } | |
745 | ||
6769140d | 746 | static int mxser_activate(struct tty_port *port, struct tty_struct *tty) |
1da177e4 | 747 | { |
6769140d | 748 | struct mxser_port *info = container_of(port, struct mxser_port, port); |
1c45607a JS |
749 | unsigned long page; |
750 | unsigned long flags; | |
1da177e4 | 751 | |
1c45607a JS |
752 | page = __get_free_page(GFP_KERNEL); |
753 | if (!page) | |
754 | return -ENOMEM; | |
1da177e4 | 755 | |
1c45607a | 756 | spin_lock_irqsave(&info->slock, flags); |
1da177e4 | 757 | |
1c45607a | 758 | if (!info->ioaddr || !info->type) { |
216ba023 | 759 | set_bit(TTY_IO_ERROR, &tty->flags); |
1c45607a JS |
760 | free_page(page); |
761 | spin_unlock_irqrestore(&info->slock, flags); | |
1da177e4 | 762 | return 0; |
1c45607a | 763 | } |
6769140d | 764 | info->port.xmit_buf = (unsigned char *) page; |
1da177e4 | 765 | |
1da177e4 | 766 | /* |
1c45607a JS |
767 | * Clear the FIFO buffers and disable them |
768 | * (they will be reenabled in mxser_change_speed()) | |
1da177e4 | 769 | */ |
292955a7 | 770 | if (info->board->must_hwid) |
1c45607a JS |
771 | outb((UART_FCR_CLEAR_RCVR | |
772 | UART_FCR_CLEAR_XMIT | | |
773 | MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR); | |
774 | else | |
775 | outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), | |
776 | info->ioaddr + UART_FCR); | |
1da177e4 | 777 | |
1c45607a JS |
778 | /* |
779 | * At this point there's no way the LSR could still be 0xFF; | |
780 | * if it is, then bail out, because there's likely no UART | |
781 | * here. | |
782 | */ | |
783 | if (inb(info->ioaddr + UART_LSR) == 0xff) { | |
784 | spin_unlock_irqrestore(&info->slock, flags); | |
785 | if (capable(CAP_SYS_ADMIN)) { | |
f43a510d | 786 | set_bit(TTY_IO_ERROR, &tty->flags); |
1c45607a JS |
787 | return 0; |
788 | } else | |
789 | return -ENODEV; | |
790 | } | |
1da177e4 | 791 | |
1c45607a JS |
792 | /* |
793 | * Clear the interrupt registers. | |
794 | */ | |
795 | (void) inb(info->ioaddr + UART_LSR); | |
796 | (void) inb(info->ioaddr + UART_RX); | |
797 | (void) inb(info->ioaddr + UART_IIR); | |
798 | (void) inb(info->ioaddr + UART_MSR); | |
799 | ||
800 | /* | |
801 | * Now, initialize the UART | |
802 | */ | |
803 | outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */ | |
804 | info->MCR = UART_MCR_DTR | UART_MCR_RTS; | |
805 | outb(info->MCR, info->ioaddr + UART_MCR); | |
806 | ||
807 | /* | |
808 | * Finally, enable interrupts | |
809 | */ | |
810 | info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; | |
811 | ||
292955a7 | 812 | if (info->board->must_hwid) |
1c45607a JS |
813 | info->IER |= MOXA_MUST_IER_EGDAI; |
814 | outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */ | |
815 | ||
816 | /* | |
817 | * And clear the interrupt registers again for luck. | |
818 | */ | |
819 | (void) inb(info->ioaddr + UART_LSR); | |
820 | (void) inb(info->ioaddr + UART_RX); | |
821 | (void) inb(info->ioaddr + UART_IIR); | |
822 | (void) inb(info->ioaddr + UART_MSR); | |
823 | ||
216ba023 | 824 | clear_bit(TTY_IO_ERROR, &tty->flags); |
1c45607a JS |
825 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; |
826 | ||
827 | /* | |
828 | * and set the speed of the serial port | |
829 | */ | |
2799707f | 830 | mxser_change_speed(tty); |
1c45607a JS |
831 | spin_unlock_irqrestore(&info->slock, flags); |
832 | ||
833 | return 0; | |
834 | } | |
835 | ||
836 | /* | |
6769140d | 837 | * This routine will shutdown a serial port |
1c45607a | 838 | */ |
6769140d | 839 | static void mxser_shutdown_port(struct tty_port *port) |
1c45607a | 840 | { |
6769140d | 841 | struct mxser_port *info = container_of(port, struct mxser_port, port); |
1c45607a JS |
842 | unsigned long flags; |
843 | ||
1c45607a JS |
844 | spin_lock_irqsave(&info->slock, flags); |
845 | ||
846 | /* | |
847 | * clear delta_msr_wait queue to avoid mem leaks: we may free the irq | |
848 | * here so the queue might never be waken up | |
849 | */ | |
bdc04e31 | 850 | wake_up_interruptible(&info->port.delta_msr_wait); |
1c45607a JS |
851 | |
852 | /* | |
6769140d | 853 | * Free the xmit buffer, if necessary |
1c45607a | 854 | */ |
0ad9e7d1 AC |
855 | if (info->port.xmit_buf) { |
856 | free_page((unsigned long) info->port.xmit_buf); | |
857 | info->port.xmit_buf = NULL; | |
1da177e4 LT |
858 | } |
859 | ||
1c45607a JS |
860 | info->IER = 0; |
861 | outb(0x00, info->ioaddr + UART_IER); | |
862 | ||
1c45607a | 863 | /* clear Rx/Tx FIFO's */ |
292955a7 | 864 | if (info->board->must_hwid) |
1c45607a JS |
865 | outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | |
866 | MOXA_MUST_FCR_GDA_MODE_ENABLE, | |
867 | info->ioaddr + UART_FCR); | |
868 | else | |
869 | outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, | |
870 | info->ioaddr + UART_FCR); | |
871 | ||
872 | /* read data port to reset things */ | |
873 | (void) inb(info->ioaddr + UART_RX); | |
874 | ||
1c45607a | 875 | |
292955a7 | 876 | if (info->board->must_hwid) |
b441eb0f | 877 | mxser_must_no_sw_flow_control(info->ioaddr); |
1c45607a JS |
878 | |
879 | spin_unlock_irqrestore(&info->slock, flags); | |
880 | } | |
881 | ||
882 | /* | |
883 | * This routine is called whenever a serial port is opened. It | |
884 | * enables interrupts for a serial port, linking in its async structure into | |
885 | * the IRQ chain. It also performs the serial-specific | |
886 | * initialization for the tty structure. | |
887 | */ | |
888 | static int mxser_open(struct tty_struct *tty, struct file *filp) | |
889 | { | |
890 | struct mxser_port *info; | |
389fc82e | 891 | int line = tty->index; |
1c45607a | 892 | |
1c45607a JS |
893 | info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD]; |
894 | if (!info->ioaddr) | |
895 | return -ENODEV; | |
896 | ||
a2d1e351 | 897 | tty->driver_data = info; |
6769140d | 898 | return tty_port_open(&info->port, tty, filp); |
1da177e4 LT |
899 | } |
900 | ||
978e595f AC |
901 | static void mxser_flush_buffer(struct tty_struct *tty) |
902 | { | |
903 | struct mxser_port *info = tty->driver_data; | |
904 | char fcr; | |
905 | unsigned long flags; | |
906 | ||
907 | ||
908 | spin_lock_irqsave(&info->slock, flags); | |
909 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; | |
910 | ||
911 | fcr = inb(info->ioaddr + UART_FCR); | |
912 | outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), | |
913 | info->ioaddr + UART_FCR); | |
914 | outb(fcr, info->ioaddr + UART_FCR); | |
915 | ||
916 | spin_unlock_irqrestore(&info->slock, flags); | |
917 | ||
918 | tty_wakeup(tty); | |
919 | } | |
920 | ||
921 | ||
6769140d | 922 | static void mxser_close_port(struct tty_port *port) |
1da177e4 | 923 | { |
1e2b0254 | 924 | struct mxser_port *info = container_of(port, struct mxser_port, port); |
1da177e4 | 925 | unsigned long timeout; |
1da177e4 LT |
926 | /* |
927 | * At this point we stop accepting input. To do this, we | |
928 | * disable the receive line status interrupts, and tell the | |
929 | * interrupt driver to stop checking the data ready bit in the | |
930 | * line status register. | |
931 | */ | |
932 | info->IER &= ~UART_IER_RLSI; | |
292955a7 | 933 | if (info->board->must_hwid) |
1da177e4 | 934 | info->IER &= ~MOXA_MUST_RECV_ISR; |
1c45607a | 935 | |
6769140d AC |
936 | outb(info->IER, info->ioaddr + UART_IER); |
937 | /* | |
938 | * Before we drop DTR, make sure the UART transmitter | |
939 | * has completely drained; this is especially | |
940 | * important if there is a transmit FIFO! | |
941 | */ | |
942 | timeout = jiffies + HZ; | |
943 | while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) { | |
944 | schedule_timeout_interruptible(5); | |
945 | if (time_after(jiffies, timeout)) | |
946 | break; | |
1da177e4 | 947 | } |
1e2b0254 AC |
948 | } |
949 | ||
950 | /* | |
951 | * This routine is called when the serial port gets closed. First, we | |
952 | * wait for the last remaining data to be sent. Then, we unlink its | |
953 | * async structure from the interrupt chain if necessary, and we free | |
954 | * that IRQ if nothing is left in the chain. | |
955 | */ | |
956 | static void mxser_close(struct tty_struct *tty, struct file *filp) | |
957 | { | |
958 | struct mxser_port *info = tty->driver_data; | |
959 | struct tty_port *port = &info->port; | |
960 | ||
389fc82e | 961 | if (info == NULL) |
1e2b0254 AC |
962 | return; |
963 | if (tty_port_close_start(port, tty, filp) == 0) | |
964 | return; | |
cd7b4b39 | 965 | info->closing = 1; |
6769140d AC |
966 | mutex_lock(&port->mutex); |
967 | mxser_close_port(port); | |
1e2b0254 | 968 | mxser_flush_buffer(tty); |
d41861ca PH |
969 | if (tty_port_initialized(port) && C_HUPCL(tty)) |
970 | tty_port_lower_dtr_rts(port); | |
6769140d | 971 | mxser_shutdown_port(port); |
d41861ca | 972 | tty_port_set_initialized(port, 0); |
6769140d | 973 | mutex_unlock(&port->mutex); |
cd7b4b39 | 974 | info->closing = 0; |
a6614999 AC |
975 | /* Right now the tty_port set is done outside of the close_end helper |
976 | as we don't yet have everyone using refcounts */ | |
977 | tty_port_close_end(port, tty); | |
978 | tty_port_tty_set(port, NULL); | |
1da177e4 LT |
979 | } |
980 | ||
981 | static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count) | |
982 | { | |
983 | int c, total = 0; | |
1c45607a | 984 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
985 | unsigned long flags; |
986 | ||
0ad9e7d1 | 987 | if (!info->port.xmit_buf) |
8ea2c2ec | 988 | return 0; |
1da177e4 LT |
989 | |
990 | while (1) { | |
8ea2c2ec JJ |
991 | c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, |
992 | SERIAL_XMIT_SIZE - info->xmit_head)); | |
1da177e4 LT |
993 | if (c <= 0) |
994 | break; | |
995 | ||
0ad9e7d1 | 996 | memcpy(info->port.xmit_buf + info->xmit_head, buf, c); |
1da177e4 | 997 | spin_lock_irqsave(&info->slock, flags); |
8ea2c2ec JJ |
998 | info->xmit_head = (info->xmit_head + c) & |
999 | (SERIAL_XMIT_SIZE - 1); | |
1da177e4 LT |
1000 | info->xmit_cnt += c; |
1001 | spin_unlock_irqrestore(&info->slock, flags); | |
1002 | ||
1003 | buf += c; | |
1004 | count -= c; | |
1005 | total += c; | |
1da177e4 LT |
1006 | } |
1007 | ||
6e94dbc7 | 1008 | if (info->xmit_cnt && !tty->flow.stopped) { |
8ea2c2ec JJ |
1009 | if (!tty->hw_stopped || |
1010 | (info->type == PORT_16550A) || | |
292955a7 | 1011 | (info->board->must_hwid)) { |
1da177e4 | 1012 | spin_lock_irqsave(&info->slock, flags); |
1c45607a JS |
1013 | outb(info->IER & ~UART_IER_THRI, info->ioaddr + |
1014 | UART_IER); | |
1da177e4 | 1015 | info->IER |= UART_IER_THRI; |
1c45607a | 1016 | outb(info->IER, info->ioaddr + UART_IER); |
1da177e4 LT |
1017 | spin_unlock_irqrestore(&info->slock, flags); |
1018 | } | |
1019 | } | |
1020 | return total; | |
1021 | } | |
1022 | ||
0be2eade | 1023 | static int mxser_put_char(struct tty_struct *tty, unsigned char ch) |
1da177e4 | 1024 | { |
1c45607a | 1025 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
1026 | unsigned long flags; |
1027 | ||
0ad9e7d1 | 1028 | if (!info->port.xmit_buf) |
0be2eade | 1029 | return 0; |
1da177e4 LT |
1030 | |
1031 | if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1) | |
0be2eade | 1032 | return 0; |
1da177e4 LT |
1033 | |
1034 | spin_lock_irqsave(&info->slock, flags); | |
0ad9e7d1 | 1035 | info->port.xmit_buf[info->xmit_head++] = ch; |
1da177e4 LT |
1036 | info->xmit_head &= SERIAL_XMIT_SIZE - 1; |
1037 | info->xmit_cnt++; | |
1038 | spin_unlock_irqrestore(&info->slock, flags); | |
6e94dbc7 | 1039 | if (!tty->flow.stopped) { |
8ea2c2ec JJ |
1040 | if (!tty->hw_stopped || |
1041 | (info->type == PORT_16550A) || | |
292955a7 | 1042 | info->board->must_hwid) { |
1da177e4 | 1043 | spin_lock_irqsave(&info->slock, flags); |
1c45607a | 1044 | outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); |
1da177e4 | 1045 | info->IER |= UART_IER_THRI; |
1c45607a | 1046 | outb(info->IER, info->ioaddr + UART_IER); |
1da177e4 LT |
1047 | spin_unlock_irqrestore(&info->slock, flags); |
1048 | } | |
1049 | } | |
0be2eade | 1050 | return 1; |
1da177e4 LT |
1051 | } |
1052 | ||
1053 | ||
1054 | static void mxser_flush_chars(struct tty_struct *tty) | |
1055 | { | |
1c45607a | 1056 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
1057 | unsigned long flags; |
1058 | ||
6e94dbc7 | 1059 | if (info->xmit_cnt <= 0 || tty->flow.stopped || !info->port.xmit_buf || |
ace7dd96 | 1060 | (tty->hw_stopped && info->type != PORT_16550A && |
292955a7 | 1061 | !info->board->must_hwid)) |
1da177e4 LT |
1062 | return; |
1063 | ||
1064 | spin_lock_irqsave(&info->slock, flags); | |
1065 | ||
1c45607a | 1066 | outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); |
1da177e4 | 1067 | info->IER |= UART_IER_THRI; |
1c45607a | 1068 | outb(info->IER, info->ioaddr + UART_IER); |
1da177e4 LT |
1069 | |
1070 | spin_unlock_irqrestore(&info->slock, flags); | |
1071 | } | |
1072 | ||
03b3b1a2 | 1073 | static unsigned int mxser_write_room(struct tty_struct *tty) |
1da177e4 | 1074 | { |
1c45607a | 1075 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
1076 | int ret; |
1077 | ||
1078 | ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1; | |
ace7dd96 | 1079 | return ret < 0 ? 0 : ret; |
1da177e4 LT |
1080 | } |
1081 | ||
fff4ef17 | 1082 | static unsigned int mxser_chars_in_buffer(struct tty_struct *tty) |
1da177e4 | 1083 | { |
1c45607a | 1084 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
1085 | return info->xmit_cnt; |
1086 | } | |
1087 | ||
1c45607a JS |
1088 | /* |
1089 | * ------------------------------------------------------------ | |
1090 | * friends of mxser_ioctl() | |
1091 | * ------------------------------------------------------------ | |
1092 | */ | |
216ba023 | 1093 | static int mxser_get_serial_info(struct tty_struct *tty, |
6da5b587 | 1094 | struct serial_struct *ss) |
1c45607a | 1095 | { |
216ba023 | 1096 | struct mxser_port *info = tty->driver_data; |
6da5b587 | 1097 | struct tty_port *port = &info->port; |
be6cf583 | 1098 | unsigned int closing_wait, close_delay; |
6da5b587 | 1099 | |
6da5b587 | 1100 | mutex_lock(&port->mutex); |
be6cf583 JH |
1101 | |
1102 | close_delay = jiffies_to_msecs(info->port.close_delay) / 10; | |
1103 | closing_wait = info->port.closing_wait; | |
1104 | if (closing_wait != ASYNC_CLOSING_WAIT_NONE) | |
1105 | closing_wait = jiffies_to_msecs(closing_wait) / 10; | |
1106 | ||
6da5b587 AV |
1107 | ss->type = info->type, |
1108 | ss->line = tty->index, | |
1109 | ss->port = info->ioaddr, | |
1110 | ss->irq = info->board->irq, | |
1111 | ss->flags = info->port.flags, | |
a6970c39 | 1112 | ss->baud_base = MXSER_BAUD_BASE, |
be6cf583 JH |
1113 | ss->close_delay = close_delay; |
1114 | ss->closing_wait = closing_wait; | |
d811b26b | 1115 | ss->custom_divisor = MXSER_CUSTOM_DIVISOR, |
6da5b587 | 1116 | mutex_unlock(&port->mutex); |
1c45607a JS |
1117 | return 0; |
1118 | } | |
1119 | ||
216ba023 | 1120 | static int mxser_set_serial_info(struct tty_struct *tty, |
6da5b587 | 1121 | struct serial_struct *ss) |
1da177e4 | 1122 | { |
216ba023 | 1123 | struct mxser_port *info = tty->driver_data; |
07f86c03 | 1124 | struct tty_port *port = &info->port; |
80ff8a80 | 1125 | speed_t baud; |
1c45607a | 1126 | unsigned long sl_flags; |
be6cf583 | 1127 | unsigned int flags, close_delay, closing_wait; |
1c45607a | 1128 | int retval = 0; |
1da177e4 | 1129 | |
6da5b587 AV |
1130 | if (tty_io_error(tty)) |
1131 | return -EIO; | |
1132 | ||
1133 | mutex_lock(&port->mutex); | |
1134 | if (!info->ioaddr) { | |
1135 | mutex_unlock(&port->mutex); | |
80ff8a80 | 1136 | return -ENODEV; |
6da5b587 | 1137 | } |
1da177e4 | 1138 | |
6da5b587 AV |
1139 | if (ss->irq != info->board->irq || |
1140 | ss->port != info->ioaddr) { | |
1141 | mutex_unlock(&port->mutex); | |
80ff8a80 | 1142 | return -EINVAL; |
6da5b587 | 1143 | } |
1da177e4 | 1144 | |
07f86c03 | 1145 | flags = port->flags & ASYNC_SPD_MASK; |
1da177e4 | 1146 | |
be6cf583 JH |
1147 | close_delay = msecs_to_jiffies(ss->close_delay * 10); |
1148 | closing_wait = ss->closing_wait; | |
1149 | if (closing_wait != ASYNC_CLOSING_WAIT_NONE) | |
1150 | closing_wait = msecs_to_jiffies(closing_wait * 10); | |
1151 | ||
1c45607a | 1152 | if (!capable(CAP_SYS_ADMIN)) { |
a6970c39 | 1153 | if ((ss->baud_base != MXSER_BAUD_BASE) || |
be6cf583 | 1154 | (close_delay != info->port.close_delay) || |
b91cfb25 | 1155 | (closing_wait != info->port.closing_wait) || |
6da5b587 AV |
1156 | ((ss->flags & ~ASYNC_USR_MASK) != (info->port.flags & ~ASYNC_USR_MASK))) { |
1157 | mutex_unlock(&port->mutex); | |
1c45607a | 1158 | return -EPERM; |
6da5b587 | 1159 | } |
0ad9e7d1 | 1160 | info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) | |
6da5b587 | 1161 | (ss->flags & ASYNC_USR_MASK)); |
1c45607a | 1162 | } else { |
1da177e4 | 1163 | /* |
1c45607a JS |
1164 | * OK, past this point, all the error checking has been done. |
1165 | * At this point, we start making changes..... | |
1da177e4 | 1166 | */ |
07f86c03 | 1167 | port->flags = ((port->flags & ~ASYNC_FLAGS) | |
6da5b587 | 1168 | (ss->flags & ASYNC_FLAGS)); |
be6cf583 JH |
1169 | port->close_delay = close_delay; |
1170 | port->closing_wait = closing_wait; | |
07f86c03 | 1171 | if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST && |
a6970c39 | 1172 | (ss->baud_base != MXSER_BAUD_BASE || |
6da5b587 | 1173 | ss->custom_divisor != |
d811b26b | 1174 | MXSER_CUSTOM_DIVISOR)) { |
6da5b587 AV |
1175 | if (ss->custom_divisor == 0) { |
1176 | mutex_unlock(&port->mutex); | |
07f86c03 | 1177 | return -EINVAL; |
6da5b587 AV |
1178 | } |
1179 | baud = ss->baud_base / ss->custom_divisor; | |
216ba023 | 1180 | tty_encode_baud_rate(tty, baud, baud); |
80ff8a80 | 1181 | } |
fc83815c | 1182 | |
b91cfb25 | 1183 | info->type = ss->type; |
1da177e4 | 1184 | |
b91cfb25 JH |
1185 | process_txrx_fifo(info); |
1186 | } | |
1c45607a | 1187 | |
d41861ca | 1188 | if (tty_port_initialized(port)) { |
07f86c03 | 1189 | if (flags != (port->flags & ASYNC_SPD_MASK)) { |
1c45607a | 1190 | spin_lock_irqsave(&info->slock, sl_flags); |
2799707f | 1191 | mxser_change_speed(tty); |
1c45607a | 1192 | spin_unlock_irqrestore(&info->slock, sl_flags); |
1da177e4 | 1193 | } |
6769140d | 1194 | } else { |
07f86c03 | 1195 | retval = mxser_activate(port, tty); |
6769140d | 1196 | if (retval == 0) |
d41861ca | 1197 | tty_port_set_initialized(port, 1); |
6769140d | 1198 | } |
6da5b587 | 1199 | mutex_unlock(&port->mutex); |
1c45607a JS |
1200 | return retval; |
1201 | } | |
1da177e4 | 1202 | |
1c45607a JS |
1203 | /* |
1204 | * mxser_get_lsr_info - get line status register info | |
1205 | * | |
1206 | * Purpose: Let user call ioctl() to get info when the UART physically | |
1207 | * is emptied. On bus types like RS485, the transmitter must | |
1208 | * release the bus after transmitting. This must be done when | |
1209 | * the transmit shift register is empty, not be done when the | |
1210 | * transmit holding register is empty. This functionality | |
1211 | * allows an RS485 driver to be written in user space. | |
1212 | */ | |
1213 | static int mxser_get_lsr_info(struct mxser_port *info, | |
1214 | unsigned int __user *value) | |
1215 | { | |
1216 | unsigned char status; | |
1217 | unsigned int result; | |
1218 | unsigned long flags; | |
1da177e4 | 1219 | |
1c45607a JS |
1220 | spin_lock_irqsave(&info->slock, flags); |
1221 | status = inb(info->ioaddr + UART_LSR); | |
1222 | spin_unlock_irqrestore(&info->slock, flags); | |
1223 | result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0); | |
1224 | return put_user(result, value); | |
1225 | } | |
1da177e4 | 1226 | |
60b33c13 | 1227 | static int mxser_tiocmget(struct tty_struct *tty) |
1c45607a JS |
1228 | { |
1229 | struct mxser_port *info = tty->driver_data; | |
1230 | unsigned char control, status; | |
1231 | unsigned long flags; | |
1da177e4 | 1232 | |
18900ca6 | 1233 | if (tty_io_error(tty)) |
1c45607a | 1234 | return -EIO; |
1da177e4 | 1235 | |
1c45607a | 1236 | control = info->MCR; |
1da177e4 | 1237 | |
1c45607a JS |
1238 | spin_lock_irqsave(&info->slock, flags); |
1239 | status = inb(info->ioaddr + UART_MSR); | |
1240 | if (status & UART_MSR_ANY_DELTA) | |
216ba023 | 1241 | mxser_check_modem_status(tty, info, status); |
1c45607a JS |
1242 | spin_unlock_irqrestore(&info->slock, flags); |
1243 | return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) | | |
1244 | ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) | | |
1245 | ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) | | |
1246 | ((status & UART_MSR_RI) ? TIOCM_RNG : 0) | | |
1247 | ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) | | |
1248 | ((status & UART_MSR_CTS) ? TIOCM_CTS : 0); | |
1249 | } | |
1da177e4 | 1250 | |
20b9d177 | 1251 | static int mxser_tiocmset(struct tty_struct *tty, |
1c45607a JS |
1252 | unsigned int set, unsigned int clear) |
1253 | { | |
1254 | struct mxser_port *info = tty->driver_data; | |
1255 | unsigned long flags; | |
1da177e4 | 1256 | |
18900ca6 | 1257 | if (tty_io_error(tty)) |
1c45607a | 1258 | return -EIO; |
1da177e4 | 1259 | |
1c45607a | 1260 | spin_lock_irqsave(&info->slock, flags); |
1da177e4 | 1261 | |
1c45607a JS |
1262 | if (set & TIOCM_RTS) |
1263 | info->MCR |= UART_MCR_RTS; | |
1264 | if (set & TIOCM_DTR) | |
1265 | info->MCR |= UART_MCR_DTR; | |
1da177e4 | 1266 | |
1c45607a JS |
1267 | if (clear & TIOCM_RTS) |
1268 | info->MCR &= ~UART_MCR_RTS; | |
1269 | if (clear & TIOCM_DTR) | |
1270 | info->MCR &= ~UART_MCR_DTR; | |
8ea2c2ec | 1271 | |
1c45607a JS |
1272 | outb(info->MCR, info->ioaddr + UART_MCR); |
1273 | spin_unlock_irqrestore(&info->slock, flags); | |
1274 | return 0; | |
1275 | } | |
1da177e4 | 1276 | |
1c45607a JS |
1277 | static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg, |
1278 | struct async_icount *cprev) | |
1da177e4 | 1279 | { |
1c45607a JS |
1280 | struct async_icount cnow; |
1281 | unsigned long flags; | |
1282 | int ret; | |
1da177e4 | 1283 | |
1c45607a JS |
1284 | spin_lock_irqsave(&info->slock, flags); |
1285 | cnow = info->icount; /* atomic copy */ | |
1286 | spin_unlock_irqrestore(&info->slock, flags); | |
1da177e4 | 1287 | |
1c45607a JS |
1288 | ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) || |
1289 | ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) || | |
1290 | ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) || | |
1291 | ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts)); | |
1da177e4 | 1292 | |
1c45607a JS |
1293 | *cprev = cnow; |
1294 | ||
1295 | return ret; | |
1296 | } | |
1297 | ||
9fae5f85 JS |
1298 | /* We should likely switch to TIOCGRS485/TIOCSRS485. */ |
1299 | static int mxser_ioctl_op_mode(struct mxser_port *port, int index, bool set, | |
1300 | int __user *u_opmode) | |
1301 | { | |
9fae5f85 JS |
1302 | int opmode, p = index % 4; |
1303 | int shiftbit = p * 2; | |
238d117d | 1304 | u8 val; |
9fae5f85 JS |
1305 | |
1306 | if (port->board->must_hwid != MOXA_MUST_MU860_HWID) | |
1307 | return -EFAULT; | |
1308 | ||
1309 | if (set) { | |
1310 | if (get_user(opmode, u_opmode)) | |
1311 | return -EFAULT; | |
1312 | ||
238d117d JS |
1313 | if (opmode & ~OP_MODE_MASK) |
1314 | return -EINVAL; | |
9fae5f85 JS |
1315 | |
1316 | spin_lock_irq(&port->slock); | |
1317 | val = inb(port->opmode_ioaddr); | |
238d117d | 1318 | val &= ~(OP_MODE_MASK << shiftbit); |
9fae5f85 JS |
1319 | val |= (opmode << shiftbit); |
1320 | outb(val, port->opmode_ioaddr); | |
1321 | spin_unlock_irq(&port->slock); | |
9fae5f85 | 1322 | |
238d117d | 1323 | return 0; |
9fae5f85 JS |
1324 | } |
1325 | ||
238d117d JS |
1326 | spin_lock_irq(&port->slock); |
1327 | opmode = inb(port->opmode_ioaddr) >> shiftbit; | |
1328 | spin_unlock_irq(&port->slock); | |
1329 | ||
1330 | return put_user(opmode & OP_MODE_MASK, u_opmode); | |
9fae5f85 JS |
1331 | } |
1332 | ||
6caa76b7 | 1333 | static int mxser_ioctl(struct tty_struct *tty, |
1c45607a | 1334 | unsigned int cmd, unsigned long arg) |
1da177e4 | 1335 | { |
1c45607a JS |
1336 | struct mxser_port *info = tty->driver_data; |
1337 | struct async_icount cnow; | |
1c45607a JS |
1338 | unsigned long flags; |
1339 | void __user *argp = (void __user *)arg; | |
1da177e4 | 1340 | |
9fae5f85 JS |
1341 | if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) |
1342 | return mxser_ioctl_op_mode(info, tty->index, | |
1343 | cmd == MOXA_SET_OP_MODE, argp); | |
1c45607a | 1344 | |
6da5b587 | 1345 | if (cmd != TIOCMIWAIT && tty_io_error(tty)) |
1c45607a JS |
1346 | return -EIO; |
1347 | ||
1348 | switch (cmd) { | |
1c45607a | 1349 | case TIOCSERGETLSR: /* Get line status register */ |
9d6d162d | 1350 | return mxser_get_lsr_info(info, argp); |
1c45607a JS |
1351 | /* |
1352 | * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change | |
1353 | * - mask passed in arg for lines of interest | |
1354 | * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) | |
1355 | * Caller should use TIOCGICOUNT to see which one it was | |
1356 | */ | |
1357 | case TIOCMIWAIT: | |
1358 | spin_lock_irqsave(&info->slock, flags); | |
1359 | cnow = info->icount; /* note the counters on entry */ | |
1360 | spin_unlock_irqrestore(&info->slock, flags); | |
1361 | ||
bdc04e31 | 1362 | return wait_event_interruptible(info->port.delta_msr_wait, |
1c45607a | 1363 | mxser_cflags_changed(info, arg, &cnow)); |
1c45607a JS |
1364 | default: |
1365 | return -ENOIOCTLCMD; | |
1366 | } | |
1367 | return 0; | |
1368 | } | |
1369 | ||
0587102c AC |
1370 | /* |
1371 | * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) | |
1372 | * Return: write counters to the user passed counter struct | |
1373 | * NB: both 1->0 and 0->1 transitions are counted except for | |
1374 | * RI where only 0->1 is counted. | |
1375 | */ | |
1376 | ||
1377 | static int mxser_get_icount(struct tty_struct *tty, | |
1378 | struct serial_icounter_struct *icount) | |
1379 | ||
1380 | { | |
1381 | struct mxser_port *info = tty->driver_data; | |
1382 | struct async_icount cnow; | |
1383 | unsigned long flags; | |
1384 | ||
1385 | spin_lock_irqsave(&info->slock, flags); | |
1386 | cnow = info->icount; | |
1387 | spin_unlock_irqrestore(&info->slock, flags); | |
1388 | ||
1389 | icount->frame = cnow.frame; | |
1390 | icount->brk = cnow.brk; | |
1391 | icount->overrun = cnow.overrun; | |
1392 | icount->buf_overrun = cnow.buf_overrun; | |
1393 | icount->parity = cnow.parity; | |
1394 | icount->rx = cnow.rx; | |
1395 | icount->tx = cnow.tx; | |
1396 | icount->cts = cnow.cts; | |
1397 | icount->dsr = cnow.dsr; | |
1398 | icount->rng = cnow.rng; | |
1399 | icount->dcd = cnow.dcd; | |
1400 | return 0; | |
1401 | } | |
1402 | ||
1c45607a JS |
1403 | static void mxser_stoprx(struct tty_struct *tty) |
1404 | { | |
1405 | struct mxser_port *info = tty->driver_data; | |
1406 | ||
1407 | info->ldisc_stop_rx = 1; | |
1408 | if (I_IXOFF(tty)) { | |
292955a7 | 1409 | if (info->board->must_hwid) { |
1c45607a JS |
1410 | info->IER &= ~MOXA_MUST_RECV_ISR; |
1411 | outb(info->IER, info->ioaddr + UART_IER); | |
1412 | } else { | |
1413 | info->x_char = STOP_CHAR(tty); | |
1414 | outb(0, info->ioaddr + UART_IER); | |
1415 | info->IER |= UART_IER_THRI; | |
1416 | outb(info->IER, info->ioaddr + UART_IER); | |
1da177e4 LT |
1417 | } |
1418 | } | |
1419 | ||
9db276f8 | 1420 | if (C_CRTSCTS(tty)) { |
1c45607a JS |
1421 | info->MCR &= ~UART_MCR_RTS; |
1422 | outb(info->MCR, info->ioaddr + UART_MCR); | |
1da177e4 LT |
1423 | } |
1424 | } | |
1425 | ||
1426 | /* | |
1427 | * This routine is called by the upper-layer tty layer to signal that | |
1428 | * incoming characters should be throttled. | |
1429 | */ | |
1430 | static void mxser_throttle(struct tty_struct *tty) | |
1431 | { | |
1da177e4 | 1432 | mxser_stoprx(tty); |
1da177e4 LT |
1433 | } |
1434 | ||
1435 | static void mxser_unthrottle(struct tty_struct *tty) | |
1436 | { | |
1c45607a | 1437 | struct mxser_port *info = tty->driver_data; |
1da177e4 | 1438 | |
1c45607a JS |
1439 | /* startrx */ |
1440 | info->ldisc_stop_rx = 0; | |
1441 | if (I_IXOFF(tty)) { | |
1442 | if (info->x_char) | |
1443 | info->x_char = 0; | |
1444 | else { | |
292955a7 | 1445 | if (info->board->must_hwid) { |
1c45607a JS |
1446 | info->IER |= MOXA_MUST_RECV_ISR; |
1447 | outb(info->IER, info->ioaddr + UART_IER); | |
1448 | } else { | |
1449 | info->x_char = START_CHAR(tty); | |
1450 | outb(0, info->ioaddr + UART_IER); | |
1451 | info->IER |= UART_IER_THRI; | |
1452 | outb(info->IER, info->ioaddr + UART_IER); | |
1453 | } | |
1da177e4 | 1454 | } |
1c45607a | 1455 | } |
1da177e4 | 1456 | |
9db276f8 | 1457 | if (C_CRTSCTS(tty)) { |
1c45607a JS |
1458 | info->MCR |= UART_MCR_RTS; |
1459 | outb(info->MCR, info->ioaddr + UART_MCR); | |
1da177e4 LT |
1460 | } |
1461 | } | |
1462 | ||
1463 | /* | |
1464 | * mxser_stop() and mxser_start() | |
1465 | * | |
6e94dbc7 | 1466 | * This routines are called before setting or resetting tty->flow.stopped. |
1da177e4 LT |
1467 | * They enable or disable transmitter interrupts, as necessary. |
1468 | */ | |
1469 | static void mxser_stop(struct tty_struct *tty) | |
1470 | { | |
1c45607a | 1471 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
1472 | unsigned long flags; |
1473 | ||
1474 | spin_lock_irqsave(&info->slock, flags); | |
1475 | if (info->IER & UART_IER_THRI) { | |
1476 | info->IER &= ~UART_IER_THRI; | |
1c45607a | 1477 | outb(info->IER, info->ioaddr + UART_IER); |
1da177e4 LT |
1478 | } |
1479 | spin_unlock_irqrestore(&info->slock, flags); | |
1480 | } | |
1481 | ||
1482 | static void mxser_start(struct tty_struct *tty) | |
1483 | { | |
1c45607a | 1484 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
1485 | unsigned long flags; |
1486 | ||
1487 | spin_lock_irqsave(&info->slock, flags); | |
0ad9e7d1 | 1488 | if (info->xmit_cnt && info->port.xmit_buf) { |
1c45607a | 1489 | outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); |
1da177e4 | 1490 | info->IER |= UART_IER_THRI; |
1c45607a | 1491 | outb(info->IER, info->ioaddr + UART_IER); |
1da177e4 LT |
1492 | } |
1493 | spin_unlock_irqrestore(&info->slock, flags); | |
1494 | } | |
1495 | ||
1c45607a JS |
1496 | static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios) |
1497 | { | |
1498 | struct mxser_port *info = tty->driver_data; | |
1499 | unsigned long flags; | |
1500 | ||
1501 | spin_lock_irqsave(&info->slock, flags); | |
2799707f | 1502 | mxser_change_speed(tty); |
1c45607a JS |
1503 | spin_unlock_irqrestore(&info->slock, flags); |
1504 | ||
9db276f8 | 1505 | if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) { |
1c45607a JS |
1506 | tty->hw_stopped = 0; |
1507 | mxser_start(tty); | |
1508 | } | |
1509 | ||
1510 | /* Handle sw stopped */ | |
9db276f8 | 1511 | if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) { |
6e94dbc7 | 1512 | tty->flow.stopped = 0; |
1c45607a | 1513 | |
292955a7 | 1514 | if (info->board->must_hwid) { |
1c45607a | 1515 | spin_lock_irqsave(&info->slock, flags); |
b441eb0f | 1516 | mxser_must_set_rx_sw_flow_control(info->ioaddr, false); |
1c45607a JS |
1517 | spin_unlock_irqrestore(&info->slock, flags); |
1518 | } | |
1519 | ||
1520 | mxser_start(tty); | |
1521 | } | |
1522 | } | |
1523 | ||
1da177e4 LT |
1524 | /* |
1525 | * mxser_wait_until_sent() --- wait until the transmitter is empty | |
1526 | */ | |
1527 | static void mxser_wait_until_sent(struct tty_struct *tty, int timeout) | |
1528 | { | |
1c45607a | 1529 | struct mxser_port *info = tty->driver_data; |
1da177e4 | 1530 | unsigned long orig_jiffies, char_time; |
07f86c03 | 1531 | unsigned long flags; |
1da177e4 LT |
1532 | int lsr; |
1533 | ||
1534 | if (info->type == PORT_UNKNOWN) | |
1535 | return; | |
1536 | ||
1537 | if (info->xmit_fifo_size == 0) | |
1538 | return; /* Just in case.... */ | |
1539 | ||
1540 | orig_jiffies = jiffies; | |
1541 | /* | |
1542 | * Set the check interval to be 1/5 of the estimated time to | |
1543 | * send a single character, and make it at least 1. The check | |
1544 | * interval should also be less than the timeout. | |
1545 | * | |
1546 | * Note: we have to use pretty tight timings here to satisfy | |
1547 | * the NIST-PCTS. | |
1548 | */ | |
1549 | char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size; | |
1550 | char_time = char_time / 5; | |
1551 | if (char_time == 0) | |
1552 | char_time = 1; | |
1553 | if (timeout && timeout < char_time) | |
1554 | char_time = timeout; | |
1555 | /* | |
1556 | * If the transmitter hasn't cleared in twice the approximate | |
1557 | * amount of time to send the entire FIFO, it probably won't | |
1558 | * ever clear. This assumes the UART isn't doing flow | |
1559 | * control, which is currently the case. Hence, if it ever | |
1560 | * takes longer than info->timeout, this is probably due to a | |
1561 | * UART bug of some kind. So, we clamp the timeout parameter at | |
1562 | * 2*info->timeout. | |
1563 | */ | |
1564 | if (!timeout || timeout > 2 * info->timeout) | |
1565 | timeout = 2 * info->timeout; | |
8bab534b | 1566 | |
07f86c03 | 1567 | spin_lock_irqsave(&info->slock, flags); |
1c45607a | 1568 | while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) { |
07f86c03 | 1569 | spin_unlock_irqrestore(&info->slock, flags); |
da4cd8df | 1570 | schedule_timeout_interruptible(char_time); |
07f86c03 | 1571 | spin_lock_irqsave(&info->slock, flags); |
1da177e4 | 1572 | if (signal_pending(current)) |
1c45607a JS |
1573 | break; |
1574 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
1575 | break; | |
1da177e4 | 1576 | } |
07f86c03 | 1577 | spin_unlock_irqrestore(&info->slock, flags); |
1c45607a | 1578 | set_current_state(TASK_RUNNING); |
1c45607a | 1579 | } |
1da177e4 | 1580 | |
1c45607a JS |
1581 | /* |
1582 | * This routine is called by tty_hangup() when a hangup is signaled. | |
1583 | */ | |
1584 | static void mxser_hangup(struct tty_struct *tty) | |
1585 | { | |
1586 | struct mxser_port *info = tty->driver_data; | |
1da177e4 | 1587 | |
1c45607a | 1588 | mxser_flush_buffer(tty); |
3b6826b2 | 1589 | tty_port_hangup(&info->port); |
1da177e4 LT |
1590 | } |
1591 | ||
1c45607a JS |
1592 | /* |
1593 | * mxser_rs_break() --- routine which turns the break handling on or off | |
1594 | */ | |
9e98966c | 1595 | static int mxser_rs_break(struct tty_struct *tty, int break_state) |
1da177e4 | 1596 | { |
1c45607a | 1597 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
1598 | unsigned long flags; |
1599 | ||
1c45607a JS |
1600 | spin_lock_irqsave(&info->slock, flags); |
1601 | if (break_state == -1) | |
1602 | outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC, | |
1603 | info->ioaddr + UART_LCR); | |
1604 | else | |
1605 | outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC, | |
1606 | info->ioaddr + UART_LCR); | |
1607 | spin_unlock_irqrestore(&info->slock, flags); | |
9e98966c | 1608 | return 0; |
1c45607a | 1609 | } |
1da177e4 | 1610 | |
e5ce1bce | 1611 | static bool mxser_receive_chars_new(struct tty_struct *tty, |
95b3ea4c | 1612 | struct mxser_port *port, u8 status) |
e5ce1bce JS |
1613 | { |
1614 | enum mxser_must_hwid hwid = port->board->must_hwid; | |
1615 | u8 gdl; | |
1616 | ||
1617 | if (hwid == MOXA_OTHER_UART) | |
1618 | return false; | |
70640052 | 1619 | if (status & UART_LSR_BRK_ERROR_BITS) |
e5ce1bce JS |
1620 | return false; |
1621 | if (hwid == MOXA_MUST_MU860_HWID && (status & MOXA_MUST_LSR_RERR)) | |
1622 | return false; | |
1623 | if (status & MOXA_MUST_LSR_RERR) | |
1624 | return false; | |
1625 | ||
1626 | gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER); | |
1627 | if (hwid == MOXA_MUST_MU150_HWID) | |
1628 | gdl &= MOXA_MUST_GDL_MASK; | |
1629 | ||
1630 | if (gdl >= tty->receive_room && !port->ldisc_stop_rx) | |
1631 | mxser_stoprx(tty); | |
1632 | ||
1633 | while (gdl--) { | |
1634 | u8 ch = inb(port->ioaddr + UART_RX); | |
1635 | tty_insert_flip_char(&port->port, ch, 0); | |
e5ce1bce JS |
1636 | } |
1637 | ||
1638 | return true; | |
1639 | } | |
1640 | ||
0c419421 | 1641 | static u8 mxser_receive_chars_old(struct tty_struct *tty, |
95b3ea4c | 1642 | struct mxser_port *port, u8 status) |
1c45607a | 1643 | { |
0c419421 JS |
1644 | enum mxser_must_hwid hwid = port->board->must_hwid; |
1645 | int recv_room = tty->receive_room; | |
1c45607a | 1646 | int ignored = 0; |
1c45607a | 1647 | int max = 256; |
95b3ea4c | 1648 | int cnt = 0; |
0c419421 | 1649 | u8 ch; |
1c45607a JS |
1650 | |
1651 | do { | |
1652 | if (max-- < 0) | |
1653 | break; | |
1da177e4 | 1654 | |
1c45607a | 1655 | ch = inb(port->ioaddr + UART_RX); |
0c419421 | 1656 | if (hwid && (status & UART_LSR_OE)) |
1c45607a | 1657 | outb(0x23, port->ioaddr + UART_FCR); |
15517806 JS |
1658 | status &= port->read_status_mask; |
1659 | if (status & port->ignore_status_mask) { | |
1c45607a JS |
1660 | if (++ignored > 100) |
1661 | break; | |
1662 | } else { | |
1663 | char flag = 0; | |
70640052 | 1664 | if (status & UART_LSR_BRK_ERROR_BITS) { |
15517806 | 1665 | if (status & UART_LSR_BI) { |
1c45607a JS |
1666 | flag = TTY_BREAK; |
1667 | port->icount.brk++; | |
1da177e4 | 1668 | |
0ad9e7d1 | 1669 | if (port->port.flags & ASYNC_SAK) |
1c45607a | 1670 | do_SAK(tty); |
15517806 | 1671 | } else if (status & UART_LSR_PE) { |
1c45607a JS |
1672 | flag = TTY_PARITY; |
1673 | port->icount.parity++; | |
15517806 | 1674 | } else if (status & UART_LSR_FE) { |
1c45607a JS |
1675 | flag = TTY_FRAME; |
1676 | port->icount.frame++; | |
15517806 | 1677 | } else if (status & UART_LSR_OE) { |
1c45607a JS |
1678 | flag = TTY_OVERRUN; |
1679 | port->icount.overrun++; | |
6de6e5c4 | 1680 | } |
1c45607a | 1681 | } |
92a19f9c | 1682 | tty_insert_flip_char(&port->port, ch, flag); |
95b3ea4c JS |
1683 | cnt++; |
1684 | if (cnt >= recv_room) { | |
1c45607a JS |
1685 | if (!port->ldisc_stop_rx) |
1686 | mxser_stoprx(tty); | |
1687 | break; | |
1688 | } | |
1da177e4 | 1689 | |
1c45607a | 1690 | } |
1da177e4 | 1691 | |
0c419421 | 1692 | if (hwid) |
1c45607a | 1693 | break; |
1da177e4 | 1694 | |
15517806 JS |
1695 | status = inb(port->ioaddr + UART_LSR); |
1696 | } while (status & UART_LSR_DR); | |
1da177e4 | 1697 | |
0c419421 JS |
1698 | return status; |
1699 | } | |
1700 | ||
1701 | static u8 mxser_receive_chars(struct tty_struct *tty, | |
1702 | struct mxser_port *port, u8 status) | |
1703 | { | |
0c419421 JS |
1704 | if (tty->receive_room == 0 && !port->ldisc_stop_rx) |
1705 | mxser_stoprx(tty); | |
1706 | ||
95b3ea4c JS |
1707 | if (!mxser_receive_chars_new(tty, port, status)) |
1708 | status = mxser_receive_chars_old(tty, port, status); | |
0c419421 | 1709 | |
2e124b4a | 1710 | tty_flip_buffer_push(&port->port); |
15517806 JS |
1711 | |
1712 | return status; | |
1da177e4 LT |
1713 | } |
1714 | ||
216ba023 | 1715 | static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port) |
1da177e4 | 1716 | { |
1c45607a | 1717 | int count, cnt; |
1da177e4 | 1718 | |
1c45607a JS |
1719 | if (port->x_char) { |
1720 | outb(port->x_char, port->ioaddr + UART_TX); | |
1721 | port->x_char = 0; | |
1c45607a JS |
1722 | port->icount.tx++; |
1723 | return; | |
1724 | } | |
1da177e4 | 1725 | |
0ad9e7d1 | 1726 | if (port->port.xmit_buf == NULL) |
1c45607a | 1727 | return; |
1da177e4 | 1728 | |
6e94dbc7 | 1729 | if (port->xmit_cnt <= 0 || tty->flow.stopped || |
216ba023 | 1730 | (tty->hw_stopped && |
1c45607a | 1731 | (port->type != PORT_16550A) && |
292955a7 | 1732 | (!port->board->must_hwid))) { |
1c45607a JS |
1733 | port->IER &= ~UART_IER_THRI; |
1734 | outb(port->IER, port->ioaddr + UART_IER); | |
1735 | return; | |
1da177e4 LT |
1736 | } |
1737 | ||
1c45607a JS |
1738 | cnt = port->xmit_cnt; |
1739 | count = port->xmit_fifo_size; | |
1740 | do { | |
0ad9e7d1 | 1741 | outb(port->port.xmit_buf[port->xmit_tail++], |
1c45607a JS |
1742 | port->ioaddr + UART_TX); |
1743 | port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1); | |
1744 | if (--port->xmit_cnt <= 0) | |
1745 | break; | |
1746 | } while (--count > 0); | |
1da177e4 | 1747 | |
1c45607a | 1748 | port->icount.tx += (cnt - port->xmit_cnt); |
1da177e4 | 1749 | |
464eb8f5 | 1750 | if (port->xmit_cnt < WAKEUP_CHARS) |
216ba023 | 1751 | tty_wakeup(tty); |
1c45607a JS |
1752 | |
1753 | if (port->xmit_cnt <= 0) { | |
1754 | port->IER &= ~UART_IER_THRI; | |
1755 | outb(port->IER, port->ioaddr + UART_IER); | |
1da177e4 | 1756 | } |
1da177e4 LT |
1757 | } |
1758 | ||
9e40ea1f JS |
1759 | static bool mxser_port_isr(struct mxser_port *port) |
1760 | { | |
1761 | struct tty_struct *tty; | |
1762 | u8 iir, msr, status; | |
1763 | bool error = false; | |
1764 | ||
1765 | iir = inb(port->ioaddr + UART_IIR); | |
1766 | if (iir & UART_IIR_NO_INT) | |
1767 | return true; | |
1768 | ||
1769 | iir &= MOXA_MUST_IIR_MASK; | |
1770 | tty = tty_port_tty_get(&port->port); | |
1771 | if (!tty || port->closing || !tty_port_initialized(&port->port)) { | |
1772 | status = inb(port->ioaddr + UART_LSR); | |
1773 | outb(0x27, port->ioaddr + UART_FCR); | |
1774 | inb(port->ioaddr + UART_MSR); | |
1775 | ||
1776 | error = true; | |
1777 | goto put_tty; | |
1778 | } | |
1779 | ||
1780 | status = inb(port->ioaddr + UART_LSR); | |
1781 | ||
9e40ea1f JS |
1782 | if (port->board->must_hwid) { |
1783 | if (iir == MOXA_MUST_IIR_GDA || | |
1784 | iir == MOXA_MUST_IIR_RDA || | |
1785 | iir == MOXA_MUST_IIR_RTO || | |
1786 | iir == MOXA_MUST_IIR_LSR) | |
1787 | status = mxser_receive_chars(tty, port, status); | |
1788 | } else { | |
1789 | status &= port->read_status_mask; | |
1790 | if (status & UART_LSR_DR) | |
1791 | status = mxser_receive_chars(tty, port, status); | |
1792 | } | |
1793 | ||
1794 | msr = inb(port->ioaddr + UART_MSR); | |
1795 | if (msr & UART_MSR_ANY_DELTA) | |
1796 | mxser_check_modem_status(tty, port, msr); | |
1797 | ||
1798 | if (port->board->must_hwid) { | |
1799 | if (iir == 0x02 && (status & UART_LSR_THRE)) | |
1800 | mxser_transmit_chars(tty, port); | |
1801 | } else { | |
1802 | if (status & UART_LSR_THRE) | |
1803 | mxser_transmit_chars(tty, port); | |
1804 | } | |
1805 | ||
1806 | put_tty: | |
1807 | tty_kref_put(tty); | |
1808 | ||
1809 | return error; | |
1810 | } | |
1811 | ||
1da177e4 | 1812 | /* |
1c45607a | 1813 | * This is the serial driver's generic interrupt routine |
1da177e4 | 1814 | */ |
1c45607a | 1815 | static irqreturn_t mxser_interrupt(int irq, void *dev_id) |
1da177e4 | 1816 | { |
cef222cb | 1817 | struct mxser_board *brd = dev_id; |
1c45607a | 1818 | struct mxser_port *port; |
1c45607a | 1819 | unsigned int int_cnt, pass_counter = 0; |
9cb5c9c3 | 1820 | unsigned int i, max = brd->info->nports; |
1c45607a | 1821 | int handled = IRQ_NONE; |
9cb5c9c3 | 1822 | u8 irqbits, bits, mask = BIT(max) - 1; |
1da177e4 | 1823 | |
1c45607a | 1824 | while (pass_counter++ < MXSER_ISR_PASS_LIMIT) { |
9cb5c9c3 JS |
1825 | irqbits = inb(brd->vector) & mask; |
1826 | if (irqbits == mask) | |
1c45607a | 1827 | break; |
1da177e4 | 1828 | |
1c45607a JS |
1829 | handled = IRQ_HANDLED; |
1830 | for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) { | |
9cb5c9c3 | 1831 | if (irqbits == mask) |
1c45607a JS |
1832 | break; |
1833 | if (bits & irqbits) | |
1834 | continue; | |
1835 | port = &brd->ports[i]; | |
1836 | ||
1837 | int_cnt = 0; | |
1838 | spin_lock(&port->slock); | |
1839 | do { | |
9e40ea1f | 1840 | if (mxser_port_isr(port)) |
1c45607a | 1841 | break; |
1c45607a JS |
1842 | } while (int_cnt++ < MXSER_ISR_PASS_LIMIT); |
1843 | spin_unlock(&port->slock); | |
1844 | } | |
1845 | } | |
1da177e4 | 1846 | |
1c45607a JS |
1847 | return handled; |
1848 | } | |
1da177e4 | 1849 | |
1c45607a JS |
1850 | static const struct tty_operations mxser_ops = { |
1851 | .open = mxser_open, | |
1852 | .close = mxser_close, | |
1853 | .write = mxser_write, | |
1854 | .put_char = mxser_put_char, | |
1855 | .flush_chars = mxser_flush_chars, | |
1856 | .write_room = mxser_write_room, | |
1857 | .chars_in_buffer = mxser_chars_in_buffer, | |
1858 | .flush_buffer = mxser_flush_buffer, | |
1859 | .ioctl = mxser_ioctl, | |
1860 | .throttle = mxser_throttle, | |
1861 | .unthrottle = mxser_unthrottle, | |
1862 | .set_termios = mxser_set_termios, | |
1863 | .stop = mxser_stop, | |
1864 | .start = mxser_start, | |
1865 | .hangup = mxser_hangup, | |
1866 | .break_ctl = mxser_rs_break, | |
1867 | .wait_until_sent = mxser_wait_until_sent, | |
1868 | .tiocmget = mxser_tiocmget, | |
1869 | .tiocmset = mxser_tiocmset, | |
6da5b587 AV |
1870 | .set_serial = mxser_set_serial_info, |
1871 | .get_serial = mxser_get_serial_info, | |
0587102c | 1872 | .get_icount = mxser_get_icount, |
1c45607a | 1873 | }; |
1da177e4 | 1874 | |
04b757df | 1875 | static const struct tty_port_operations mxser_port_ops = { |
31f35939 | 1876 | .carrier_raised = mxser_carrier_raised, |
fcc8ac18 | 1877 | .dtr_rts = mxser_dtr_rts, |
6769140d AC |
1878 | .activate = mxser_activate, |
1879 | .shutdown = mxser_shutdown_port, | |
31f35939 AC |
1880 | }; |
1881 | ||
1c45607a JS |
1882 | /* |
1883 | * The MOXA Smartio/Industio serial driver boot-time initialization code! | |
1884 | */ | |
1da177e4 | 1885 | |
2799707f | 1886 | static int mxser_initbrd(struct mxser_board *brd) |
1da177e4 | 1887 | { |
1c45607a JS |
1888 | struct mxser_port *info; |
1889 | unsigned int i; | |
1890 | int retval; | |
57faa7d6 JS |
1891 | bool is_mu860; |
1892 | ||
1893 | brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr); | |
1894 | is_mu860 = brd->must_hwid == MOXA_MUST_MU860_HWID; | |
1895 | ||
1896 | for (i = 0; i < UART_INFO_NUM; i++) { | |
1897 | if (Gpci_uart_info[i].type == brd->must_hwid) { | |
1898 | brd->max_baud = Gpci_uart_info[i].max_baud; | |
1899 | ||
1900 | /* exception....CP-102 */ | |
1901 | if (brd->info->flags & MXSER_HIGHBAUD) | |
1902 | brd->max_baud = 921600; | |
1903 | break; | |
1904 | } | |
1905 | } | |
1906 | ||
1907 | if (is_mu860) { | |
1908 | /* set to RS232 mode by default */ | |
1909 | outb(0, brd->vector + 4); | |
1910 | outb(0, brd->vector + 0x0c); | |
1911 | } | |
1da177e4 | 1912 | |
1c45607a JS |
1913 | for (i = 0; i < brd->info->nports; i++) { |
1914 | info = &brd->ports[i]; | |
57faa7d6 JS |
1915 | if (is_mu860) { |
1916 | if (i < 4) | |
1917 | info->opmode_ioaddr = brd->vector + 4; | |
1918 | else | |
1919 | info->opmode_ioaddr = brd->vector + 0x0c; | |
1920 | } | |
44b7d1b3 | 1921 | tty_port_init(&info->port); |
31f35939 | 1922 | info->port.ops = &mxser_port_ops; |
1c45607a | 1923 | info->board = brd; |
1c45607a | 1924 | info->ldisc_stop_rx = 0; |
1da177e4 | 1925 | |
1c45607a | 1926 | /* Enhance mode enabled here */ |
292955a7 | 1927 | if (brd->must_hwid != MOXA_OTHER_UART) |
edb7d27c | 1928 | mxser_must_set_enhance_mode(info->ioaddr, true); |
1da177e4 | 1929 | |
58a2ddb3 | 1930 | info->type = PORT_16550A; |
1da177e4 | 1931 | |
1c45607a | 1932 | process_txrx_fifo(info); |
1da177e4 | 1933 | |
44b7d1b3 AC |
1934 | info->port.close_delay = 5 * HZ / 10; |
1935 | info->port.closing_wait = 30 * HZ; | |
1c45607a | 1936 | spin_lock_init(&info->slock); |
1da177e4 | 1937 | |
1c45607a JS |
1938 | /* before set INT ISR, disable all int */ |
1939 | outb(inb(info->ioaddr + UART_IER) & 0xf0, | |
1940 | info->ioaddr + UART_IER); | |
1941 | } | |
1da177e4 | 1942 | |
1c45607a JS |
1943 | retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser", |
1944 | brd); | |
191c5f10 JS |
1945 | if (retval) { |
1946 | for (i = 0; i < brd->info->nports; i++) | |
1947 | tty_port_destroy(&brd->ports[i].port); | |
1c45607a JS |
1948 | printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may " |
1949 | "conflict with another device.\n", | |
1950 | brd->info->name, brd->irq); | |
191c5f10 | 1951 | } |
df480518 | 1952 | |
1c45607a JS |
1953 | return retval; |
1954 | } | |
1da177e4 | 1955 | |
9671f099 | 1956 | static int mxser_probe(struct pci_dev *pdev, |
1c45607a | 1957 | const struct pci_device_id *ent) |
1da177e4 | 1958 | { |
1c45607a | 1959 | struct mxser_board *brd; |
57faa7d6 | 1960 | unsigned int i; |
1c45607a | 1961 | unsigned long ioaddress; |
9e17df37 | 1962 | struct device *tty_dev; |
1c45607a | 1963 | int retval = -EINVAL; |
1da177e4 | 1964 | |
1c45607a JS |
1965 | for (i = 0; i < MXSER_BOARDS; i++) |
1966 | if (mxser_boards[i].info == NULL) | |
1967 | break; | |
1968 | ||
1969 | if (i >= MXSER_BOARDS) { | |
83766bc6 JS |
1970 | dev_err(&pdev->dev, "too many boards found (maximum %d), board " |
1971 | "not configured\n", MXSER_BOARDS); | |
1c45607a JS |
1972 | goto err; |
1973 | } | |
1974 | ||
1975 | brd = &mxser_boards[i]; | |
1976 | brd->idx = i * MXSER_PORTS_PER_BOARD; | |
83766bc6 | 1977 | dev_info(&pdev->dev, "found MOXA %s board (BusNo=%d, DevNo=%d)\n", |
1c45607a JS |
1978 | mxser_cards[ent->driver_data].name, |
1979 | pdev->bus->number, PCI_SLOT(pdev->devfn)); | |
1980 | ||
dcb04e21 | 1981 | retval = pcim_enable_device(pdev); |
1c45607a | 1982 | if (retval) { |
83766bc6 | 1983 | dev_err(&pdev->dev, "PCI enable failed\n"); |
1c45607a JS |
1984 | goto err; |
1985 | } | |
1986 | ||
1987 | /* io address */ | |
1988 | ioaddress = pci_resource_start(pdev, 2); | |
1989 | retval = pci_request_region(pdev, 2, "mxser(IO)"); | |
1990 | if (retval) | |
dcb04e21 | 1991 | goto err; |
1c45607a JS |
1992 | |
1993 | brd->info = &mxser_cards[ent->driver_data]; | |
1994 | for (i = 0; i < brd->info->nports; i++) | |
1995 | brd->ports[i].ioaddr = ioaddress + 8 * i; | |
1996 | ||
1997 | /* vector */ | |
1998 | ioaddress = pci_resource_start(pdev, 3); | |
1999 | retval = pci_request_region(pdev, 3, "mxser(vector)"); | |
2000 | if (retval) | |
df480518 | 2001 | goto err_zero; |
1c45607a JS |
2002 | brd->vector = ioaddress; |
2003 | ||
2004 | /* irq */ | |
2005 | brd->irq = pdev->irq; | |
2006 | ||
1c45607a | 2007 | /* mxser_initbrd will hook ISR. */ |
2799707f | 2008 | retval = mxser_initbrd(brd); |
1c45607a | 2009 | if (retval) |
dcb04e21 | 2010 | goto err_zero; |
1c45607a | 2011 | |
9e17df37 AK |
2012 | for (i = 0; i < brd->info->nports; i++) { |
2013 | tty_dev = tty_port_register_device(&brd->ports[i].port, | |
2014 | mxvar_sdriver, brd->idx + i, &pdev->dev); | |
2015 | if (IS_ERR(tty_dev)) { | |
2016 | retval = PTR_ERR(tty_dev); | |
1b581f17 | 2017 | for (; i > 0; i--) |
9e17df37 | 2018 | tty_unregister_device(mxvar_sdriver, |
1b581f17 | 2019 | brd->idx + i - 1); |
9e17df37 AK |
2020 | goto err_relbrd; |
2021 | } | |
2022 | } | |
1c45607a JS |
2023 | |
2024 | pci_set_drvdata(pdev, brd); | |
2025 | ||
2026 | return 0; | |
9e17df37 AK |
2027 | err_relbrd: |
2028 | for (i = 0; i < brd->info->nports; i++) | |
2029 | tty_port_destroy(&brd->ports[i].port); | |
2030 | free_irq(brd->irq, brd); | |
df480518 | 2031 | err_zero: |
1c45607a JS |
2032 | brd->info = NULL; |
2033 | err: | |
2034 | return retval; | |
1da177e4 LT |
2035 | } |
2036 | ||
ae8d8a14 | 2037 | static void mxser_remove(struct pci_dev *pdev) |
1da177e4 | 2038 | { |
1c45607a | 2039 | struct mxser_board *brd = pci_get_drvdata(pdev); |
d450f085 JS |
2040 | unsigned int i; |
2041 | ||
2042 | for (i = 0; i < brd->info->nports; i++) { | |
2043 | tty_unregister_device(mxvar_sdriver, brd->idx + i); | |
2044 | tty_port_destroy(&brd->ports[i].port); | |
2045 | } | |
1da177e4 | 2046 | |
d450f085 | 2047 | free_irq(brd->irq, brd); |
1da177e4 | 2048 | |
1c45607a | 2049 | brd->info = NULL; |
1da177e4 LT |
2050 | } |
2051 | ||
1c45607a JS |
2052 | static struct pci_driver mxser_driver = { |
2053 | .name = "mxser", | |
2054 | .id_table = mxser_pcibrds, | |
2055 | .probe = mxser_probe, | |
91116cba | 2056 | .remove = mxser_remove |
1c45607a JS |
2057 | }; |
2058 | ||
2059 | static int __init mxser_module_init(void) | |
1da177e4 | 2060 | { |
1df00924 | 2061 | int retval; |
1da177e4 | 2062 | |
389fc82e | 2063 | mxvar_sdriver = alloc_tty_driver(MXSER_PORTS); |
1c45607a JS |
2064 | if (!mxvar_sdriver) |
2065 | return -ENOMEM; | |
2066 | ||
1c45607a | 2067 | /* Initialize the tty_driver structure */ |
1c45607a JS |
2068 | mxvar_sdriver->name = "ttyMI"; |
2069 | mxvar_sdriver->major = ttymajor; | |
2070 | mxvar_sdriver->minor_start = 0; | |
1c45607a JS |
2071 | mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL; |
2072 | mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL; | |
2073 | mxvar_sdriver->init_termios = tty_std_termios; | |
2074 | mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL; | |
2075 | mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV; | |
2076 | tty_set_operations(mxvar_sdriver, &mxser_ops); | |
2077 | ||
2078 | retval = tty_register_driver(mxvar_sdriver); | |
2079 | if (retval) { | |
2080 | printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family " | |
2081 | "tty driver !\n"); | |
2082 | goto err_put; | |
1da177e4 | 2083 | } |
1c45607a | 2084 | |
1c45607a JS |
2085 | retval = pci_register_driver(&mxser_driver); |
2086 | if (retval) { | |
83766bc6 | 2087 | printk(KERN_ERR "mxser: can't register pci driver\n"); |
29134367 | 2088 | goto err_unr; |
1c45607a JS |
2089 | } |
2090 | ||
1c45607a JS |
2091 | return 0; |
2092 | err_unr: | |
2093 | tty_unregister_driver(mxvar_sdriver); | |
2094 | err_put: | |
2095 | put_tty_driver(mxvar_sdriver); | |
2096 | return retval; | |
2097 | } | |
2098 | ||
2099 | static void __exit mxser_module_exit(void) | |
2100 | { | |
1c45607a | 2101 | pci_unregister_driver(&mxser_driver); |
1c45607a JS |
2102 | tty_unregister_driver(mxvar_sdriver); |
2103 | put_tty_driver(mxvar_sdriver); | |
1da177e4 LT |
2104 | } |
2105 | ||
2106 | module_init(mxser_module_init); | |
2107 | module_exit(mxser_module_exit); |