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mxser: correct types for uart variables
[linux-2.6-block.git] / drivers / tty / mxser.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
1da177e4
LT		 2/*
3 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
4 *
80ff8a80
JS		 5 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com).
6 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com>
1da177e4 7 *
1c45607a
JS		 8 * This code is loosely based on the 1.8 moxa driver which is based on
9 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
10 * others.
1da177e4 11 *
1da177e4 12 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
8eb04cf3
AC		 13 * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on
14 * www.moxa.com.
1da177e4 15 * - Fixed x86_64 cleanness
1da177e4
LT		 16 */
17
1da177e4 18#include <linux/module.h>
1da177e4
LT		 19#include <linux/errno.h>
20#include <linux/signal.h>
21#include <linux/sched.h>
22#include <linux/timer.h>
23#include <linux/interrupt.h>
24#include <linux/tty.h>
25#include <linux/tty_flip.h>
26#include <linux/serial.h>
27#include <linux/serial_reg.h>
28#include <linux/major.h>
29#include <linux/string.h>
30#include <linux/fcntl.h>
31#include <linux/ptrace.h>
1da177e4
LT		 32#include <linux/ioport.h>
33#include <linux/mm.h>
1da177e4
LT		 34#include <linux/delay.h>
35#include <linux/pci.h>
1977f032 36#include <linux/bitops.h>
5a0e3ad6 37#include <linux/slab.h>
5a3c6b25 38#include <linux/ratelimit.h>
1da177e4 39
1da177e4
LT		 40#include <asm/io.h>
41#include <asm/irq.h>
7c0f6ba6 42#include <linux/uaccess.h>
1da177e4 43
4463cc5b
JS		 44/*
45 * Semi-public control interfaces
46 */
47
48/*
49 * MOXA ioctls
50 */
51
52#define MOXA 0x400
53#define MOXA_GETDATACOUNT (MOXA + 23)
54#define MOXA_DIAGNOSE (MOXA + 50)
55#define MOXA_CHKPORTENABLE (MOXA + 60)
56#define MOXA_HighSpeedOn (MOXA + 61)
57#define MOXA_GET_MAJOR (MOXA + 63)
58#define MOXA_GETMSTATUS (MOXA + 65)
59#define MOXA_SET_OP_MODE (MOXA + 66)
60#define MOXA_GET_OP_MODE (MOXA + 67)
61
62#define RS232_MODE 0
63#define RS485_2WIRE_MODE 1
64#define RS422_MODE 2
65#define RS485_4WIRE_MODE 3
66#define OP_MODE_MASK 3
67
68#define MOXA_SDS_RSTICOUNTER (MOXA + 69)
69#define MOXA_ASPP_OQUEUE (MOXA + 70)
70#define MOXA_ASPP_MON (MOXA + 73)
71#define MOXA_ASPP_LSTATUS (MOXA + 74)
72#define MOXA_ASPP_MON_EXT (MOXA + 75)
73#define MOXA_SET_BAUD_METHOD (MOXA + 76)
74
75/* --------------------------------------------------- */
76
77#define NPPI_NOTIFY_PARITY 0x01
78#define NPPI_NOTIFY_FRAMING 0x02
79#define NPPI_NOTIFY_HW_OVERRUN 0x04
80#define NPPI_NOTIFY_SW_OVERRUN 0x08
81#define NPPI_NOTIFY_BREAK 0x10
82
83#define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */
84#define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */
85#define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */
86#define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */
87
88/*
89 * Follow just what Moxa Must chip defines.
90 *
91 * When LCR register (offset 0x03) writes the following value, the Must chip
92 * will enter enchance mode. And write value on EFR (offset 0x02) bit 6,7 to
93 * change bank.
94 */
95#define MOXA_MUST_ENTER_ENCHANCE 0xBF
96
97/* when enhance mode enabled, access on general bank register */
98#define MOXA_MUST_GDL_REGISTER 0x07
99#define MOXA_MUST_GDL_MASK 0x7F
100#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
101
102#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
103/* enchance register bank select and enchance mode setting register */
104/* when LCR register equals to 0xBF */
105#define MOXA_MUST_EFR_REGISTER 0x02
106#define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enchance mode enable */
107/* enchance register bank set 0, 1, 2 */
108#define MOXA_MUST_EFR_BANK0 0x00
109#define MOXA_MUST_EFR_BANK1 0x40
110#define MOXA_MUST_EFR_BANK2 0x80
111#define MOXA_MUST_EFR_BANK3 0xC0
112#define MOXA_MUST_EFR_BANK_MASK 0xC0
113
114/* set XON1 value register, when LCR=0xBF and change to bank0 */
115#define MOXA_MUST_XON1_REGISTER 0x04
116
117/* set XON2 value register, when LCR=0xBF and change to bank0 */
118#define MOXA_MUST_XON2_REGISTER 0x05
119
120/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
121#define MOXA_MUST_XOFF1_REGISTER 0x06
122
123/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
124#define MOXA_MUST_XOFF2_REGISTER 0x07
125
126#define MOXA_MUST_RBRTL_REGISTER 0x04
127#define MOXA_MUST_RBRTH_REGISTER 0x05
128#define MOXA_MUST_RBRTI_REGISTER 0x06
129#define MOXA_MUST_THRTL_REGISTER 0x07
130#define MOXA_MUST_ENUM_REGISTER 0x04
131#define MOXA_MUST_HWID_REGISTER 0x05
132#define MOXA_MUST_ECR_REGISTER 0x06
133#define MOXA_MUST_CSR_REGISTER 0x07
134
135#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */
136#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */
137
138#define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */
139#define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */
140#define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */
141#define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */
142
143#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
144
145/* GDA interrupt pending */
146#define MOXA_MUST_IIR_GDA 0x1C
147#define MOXA_MUST_IIR_RDA 0x04
148#define MOXA_MUST_IIR_RTO 0x0C
149#define MOXA_MUST_IIR_LSR 0x06
150
151/* received Xon/Xoff or specical interrupt pending */
152#define MOXA_MUST_IIR_XSC 0x10
153
154/* RTS/CTS change state interrupt pending */
155#define MOXA_MUST_IIR_RTSCTS 0x20
156#define MOXA_MUST_IIR_MASK 0x3E
157
158#define MOXA_MUST_MCR_XON_FLAG 0x40
159#define MOXA_MUST_MCR_XON_ANY 0x80
160#define MOXA_MUST_MCR_TX_XON 0x08
161
162#define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */
163#define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */
164#define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */
165#define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */
166#define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */
167#define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */
168#define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */
169#define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */
170#define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */
171#define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */
172#define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */
1da177e4 173
1da177e4 174#define MXSERMAJOR 174
1da177e4 175
1da177e4 176#define MXSER_BOARDS 4 /* Max. boards */
1da177e4 177#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
1c45607a
JS		 178#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
179#define MXSER_ISR_PASS_LIMIT 100
1da177e4 180
1da177e4
LT		 181#define WAKEUP_CHARS 256
182
183#define UART_MCR_AFE 0x20
184#define UART_LSR_SPECIAL 0x1E
185
e129deff 186#define PCI_DEVICE_ID_POS104UL 0x1044
1c45607a 187#define PCI_DEVICE_ID_CB108 0x1080
e129deff 188#define PCI_DEVICE_ID_CP102UF 0x1023
502f295f 189#define PCI_DEVICE_ID_CP112UL 0x1120
1c45607a 190#define PCI_DEVICE_ID_CB114 0x1142
80ff8a80 191#define PCI_DEVICE_ID_CP114UL 0x1143
1c45607a
JS		 192#define PCI_DEVICE_ID_CB134I 0x1341
193#define PCI_DEVICE_ID_CP138U 0x1380
1da177e4 194
1c45607a 195#define MXSER_HIGHBAUD 1
1da177e4 196
e4558366
JS		 197enum mxser_must_hwid {
198 MOXA_OTHER_UART = 0x00,
199 MOXA_MUST_MU150_HWID = 0x01,
200 MOXA_MUST_MU860_HWID = 0x02,
201};
202
1c45607a 203static const struct {
dc33f644
JS		 204 u8 type;
205 u8 fifo_size;
206 u8 rx_high_water;
207 u8 rx_low_water;
208 speed_t max_baud;
1c45607a 209} Gpci_uart_info[] = {
dc33f644
JS		 210 { MOXA_OTHER_UART, 16, 14, 1, 921600 },
211 { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 },
212 { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 }
1da177e4 213};
1c45607a 214#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
1da177e4 215
1c45607a
JS		 216struct mxser_cardinfo {
217 char *name;
218 unsigned int nports;
219 unsigned int flags;
220};
1da177e4 221
1c45607a 222static const struct mxser_cardinfo mxser_cards[] = {
15254902 223/* 0*/ { "C168H/PCI series", 8, },
1c45607a 224 { "C104H/PCI series", 4, },
1c45607a
JS		 225 { "CP-132 series", 2, },
226 { "CP-114 series", 4, },
15254902
JS		 227 { "CT-114 series", 4, },
228/* 5*/ { "CP-102 series", 2, MXSER_HIGHBAUD },
1c45607a
JS		 229 { "CP-104U series", 4, },
230 { "CP-168U series", 8, },
231 { "CP-132U series", 2, },
15254902
JS		 232 { "CP-134U series", 4, },
233/*10*/ { "CP-104JU series", 4, },
1c45607a
JS		 234 { "Moxa UC7000 Serial", 8, }, /* RC7000 */
235 { "CP-118U series", 8, },
236 { "CP-102UL series", 2, },
15254902
JS		 237 { "CP-102U series", 2, },
238/*15*/ { "CP-118EL series", 8, },
1c45607a
JS		 239 { "CP-168EL series", 8, },
240 { "CP-104EL series", 4, },
241 { "CB-108 series", 8, },
15254902
JS		 242 { "CB-114 series", 4, },
243/*20*/ { "CB-134I series", 4, },
1c45607a 244 { "CP-138U series", 8, },
80ff8a80 245 { "POS-104UL series", 4, },
e129deff 246 { "CP-114UL series", 4, },
15254902
JS		 247 { "CP-102UF series", 2, },
248/*25*/ { "CP-112UL series", 2, },
1c45607a 249};
1da177e4 250
1c45607a
JS		 251/* driver_data correspond to the lines in the structure above
252 see also ISA probe function before you change something */
3385ecf8 253static const struct pci_device_id mxser_pcibrds[] = {
15254902
JS		 254 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 0 },
255 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 1 },
256 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 2 },
257 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 3 },
258 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 4 },
259 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 5 },
260 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 6 },
261 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 7 },
262 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 8 },
263 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 9 },
264 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 10 },
265 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 11 },
266 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 12 },
267 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 13 },
268 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 14 },
269 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 15 },
270 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 16 },
271 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 17 },
272 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 18 },
273 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 19 },
274 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 20 },
275 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 21 },
276 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 22 },
277 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL), .driver_data = 23 },
278 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP102UF), .driver_data = 24 },
279 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP112UL), .driver_data = 25 },
1c45607a 280 { }
1da177e4 281};
1da177e4
LT		 282MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
283
1da177e4 284static int ttymajor = MXSERMAJOR;
1da177e4
LT		 285
286/* Variables for insmod */
287
288MODULE_AUTHOR("Casper Yang");
289MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
8d3b33f6 290module_param(ttymajor, int, 0);
1da177e4
LT		 291MODULE_LICENSE("GPL");
292
293struct mxser_log {
294 int tick;
295 unsigned long rxcnt[MXSER_PORTS];
296 unsigned long txcnt[MXSER_PORTS];
297};
298
1da177e4
LT		 299struct mxser_mon {
300 unsigned long rxcnt;
301 unsigned long txcnt;
302 unsigned long up_rxcnt;
303 unsigned long up_txcnt;
304 int modem_status;
305 unsigned char hold_reason;
306};
307
308struct mxser_mon_ext {
309 unsigned long rx_cnt[32];
310 unsigned long tx_cnt[32];
311 unsigned long up_rxcnt[32];
312 unsigned long up_txcnt[32];
313 int modem_status[32];
314
315 long baudrate[32];
316 int databits[32];
317 int stopbits[32];
318 int parity[32];
319 int flowctrl[32];
320 int fifo[32];
321 int iftype[32];
322};
8ea2c2ec 323
1c45607a
JS		 324struct mxser_board;
325
326struct mxser_port {
0ad9e7d1 327 struct tty_port port;
1c45607a 328 struct mxser_board *board;
1c45607a
JS		 329
330 unsigned long ioaddr;
331 unsigned long opmode_ioaddr;
1da177e4 332
dc33f644
JS		 333 u8 rx_high_water;
334 u8 rx_low_water;
1da177e4 335 int baud_base; /* max. speed */
1da177e4 336 int type; /* UART type */
1c45607a 337
a93963e4
JS		 338 unsigned char x_char; /* xon/xoff character */
339 u8 IER; /* Interrupt Enable Register */
340 u8 MCR; /* Modem control register */
1c45607a
JS		 341
342 unsigned char stop_rx;
343 unsigned char ldisc_stop_rx;
344
345 int custom_divisor;
1c45607a 346 unsigned char err_shadow;
1c45607a 347
1c45607a 348 struct async_icount icount; /* kernel counters for 4 input interrupts */
104583b5 349 unsigned int timeout;
1c45607a 350
a93963e4
JS		 351 u8 read_status_mask;
352 u8 ignore_status_mask;
dc33f644 353 u8 xmit_fifo_size;
1da177e4
LT		 354 int xmit_head;
355 int xmit_tail;
356 int xmit_cnt;
cd7b4b39 357 int closing;
1c45607a 358
606d099c 359 struct ktermios normal_termios;
1c45607a 360
1da177e4 361 struct mxser_mon mon_data;
1c45607a 362
1da177e4 363 spinlock_t slock;
1c45607a
JS		 364};
365
366struct mxser_board {
367 unsigned int idx;
368 int irq;
369 const struct mxser_cardinfo *info;
370 unsigned long vector;
1c45607a 371
e4558366 372 enum mxser_must_hwid must_hwid;
928f9464 373 speed_t max_baud;
1c45607a
JS		 374
375 struct mxser_port ports[MXSER_PORTS_PER_BOARD];
1da177e4
LT		 376};
377
1da177e4
LT		 378struct mxser_mstatus {
379 tcflag_t cflag;
380 int cts;
381 int dsr;
382 int ri;
383 int dcd;
384};
385
1c45607a 386static struct mxser_board mxser_boards[MXSER_BOARDS];
1da177e4 387static struct tty_driver *mxvar_sdriver;
1da177e4 388static struct mxser_log mxvar_log;
1da177e4 389static int mxser_set_baud_method[MXSER_PORTS + 1];
1da177e4 390
148ff86b
CH		 391static void mxser_enable_must_enchance_mode(unsigned long baseio)
392{
393 u8 oldlcr;
394 u8 efr;
395
396 oldlcr = inb(baseio + UART_LCR);
397 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
398
399 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
400 efr |= MOXA_MUST_EFR_EFRB_ENABLE;
401
402 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
403 outb(oldlcr, baseio + UART_LCR);
404}
405
406static void mxser_disable_must_enchance_mode(unsigned long baseio)
407{
408 u8 oldlcr;
409 u8 efr;
410
411 oldlcr = inb(baseio + UART_LCR);
412 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
413
414 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
415 efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;
416
417 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
418 outb(oldlcr, baseio + UART_LCR);
419}
420
421static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
422{
423 u8 oldlcr;
424 u8 efr;
425
426 oldlcr = inb(baseio + UART_LCR);
427 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
428
429 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
430 efr &= ~MOXA_MUST_EFR_BANK_MASK;
431 efr |= MOXA_MUST_EFR_BANK0;
432
433 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
434 outb(value, baseio + MOXA_MUST_XON1_REGISTER);
435 outb(oldlcr, baseio + UART_LCR);
436}
437
438static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
439{
440 u8 oldlcr;
441 u8 efr;
442
443 oldlcr = inb(baseio + UART_LCR);
444 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
445
446 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
447 efr &= ~MOXA_MUST_EFR_BANK_MASK;
448 efr |= MOXA_MUST_EFR_BANK0;
449
450 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
451 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
452 outb(oldlcr, baseio + UART_LCR);
453}
454
455static void mxser_set_must_fifo_value(struct mxser_port *info)
456{
457 u8 oldlcr;
458 u8 efr;
459
460 oldlcr = inb(info->ioaddr + UART_LCR);
461 outb(MOXA_MUST_ENTER_ENCHANCE, info->ioaddr + UART_LCR);
462
463 efr = inb(info->ioaddr + MOXA_MUST_EFR_REGISTER);
464 efr &= ~MOXA_MUST_EFR_BANK_MASK;
465 efr |= MOXA_MUST_EFR_BANK1;
466
467 outb(efr, info->ioaddr + MOXA_MUST_EFR_REGISTER);
dc33f644
JS		 468 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
469 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
470 outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
148ff86b
CH		 471 outb(oldlcr, info->ioaddr + UART_LCR);
472}
473
474static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
475{
476 u8 oldlcr;
477 u8 efr;
478
479 oldlcr = inb(baseio + UART_LCR);
480 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
481
482 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
483 efr &= ~MOXA_MUST_EFR_BANK_MASK;
484 efr |= MOXA_MUST_EFR_BANK2;
485
486 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
487 outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
488 outb(oldlcr, baseio + UART_LCR);
489}
490
491static void mxser_get_must_hardware_id(unsigned long baseio, u8 *pId)
492{
493 u8 oldlcr;
494 u8 efr;
495
496 oldlcr = inb(baseio + UART_LCR);
497 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
498
499 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
500 efr &= ~MOXA_MUST_EFR_BANK_MASK;
501 efr |= MOXA_MUST_EFR_BANK2;
502
503 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
504 *pId = inb(baseio + MOXA_MUST_HWID_REGISTER);
505 outb(oldlcr, baseio + UART_LCR);
506}
507
508static void SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(unsigned long baseio)
509{
510 u8 oldlcr;
511 u8 efr;
512
513 oldlcr = inb(baseio + UART_LCR);
514 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
515
516 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
517 efr &= ~MOXA_MUST_EFR_SF_MASK;
518
519 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
520 outb(oldlcr, baseio + UART_LCR);
521}
522
523static void mxser_enable_must_tx_software_flow_control(unsigned long baseio)
524{
525 u8 oldlcr;
526 u8 efr;
527
528 oldlcr = inb(baseio + UART_LCR);
529 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
530
531 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
532 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
533 efr |= MOXA_MUST_EFR_SF_TX1;
534
535 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
536 outb(oldlcr, baseio + UART_LCR);
537}
538
539static void mxser_disable_must_tx_software_flow_control(unsigned long baseio)
540{
541 u8 oldlcr;
542 u8 efr;
543
544 oldlcr = inb(baseio + UART_LCR);
545 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
546
547 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
548 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
549
550 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
551 outb(oldlcr, baseio + UART_LCR);
552}
553
554static void mxser_enable_must_rx_software_flow_control(unsigned long baseio)
555{
556 u8 oldlcr;
557 u8 efr;
558
559 oldlcr = inb(baseio + UART_LCR);
560 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
561
562 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
563 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
564 efr |= MOXA_MUST_EFR_SF_RX1;
565
566 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
567 outb(oldlcr, baseio + UART_LCR);
568}
569
570static void mxser_disable_must_rx_software_flow_control(unsigned long baseio)
571{
572 u8 oldlcr;
573 u8 efr;
574
575 oldlcr = inb(baseio + UART_LCR);
576 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
577
578 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
579 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
580
581 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
582 outb(oldlcr, baseio + UART_LCR);
583}
584
e4558366 585static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io)
1da177e4
LT		 586{
587 u8 oldmcr, hwid;
588 int i;
589
590 outb(0, io + UART_LCR);
148ff86b 591 mxser_disable_must_enchance_mode(io);
1da177e4
LT		 592 oldmcr = inb(io + UART_MCR);
593 outb(0, io + UART_MCR);
148ff86b 594 mxser_set_must_xon1_value(io, 0x11);
1da177e4
LT		 595 if ((hwid = inb(io + UART_MCR)) != 0) {
596 outb(oldmcr, io + UART_MCR);
8ea2c2ec 597 return MOXA_OTHER_UART;
1da177e4
LT		 598 }
599
148ff86b 600 mxser_get_must_hardware_id(io, &hwid);
e4558366 601 for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */
1c45607a 602 if (hwid == Gpci_uart_info[i].type)
e4558366
JS		 603 return hwid;
604
1da177e4
LT		 605 return MOXA_OTHER_UART;
606}
607
1c45607a 608static void process_txrx_fifo(struct mxser_port *info)
1da177e4
LT		 609{
610 int i;
611
612 if ((info->type == PORT_16450) || (info->type == PORT_8250)) {
1da177e4
LT		 613 info->rx_high_water = 1;
614 info->rx_low_water = 1;
615 info->xmit_fifo_size = 1;
1c45607a
JS		 616 } else
617 for (i = 0; i < UART_INFO_NUM; i++)
292955a7 618 if (info->board->must_hwid == Gpci_uart_info[i].type) {
1da177e4
LT		 619 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
620 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
dc33f644 621 info->xmit_fifo_size = Gpci_uart_info[i].fifo_size;
1da177e4
LT		 622 break;
623 }
1da177e4
LT		 624}
625
1c45607a 626static unsigned char mxser_get_msr(int baseaddr, int mode, int port)
1da177e4 627{
72800df9 628 static unsigned char mxser_msr[MXSER_PORTS + 1];
1c45607a 629 unsigned char status = 0;
1da177e4 630
1c45607a 631 status = inb(baseaddr + UART_MSR);
1da177e4 632
1c45607a
JS		 633 mxser_msr[port] &= 0x0F;
634 mxser_msr[port] |= status;
635 status = mxser_msr[port];
636 if (mode)
637 mxser_msr[port] = 0;
1da177e4 638
1c45607a
JS		 639 return status;
640}
1da177e4 641
31f35939
AC		 642static int mxser_carrier_raised(struct tty_port *port)
643{
644 struct mxser_port *mp = container_of(port, struct mxser_port, port);
645 return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0;
646}
647
fcc8ac18 648static void mxser_dtr_rts(struct tty_port *port, int on)
5d951fb4
AC		 649{
650 struct mxser_port *mp = container_of(port, struct mxser_port, port);
651 unsigned long flags;
652
653 spin_lock_irqsave(&mp->slock, flags);
fcc8ac18
AC		 654 if (on)
655 outb(inb(mp->ioaddr + UART_MCR) |
656 UART_MCR_DTR | UART_MCR_RTS, mp->ioaddr + UART_MCR);
657 else
658 outb(inb(mp->ioaddr + UART_MCR)&~(UART_MCR_DTR | UART_MCR_RTS),
659 mp->ioaddr + UART_MCR);
5d951fb4
AC		 660 spin_unlock_irqrestore(&mp->slock, flags);
661}
662
dc33f644 663static int mxser_set_baud(struct tty_struct *tty, speed_t newspd)
1da177e4 664{
216ba023 665 struct mxser_port *info = tty->driver_data;
104583b5 666 unsigned int quot = 0, baud;
1c45607a 667 unsigned char cval;
104583b5 668 u64 timeout;
1da177e4 669
216ba023 670 if (!info->ioaddr)
1c45607a 671 return -1;
1da177e4 672
928f9464 673 if (newspd > info->board->max_baud)
1c45607a 674 return -1;
1da177e4 675
1c45607a
JS		 676 if (newspd == 134) {
677 quot = 2 * info->baud_base / 269;
216ba023 678 tty_encode_baud_rate(tty, 134, 134);
1c45607a
JS		 679 } else if (newspd) {
680 quot = info->baud_base / newspd;
681 if (quot == 0)
682 quot = 1;
683 baud = info->baud_base/quot;
216ba023 684 tty_encode_baud_rate(tty, baud, baud);
1c45607a
JS		 685 } else {
686 quot = 0;
687 }
1da177e4 688
104583b5
JS		 689 /*
690 * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the
691 * u64 domain
692 */
693 timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot;
694 do_div(timeout, info->baud_base);
695 info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */
1da177e4 696
1c45607a
JS		 697 if (quot) {
698 info->MCR |= UART_MCR_DTR;
699 outb(info->MCR, info->ioaddr + UART_MCR);
700 } else {
701 info->MCR &= ~UART_MCR_DTR;
702 outb(info->MCR, info->ioaddr + UART_MCR);
703 return 0;
704 }
1da177e4 705
1c45607a 706 cval = inb(info->ioaddr + UART_LCR);
1da177e4 707
1c45607a 708 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
1da177e4 709
1c45607a
JS		 710 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
711 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
712 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
1da177e4 713
1c45607a 714#ifdef BOTHER
216ba023 715 if (C_BAUD(tty) == BOTHER) {
1c45607a
JS		 716 quot = info->baud_base % newspd;
717 quot *= 8;
718 if (quot % newspd > newspd / 2) {
719 quot /= newspd;
720 quot++;
721 } else
722 quot /= newspd;
723
148ff86b 724 mxser_set_must_enum_value(info->ioaddr, quot);
1c45607a
JS		 725 } else
726#endif
148ff86b 727 mxser_set_must_enum_value(info->ioaddr, 0);
1da177e4 728
8ea2c2ec 729 return 0;
1da177e4 730}
1da177e4 731
1c45607a
JS		 732/*
733 * This routine is called to set the UART divisor registers to match
734 * the specified baud rate for a serial port.
735 */
beca62c4 736static void mxser_change_speed(struct tty_struct *tty)
1da177e4 737{
216ba023 738 struct mxser_port *info = tty->driver_data;
1c45607a 739 unsigned cflag, cval, fcr;
1c45607a 740 unsigned char status;
1da177e4 741
adc8d746 742 cflag = tty->termios.c_cflag;
216ba023 743 if (!info->ioaddr)
beca62c4 744 return;
1da177e4 745
216ba023
AC		 746 if (mxser_set_baud_method[tty->index] == 0)
747 mxser_set_baud(tty, tty_get_baud_rate(tty));
1da177e4 748
1c45607a
JS		 749 /* byte size and parity */
750 switch (cflag & CSIZE) {
751 case CS5:
752 cval = 0x00;
753 break;
754 case CS6:
755 cval = 0x01;
756 break;
757 case CS7:
758 cval = 0x02;
759 break;
760 case CS8:
761 cval = 0x03;
762 break;
763 default:
764 cval = 0x00;
765 break; /* too keep GCC shut... */
766 }
767 if (cflag & CSTOPB)
768 cval |= 0x04;
769 if (cflag & PARENB)
770 cval |= UART_LCR_PARITY;
771 if (!(cflag & PARODD))
772 cval |= UART_LCR_EPAR;
773 if (cflag & CMSPAR)
774 cval |= UART_LCR_SPAR;
1da177e4 775
1c45607a 776 if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
292955a7 777 if (info->board->must_hwid) {
1c45607a
JS		 778 fcr = UART_FCR_ENABLE_FIFO;
779 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
148ff86b 780 mxser_set_must_fifo_value(info);
1c45607a
JS		 781 } else
782 fcr = 0;
783 } else {
784 fcr = UART_FCR_ENABLE_FIFO;
292955a7 785 if (info->board->must_hwid) {
1c45607a 786 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
148ff86b 787 mxser_set_must_fifo_value(info);
1c45607a 788 } else {
dc33f644 789 switch (info->rx_high_water) {
1c45607a
JS		 790 case 1:
791 fcr |= UART_FCR_TRIGGER_1;
792 break;
793 case 4:
794 fcr |= UART_FCR_TRIGGER_4;
795 break;
796 case 8:
797 fcr |= UART_FCR_TRIGGER_8;
798 break;
799 default:
800 fcr |= UART_FCR_TRIGGER_14;
801 break;
802 }
1da177e4 803 }
1da177e4
LT		 804 }
805
1c45607a
JS		 806 /* CTS flow control flag and modem status interrupts */
807 info->IER &= ~UART_IER_MSI;
808 info->MCR &= ~UART_MCR_AFE;
5604a98e 809 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
1c45607a 810 if (cflag & CRTSCTS) {
1c45607a 811 info->IER |= UART_IER_MSI;
292955a7 812 if ((info->type == PORT_16550A) || (info->board->must_hwid)) {
1c45607a
JS		 813 info->MCR |= UART_MCR_AFE;
814 } else {
815 status = inb(info->ioaddr + UART_MSR);
216ba023 816 if (tty->hw_stopped) {
1c45607a 817 if (status & UART_MSR_CTS) {
216ba023 818 tty->hw_stopped = 0;
1c45607a 819 if (info->type != PORT_16550A &&
292955a7 820 !info->board->must_hwid) {
1c45607a
JS		 821 outb(info->IER & ~UART_IER_THRI,
822 info->ioaddr +
823 UART_IER);
824 info->IER |= UART_IER_THRI;
825 outb(info->IER, info->ioaddr +
826 UART_IER);
827 }
216ba023 828 tty_wakeup(tty);
1c45607a
JS		 829 }
830 } else {
831 if (!(status & UART_MSR_CTS)) {
216ba023 832 tty->hw_stopped = 1;
1c45607a 833 if ((info->type != PORT_16550A) &&
292955a7 834 (!info->board->must_hwid)) {
1c45607a
JS		 835 info->IER &= ~UART_IER_THRI;
836 outb(info->IER, info->ioaddr +
837 UART_IER);
838 }
839 }
840 }
1da177e4 841 }
1c45607a
JS		 842 }
843 outb(info->MCR, info->ioaddr + UART_MCR);
2d68655d
PH		 844 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
845 if (~cflag & CLOCAL)
1c45607a 846 info->IER |= UART_IER_MSI;
1c45607a
JS		 847 outb(info->IER, info->ioaddr + UART_IER);
848
849 /*
850 * Set up parity check flag
851 */
852 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
216ba023 853 if (I_INPCK(tty))
1c45607a 854 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
216ba023 855 if (I_BRKINT(tty) || I_PARMRK(tty))
1c45607a 856 info->read_status_mask |= UART_LSR_BI;
1da177e4 857
1c45607a 858 info->ignore_status_mask = 0;
1da177e4 859
216ba023 860 if (I_IGNBRK(tty)) {
1c45607a
JS		 861 info->ignore_status_mask |= UART_LSR_BI;
862 info->read_status_mask |= UART_LSR_BI;
8ea2c2ec 863 /*
1c45607a
JS		 864 * If we're ignore parity and break indicators, ignore
865 * overruns too. (For real raw support).
8ea2c2ec 866 */
216ba023 867 if (I_IGNPAR(tty)) {
1c45607a
JS		 868 info->ignore_status_mask |=
869 UART_LSR_OE |
870 UART_LSR_PE |
871 UART_LSR_FE;
872 info->read_status_mask |=
873 UART_LSR_OE |
874 UART_LSR_PE |
875 UART_LSR_FE;
876 }
1da177e4 877 }
292955a7 878 if (info->board->must_hwid) {
216ba023
AC		 879 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty));
880 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty));
881 if (I_IXON(tty)) {
148ff86b
CH		 882 mxser_enable_must_rx_software_flow_control(
883 info->ioaddr);
1c45607a 884 } else {
148ff86b
CH		 885 mxser_disable_must_rx_software_flow_control(
886 info->ioaddr);
1da177e4 887 }
216ba023 888 if (I_IXOFF(tty)) {
148ff86b
CH		 889 mxser_enable_must_tx_software_flow_control(
890 info->ioaddr);
1c45607a 891 } else {
148ff86b
CH		 892 mxser_disable_must_tx_software_flow_control(
893 info->ioaddr);
1da177e4
LT		 894 }
895 }
1da177e4 896
1da177e4 897
1c45607a
JS		 898 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */
899 outb(cval, info->ioaddr + UART_LCR);
1da177e4
LT		 900}
901
216ba023
AC		 902static void mxser_check_modem_status(struct tty_struct *tty,
903 struct mxser_port *port, int status)
1da177e4 904{
1c45607a
JS		 905 /* update input line counters */
906 if (status & UART_MSR_TERI)
907 port->icount.rng++;
908 if (status & UART_MSR_DDSR)
909 port->icount.dsr++;
910 if (status & UART_MSR_DDCD)
911 port->icount.dcd++;
912 if (status & UART_MSR_DCTS)
913 port->icount.cts++;
914 port->mon_data.modem_status = status;
bdc04e31 915 wake_up_interruptible(&port->port.delta_msr_wait);
1da177e4 916
2d68655d 917 if (tty_port_check_carrier(&port->port) && (status & UART_MSR_DDCD)) {
1c45607a 918 if (status & UART_MSR_DCD)
0ad9e7d1 919 wake_up_interruptible(&port->port.open_wait);
1c45607a 920 }
1da177e4 921
f21ec3d2 922 if (tty_port_cts_enabled(&port->port)) {
216ba023 923 if (tty->hw_stopped) {
1c45607a 924 if (status & UART_MSR_CTS) {
216ba023 925 tty->hw_stopped = 0;
1c45607a
JS		 926
927 if ((port->type != PORT_16550A) &&
292955a7 928 (!port->board->must_hwid)) {
1c45607a
JS		 929 outb(port->IER & ~UART_IER_THRI,
930 port->ioaddr + UART_IER);
931 port->IER |= UART_IER_THRI;
932 outb(port->IER, port->ioaddr +
933 UART_IER);
934 }
216ba023 935 tty_wakeup(tty);
1c45607a
JS		 936 }
937 } else {
938 if (!(status & UART_MSR_CTS)) {
216ba023 939 tty->hw_stopped = 1;
1c45607a 940 if (port->type != PORT_16550A &&
292955a7 941 !port->board->must_hwid) {
1c45607a
JS		 942 port->IER &= ~UART_IER_THRI;
943 outb(port->IER, port->ioaddr +
944 UART_IER);
945 }
946 }
947 }
1da177e4
LT		 948 }
949}
950
6769140d 951static int mxser_activate(struct tty_port *port, struct tty_struct *tty)
1da177e4 952{
6769140d 953 struct mxser_port *info = container_of(port, struct mxser_port, port);
1c45607a
JS		 954 unsigned long page;
955 unsigned long flags;
1da177e4 956
1c45607a
JS		 957 page = __get_free_page(GFP_KERNEL);
958 if (!page)
959 return -ENOMEM;
1da177e4 960
1c45607a 961 spin_lock_irqsave(&info->slock, flags);
1da177e4 962
1c45607a 963 if (!info->ioaddr || !info->type) {
216ba023 964 set_bit(TTY_IO_ERROR, &tty->flags);
1c45607a
JS		 965 free_page(page);
966 spin_unlock_irqrestore(&info->slock, flags);
1da177e4 967 return 0;
1c45607a 968 }
6769140d 969 info->port.xmit_buf = (unsigned char *) page;
1da177e4 970
1da177e4 971 /*
1c45607a
JS		 972 * Clear the FIFO buffers and disable them
973 * (they will be reenabled in mxser_change_speed())
1da177e4 974 */
292955a7 975 if (info->board->must_hwid)
1c45607a
JS		 976 outb((UART_FCR_CLEAR_RCVR |
977 UART_FCR_CLEAR_XMIT |
978 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR);
979 else
980 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
981 info->ioaddr + UART_FCR);
1da177e4 982
1c45607a
JS		 983 /*
984 * At this point there's no way the LSR could still be 0xFF;
985 * if it is, then bail out, because there's likely no UART
986 * here.
987 */
988 if (inb(info->ioaddr + UART_LSR) == 0xff) {
989 spin_unlock_irqrestore(&info->slock, flags);
990 if (capable(CAP_SYS_ADMIN)) {
f43a510d 991 set_bit(TTY_IO_ERROR, &tty->flags);
1c45607a
JS		 992 return 0;
993 } else
994 return -ENODEV;
995 }
1da177e4 996
1c45607a
JS		 997 /*
998 * Clear the interrupt registers.
999 */
1000 (void) inb(info->ioaddr + UART_LSR);
1001 (void) inb(info->ioaddr + UART_RX);
1002 (void) inb(info->ioaddr + UART_IIR);
1003 (void) inb(info->ioaddr + UART_MSR);
1004
1005 /*
1006 * Now, initialize the UART
1007 */
1008 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
1009 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
1010 outb(info->MCR, info->ioaddr + UART_MCR);
1011
1012 /*
1013 * Finally, enable interrupts
1014 */
1015 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
1016
292955a7 1017 if (info->board->must_hwid)
1c45607a
JS		 1018 info->IER |= MOXA_MUST_IER_EGDAI;
1019 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
1020
1021 /*
1022 * And clear the interrupt registers again for luck.
1023 */
1024 (void) inb(info->ioaddr + UART_LSR);
1025 (void) inb(info->ioaddr + UART_RX);
1026 (void) inb(info->ioaddr + UART_IIR);
1027 (void) inb(info->ioaddr + UART_MSR);
1028
216ba023 1029 clear_bit(TTY_IO_ERROR, &tty->flags);
1c45607a
JS		 1030 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1031
1032 /*
1033 * and set the speed of the serial port
1034 */
2799707f 1035 mxser_change_speed(tty);
1c45607a
JS		 1036 spin_unlock_irqrestore(&info->slock, flags);
1037
1038 return 0;
1039}
1040
1041/*
6769140d 1042 * This routine will shutdown a serial port
1c45607a 1043 */
6769140d 1044static void mxser_shutdown_port(struct tty_port *port)
1c45607a 1045{
6769140d 1046 struct mxser_port *info = container_of(port, struct mxser_port, port);
1c45607a
JS		 1047 unsigned long flags;
1048
1c45607a
JS		 1049 spin_lock_irqsave(&info->slock, flags);
1050
1051 /*
1052 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
1053 * here so the queue might never be waken up
1054 */
bdc04e31 1055 wake_up_interruptible(&info->port.delta_msr_wait);
1c45607a
JS		 1056
1057 /*
6769140d 1058 * Free the xmit buffer, if necessary
1c45607a 1059 */
0ad9e7d1
AC		 1060 if (info->port.xmit_buf) {
1061 free_page((unsigned long) info->port.xmit_buf);
1062 info->port.xmit_buf = NULL;
1da177e4
LT		 1063 }
1064
1c45607a
JS		 1065 info->IER = 0;
1066 outb(0x00, info->ioaddr + UART_IER);
1067
1c45607a 1068 /* clear Rx/Tx FIFO's */
292955a7 1069 if (info->board->must_hwid)
1c45607a
JS		 1070 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |
1071 MOXA_MUST_FCR_GDA_MODE_ENABLE,
1072 info->ioaddr + UART_FCR);
1073 else
1074 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1075 info->ioaddr + UART_FCR);
1076
1077 /* read data port to reset things */
1078 (void) inb(info->ioaddr + UART_RX);
1079
1c45607a 1080
292955a7 1081 if (info->board->must_hwid)
1c45607a
JS		 1082 SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr);
1083
1084 spin_unlock_irqrestore(&info->slock, flags);
1085}
1086
1087/*
1088 * This routine is called whenever a serial port is opened. It
1089 * enables interrupts for a serial port, linking in its async structure into
1090 * the IRQ chain. It also performs the serial-specific
1091 * initialization for the tty structure.
1092 */
1093static int mxser_open(struct tty_struct *tty, struct file *filp)
1094{
1095 struct mxser_port *info;
6769140d 1096 int line;
1c45607a
JS		 1097
1098 line = tty->index;
1099 if (line == MXSER_PORTS)
1100 return 0;
1c45607a
JS		 1101 info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD];
1102 if (!info->ioaddr)
1103 return -ENODEV;
1104
a2d1e351 1105 tty->driver_data = info;
6769140d 1106 return tty_port_open(&info->port, tty, filp);
1da177e4
LT		 1107}
1108
978e595f
AC		 1109static void mxser_flush_buffer(struct tty_struct *tty)
1110{
1111 struct mxser_port *info = tty->driver_data;
1112 char fcr;
1113 unsigned long flags;
1114
1115
1116 spin_lock_irqsave(&info->slock, flags);
1117 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1118
1119 fcr = inb(info->ioaddr + UART_FCR);
1120 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
1121 info->ioaddr + UART_FCR);
1122 outb(fcr, info->ioaddr + UART_FCR);
1123
1124 spin_unlock_irqrestore(&info->slock, flags);
1125
1126 tty_wakeup(tty);
1127}
1128
1129
6769140d 1130static void mxser_close_port(struct tty_port *port)
1da177e4 1131{
1e2b0254 1132 struct mxser_port *info = container_of(port, struct mxser_port, port);
1da177e4 1133 unsigned long timeout;
1da177e4
LT		 1134 /*
1135 * At this point we stop accepting input. To do this, we
1136 * disable the receive line status interrupts, and tell the
1137 * interrupt driver to stop checking the data ready bit in the
1138 * line status register.
1139 */
1140 info->IER &= ~UART_IER_RLSI;
292955a7 1141 if (info->board->must_hwid)
1da177e4 1142 info->IER &= ~MOXA_MUST_RECV_ISR;
1c45607a 1143
6769140d
AC		 1144 outb(info->IER, info->ioaddr + UART_IER);
1145 /*
1146 * Before we drop DTR, make sure the UART transmitter
1147 * has completely drained; this is especially
1148 * important if there is a transmit FIFO!
1149 */
1150 timeout = jiffies + HZ;
1151 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) {
1152 schedule_timeout_interruptible(5);
1153 if (time_after(jiffies, timeout))
1154 break;
1da177e4 1155 }
1e2b0254
AC		 1156}
1157
1158/*
1159 * This routine is called when the serial port gets closed. First, we
1160 * wait for the last remaining data to be sent. Then, we unlink its
1161 * async structure from the interrupt chain if necessary, and we free
1162 * that IRQ if nothing is left in the chain.
1163 */
1164static void mxser_close(struct tty_struct *tty, struct file *filp)
1165{
1166 struct mxser_port *info = tty->driver_data;
1167 struct tty_port *port = &info->port;
1168
a2d1e351 1169 if (tty->index == MXSER_PORTS || info == NULL)
1e2b0254
AC		 1170 return;
1171 if (tty_port_close_start(port, tty, filp) == 0)
1172 return;
cd7b4b39 1173 info->closing = 1;
6769140d
AC		 1174 mutex_lock(&port->mutex);
1175 mxser_close_port(port);
1e2b0254 1176 mxser_flush_buffer(tty);
d41861ca
PH		 1177 if (tty_port_initialized(port) && C_HUPCL(tty))
1178 tty_port_lower_dtr_rts(port);
6769140d 1179 mxser_shutdown_port(port);
d41861ca 1180 tty_port_set_initialized(port, 0);
6769140d 1181 mutex_unlock(&port->mutex);
cd7b4b39 1182 info->closing = 0;
a6614999
AC		 1183 /* Right now the tty_port set is done outside of the close_end helper
1184 as we don't yet have everyone using refcounts */
1185 tty_port_close_end(port, tty);
1186 tty_port_tty_set(port, NULL);
1da177e4
LT		 1187}
1188
1189static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
1190{
1191 int c, total = 0;
1c45607a 1192 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1193 unsigned long flags;
1194
0ad9e7d1 1195 if (!info->port.xmit_buf)
8ea2c2ec 1196 return 0;
1da177e4
LT		 1197
1198 while (1) {
8ea2c2ec
JJ		 1199 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
1200 SERIAL_XMIT_SIZE - info->xmit_head));
1da177e4
LT		 1201 if (c <= 0)
1202 break;
1203
0ad9e7d1 1204 memcpy(info->port.xmit_buf + info->xmit_head, buf, c);
1da177e4 1205 spin_lock_irqsave(&info->slock, flags);
8ea2c2ec
JJ		 1206 info->xmit_head = (info->xmit_head + c) &
1207 (SERIAL_XMIT_SIZE - 1);
1da177e4
LT		 1208 info->xmit_cnt += c;
1209 spin_unlock_irqrestore(&info->slock, flags);
1210
1211 buf += c;
1212 count -= c;
1213 total += c;
1da177e4
LT		 1214 }
1215
6e94dbc7 1216 if (info->xmit_cnt && !tty->flow.stopped) {
8ea2c2ec
JJ		 1217 if (!tty->hw_stopped ||
1218 (info->type == PORT_16550A) ||
292955a7 1219 (info->board->must_hwid)) {
1da177e4 1220 spin_lock_irqsave(&info->slock, flags);
1c45607a
JS		 1221 outb(info->IER & ~UART_IER_THRI, info->ioaddr +
1222 UART_IER);
1da177e4 1223 info->IER |= UART_IER_THRI;
1c45607a 1224 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1225 spin_unlock_irqrestore(&info->slock, flags);
1226 }
1227 }
1228 return total;
1229}
1230
0be2eade 1231static int mxser_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 1232{
1c45607a 1233 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1234 unsigned long flags;
1235
0ad9e7d1 1236 if (!info->port.xmit_buf)
0be2eade 1237 return 0;
1da177e4
LT		 1238
1239 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1)
0be2eade 1240 return 0;
1da177e4
LT		 1241
1242 spin_lock_irqsave(&info->slock, flags);
0ad9e7d1 1243 info->port.xmit_buf[info->xmit_head++] = ch;
1da177e4
LT		 1244 info->xmit_head &= SERIAL_XMIT_SIZE - 1;
1245 info->xmit_cnt++;
1246 spin_unlock_irqrestore(&info->slock, flags);
6e94dbc7 1247 if (!tty->flow.stopped) {
8ea2c2ec
JJ		 1248 if (!tty->hw_stopped ||
1249 (info->type == PORT_16550A) ||
292955a7 1250 info->board->must_hwid) {
1da177e4 1251 spin_lock_irqsave(&info->slock, flags);
1c45607a 1252 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1253 info->IER |= UART_IER_THRI;
1c45607a 1254 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1255 spin_unlock_irqrestore(&info->slock, flags);
1256 }
1257 }
0be2eade 1258 return 1;
1da177e4
LT		 1259}
1260
1261
1262static void mxser_flush_chars(struct tty_struct *tty)
1263{
1c45607a 1264 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1265 unsigned long flags;
1266
6e94dbc7 1267 if (info->xmit_cnt <= 0 || tty->flow.stopped || !info->port.xmit_buf ||
ace7dd96 1268 (tty->hw_stopped && info->type != PORT_16550A &&
292955a7 1269 !info->board->must_hwid))
1da177e4
LT		 1270 return;
1271
1272 spin_lock_irqsave(&info->slock, flags);
1273
1c45607a 1274 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1275 info->IER |= UART_IER_THRI;
1c45607a 1276 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1277
1278 spin_unlock_irqrestore(&info->slock, flags);
1279}
1280
03b3b1a2 1281static unsigned int mxser_write_room(struct tty_struct *tty)
1da177e4 1282{
1c45607a 1283 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1284 int ret;
1285
1286 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
ace7dd96 1287 return ret < 0 ? 0 : ret;
1da177e4
LT		 1288}
1289
fff4ef17 1290static unsigned int mxser_chars_in_buffer(struct tty_struct *tty)
1da177e4 1291{
1c45607a 1292 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1293 return info->xmit_cnt;
1294}
1295
1c45607a
JS		 1296/*
1297 * ------------------------------------------------------------
1298 * friends of mxser_ioctl()
1299 * ------------------------------------------------------------
1300 */
216ba023 1301static int mxser_get_serial_info(struct tty_struct *tty,
6da5b587 1302 struct serial_struct *ss)
1c45607a 1303{
216ba023 1304 struct mxser_port *info = tty->driver_data;
6da5b587 1305 struct tty_port *port = &info->port;
be6cf583 1306 unsigned int closing_wait, close_delay;
6da5b587
AV		 1307
1308 if (tty->index == MXSER_PORTS)
1309 return -ENOTTY;
1310
1311 mutex_lock(&port->mutex);
be6cf583
JH		 1312
1313 close_delay = jiffies_to_msecs(info->port.close_delay) / 10;
1314 closing_wait = info->port.closing_wait;
1315 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
1316 closing_wait = jiffies_to_msecs(closing_wait) / 10;
1317
6da5b587
AV		 1318 ss->type = info->type,
1319 ss->line = tty->index,
1320 ss->port = info->ioaddr,
1321 ss->irq = info->board->irq,
1322 ss->flags = info->port.flags,
1323 ss->baud_base = info->baud_base,
be6cf583
JH		 1324 ss->close_delay = close_delay;
1325 ss->closing_wait = closing_wait;
6da5b587
AV		 1326 ss->custom_divisor = info->custom_divisor,
1327 mutex_unlock(&port->mutex);
1c45607a
JS		 1328 return 0;
1329}
1330
216ba023 1331static int mxser_set_serial_info(struct tty_struct *tty,
6da5b587 1332 struct serial_struct *ss)
1da177e4 1333{
216ba023 1334 struct mxser_port *info = tty->driver_data;
07f86c03 1335 struct tty_port *port = &info->port;
80ff8a80 1336 speed_t baud;
1c45607a 1337 unsigned long sl_flags;
be6cf583 1338 unsigned int flags, close_delay, closing_wait;
1c45607a 1339 int retval = 0;
1da177e4 1340
6da5b587
AV		 1341 if (tty->index == MXSER_PORTS)
1342 return -ENOTTY;
1343 if (tty_io_error(tty))
1344 return -EIO;
1345
1346 mutex_lock(&port->mutex);
1347 if (!info->ioaddr) {
1348 mutex_unlock(&port->mutex);
80ff8a80 1349 return -ENODEV;
6da5b587 1350 }
1da177e4 1351
6da5b587
AV		 1352 if (ss->irq != info->board->irq ||
1353 ss->port != info->ioaddr) {
1354 mutex_unlock(&port->mutex);
80ff8a80 1355 return -EINVAL;
6da5b587 1356 }
1da177e4 1357
07f86c03 1358 flags = port->flags & ASYNC_SPD_MASK;
1da177e4 1359
be6cf583
JH		 1360 close_delay = msecs_to_jiffies(ss->close_delay * 10);
1361 closing_wait = ss->closing_wait;
1362 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
1363 closing_wait = msecs_to_jiffies(closing_wait * 10);
1364
1c45607a 1365 if (!capable(CAP_SYS_ADMIN)) {
6da5b587 1366 if ((ss->baud_base != info->baud_base) ||
be6cf583 1367 (close_delay != info->port.close_delay) ||
b91cfb25 1368 (closing_wait != info->port.closing_wait) ||
6da5b587
AV		 1369 ((ss->flags & ~ASYNC_USR_MASK) != (info->port.flags & ~ASYNC_USR_MASK))) {
1370 mutex_unlock(&port->mutex);
1c45607a 1371 return -EPERM;
6da5b587 1372 }
0ad9e7d1 1373 info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) |
6da5b587 1374 (ss->flags & ASYNC_USR_MASK));
1c45607a 1375 } else {
1da177e4 1376 /*
1c45607a
JS		 1377 * OK, past this point, all the error checking has been done.
1378 * At this point, we start making changes.....
1da177e4 1379 */
07f86c03 1380 port->flags = ((port->flags & ~ASYNC_FLAGS) |
6da5b587 1381 (ss->flags & ASYNC_FLAGS));
be6cf583
JH		 1382 port->close_delay = close_delay;
1383 port->closing_wait = closing_wait;
07f86c03 1384 if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
6da5b587
AV		 1385 (ss->baud_base != info->baud_base ||
1386 ss->custom_divisor !=
80ff8a80 1387 info->custom_divisor)) {
6da5b587
AV		 1388 if (ss->custom_divisor == 0) {
1389 mutex_unlock(&port->mutex);
07f86c03 1390 return -EINVAL;
6da5b587
AV		 1391 }
1392 baud = ss->baud_base / ss->custom_divisor;
216ba023 1393 tty_encode_baud_rate(tty, baud, baud);
80ff8a80 1394 }
fc83815c 1395
b91cfb25 1396 info->type = ss->type;
1da177e4 1397
b91cfb25
JH		 1398 process_txrx_fifo(info);
1399 }
1c45607a 1400
d41861ca 1401 if (tty_port_initialized(port)) {
07f86c03 1402 if (flags != (port->flags & ASYNC_SPD_MASK)) {
1c45607a 1403 spin_lock_irqsave(&info->slock, sl_flags);
2799707f 1404 mxser_change_speed(tty);
1c45607a 1405 spin_unlock_irqrestore(&info->slock, sl_flags);
1da177e4 1406 }
6769140d 1407 } else {
07f86c03 1408 retval = mxser_activate(port, tty);
6769140d 1409 if (retval == 0)
d41861ca 1410 tty_port_set_initialized(port, 1);
6769140d 1411 }
6da5b587 1412 mutex_unlock(&port->mutex);
1c45607a
JS		 1413 return retval;
1414}
1da177e4 1415
1c45607a
JS		 1416/*
1417 * mxser_get_lsr_info - get line status register info
1418 *
1419 * Purpose: Let user call ioctl() to get info when the UART physically
1420 * is emptied. On bus types like RS485, the transmitter must
1421 * release the bus after transmitting. This must be done when
1422 * the transmit shift register is empty, not be done when the
1423 * transmit holding register is empty. This functionality
1424 * allows an RS485 driver to be written in user space.
1425 */
1426static int mxser_get_lsr_info(struct mxser_port *info,
1427 unsigned int __user *value)
1428{
1429 unsigned char status;
1430 unsigned int result;
1431 unsigned long flags;
1da177e4 1432
1c45607a
JS		 1433 spin_lock_irqsave(&info->slock, flags);
1434 status = inb(info->ioaddr + UART_LSR);
1435 spin_unlock_irqrestore(&info->slock, flags);
1436 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1437 return put_user(result, value);
1438}
1da177e4 1439
60b33c13 1440static int mxser_tiocmget(struct tty_struct *tty)
1c45607a
JS		 1441{
1442 struct mxser_port *info = tty->driver_data;
1443 unsigned char control, status;
1444 unsigned long flags;
1da177e4 1445
8ea2c2ec 1446
1c45607a
JS		 1447 if (tty->index == MXSER_PORTS)
1448 return -ENOIOCTLCMD;
18900ca6 1449 if (tty_io_error(tty))
1c45607a 1450 return -EIO;
1da177e4 1451
1c45607a 1452 control = info->MCR;
1da177e4 1453
1c45607a
JS		 1454 spin_lock_irqsave(&info->slock, flags);
1455 status = inb(info->ioaddr + UART_MSR);
1456 if (status & UART_MSR_ANY_DELTA)
216ba023 1457 mxser_check_modem_status(tty, info, status);
1c45607a
JS		 1458 spin_unlock_irqrestore(&info->slock, flags);
1459 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1460 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1461 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1462 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
1463 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1464 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1465}
1da177e4 1466
20b9d177 1467static int mxser_tiocmset(struct tty_struct *tty,
1c45607a
JS		 1468 unsigned int set, unsigned int clear)
1469{
1470 struct mxser_port *info = tty->driver_data;
1471 unsigned long flags;
1da177e4 1472
1da177e4 1473
1c45607a
JS		 1474 if (tty->index == MXSER_PORTS)
1475 return -ENOIOCTLCMD;
18900ca6 1476 if (tty_io_error(tty))
1c45607a 1477 return -EIO;
1da177e4 1478
1c45607a 1479 spin_lock_irqsave(&info->slock, flags);
1da177e4 1480
1c45607a
JS		 1481 if (set & TIOCM_RTS)
1482 info->MCR |= UART_MCR_RTS;
1483 if (set & TIOCM_DTR)
1484 info->MCR |= UART_MCR_DTR;
1da177e4 1485
1c45607a
JS		 1486 if (clear & TIOCM_RTS)
1487 info->MCR &= ~UART_MCR_RTS;
1488 if (clear & TIOCM_DTR)
1489 info->MCR &= ~UART_MCR_DTR;
8ea2c2ec 1490
1c45607a
JS		 1491 outb(info->MCR, info->ioaddr + UART_MCR);
1492 spin_unlock_irqrestore(&info->slock, flags);
1493 return 0;
1494}
1da177e4 1495
1da177e4
LT		 1496static int mxser_ioctl_special(unsigned int cmd, void __user *argp)
1497{
07f86c03
AC		 1498 struct mxser_port *ip;
1499 struct tty_port *port;
216ba023 1500 struct tty_struct *tty;
1c45607a
JS		 1501 int result, status;
1502 unsigned int i, j;
9d6d162d 1503 int ret = 0;
1da177e4
LT		 1504
1505 switch (cmd) {
1da177e4 1506 case MOXA_GET_MAJOR:
5a3c6b25 1507 printk_ratelimited(KERN_WARNING "mxser: '%s' uses deprecated ioctl "
8f3d137e
JS		 1508 "%x (GET_MAJOR), fix your userspace\n",
1509 current->comm, cmd);
1c45607a 1510 return put_user(ttymajor, (int __user *)argp);
1da177e4
LT		 1511
1512 case MOXA_CHKPORTENABLE:
1513 result = 0;
1c45607a
JS		 1514 for (i = 0; i < MXSER_BOARDS; i++)
1515 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++)
1516 if (mxser_boards[i].ports[j].ioaddr)
1517 result |= (1 << i);
8ea2c2ec 1518 return put_user(result, (unsigned long __user *)argp);
1da177e4 1519 case MOXA_GETDATACOUNT:
07f86c03
AC		 1520 /* The receive side is locked by port->slock but it isn't
1521 clear that an exact snapshot is worth copying here */
1da177e4 1522 if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log)))
9d6d162d 1523 ret = -EFAULT;
9d6d162d 1524 return ret;
72800df9
JS		 1525 case MOXA_GETMSTATUS: {
1526 struct mxser_mstatus ms, __user *msu = argp;
1c45607a
JS		 1527 for (i = 0; i < MXSER_BOARDS; i++)
1528 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
07f86c03
AC		 1529 ip = &mxser_boards[i].ports[j];
1530 port = &ip->port;
72800df9 1531 memset(&ms, 0, sizeof(ms));
1c45607a 1532
07f86c03
AC		 1533 mutex_lock(&port->mutex);
1534 if (!ip->ioaddr)
72800df9 1535 goto copy;
216ba023 1536
07f86c03 1537 tty = tty_port_tty_get(port);
1da177e4 1538
adc8d746 1539 if (!tty)
07f86c03 1540 ms.cflag = ip->normal_termios.c_cflag;
1c45607a 1541 else
adc8d746 1542 ms.cflag = tty->termios.c_cflag;
216ba023 1543 tty_kref_put(tty);
07f86c03
AC		 1544 spin_lock_irq(&ip->slock);
1545 status = inb(ip->ioaddr + UART_MSR);
1546 spin_unlock_irq(&ip->slock);
72800df9
JS		 1547 if (status & UART_MSR_DCD)
1548 ms.dcd = 1;
1549 if (status & UART_MSR_DSR)
1550 ms.dsr = 1;
1551 if (status & UART_MSR_CTS)
1552 ms.cts = 1;
1553 copy:
07f86c03
AC		 1554 mutex_unlock(&port->mutex);
1555 if (copy_to_user(msu, &ms, sizeof(ms)))
72800df9 1556 return -EFAULT;
72800df9 1557 msu++;
1c45607a 1558 }
1da177e4 1559 return 0;
72800df9 1560 }
8ea2c2ec 1561 case MOXA_ASPP_MON_EXT: {
72800df9
JS		 1562 struct mxser_mon_ext *me; /* it's 2k, stack unfriendly */
1563 unsigned int cflag, iflag, p;
1564 u8 opmode;
1565
1566 me = kzalloc(sizeof(*me), GFP_KERNEL);
1567 if (!me)
1568 return -ENOMEM;
1c45607a 1569
72800df9
JS		 1570 for (i = 0, p = 0; i < MXSER_BOARDS; i++) {
1571 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++, p++) {
1572 if (p >= ARRAY_SIZE(me->rx_cnt)) {
1573 i = MXSER_BOARDS;
1574 break;
1575 }
07f86c03
AC		 1576 ip = &mxser_boards[i].ports[j];
1577 port = &ip->port;
1578
1579 mutex_lock(&port->mutex);
1580 if (!ip->ioaddr) {
1581 mutex_unlock(&port->mutex);
1da177e4 1582 continue;
07f86c03 1583 }
1da177e4 1584
07f86c03
AC		 1585 spin_lock_irq(&ip->slock);
1586 status = mxser_get_msr(ip->ioaddr, 0, p);
1c45607a 1587
1da177e4 1588 if (status & UART_MSR_TERI)
07f86c03 1589 ip->icount.rng++;
1da177e4 1590 if (status & UART_MSR_DDSR)
07f86c03 1591 ip->icount.dsr++;
1da177e4 1592 if (status & UART_MSR_DDCD)
07f86c03 1593 ip->icount.dcd++;
1da177e4 1594 if (status & UART_MSR_DCTS)
07f86c03 1595 ip->icount.cts++;
1c45607a 1596
07f86c03
AC		 1597 ip->mon_data.modem_status = status;
1598 me->rx_cnt[p] = ip->mon_data.rxcnt;
1599 me->tx_cnt[p] = ip->mon_data.txcnt;
1600 me->up_rxcnt[p] = ip->mon_data.up_rxcnt;
1601 me->up_txcnt[p] = ip->mon_data.up_txcnt;
72800df9 1602 me->modem_status[p] =
07f86c03
AC		 1603 ip->mon_data.modem_status;
1604 spin_unlock_irq(&ip->slock);
1605
1606 tty = tty_port_tty_get(&ip->port);
1c45607a 1607
adc8d746 1608 if (!tty) {
07f86c03
AC		 1609 cflag = ip->normal_termios.c_cflag;
1610 iflag = ip->normal_termios.c_iflag;
1611 me->baudrate[p] = tty_termios_baud_rate(&ip->normal_termios);
1da177e4 1612 } else {
adc8d746
AC		 1613 cflag = tty->termios.c_cflag;
1614 iflag = tty->termios.c_iflag;
216ba023 1615 me->baudrate[p] = tty_get_baud_rate(tty);
1da177e4 1616 }
216ba023 1617 tty_kref_put(tty);
1da177e4 1618
72800df9
JS		 1619 me->databits[p] = cflag & CSIZE;
1620 me->stopbits[p] = cflag & CSTOPB;
1621 me->parity[p] = cflag & (PARENB | PARODD |
1622 CMSPAR);
1da177e4
LT		 1623
1624 if (cflag & CRTSCTS)
72800df9 1625 me->flowctrl[p] |= 0x03;
1da177e4
LT		 1626
1627 if (iflag & (IXON | IXOFF))
72800df9 1628 me->flowctrl[p] |= 0x0C;
1da177e4 1629
07f86c03 1630 if (ip->type == PORT_16550A)
72800df9 1631 me->fifo[p] = 1;
1da177e4 1632
292955a7 1633 if (ip->board->must_hwid == MOXA_MUST_MU860_HWID) {
dfc7b837
MK		 1634 opmode = inb(ip->opmode_ioaddr)>>((p % 4) * 2);
1635 opmode &= OP_MODE_MASK;
1636 } else {
1637 opmode = RS232_MODE;
1638 }
72800df9 1639 me->iftype[p] = opmode;
07f86c03 1640 mutex_unlock(&port->mutex);
1da177e4 1641 }
9d6d162d 1642 }
72800df9
JS		 1643 if (copy_to_user(argp, me, sizeof(*me)))
1644 ret = -EFAULT;
1645 kfree(me);
1646 return ret;
9d6d162d
AC		 1647 }
1648 default:
1da177e4
LT		 1649 return -ENOIOCTLCMD;
1650 }
1651 return 0;
1652}
1653
1c45607a
JS		 1654static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1655 struct async_icount *cprev)
1da177e4 1656{
1c45607a
JS		 1657 struct async_icount cnow;
1658 unsigned long flags;
1659 int ret;
1da177e4 1660
1c45607a
JS		 1661 spin_lock_irqsave(&info->slock, flags);
1662 cnow = info->icount; /* atomic copy */
1663 spin_unlock_irqrestore(&info->slock, flags);
1da177e4 1664
1c45607a
JS		 1665 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1666 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1667 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
1668 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1da177e4 1669
1c45607a
JS		 1670 *cprev = cnow;
1671
1672 return ret;
1673}
1674
6caa76b7 1675static int mxser_ioctl(struct tty_struct *tty,
1c45607a 1676 unsigned int cmd, unsigned long arg)
1da177e4 1677{
1c45607a
JS		 1678 struct mxser_port *info = tty->driver_data;
1679 struct async_icount cnow;
1c45607a
JS		 1680 unsigned long flags;
1681 void __user *argp = (void __user *)arg;
1da177e4 1682
1c45607a
JS		 1683 if (tty->index == MXSER_PORTS)
1684 return mxser_ioctl_special(cmd, argp);
1da177e4 1685
1c45607a
JS		 1686 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) {
1687 int p;
1688 unsigned long opmode;
1689 static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f };
1690 int shiftbit;
1691 unsigned char val, mask;
1da177e4 1692
292955a7 1693 if (info->board->must_hwid != MOXA_MUST_MU860_HWID)
e037f95f
MK		 1694 return -EFAULT;
1695
1c45607a
JS		 1696 p = tty->index % 4;
1697 if (cmd == MOXA_SET_OP_MODE) {
1698 if (get_user(opmode, (int __user *) argp))
1699 return -EFAULT;
1700 if (opmode != RS232_MODE &&
1701 opmode != RS485_2WIRE_MODE &&
1702 opmode != RS422_MODE &&
1703 opmode != RS485_4WIRE_MODE)
1704 return -EFAULT;
1705 mask = ModeMask[p];
1706 shiftbit = p * 2;
07f86c03 1707 spin_lock_irq(&info->slock);
1c45607a
JS		 1708 val = inb(info->opmode_ioaddr);
1709 val &= mask;
1710 val |= (opmode << shiftbit);
1711 outb(val, info->opmode_ioaddr);
07f86c03 1712 spin_unlock_irq(&info->slock);
1c45607a
JS		 1713 } else {
1714 shiftbit = p * 2;
07f86c03 1715 spin_lock_irq(&info->slock);
1c45607a 1716 opmode = inb(info->opmode_ioaddr) >> shiftbit;
07f86c03 1717 spin_unlock_irq(&info->slock);
1c45607a
JS		 1718 opmode &= OP_MODE_MASK;
1719 if (put_user(opmode, (int __user *)argp))
1720 return -EFAULT;
1721 }
1722 return 0;
1723 }
1724
6da5b587 1725 if (cmd != TIOCMIWAIT && tty_io_error(tty))
1c45607a
JS		 1726 return -EIO;
1727
1728 switch (cmd) {
1c45607a 1729 case TIOCSERGETLSR: /* Get line status register */
9d6d162d 1730 return mxser_get_lsr_info(info, argp);
1c45607a
JS		 1731 /*
1732 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1733 * - mask passed in arg for lines of interest
1734 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1735 * Caller should use TIOCGICOUNT to see which one it was
1736 */
1737 case TIOCMIWAIT:
1738 spin_lock_irqsave(&info->slock, flags);
1739 cnow = info->icount; /* note the counters on entry */
1740 spin_unlock_irqrestore(&info->slock, flags);
1741
bdc04e31 1742 return wait_event_interruptible(info->port.delta_msr_wait,
1c45607a 1743 mxser_cflags_changed(info, arg, &cnow));
1c45607a
JS		 1744 case MOXA_HighSpeedOn:
1745 return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp);
1746 case MOXA_SDS_RSTICOUNTER:
07f86c03 1747 spin_lock_irq(&info->slock);
1c45607a
JS		 1748 info->mon_data.rxcnt = 0;
1749 info->mon_data.txcnt = 0;
07f86c03 1750 spin_unlock_irq(&info->slock);
1c45607a
JS		 1751 return 0;
1752
1753 case MOXA_ASPP_OQUEUE:{
1754 int len, lsr;
1755
1756 len = mxser_chars_in_buffer(tty);
c6eb69ac 1757 spin_lock_irq(&info->slock);
a75b7b68 1758 lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_THRE;
07f86c03 1759 spin_unlock_irq(&info->slock);
1c45607a
JS		 1760 len += (lsr ? 0 : 1);
1761
1762 return put_user(len, (int __user *)argp);
1763 }
1764 case MOXA_ASPP_MON: {
1765 int mcr, status;
1766
c6eb69ac 1767 spin_lock_irq(&info->slock);
1c45607a 1768 status = mxser_get_msr(info->ioaddr, 1, tty->index);
216ba023 1769 mxser_check_modem_status(tty, info, status);
1c45607a
JS		 1770
1771 mcr = inb(info->ioaddr + UART_MCR);
c6eb69ac 1772 spin_unlock_irq(&info->slock);
07f86c03 1773
1c45607a
JS		 1774 if (mcr & MOXA_MUST_MCR_XON_FLAG)
1775 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD;
1776 else
1777 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD;
1778
1779 if (mcr & MOXA_MUST_MCR_TX_XON)
1780 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT;
1781 else
1782 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT;
1783
216ba023 1784 if (tty->hw_stopped)
1c45607a
JS		 1785 info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD;
1786 else
1787 info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD;
07f86c03 1788
1c45607a
JS		 1789 if (copy_to_user(argp, &info->mon_data,
1790 sizeof(struct mxser_mon)))
1791 return -EFAULT;
1792
1793 return 0;
1794 }
1795 case MOXA_ASPP_LSTATUS: {
1796 if (put_user(info->err_shadow, (unsigned char __user *)argp))
1797 return -EFAULT;
1798
1799 info->err_shadow = 0;
1800 return 0;
1801 }
1802 case MOXA_SET_BAUD_METHOD: {
1803 int method;
1804
1805 if (get_user(method, (int __user *)argp))
1806 return -EFAULT;
1807 mxser_set_baud_method[tty->index] = method;
1808 return put_user(method, (int __user *)argp);
1809 }
1810 default:
1811 return -ENOIOCTLCMD;
1812 }
1813 return 0;
1814}
1815
0587102c
AC		 1816 /*
1817 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1818 * Return: write counters to the user passed counter struct
1819 * NB: both 1->0 and 0->1 transitions are counted except for
1820 * RI where only 0->1 is counted.
1821 */
1822
1823static int mxser_get_icount(struct tty_struct *tty,
1824 struct serial_icounter_struct *icount)
1825
1826{
1827 struct mxser_port *info = tty->driver_data;
1828 struct async_icount cnow;
1829 unsigned long flags;
1830
1831 spin_lock_irqsave(&info->slock, flags);
1832 cnow = info->icount;
1833 spin_unlock_irqrestore(&info->slock, flags);
1834
1835 icount->frame = cnow.frame;
1836 icount->brk = cnow.brk;
1837 icount->overrun = cnow.overrun;
1838 icount->buf_overrun = cnow.buf_overrun;
1839 icount->parity = cnow.parity;
1840 icount->rx = cnow.rx;
1841 icount->tx = cnow.tx;
1842 icount->cts = cnow.cts;
1843 icount->dsr = cnow.dsr;
1844 icount->rng = cnow.rng;
1845 icount->dcd = cnow.dcd;
1846 return 0;
1847}
1848
1c45607a
JS		 1849static void mxser_stoprx(struct tty_struct *tty)
1850{
1851 struct mxser_port *info = tty->driver_data;
1852
1853 info->ldisc_stop_rx = 1;
1854 if (I_IXOFF(tty)) {
292955a7 1855 if (info->board->must_hwid) {
1c45607a
JS		 1856 info->IER &= ~MOXA_MUST_RECV_ISR;
1857 outb(info->IER, info->ioaddr + UART_IER);
1858 } else {
1859 info->x_char = STOP_CHAR(tty);
1860 outb(0, info->ioaddr + UART_IER);
1861 info->IER |= UART_IER_THRI;
1862 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1863 }
1864 }
1865
9db276f8 1866 if (C_CRTSCTS(tty)) {
1c45607a
JS		 1867 info->MCR &= ~UART_MCR_RTS;
1868 outb(info->MCR, info->ioaddr + UART_MCR);
1da177e4
LT		 1869 }
1870}
1871
1872/*
1873 * This routine is called by the upper-layer tty layer to signal that
1874 * incoming characters should be throttled.
1875 */
1876static void mxser_throttle(struct tty_struct *tty)
1877{
1da177e4 1878 mxser_stoprx(tty);
1da177e4
LT		 1879}
1880
1881static void mxser_unthrottle(struct tty_struct *tty)
1882{
1c45607a 1883 struct mxser_port *info = tty->driver_data;
1da177e4 1884
1c45607a
JS		 1885 /* startrx */
1886 info->ldisc_stop_rx = 0;
1887 if (I_IXOFF(tty)) {
1888 if (info->x_char)
1889 info->x_char = 0;
1890 else {
292955a7 1891 if (info->board->must_hwid) {
1c45607a
JS		 1892 info->IER |= MOXA_MUST_RECV_ISR;
1893 outb(info->IER, info->ioaddr + UART_IER);
1894 } else {
1895 info->x_char = START_CHAR(tty);
1896 outb(0, info->ioaddr + UART_IER);
1897 info->IER |= UART_IER_THRI;
1898 outb(info->IER, info->ioaddr + UART_IER);
1899 }
1da177e4 1900 }
1c45607a 1901 }
1da177e4 1902
9db276f8 1903 if (C_CRTSCTS(tty)) {
1c45607a
JS		 1904 info->MCR |= UART_MCR_RTS;
1905 outb(info->MCR, info->ioaddr + UART_MCR);
1da177e4
LT		 1906 }
1907}
1908
1909/*
1910 * mxser_stop() and mxser_start()
1911 *
6e94dbc7 1912 * This routines are called before setting or resetting tty->flow.stopped.
1da177e4
LT		 1913 * They enable or disable transmitter interrupts, as necessary.
1914 */
1915static void mxser_stop(struct tty_struct *tty)
1916{
1c45607a 1917 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1918 unsigned long flags;
1919
1920 spin_lock_irqsave(&info->slock, flags);
1921 if (info->IER & UART_IER_THRI) {
1922 info->IER &= ~UART_IER_THRI;
1c45607a 1923 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1924 }
1925 spin_unlock_irqrestore(&info->slock, flags);
1926}
1927
1928static void mxser_start(struct tty_struct *tty)
1929{
1c45607a 1930 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1931 unsigned long flags;
1932
1933 spin_lock_irqsave(&info->slock, flags);
0ad9e7d1 1934 if (info->xmit_cnt && info->port.xmit_buf) {
1c45607a 1935 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1936 info->IER |= UART_IER_THRI;
1c45607a 1937 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1938 }
1939 spin_unlock_irqrestore(&info->slock, flags);
1940}
1941
1c45607a
JS		 1942static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1943{
1944 struct mxser_port *info = tty->driver_data;
1945 unsigned long flags;
1946
1947 spin_lock_irqsave(&info->slock, flags);
2799707f 1948 mxser_change_speed(tty);
1c45607a
JS		 1949 spin_unlock_irqrestore(&info->slock, flags);
1950
9db276f8 1951 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
1c45607a
JS		 1952 tty->hw_stopped = 0;
1953 mxser_start(tty);
1954 }
1955
1956 /* Handle sw stopped */
9db276f8 1957 if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) {
6e94dbc7 1958 tty->flow.stopped = 0;
1c45607a 1959
292955a7 1960 if (info->board->must_hwid) {
1c45607a 1961 spin_lock_irqsave(&info->slock, flags);
148ff86b
CH		 1962 mxser_disable_must_rx_software_flow_control(
1963 info->ioaddr);
1c45607a
JS		 1964 spin_unlock_irqrestore(&info->slock, flags);
1965 }
1966
1967 mxser_start(tty);
1968 }
1969}
1970
1da177e4
LT		 1971/*
1972 * mxser_wait_until_sent() --- wait until the transmitter is empty
1973 */
1974static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1975{
1c45607a 1976 struct mxser_port *info = tty->driver_data;
1da177e4 1977 unsigned long orig_jiffies, char_time;
07f86c03 1978 unsigned long flags;
1da177e4
LT		 1979 int lsr;
1980
1981 if (info->type == PORT_UNKNOWN)
1982 return;
1983
1984 if (info->xmit_fifo_size == 0)
1985 return; /* Just in case.... */
1986
1987 orig_jiffies = jiffies;
1988 /*
1989 * Set the check interval to be 1/5 of the estimated time to
1990 * send a single character, and make it at least 1. The check
1991 * interval should also be less than the timeout.
1992 *
1993 * Note: we have to use pretty tight timings here to satisfy
1994 * the NIST-PCTS.
1995 */
1996 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
1997 char_time = char_time / 5;
1998 if (char_time == 0)
1999 char_time = 1;
2000 if (timeout && timeout < char_time)
2001 char_time = timeout;
2002 /*
2003 * If the transmitter hasn't cleared in twice the approximate
2004 * amount of time to send the entire FIFO, it probably won't
2005 * ever clear. This assumes the UART isn't doing flow
2006 * control, which is currently the case. Hence, if it ever
2007 * takes longer than info->timeout, this is probably due to a
2008 * UART bug of some kind. So, we clamp the timeout parameter at
2009 * 2*info->timeout.
2010 */
2011 if (!timeout || timeout > 2 * info->timeout)
2012 timeout = 2 * info->timeout;
8bab534b 2013
07f86c03 2014 spin_lock_irqsave(&info->slock, flags);
1c45607a 2015 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) {
07f86c03 2016 spin_unlock_irqrestore(&info->slock, flags);
da4cd8df 2017 schedule_timeout_interruptible(char_time);
07f86c03 2018 spin_lock_irqsave(&info->slock, flags);
1da177e4 2019 if (signal_pending(current))
1c45607a
JS		 2020 break;
2021 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2022 break;
1da177e4 2023 }
07f86c03 2024 spin_unlock_irqrestore(&info->slock, flags);
1c45607a 2025 set_current_state(TASK_RUNNING);
1c45607a 2026}
1da177e4 2027
1c45607a
JS		 2028/*
2029 * This routine is called by tty_hangup() when a hangup is signaled.
2030 */
2031static void mxser_hangup(struct tty_struct *tty)
2032{
2033 struct mxser_port *info = tty->driver_data;
1da177e4 2034
1c45607a 2035 mxser_flush_buffer(tty);
3b6826b2 2036 tty_port_hangup(&info->port);
1da177e4
LT		 2037}
2038
1c45607a
JS		 2039/*
2040 * mxser_rs_break() --- routine which turns the break handling on or off
2041 */
9e98966c 2042static int mxser_rs_break(struct tty_struct *tty, int break_state)
1da177e4 2043{
1c45607a 2044 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 2045 unsigned long flags;
2046
1c45607a
JS		 2047 spin_lock_irqsave(&info->slock, flags);
2048 if (break_state == -1)
2049 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
2050 info->ioaddr + UART_LCR);
2051 else
2052 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
2053 info->ioaddr + UART_LCR);
2054 spin_unlock_irqrestore(&info->slock, flags);
9e98966c 2055 return 0;
1c45607a 2056}
1da177e4 2057
e5ce1bce
JS		 2058static bool mxser_receive_chars_new(struct tty_struct *tty,
2059 struct mxser_port *port, u8 status, int *cnt)
2060{
2061 enum mxser_must_hwid hwid = port->board->must_hwid;
2062 u8 gdl;
2063
2064 if (hwid == MOXA_OTHER_UART)
2065 return false;
2066 if (status & UART_LSR_SPECIAL)
2067 return false;
2068 if (hwid == MOXA_MUST_MU860_HWID && (status & MOXA_MUST_LSR_RERR))
2069 return false;
2070 if (status & MOXA_MUST_LSR_RERR)
2071 return false;
2072
2073 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
2074 if (hwid == MOXA_MUST_MU150_HWID)
2075 gdl &= MOXA_MUST_GDL_MASK;
2076
2077 if (gdl >= tty->receive_room && !port->ldisc_stop_rx)
2078 mxser_stoprx(tty);
2079
2080 while (gdl--) {
2081 u8 ch = inb(port->ioaddr + UART_RX);
2082 tty_insert_flip_char(&port->port, ch, 0);
2083 (*cnt)++;
2084 }
2085
2086 return true;
2087}
2088
0c419421
JS		 2089static u8 mxser_receive_chars_old(struct tty_struct *tty,
2090 struct mxser_port *port, u8 status, int *cnt)
1c45607a 2091{
0c419421
JS		 2092 enum mxser_must_hwid hwid = port->board->must_hwid;
2093 int recv_room = tty->receive_room;
1c45607a 2094 int ignored = 0;
1c45607a 2095 int max = 256;
0c419421 2096 u8 ch;
1c45607a
JS		 2097
2098 do {
2099 if (max-- < 0)
2100 break;
1da177e4 2101
1c45607a 2102 ch = inb(port->ioaddr + UART_RX);
0c419421 2103 if (hwid && (status & UART_LSR_OE))
1c45607a 2104 outb(0x23, port->ioaddr + UART_FCR);
15517806
JS		 2105 status &= port->read_status_mask;
2106 if (status & port->ignore_status_mask) {
1c45607a
JS		 2107 if (++ignored > 100)
2108 break;
2109 } else {
2110 char flag = 0;
15517806
JS		 2111 if (status & UART_LSR_SPECIAL) {
2112 if (status & UART_LSR_BI) {
1c45607a
JS		 2113 flag = TTY_BREAK;
2114 port->icount.brk++;
1da177e4 2115
0ad9e7d1 2116 if (port->port.flags & ASYNC_SAK)
1c45607a 2117 do_SAK(tty);
15517806 2118 } else if (status & UART_LSR_PE) {
1c45607a
JS		 2119 flag = TTY_PARITY;
2120 port->icount.parity++;
15517806 2121 } else if (status & UART_LSR_FE) {
1c45607a
JS		 2122 flag = TTY_FRAME;
2123 port->icount.frame++;
15517806 2124 } else if (status & UART_LSR_OE) {
1c45607a
JS		 2125 flag = TTY_OVERRUN;
2126 port->icount.overrun++;
6de6e5c4 2127 }
1c45607a 2128 }
92a19f9c 2129 tty_insert_flip_char(&port->port, ch, flag);
0c419421
JS		 2130 (*cnt)++;
2131 if (*cnt >= recv_room) {
1c45607a
JS		 2132 if (!port->ldisc_stop_rx)
2133 mxser_stoprx(tty);
2134 break;
2135 }
1da177e4 2136
1c45607a 2137 }
1da177e4 2138
0c419421 2139 if (hwid)
1c45607a 2140 break;
1da177e4 2141
15517806
JS		 2142 status = inb(port->ioaddr + UART_LSR);
2143 } while (status & UART_LSR_DR);
1da177e4 2144
0c419421
JS		 2145 return status;
2146}
2147
2148static u8 mxser_receive_chars(struct tty_struct *tty,
2149 struct mxser_port *port, u8 status)
2150{
2151 int cnt = 0;
2152
2153 if (tty->receive_room == 0 && !port->ldisc_stop_rx)
2154 mxser_stoprx(tty);
2155
2156 if (!mxser_receive_chars_new(tty, port, status, &cnt))
2157 status = mxser_receive_chars_old(tty, port, status, &cnt);
2158
216ba023 2159 mxvar_log.rxcnt[tty->index] += cnt;
1c45607a
JS		 2160 port->mon_data.rxcnt += cnt;
2161 port->mon_data.up_rxcnt += cnt;
1da177e4 2162
2e124b4a 2163 tty_flip_buffer_push(&port->port);
15517806
JS		 2164
2165 return status;
1da177e4
LT		 2166}
2167
216ba023 2168static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port)
1da177e4 2169{
1c45607a 2170 int count, cnt;
1da177e4 2171
1c45607a
JS		 2172 if (port->x_char) {
2173 outb(port->x_char, port->ioaddr + UART_TX);
2174 port->x_char = 0;
216ba023 2175 mxvar_log.txcnt[tty->index]++;
1c45607a
JS		 2176 port->mon_data.txcnt++;
2177 port->mon_data.up_txcnt++;
2178 port->icount.tx++;
2179 return;
2180 }
1da177e4 2181
0ad9e7d1 2182 if (port->port.xmit_buf == NULL)
1c45607a 2183 return;
1da177e4 2184
6e94dbc7 2185 if (port->xmit_cnt <= 0 || tty->flow.stopped ||
216ba023 2186 (tty->hw_stopped &&
1c45607a 2187 (port->type != PORT_16550A) &&
292955a7 2188 (!port->board->must_hwid))) {
1c45607a
JS		 2189 port->IER &= ~UART_IER_THRI;
2190 outb(port->IER, port->ioaddr + UART_IER);
2191 return;
1da177e4
LT		 2192 }
2193
1c45607a
JS		 2194 cnt = port->xmit_cnt;
2195 count = port->xmit_fifo_size;
2196 do {
0ad9e7d1 2197 outb(port->port.xmit_buf[port->xmit_tail++],
1c45607a
JS		 2198 port->ioaddr + UART_TX);
2199 port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1);
2200 if (--port->xmit_cnt <= 0)
2201 break;
2202 } while (--count > 0);
216ba023 2203 mxvar_log.txcnt[tty->index] += (cnt - port->xmit_cnt);
1da177e4 2204
1c45607a
JS		 2205 port->mon_data.txcnt += (cnt - port->xmit_cnt);
2206 port->mon_data.up_txcnt += (cnt - port->xmit_cnt);
2207 port->icount.tx += (cnt - port->xmit_cnt);
1da177e4 2208
464eb8f5 2209 if (port->xmit_cnt < WAKEUP_CHARS)
216ba023 2210 tty_wakeup(tty);
1c45607a
JS		 2211
2212 if (port->xmit_cnt <= 0) {
2213 port->IER &= ~UART_IER_THRI;
2214 outb(port->IER, port->ioaddr + UART_IER);
1da177e4 2215 }
1da177e4
LT		 2216}
2217
9e40ea1f
JS		 2218static bool mxser_port_isr(struct mxser_port *port)
2219{
2220 struct tty_struct *tty;
2221 u8 iir, msr, status;
2222 bool error = false;
2223
2224 iir = inb(port->ioaddr + UART_IIR);
2225 if (iir & UART_IIR_NO_INT)
2226 return true;
2227
2228 iir &= MOXA_MUST_IIR_MASK;
2229 tty = tty_port_tty_get(&port->port);
2230 if (!tty || port->closing || !tty_port_initialized(&port->port)) {
2231 status = inb(port->ioaddr + UART_LSR);
2232 outb(0x27, port->ioaddr + UART_FCR);
2233 inb(port->ioaddr + UART_MSR);
2234
2235 error = true;
2236 goto put_tty;
2237 }
2238
2239 status = inb(port->ioaddr + UART_LSR);
2240
2241 if (status & UART_LSR_PE)
2242 port->err_shadow |= NPPI_NOTIFY_PARITY;
2243 if (status & UART_LSR_FE)
2244 port->err_shadow |= NPPI_NOTIFY_FRAMING;
2245 if (status & UART_LSR_OE)
2246 port->err_shadow |= NPPI_NOTIFY_HW_OVERRUN;
2247 if (status & UART_LSR_BI)
2248 port->err_shadow |= NPPI_NOTIFY_BREAK;
2249
2250 if (port->board->must_hwid) {
2251 if (iir == MOXA_MUST_IIR_GDA ||
2252 iir == MOXA_MUST_IIR_RDA ||
2253 iir == MOXA_MUST_IIR_RTO ||
2254 iir == MOXA_MUST_IIR_LSR)
2255 status = mxser_receive_chars(tty, port, status);
2256 } else {
2257 status &= port->read_status_mask;
2258 if (status & UART_LSR_DR)
2259 status = mxser_receive_chars(tty, port, status);
2260 }
2261
2262 msr = inb(port->ioaddr + UART_MSR);
2263 if (msr & UART_MSR_ANY_DELTA)
2264 mxser_check_modem_status(tty, port, msr);
2265
2266 if (port->board->must_hwid) {
2267 if (iir == 0x02 && (status & UART_LSR_THRE))
2268 mxser_transmit_chars(tty, port);
2269 } else {
2270 if (status & UART_LSR_THRE)
2271 mxser_transmit_chars(tty, port);
2272 }
2273
2274put_tty:
2275 tty_kref_put(tty);
2276
2277 return error;
2278}
2279
1da177e4 2280/*
1c45607a 2281 * This is the serial driver's generic interrupt routine
1da177e4 2282 */
1c45607a 2283static irqreturn_t mxser_interrupt(int irq, void *dev_id)
1da177e4 2284{
cef222cb 2285 struct mxser_board *brd = dev_id;
1c45607a 2286 struct mxser_port *port;
1c45607a 2287 unsigned int int_cnt, pass_counter = 0;
9cb5c9c3 2288 unsigned int i, max = brd->info->nports;
1c45607a 2289 int handled = IRQ_NONE;
9cb5c9c3 2290 u8 irqbits, bits, mask = BIT(max) - 1;
1da177e4 2291
1c45607a 2292 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
9cb5c9c3
JS		 2293 irqbits = inb(brd->vector) & mask;
2294 if (irqbits == mask)
1c45607a 2295 break;
1da177e4 2296
1c45607a
JS		 2297 handled = IRQ_HANDLED;
2298 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
9cb5c9c3 2299 if (irqbits == mask)
1c45607a
JS		 2300 break;
2301 if (bits & irqbits)
2302 continue;
2303 port = &brd->ports[i];
2304
2305 int_cnt = 0;
2306 spin_lock(&port->slock);
2307 do {
9e40ea1f 2308 if (mxser_port_isr(port))
1c45607a 2309 break;
1c45607a
JS		 2310 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
2311 spin_unlock(&port->slock);
2312 }
2313 }
1da177e4 2314
1c45607a
JS		 2315 return handled;
2316}
1da177e4 2317
1c45607a
JS		 2318static const struct tty_operations mxser_ops = {
2319 .open = mxser_open,
2320 .close = mxser_close,
2321 .write = mxser_write,
2322 .put_char = mxser_put_char,
2323 .flush_chars = mxser_flush_chars,
2324 .write_room = mxser_write_room,
2325 .chars_in_buffer = mxser_chars_in_buffer,
2326 .flush_buffer = mxser_flush_buffer,
2327 .ioctl = mxser_ioctl,
2328 .throttle = mxser_throttle,
2329 .unthrottle = mxser_unthrottle,
2330 .set_termios = mxser_set_termios,
2331 .stop = mxser_stop,
2332 .start = mxser_start,
2333 .hangup = mxser_hangup,
2334 .break_ctl = mxser_rs_break,
2335 .wait_until_sent = mxser_wait_until_sent,
2336 .tiocmget = mxser_tiocmget,
2337 .tiocmset = mxser_tiocmset,
6da5b587
AV		 2338 .set_serial = mxser_set_serial_info,
2339 .get_serial = mxser_get_serial_info,
0587102c 2340 .get_icount = mxser_get_icount,
1c45607a 2341};
1da177e4 2342
04b757df 2343static const struct tty_port_operations mxser_port_ops = {
31f35939 2344 .carrier_raised = mxser_carrier_raised,
fcc8ac18 2345 .dtr_rts = mxser_dtr_rts,
6769140d
AC		 2346 .activate = mxser_activate,
2347 .shutdown = mxser_shutdown_port,
31f35939
AC		 2348};
2349
1c45607a
JS		 2350/*
2351 * The MOXA Smartio/Industio serial driver boot-time initialization code!
2352 */
1da177e4 2353
2799707f 2354static int mxser_initbrd(struct mxser_board *brd)
1da177e4 2355{
1c45607a
JS		 2356 struct mxser_port *info;
2357 unsigned int i;
2358 int retval;
1da177e4 2359
1c45607a
JS		 2360 for (i = 0; i < brd->info->nports; i++) {
2361 info = &brd->ports[i];
44b7d1b3 2362 tty_port_init(&info->port);
31f35939 2363 info->port.ops = &mxser_port_ops;
1c45607a
JS		 2364 info->board = brd;
2365 info->stop_rx = 0;
2366 info->ldisc_stop_rx = 0;
1da177e4 2367
1c45607a 2368 /* Enhance mode enabled here */
292955a7 2369 if (brd->must_hwid != MOXA_OTHER_UART)
148ff86b 2370 mxser_enable_must_enchance_mode(info->ioaddr);
1da177e4 2371
58a2ddb3 2372 info->type = PORT_16550A;
1da177e4 2373
1c45607a 2374 process_txrx_fifo(info);
1da177e4 2375
1c45607a 2376 info->custom_divisor = info->baud_base * 16;
44b7d1b3
AC		 2377 info->port.close_delay = 5 * HZ / 10;
2378 info->port.closing_wait = 30 * HZ;
1c45607a 2379 info->normal_termios = mxvar_sdriver->init_termios;
1c45607a
JS		 2380 memset(&info->mon_data, 0, sizeof(struct mxser_mon));
2381 info->err_shadow = 0;
2382 spin_lock_init(&info->slock);
1da177e4 2383
1c45607a
JS		 2384 /* before set INT ISR, disable all int */
2385 outb(inb(info->ioaddr + UART_IER) & 0xf0,
2386 info->ioaddr + UART_IER);
2387 }
1da177e4 2388
1c45607a
JS		 2389 retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser",
2390 brd);
191c5f10
JS		 2391 if (retval) {
2392 for (i = 0; i < brd->info->nports; i++)
2393 tty_port_destroy(&brd->ports[i].port);
1c45607a
JS		 2394 printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may "
2395 "conflict with another device.\n",
2396 brd->info->name, brd->irq);
191c5f10 2397 }
df480518 2398
1c45607a
JS		 2399 return retval;
2400}
1da177e4 2401
191c5f10
JS		 2402static void mxser_board_remove(struct mxser_board *brd)
2403{
2404 unsigned int i;
2405
2406 for (i = 0; i < brd->info->nports; i++) {
2407 tty_unregister_device(mxvar_sdriver, brd->idx + i);
2408 tty_port_destroy(&brd->ports[i].port);
2409 }
9e17df37 2410 free_irq(brd->irq, brd);
191c5f10
JS		 2411}
2412
9671f099 2413static int mxser_probe(struct pci_dev *pdev,
1c45607a 2414 const struct pci_device_id *ent)
1da177e4 2415{
1c45607a
JS		 2416 struct mxser_board *brd;
2417 unsigned int i, j;
2418 unsigned long ioaddress;
9e17df37 2419 struct device *tty_dev;
1c45607a 2420 int retval = -EINVAL;
1da177e4 2421
1c45607a
JS		 2422 for (i = 0; i < MXSER_BOARDS; i++)
2423 if (mxser_boards[i].info == NULL)
2424 break;
2425
2426 if (i >= MXSER_BOARDS) {
83766bc6
JS		 2427 dev_err(&pdev->dev, "too many boards found (maximum %d), board "
2428 "not configured\n", MXSER_BOARDS);
1c45607a
JS		 2429 goto err;
2430 }
2431
2432 brd = &mxser_boards[i];
2433 brd->idx = i * MXSER_PORTS_PER_BOARD;
83766bc6 2434 dev_info(&pdev->dev, "found MOXA %s board (BusNo=%d, DevNo=%d)\n",
1c45607a
JS		 2435 mxser_cards[ent->driver_data].name,
2436 pdev->bus->number, PCI_SLOT(pdev->devfn));
2437
2438 retval = pci_enable_device(pdev);
2439 if (retval) {
83766bc6 2440 dev_err(&pdev->dev, "PCI enable failed\n");
1c45607a
JS		 2441 goto err;
2442 }
2443
2444 /* io address */
2445 ioaddress = pci_resource_start(pdev, 2);
2446 retval = pci_request_region(pdev, 2, "mxser(IO)");
2447 if (retval)
df480518 2448 goto err_dis;
1c45607a
JS		 2449
2450 brd->info = &mxser_cards[ent->driver_data];
2451 for (i = 0; i < brd->info->nports; i++)
2452 brd->ports[i].ioaddr = ioaddress + 8 * i;
2453
2454 /* vector */
2455 ioaddress = pci_resource_start(pdev, 3);
2456 retval = pci_request_region(pdev, 3, "mxser(vector)");
2457 if (retval)
df480518 2458 goto err_zero;
1c45607a
JS		 2459 brd->vector = ioaddress;
2460
2461 /* irq */
2462 brd->irq = pdev->irq;
2463
292955a7 2464 brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr);
1c45607a 2465
928f9464
JS		 2466 for (j = 0; j < UART_INFO_NUM; j++) {
2467 if (Gpci_uart_info[j].type == brd->must_hwid) {
2468 brd->max_baud = Gpci_uart_info[j].max_baud;
2469
2470 /* exception....CP-102 */
2471 if (brd->info->flags & MXSER_HIGHBAUD)
2472 brd->max_baud = 921600;
2473 break;
1da177e4 2474 }
1c45607a
JS		 2475 }
2476
292955a7 2477 if (brd->must_hwid == MOXA_MUST_MU860_HWID) {
1c45607a
JS		 2478 for (i = 0; i < brd->info->nports; i++) {
2479 if (i < 4)
2480 brd->ports[i].opmode_ioaddr = ioaddress + 4;
2481 else
2482 brd->ports[i].opmode_ioaddr = ioaddress + 0x0c;
1da177e4 2483 }
1c45607a
JS		 2484 outb(0, ioaddress + 4); /* default set to RS232 mode */
2485 outb(0, ioaddress + 0x0c); /* default set to RS232 mode */
1da177e4 2486 }
1c45607a
JS		 2487
2488 for (i = 0; i < brd->info->nports; i++) {
1c45607a
JS		 2489 brd->ports[i].baud_base = 921600;
2490 }
2491
2492 /* mxser_initbrd will hook ISR. */
2799707f 2493 retval = mxser_initbrd(brd);
1c45607a 2494 if (retval)
df480518 2495 goto err_rel3;
1c45607a 2496
9e17df37
AK		 2497 for (i = 0; i < brd->info->nports; i++) {
2498 tty_dev = tty_port_register_device(&brd->ports[i].port,
2499 mxvar_sdriver, brd->idx + i, &pdev->dev);
2500 if (IS_ERR(tty_dev)) {
2501 retval = PTR_ERR(tty_dev);
1b581f17 2502 for (; i > 0; i--)
9e17df37 2503 tty_unregister_device(mxvar_sdriver,
1b581f17 2504 brd->idx + i - 1);
9e17df37
AK		 2505 goto err_relbrd;
2506 }
2507 }
1c45607a
JS		 2508
2509 pci_set_drvdata(pdev, brd);
2510
2511 return 0;
9e17df37
AK		 2512err_relbrd:
2513 for (i = 0; i < brd->info->nports; i++)
2514 tty_port_destroy(&brd->ports[i].port);
2515 free_irq(brd->irq, brd);
df480518
JS		 2516err_rel3:
2517 pci_release_region(pdev, 3);
2518err_zero:
1c45607a 2519 brd->info = NULL;
df480518
JS		 2520 pci_release_region(pdev, 2);
2521err_dis:
2522 pci_disable_device(pdev);
1c45607a
JS		 2523err:
2524 return retval;
1da177e4
LT		 2525}
2526
ae8d8a14 2527static void mxser_remove(struct pci_dev *pdev)
1da177e4 2528{
1c45607a 2529 struct mxser_board *brd = pci_get_drvdata(pdev);
1da177e4 2530
191c5f10 2531 mxser_board_remove(brd);
1da177e4 2532
df480518
JS		 2533 pci_release_region(pdev, 2);
2534 pci_release_region(pdev, 3);
2535 pci_disable_device(pdev);
1c45607a 2536 brd->info = NULL;
1da177e4
LT		 2537}
2538
1c45607a
JS		 2539static struct pci_driver mxser_driver = {
2540 .name = "mxser",
2541 .id_table = mxser_pcibrds,
2542 .probe = mxser_probe,
91116cba 2543 .remove = mxser_remove
1c45607a
JS		 2544};
2545
2546static int __init mxser_module_init(void)
1da177e4 2547{
1df00924 2548 int retval;
1da177e4 2549
1c45607a
JS		 2550 mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
2551 if (!mxvar_sdriver)
2552 return -ENOMEM;
2553
1c45607a 2554 /* Initialize the tty_driver structure */
1c45607a
JS		 2555 mxvar_sdriver->name = "ttyMI";
2556 mxvar_sdriver->major = ttymajor;
2557 mxvar_sdriver->minor_start = 0;
1c45607a
JS		 2558 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
2559 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
2560 mxvar_sdriver->init_termios = tty_std_termios;
2561 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
2562 mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV;
2563 tty_set_operations(mxvar_sdriver, &mxser_ops);
2564
2565 retval = tty_register_driver(mxvar_sdriver);
2566 if (retval) {
2567 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
2568 "tty driver !\n");
2569 goto err_put;
1da177e4 2570 }
1c45607a 2571
1c45607a
JS		 2572 retval = pci_register_driver(&mxser_driver);
2573 if (retval) {
83766bc6 2574 printk(KERN_ERR "mxser: can't register pci driver\n");
29134367 2575 goto err_unr;
1c45607a
JS		 2576 }
2577
1c45607a
JS		 2578 return 0;
2579err_unr:
2580 tty_unregister_driver(mxvar_sdriver);
2581err_put:
2582 put_tty_driver(mxvar_sdriver);
2583 return retval;
2584}
2585
2586static void __exit mxser_module_exit(void)
2587{
1c45607a 2588 pci_unregister_driver(&mxser_driver);
1c45607a
JS		 2589 tty_unregister_driver(mxvar_sdriver);
2590 put_tty_driver(mxvar_sdriver);
1da177e4
LT		 2591}
2592
2593module_init(mxser_module_init);
2594module_exit(mxser_module_exit);
Linux 6.x block layer and io_uring tree(s)