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mxser: remove MOXA_HighSpeedOn ioctl
[linux-2.6-block.git] / drivers / tty / mxser.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
1da177e4
LT		 2/*
3 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
4 *
80ff8a80
JS		 5 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com).
6 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com>
1da177e4 7 *
1c45607a
JS		 8 * This code is loosely based on the 1.8 moxa driver which is based on
9 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
10 * others.
1da177e4 11 *
1da177e4 12 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
8eb04cf3
AC		 13 * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on
14 * www.moxa.com.
1da177e4 15 * - Fixed x86_64 cleanness
1da177e4
LT		 16 */
17
1da177e4 18#include <linux/module.h>
1da177e4
LT		 19#include <linux/errno.h>
20#include <linux/signal.h>
21#include <linux/sched.h>
22#include <linux/timer.h>
23#include <linux/interrupt.h>
24#include <linux/tty.h>
25#include <linux/tty_flip.h>
26#include <linux/serial.h>
27#include <linux/serial_reg.h>
28#include <linux/major.h>
29#include <linux/string.h>
30#include <linux/fcntl.h>
31#include <linux/ptrace.h>
1da177e4
LT		 32#include <linux/ioport.h>
33#include <linux/mm.h>
1da177e4
LT		 34#include <linux/delay.h>
35#include <linux/pci.h>
1977f032 36#include <linux/bitops.h>
5a0e3ad6 37#include <linux/slab.h>
5a3c6b25 38#include <linux/ratelimit.h>
1da177e4 39
1da177e4
LT		 40#include <asm/io.h>
41#include <asm/irq.h>
7c0f6ba6 42#include <linux/uaccess.h>
1da177e4 43
4463cc5b
JS		 44/*
45 * Semi-public control interfaces
46 */
47
48/*
49 * MOXA ioctls
50 */
51
52#define MOXA 0x400
4463cc5b
JS		 53#define MOXA_SET_OP_MODE (MOXA + 66)
54#define MOXA_GET_OP_MODE (MOXA + 67)
55
56#define RS232_MODE 0
57#define RS485_2WIRE_MODE 1
58#define RS422_MODE 2
59#define RS485_4WIRE_MODE 3
60#define OP_MODE_MASK 3
61
4463cc5b
JS		 62/* --------------------------------------------------- */
63
4463cc5b
JS		 64/*
65 * Follow just what Moxa Must chip defines.
66 *
67 * When LCR register (offset 0x03) writes the following value, the Must chip
68 * will enter enchance mode. And write value on EFR (offset 0x02) bit 6,7 to
69 * change bank.
70 */
71#define MOXA_MUST_ENTER_ENCHANCE 0xBF
72
73/* when enhance mode enabled, access on general bank register */
74#define MOXA_MUST_GDL_REGISTER 0x07
75#define MOXA_MUST_GDL_MASK 0x7F
76#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
77
78#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
79/* enchance register bank select and enchance mode setting register */
80/* when LCR register equals to 0xBF */
81#define MOXA_MUST_EFR_REGISTER 0x02
82#define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enchance mode enable */
83/* enchance register bank set 0, 1, 2 */
84#define MOXA_MUST_EFR_BANK0 0x00
85#define MOXA_MUST_EFR_BANK1 0x40
86#define MOXA_MUST_EFR_BANK2 0x80
87#define MOXA_MUST_EFR_BANK3 0xC0
88#define MOXA_MUST_EFR_BANK_MASK 0xC0
89
90/* set XON1 value register, when LCR=0xBF and change to bank0 */
91#define MOXA_MUST_XON1_REGISTER 0x04
92
93/* set XON2 value register, when LCR=0xBF and change to bank0 */
94#define MOXA_MUST_XON2_REGISTER 0x05
95
96/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
97#define MOXA_MUST_XOFF1_REGISTER 0x06
98
99/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
100#define MOXA_MUST_XOFF2_REGISTER 0x07
101
102#define MOXA_MUST_RBRTL_REGISTER 0x04
103#define MOXA_MUST_RBRTH_REGISTER 0x05
104#define MOXA_MUST_RBRTI_REGISTER 0x06
105#define MOXA_MUST_THRTL_REGISTER 0x07
106#define MOXA_MUST_ENUM_REGISTER 0x04
107#define MOXA_MUST_HWID_REGISTER 0x05
108#define MOXA_MUST_ECR_REGISTER 0x06
109#define MOXA_MUST_CSR_REGISTER 0x07
110
111#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */
112#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */
113
114#define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */
115#define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */
116#define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */
117#define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */
118
119#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
120
121/* GDA interrupt pending */
122#define MOXA_MUST_IIR_GDA 0x1C
123#define MOXA_MUST_IIR_RDA 0x04
124#define MOXA_MUST_IIR_RTO 0x0C
125#define MOXA_MUST_IIR_LSR 0x06
126
127/* received Xon/Xoff or specical interrupt pending */
128#define MOXA_MUST_IIR_XSC 0x10
129
130/* RTS/CTS change state interrupt pending */
131#define MOXA_MUST_IIR_RTSCTS 0x20
132#define MOXA_MUST_IIR_MASK 0x3E
133
134#define MOXA_MUST_MCR_XON_FLAG 0x40
135#define MOXA_MUST_MCR_XON_ANY 0x80
136#define MOXA_MUST_MCR_TX_XON 0x08
137
138#define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */
139#define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */
140#define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */
141#define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */
142#define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */
143#define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */
144#define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */
145#define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */
146#define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */
147#define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */
148#define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */
1da177e4 149
1da177e4 150#define MXSERMAJOR 174
1da177e4 151
1da177e4 152#define MXSER_BOARDS 4 /* Max. boards */
1da177e4 153#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
1c45607a
JS		 154#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
155#define MXSER_ISR_PASS_LIMIT 100
1da177e4 156
1da177e4
LT		 157#define WAKEUP_CHARS 256
158
e129deff 159#define PCI_DEVICE_ID_POS104UL 0x1044
1c45607a 160#define PCI_DEVICE_ID_CB108 0x1080
e129deff 161#define PCI_DEVICE_ID_CP102UF 0x1023
502f295f 162#define PCI_DEVICE_ID_CP112UL 0x1120
1c45607a 163#define PCI_DEVICE_ID_CB114 0x1142
80ff8a80 164#define PCI_DEVICE_ID_CP114UL 0x1143
1c45607a
JS		 165#define PCI_DEVICE_ID_CB134I 0x1341
166#define PCI_DEVICE_ID_CP138U 0x1380
1da177e4 167
1c45607a 168#define MXSER_HIGHBAUD 1
1da177e4 169
e4558366
JS		 170enum mxser_must_hwid {
171 MOXA_OTHER_UART = 0x00,
172 MOXA_MUST_MU150_HWID = 0x01,
173 MOXA_MUST_MU860_HWID = 0x02,
174};
175
1c45607a 176static const struct {
dc33f644
JS		 177 u8 type;
178 u8 fifo_size;
179 u8 rx_high_water;
180 u8 rx_low_water;
181 speed_t max_baud;
1c45607a 182} Gpci_uart_info[] = {
dc33f644
JS		 183 { MOXA_OTHER_UART, 16, 14, 1, 921600 },
184 { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 },
185 { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 }
1da177e4 186};
1c45607a 187#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
1da177e4 188
1c45607a
JS		 189struct mxser_cardinfo {
190 char *name;
191 unsigned int nports;
192 unsigned int flags;
193};
1da177e4 194
1c45607a 195static const struct mxser_cardinfo mxser_cards[] = {
15254902 196/* 0*/ { "C168H/PCI series", 8, },
1c45607a 197 { "C104H/PCI series", 4, },
1c45607a
JS		 198 { "CP-132 series", 2, },
199 { "CP-114 series", 4, },
15254902
JS		 200 { "CT-114 series", 4, },
201/* 5*/ { "CP-102 series", 2, MXSER_HIGHBAUD },
1c45607a
JS		 202 { "CP-104U series", 4, },
203 { "CP-168U series", 8, },
204 { "CP-132U series", 2, },
15254902
JS		 205 { "CP-134U series", 4, },
206/*10*/ { "CP-104JU series", 4, },
1c45607a
JS		 207 { "Moxa UC7000 Serial", 8, }, /* RC7000 */
208 { "CP-118U series", 8, },
209 { "CP-102UL series", 2, },
15254902
JS		 210 { "CP-102U series", 2, },
211/*15*/ { "CP-118EL series", 8, },
1c45607a
JS		 212 { "CP-168EL series", 8, },
213 { "CP-104EL series", 4, },
214 { "CB-108 series", 8, },
15254902
JS		 215 { "CB-114 series", 4, },
216/*20*/ { "CB-134I series", 4, },
1c45607a 217 { "CP-138U series", 8, },
80ff8a80 218 { "POS-104UL series", 4, },
e129deff 219 { "CP-114UL series", 4, },
15254902
JS		 220 { "CP-102UF series", 2, },
221/*25*/ { "CP-112UL series", 2, },
1c45607a 222};
1da177e4 223
1c45607a
JS		 224/* driver_data correspond to the lines in the structure above
225 see also ISA probe function before you change something */
3385ecf8 226static const struct pci_device_id mxser_pcibrds[] = {
15254902
JS		 227 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 0 },
228 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 1 },
229 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 2 },
230 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 3 },
231 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 4 },
232 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 5 },
233 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 6 },
234 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 7 },
235 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 8 },
236 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 9 },
237 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 10 },
238 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 11 },
239 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 12 },
240 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 13 },
241 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 14 },
242 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 15 },
243 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 16 },
244 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 17 },
245 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 18 },
246 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 19 },
247 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 20 },
248 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 21 },
249 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 22 },
250 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL), .driver_data = 23 },
251 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP102UF), .driver_data = 24 },
252 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP112UL), .driver_data = 25 },
1c45607a 253 { }
1da177e4 254};
1da177e4
LT		 255MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
256
1da177e4 257static int ttymajor = MXSERMAJOR;
1da177e4
LT		 258
259/* Variables for insmod */
260
261MODULE_AUTHOR("Casper Yang");
262MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
8d3b33f6 263module_param(ttymajor, int, 0);
1da177e4
LT		 264MODULE_LICENSE("GPL");
265
1c45607a
JS		 266struct mxser_board;
267
268struct mxser_port {
0ad9e7d1 269 struct tty_port port;
1c45607a 270 struct mxser_board *board;
1c45607a
JS		 271
272 unsigned long ioaddr;
273 unsigned long opmode_ioaddr;
1da177e4 274
dc33f644
JS		 275 u8 rx_high_water;
276 u8 rx_low_water;
1da177e4 277 int baud_base; /* max. speed */
1da177e4 278 int type; /* UART type */
1c45607a 279
a93963e4
JS		 280 unsigned char x_char; /* xon/xoff character */
281 u8 IER; /* Interrupt Enable Register */
282 u8 MCR; /* Modem control register */
1c45607a
JS		 283
284 unsigned char stop_rx;
285 unsigned char ldisc_stop_rx;
286
287 int custom_divisor;
1c45607a 288
1c45607a 289 struct async_icount icount; /* kernel counters for 4 input interrupts */
104583b5 290 unsigned int timeout;
1c45607a 291
a93963e4
JS		 292 u8 read_status_mask;
293 u8 ignore_status_mask;
dc33f644 294 u8 xmit_fifo_size;
02e43144
JS		 295 unsigned int xmit_head;
296 unsigned int xmit_tail;
297 unsigned int xmit_cnt;
cd7b4b39 298 int closing;
1c45607a 299
606d099c 300 struct ktermios normal_termios;
1c45607a 301
1da177e4 302 spinlock_t slock;
1c45607a
JS		 303};
304
305struct mxser_board {
306 unsigned int idx;
307 int irq;
308 const struct mxser_cardinfo *info;
309 unsigned long vector;
1c45607a 310
e4558366 311 enum mxser_must_hwid must_hwid;
928f9464 312 speed_t max_baud;
1c45607a
JS		 313
314 struct mxser_port ports[MXSER_PORTS_PER_BOARD];
1da177e4
LT		 315};
316
1c45607a 317static struct mxser_board mxser_boards[MXSER_BOARDS];
1da177e4 318static struct tty_driver *mxvar_sdriver;
1da177e4 319
148ff86b
CH		 320static void mxser_enable_must_enchance_mode(unsigned long baseio)
321{
322 u8 oldlcr;
323 u8 efr;
324
325 oldlcr = inb(baseio + UART_LCR);
326 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
327
328 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
329 efr |= MOXA_MUST_EFR_EFRB_ENABLE;
330
331 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
332 outb(oldlcr, baseio + UART_LCR);
333}
334
335static void mxser_disable_must_enchance_mode(unsigned long baseio)
336{
337 u8 oldlcr;
338 u8 efr;
339
340 oldlcr = inb(baseio + UART_LCR);
341 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
342
343 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
344 efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;
345
346 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
347 outb(oldlcr, baseio + UART_LCR);
348}
349
350static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
351{
352 u8 oldlcr;
353 u8 efr;
354
355 oldlcr = inb(baseio + UART_LCR);
356 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
357
358 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
359 efr &= ~MOXA_MUST_EFR_BANK_MASK;
360 efr |= MOXA_MUST_EFR_BANK0;
361
362 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
363 outb(value, baseio + MOXA_MUST_XON1_REGISTER);
364 outb(oldlcr, baseio + UART_LCR);
365}
366
367static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
368{
369 u8 oldlcr;
370 u8 efr;
371
372 oldlcr = inb(baseio + UART_LCR);
373 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
374
375 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
376 efr &= ~MOXA_MUST_EFR_BANK_MASK;
377 efr |= MOXA_MUST_EFR_BANK0;
378
379 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
380 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
381 outb(oldlcr, baseio + UART_LCR);
382}
383
384static void mxser_set_must_fifo_value(struct mxser_port *info)
385{
386 u8 oldlcr;
387 u8 efr;
388
389 oldlcr = inb(info->ioaddr + UART_LCR);
390 outb(MOXA_MUST_ENTER_ENCHANCE, info->ioaddr + UART_LCR);
391
392 efr = inb(info->ioaddr + MOXA_MUST_EFR_REGISTER);
393 efr &= ~MOXA_MUST_EFR_BANK_MASK;
394 efr |= MOXA_MUST_EFR_BANK1;
395
396 outb(efr, info->ioaddr + MOXA_MUST_EFR_REGISTER);
dc33f644
JS		 397 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
398 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
399 outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
148ff86b
CH		 400 outb(oldlcr, info->ioaddr + UART_LCR);
401}
402
403static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
404{
405 u8 oldlcr;
406 u8 efr;
407
408 oldlcr = inb(baseio + UART_LCR);
409 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
410
411 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
412 efr &= ~MOXA_MUST_EFR_BANK_MASK;
413 efr |= MOXA_MUST_EFR_BANK2;
414
415 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
416 outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
417 outb(oldlcr, baseio + UART_LCR);
418}
419
420static void mxser_get_must_hardware_id(unsigned long baseio, u8 *pId)
421{
422 u8 oldlcr;
423 u8 efr;
424
425 oldlcr = inb(baseio + UART_LCR);
426 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
427
428 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
429 efr &= ~MOXA_MUST_EFR_BANK_MASK;
430 efr |= MOXA_MUST_EFR_BANK2;
431
432 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
433 *pId = inb(baseio + MOXA_MUST_HWID_REGISTER);
434 outb(oldlcr, baseio + UART_LCR);
435}
436
437static void SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(unsigned long baseio)
438{
439 u8 oldlcr;
440 u8 efr;
441
442 oldlcr = inb(baseio + UART_LCR);
443 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
444
445 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
446 efr &= ~MOXA_MUST_EFR_SF_MASK;
447
448 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
449 outb(oldlcr, baseio + UART_LCR);
450}
451
452static void mxser_enable_must_tx_software_flow_control(unsigned long baseio)
453{
454 u8 oldlcr;
455 u8 efr;
456
457 oldlcr = inb(baseio + UART_LCR);
458 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
459
460 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
461 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
462 efr |= MOXA_MUST_EFR_SF_TX1;
463
464 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
465 outb(oldlcr, baseio + UART_LCR);
466}
467
468static void mxser_disable_must_tx_software_flow_control(unsigned long baseio)
469{
470 u8 oldlcr;
471 u8 efr;
472
473 oldlcr = inb(baseio + UART_LCR);
474 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
475
476 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
477 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
478
479 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
480 outb(oldlcr, baseio + UART_LCR);
481}
482
483static void mxser_enable_must_rx_software_flow_control(unsigned long baseio)
484{
485 u8 oldlcr;
486 u8 efr;
487
488 oldlcr = inb(baseio + UART_LCR);
489 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
490
491 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
492 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
493 efr |= MOXA_MUST_EFR_SF_RX1;
494
495 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
496 outb(oldlcr, baseio + UART_LCR);
497}
498
499static void mxser_disable_must_rx_software_flow_control(unsigned long baseio)
500{
501 u8 oldlcr;
502 u8 efr;
503
504 oldlcr = inb(baseio + UART_LCR);
505 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
506
507 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
508 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
509
510 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
511 outb(oldlcr, baseio + UART_LCR);
512}
513
e4558366 514static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io)
1da177e4
LT		 515{
516 u8 oldmcr, hwid;
517 int i;
518
519 outb(0, io + UART_LCR);
148ff86b 520 mxser_disable_must_enchance_mode(io);
1da177e4
LT		 521 oldmcr = inb(io + UART_MCR);
522 outb(0, io + UART_MCR);
148ff86b 523 mxser_set_must_xon1_value(io, 0x11);
1da177e4
LT		 524 if ((hwid = inb(io + UART_MCR)) != 0) {
525 outb(oldmcr, io + UART_MCR);
8ea2c2ec 526 return MOXA_OTHER_UART;
1da177e4
LT		 527 }
528
148ff86b 529 mxser_get_must_hardware_id(io, &hwid);
e4558366 530 for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */
1c45607a 531 if (hwid == Gpci_uart_info[i].type)
e4558366
JS		 532 return hwid;
533
1da177e4
LT		 534 return MOXA_OTHER_UART;
535}
536
1c45607a 537static void process_txrx_fifo(struct mxser_port *info)
1da177e4
LT		 538{
539 int i;
540
541 if ((info->type == PORT_16450) || (info->type == PORT_8250)) {
1da177e4
LT		 542 info->rx_high_water = 1;
543 info->rx_low_water = 1;
544 info->xmit_fifo_size = 1;
1c45607a
JS		 545 } else
546 for (i = 0; i < UART_INFO_NUM; i++)
292955a7 547 if (info->board->must_hwid == Gpci_uart_info[i].type) {
1da177e4
LT		 548 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
549 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
dc33f644 550 info->xmit_fifo_size = Gpci_uart_info[i].fifo_size;
1da177e4
LT		 551 break;
552 }
1da177e4
LT		 553}
554
31f35939
AC		 555static int mxser_carrier_raised(struct tty_port *port)
556{
557 struct mxser_port *mp = container_of(port, struct mxser_port, port);
558 return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0;
559}
560
fcc8ac18 561static void mxser_dtr_rts(struct tty_port *port, int on)
5d951fb4
AC		 562{
563 struct mxser_port *mp = container_of(port, struct mxser_port, port);
564 unsigned long flags;
565
566 spin_lock_irqsave(&mp->slock, flags);
fcc8ac18
AC		 567 if (on)
568 outb(inb(mp->ioaddr + UART_MCR) |
569 UART_MCR_DTR | UART_MCR_RTS, mp->ioaddr + UART_MCR);
570 else
571 outb(inb(mp->ioaddr + UART_MCR)&~(UART_MCR_DTR | UART_MCR_RTS),
572 mp->ioaddr + UART_MCR);
5d951fb4
AC		 573 spin_unlock_irqrestore(&mp->slock, flags);
574}
575
dc33f644 576static int mxser_set_baud(struct tty_struct *tty, speed_t newspd)
1da177e4 577{
216ba023 578 struct mxser_port *info = tty->driver_data;
104583b5 579 unsigned int quot = 0, baud;
1c45607a 580 unsigned char cval;
104583b5 581 u64 timeout;
1da177e4 582
216ba023 583 if (!info->ioaddr)
1c45607a 584 return -1;
1da177e4 585
928f9464 586 if (newspd > info->board->max_baud)
1c45607a 587 return -1;
1da177e4 588
1c45607a
JS		 589 if (newspd == 134) {
590 quot = 2 * info->baud_base / 269;
216ba023 591 tty_encode_baud_rate(tty, 134, 134);
1c45607a
JS		 592 } else if (newspd) {
593 quot = info->baud_base / newspd;
594 if (quot == 0)
595 quot = 1;
596 baud = info->baud_base/quot;
216ba023 597 tty_encode_baud_rate(tty, baud, baud);
1c45607a
JS		 598 } else {
599 quot = 0;
600 }
1da177e4 601
104583b5
JS		 602 /*
603 * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the
604 * u64 domain
605 */
606 timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot;
607 do_div(timeout, info->baud_base);
608 info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */
1da177e4 609
1c45607a
JS		 610 if (quot) {
611 info->MCR |= UART_MCR_DTR;
612 outb(info->MCR, info->ioaddr + UART_MCR);
613 } else {
614 info->MCR &= ~UART_MCR_DTR;
615 outb(info->MCR, info->ioaddr + UART_MCR);
616 return 0;
617 }
1da177e4 618
1c45607a 619 cval = inb(info->ioaddr + UART_LCR);
1da177e4 620
1c45607a 621 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
1da177e4 622
1c45607a
JS		 623 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
624 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
625 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
1da177e4 626
1c45607a 627#ifdef BOTHER
216ba023 628 if (C_BAUD(tty) == BOTHER) {
1c45607a
JS		 629 quot = info->baud_base % newspd;
630 quot *= 8;
631 if (quot % newspd > newspd / 2) {
632 quot /= newspd;
633 quot++;
634 } else
635 quot /= newspd;
636
148ff86b 637 mxser_set_must_enum_value(info->ioaddr, quot);
1c45607a
JS		 638 } else
639#endif
148ff86b 640 mxser_set_must_enum_value(info->ioaddr, 0);
1da177e4 641
8ea2c2ec 642 return 0;
1da177e4 643}
1da177e4 644
1c45607a
JS		 645/*
646 * This routine is called to set the UART divisor registers to match
647 * the specified baud rate for a serial port.
648 */
beca62c4 649static void mxser_change_speed(struct tty_struct *tty)
1da177e4 650{
216ba023 651 struct mxser_port *info = tty->driver_data;
1c45607a 652 unsigned cflag, cval, fcr;
1c45607a 653 unsigned char status;
1da177e4 654
adc8d746 655 cflag = tty->termios.c_cflag;
216ba023 656 if (!info->ioaddr)
beca62c4 657 return;
1da177e4 658
ef3dff8a 659 mxser_set_baud(tty, tty_get_baud_rate(tty));
1da177e4 660
1c45607a
JS		 661 /* byte size and parity */
662 switch (cflag & CSIZE) {
663 case CS5:
664 cval = 0x00;
665 break;
666 case CS6:
667 cval = 0x01;
668 break;
669 case CS7:
670 cval = 0x02;
671 break;
672 case CS8:
673 cval = 0x03;
674 break;
675 default:
676 cval = 0x00;
677 break; /* too keep GCC shut... */
678 }
679 if (cflag & CSTOPB)
680 cval |= 0x04;
681 if (cflag & PARENB)
682 cval |= UART_LCR_PARITY;
683 if (!(cflag & PARODD))
684 cval |= UART_LCR_EPAR;
685 if (cflag & CMSPAR)
686 cval |= UART_LCR_SPAR;
1da177e4 687
1c45607a 688 if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
292955a7 689 if (info->board->must_hwid) {
1c45607a
JS		 690 fcr = UART_FCR_ENABLE_FIFO;
691 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
148ff86b 692 mxser_set_must_fifo_value(info);
1c45607a
JS		 693 } else
694 fcr = 0;
695 } else {
696 fcr = UART_FCR_ENABLE_FIFO;
292955a7 697 if (info->board->must_hwid) {
1c45607a 698 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
148ff86b 699 mxser_set_must_fifo_value(info);
1c45607a 700 } else {
dc33f644 701 switch (info->rx_high_water) {
1c45607a
JS		 702 case 1:
703 fcr |= UART_FCR_TRIGGER_1;
704 break;
705 case 4:
706 fcr |= UART_FCR_TRIGGER_4;
707 break;
708 case 8:
709 fcr |= UART_FCR_TRIGGER_8;
710 break;
711 default:
712 fcr |= UART_FCR_TRIGGER_14;
713 break;
714 }
1da177e4 715 }
1da177e4
LT		 716 }
717
1c45607a
JS		 718 /* CTS flow control flag and modem status interrupts */
719 info->IER &= ~UART_IER_MSI;
720 info->MCR &= ~UART_MCR_AFE;
5604a98e 721 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
1c45607a 722 if (cflag & CRTSCTS) {
1c45607a 723 info->IER |= UART_IER_MSI;
292955a7 724 if ((info->type == PORT_16550A) || (info->board->must_hwid)) {
1c45607a
JS		 725 info->MCR |= UART_MCR_AFE;
726 } else {
727 status = inb(info->ioaddr + UART_MSR);
216ba023 728 if (tty->hw_stopped) {
1c45607a 729 if (status & UART_MSR_CTS) {
216ba023 730 tty->hw_stopped = 0;
1c45607a 731 if (info->type != PORT_16550A &&
292955a7 732 !info->board->must_hwid) {
1c45607a
JS		 733 outb(info->IER & ~UART_IER_THRI,
734 info->ioaddr +
735 UART_IER);
736 info->IER |= UART_IER_THRI;
737 outb(info->IER, info->ioaddr +
738 UART_IER);
739 }
216ba023 740 tty_wakeup(tty);
1c45607a
JS		 741 }
742 } else {
743 if (!(status & UART_MSR_CTS)) {
216ba023 744 tty->hw_stopped = 1;
1c45607a 745 if ((info->type != PORT_16550A) &&
292955a7 746 (!info->board->must_hwid)) {
1c45607a
JS		 747 info->IER &= ~UART_IER_THRI;
748 outb(info->IER, info->ioaddr +
749 UART_IER);
750 }
751 }
752 }
1da177e4 753 }
1c45607a
JS		 754 }
755 outb(info->MCR, info->ioaddr + UART_MCR);
2d68655d
PH		 756 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
757 if (~cflag & CLOCAL)
1c45607a 758 info->IER |= UART_IER_MSI;
1c45607a
JS		 759 outb(info->IER, info->ioaddr + UART_IER);
760
761 /*
762 * Set up parity check flag
763 */
764 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
216ba023 765 if (I_INPCK(tty))
1c45607a 766 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
216ba023 767 if (I_BRKINT(tty) || I_PARMRK(tty))
1c45607a 768 info->read_status_mask |= UART_LSR_BI;
1da177e4 769
1c45607a 770 info->ignore_status_mask = 0;
1da177e4 771
216ba023 772 if (I_IGNBRK(tty)) {
1c45607a
JS		 773 info->ignore_status_mask |= UART_LSR_BI;
774 info->read_status_mask |= UART_LSR_BI;
8ea2c2ec 775 /*
1c45607a
JS		 776 * If we're ignore parity and break indicators, ignore
777 * overruns too. (For real raw support).
8ea2c2ec 778 */
216ba023 779 if (I_IGNPAR(tty)) {
1c45607a
JS		 780 info->ignore_status_mask |=
781 UART_LSR_OE |
782 UART_LSR_PE |
783 UART_LSR_FE;
784 info->read_status_mask |=
785 UART_LSR_OE |
786 UART_LSR_PE |
787 UART_LSR_FE;
788 }
1da177e4 789 }
292955a7 790 if (info->board->must_hwid) {
216ba023
AC		 791 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty));
792 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty));
793 if (I_IXON(tty)) {
148ff86b
CH		 794 mxser_enable_must_rx_software_flow_control(
795 info->ioaddr);
1c45607a 796 } else {
148ff86b
CH		 797 mxser_disable_must_rx_software_flow_control(
798 info->ioaddr);
1da177e4 799 }
216ba023 800 if (I_IXOFF(tty)) {
148ff86b
CH		 801 mxser_enable_must_tx_software_flow_control(
802 info->ioaddr);
1c45607a 803 } else {
148ff86b
CH		 804 mxser_disable_must_tx_software_flow_control(
805 info->ioaddr);
1da177e4
LT		 806 }
807 }
1da177e4 808
1da177e4 809
1c45607a
JS		 810 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */
811 outb(cval, info->ioaddr + UART_LCR);
1da177e4
LT		 812}
813
216ba023
AC		 814static void mxser_check_modem_status(struct tty_struct *tty,
815 struct mxser_port *port, int status)
1da177e4 816{
1c45607a
JS		 817 /* update input line counters */
818 if (status & UART_MSR_TERI)
819 port->icount.rng++;
820 if (status & UART_MSR_DDSR)
821 port->icount.dsr++;
822 if (status & UART_MSR_DDCD)
823 port->icount.dcd++;
824 if (status & UART_MSR_DCTS)
825 port->icount.cts++;
bdc04e31 826 wake_up_interruptible(&port->port.delta_msr_wait);
1da177e4 827
2d68655d 828 if (tty_port_check_carrier(&port->port) && (status & UART_MSR_DDCD)) {
1c45607a 829 if (status & UART_MSR_DCD)
0ad9e7d1 830 wake_up_interruptible(&port->port.open_wait);
1c45607a 831 }
1da177e4 832
f21ec3d2 833 if (tty_port_cts_enabled(&port->port)) {
216ba023 834 if (tty->hw_stopped) {
1c45607a 835 if (status & UART_MSR_CTS) {
216ba023 836 tty->hw_stopped = 0;
1c45607a
JS		 837
838 if ((port->type != PORT_16550A) &&
292955a7 839 (!port->board->must_hwid)) {
1c45607a
JS		 840 outb(port->IER & ~UART_IER_THRI,
841 port->ioaddr + UART_IER);
842 port->IER |= UART_IER_THRI;
843 outb(port->IER, port->ioaddr +
844 UART_IER);
845 }
216ba023 846 tty_wakeup(tty);
1c45607a
JS		 847 }
848 } else {
849 if (!(status & UART_MSR_CTS)) {
216ba023 850 tty->hw_stopped = 1;
1c45607a 851 if (port->type != PORT_16550A &&
292955a7 852 !port->board->must_hwid) {
1c45607a
JS		 853 port->IER &= ~UART_IER_THRI;
854 outb(port->IER, port->ioaddr +
855 UART_IER);
856 }
857 }
858 }
1da177e4
LT		 859 }
860}
861
6769140d 862static int mxser_activate(struct tty_port *port, struct tty_struct *tty)
1da177e4 863{
6769140d 864 struct mxser_port *info = container_of(port, struct mxser_port, port);
1c45607a
JS		 865 unsigned long page;
866 unsigned long flags;
1da177e4 867
1c45607a
JS		 868 page = __get_free_page(GFP_KERNEL);
869 if (!page)
870 return -ENOMEM;
1da177e4 871
1c45607a 872 spin_lock_irqsave(&info->slock, flags);
1da177e4 873
1c45607a 874 if (!info->ioaddr || !info->type) {
216ba023 875 set_bit(TTY_IO_ERROR, &tty->flags);
1c45607a
JS		 876 free_page(page);
877 spin_unlock_irqrestore(&info->slock, flags);
1da177e4 878 return 0;
1c45607a 879 }
6769140d 880 info->port.xmit_buf = (unsigned char *) page;
1da177e4 881
1da177e4 882 /*
1c45607a
JS		 883 * Clear the FIFO buffers and disable them
884 * (they will be reenabled in mxser_change_speed())
1da177e4 885 */
292955a7 886 if (info->board->must_hwid)
1c45607a
JS		 887 outb((UART_FCR_CLEAR_RCVR |
888 UART_FCR_CLEAR_XMIT |
889 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR);
890 else
891 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
892 info->ioaddr + UART_FCR);
1da177e4 893
1c45607a
JS		 894 /*
895 * At this point there's no way the LSR could still be 0xFF;
896 * if it is, then bail out, because there's likely no UART
897 * here.
898 */
899 if (inb(info->ioaddr + UART_LSR) == 0xff) {
900 spin_unlock_irqrestore(&info->slock, flags);
901 if (capable(CAP_SYS_ADMIN)) {
f43a510d 902 set_bit(TTY_IO_ERROR, &tty->flags);
1c45607a
JS		 903 return 0;
904 } else
905 return -ENODEV;
906 }
1da177e4 907
1c45607a
JS		 908 /*
909 * Clear the interrupt registers.
910 */
911 (void) inb(info->ioaddr + UART_LSR);
912 (void) inb(info->ioaddr + UART_RX);
913 (void) inb(info->ioaddr + UART_IIR);
914 (void) inb(info->ioaddr + UART_MSR);
915
916 /*
917 * Now, initialize the UART
918 */
919 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
920 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
921 outb(info->MCR, info->ioaddr + UART_MCR);
922
923 /*
924 * Finally, enable interrupts
925 */
926 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
927
292955a7 928 if (info->board->must_hwid)
1c45607a
JS		 929 info->IER |= MOXA_MUST_IER_EGDAI;
930 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
931
932 /*
933 * And clear the interrupt registers again for luck.
934 */
935 (void) inb(info->ioaddr + UART_LSR);
936 (void) inb(info->ioaddr + UART_RX);
937 (void) inb(info->ioaddr + UART_IIR);
938 (void) inb(info->ioaddr + UART_MSR);
939
216ba023 940 clear_bit(TTY_IO_ERROR, &tty->flags);
1c45607a
JS		 941 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
942
943 /*
944 * and set the speed of the serial port
945 */
2799707f 946 mxser_change_speed(tty);
1c45607a
JS		 947 spin_unlock_irqrestore(&info->slock, flags);
948
949 return 0;
950}
951
952/*
6769140d 953 * This routine will shutdown a serial port
1c45607a 954 */
6769140d 955static void mxser_shutdown_port(struct tty_port *port)
1c45607a 956{
6769140d 957 struct mxser_port *info = container_of(port, struct mxser_port, port);
1c45607a
JS		 958 unsigned long flags;
959
1c45607a
JS		 960 spin_lock_irqsave(&info->slock, flags);
961
962 /*
963 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
964 * here so the queue might never be waken up
965 */
bdc04e31 966 wake_up_interruptible(&info->port.delta_msr_wait);
1c45607a
JS		 967
968 /*
6769140d 969 * Free the xmit buffer, if necessary
1c45607a 970 */
0ad9e7d1
AC		 971 if (info->port.xmit_buf) {
972 free_page((unsigned long) info->port.xmit_buf);
973 info->port.xmit_buf = NULL;
1da177e4
LT		 974 }
975
1c45607a
JS		 976 info->IER = 0;
977 outb(0x00, info->ioaddr + UART_IER);
978
1c45607a 979 /* clear Rx/Tx FIFO's */
292955a7 980 if (info->board->must_hwid)
1c45607a
JS		 981 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |
982 MOXA_MUST_FCR_GDA_MODE_ENABLE,
983 info->ioaddr + UART_FCR);
984 else
985 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
986 info->ioaddr + UART_FCR);
987
988 /* read data port to reset things */
989 (void) inb(info->ioaddr + UART_RX);
990
1c45607a 991
292955a7 992 if (info->board->must_hwid)
1c45607a
JS		 993 SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr);
994
995 spin_unlock_irqrestore(&info->slock, flags);
996}
997
998/*
999 * This routine is called whenever a serial port is opened. It
1000 * enables interrupts for a serial port, linking in its async structure into
1001 * the IRQ chain. It also performs the serial-specific
1002 * initialization for the tty structure.
1003 */
1004static int mxser_open(struct tty_struct *tty, struct file *filp)
1005{
1006 struct mxser_port *info;
6769140d 1007 int line;
1c45607a
JS		 1008
1009 line = tty->index;
1010 if (line == MXSER_PORTS)
1011 return 0;
1c45607a
JS		 1012 info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD];
1013 if (!info->ioaddr)
1014 return -ENODEV;
1015
a2d1e351 1016 tty->driver_data = info;
6769140d 1017 return tty_port_open(&info->port, tty, filp);
1da177e4
LT		 1018}
1019
978e595f
AC		 1020static void mxser_flush_buffer(struct tty_struct *tty)
1021{
1022 struct mxser_port *info = tty->driver_data;
1023 char fcr;
1024 unsigned long flags;
1025
1026
1027 spin_lock_irqsave(&info->slock, flags);
1028 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1029
1030 fcr = inb(info->ioaddr + UART_FCR);
1031 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
1032 info->ioaddr + UART_FCR);
1033 outb(fcr, info->ioaddr + UART_FCR);
1034
1035 spin_unlock_irqrestore(&info->slock, flags);
1036
1037 tty_wakeup(tty);
1038}
1039
1040
6769140d 1041static void mxser_close_port(struct tty_port *port)
1da177e4 1042{
1e2b0254 1043 struct mxser_port *info = container_of(port, struct mxser_port, port);
1da177e4 1044 unsigned long timeout;
1da177e4
LT		 1045 /*
1046 * At this point we stop accepting input. To do this, we
1047 * disable the receive line status interrupts, and tell the
1048 * interrupt driver to stop checking the data ready bit in the
1049 * line status register.
1050 */
1051 info->IER &= ~UART_IER_RLSI;
292955a7 1052 if (info->board->must_hwid)
1da177e4 1053 info->IER &= ~MOXA_MUST_RECV_ISR;
1c45607a 1054
6769140d
AC		 1055 outb(info->IER, info->ioaddr + UART_IER);
1056 /*
1057 * Before we drop DTR, make sure the UART transmitter
1058 * has completely drained; this is especially
1059 * important if there is a transmit FIFO!
1060 */
1061 timeout = jiffies + HZ;
1062 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) {
1063 schedule_timeout_interruptible(5);
1064 if (time_after(jiffies, timeout))
1065 break;
1da177e4 1066 }
1e2b0254
AC		 1067}
1068
1069/*
1070 * This routine is called when the serial port gets closed. First, we
1071 * wait for the last remaining data to be sent. Then, we unlink its
1072 * async structure from the interrupt chain if necessary, and we free
1073 * that IRQ if nothing is left in the chain.
1074 */
1075static void mxser_close(struct tty_struct *tty, struct file *filp)
1076{
1077 struct mxser_port *info = tty->driver_data;
1078 struct tty_port *port = &info->port;
1079
a2d1e351 1080 if (tty->index == MXSER_PORTS || info == NULL)
1e2b0254
AC		 1081 return;
1082 if (tty_port_close_start(port, tty, filp) == 0)
1083 return;
cd7b4b39 1084 info->closing = 1;
6769140d
AC		 1085 mutex_lock(&port->mutex);
1086 mxser_close_port(port);
1e2b0254 1087 mxser_flush_buffer(tty);
d41861ca
PH		 1088 if (tty_port_initialized(port) && C_HUPCL(tty))
1089 tty_port_lower_dtr_rts(port);
6769140d 1090 mxser_shutdown_port(port);
d41861ca 1091 tty_port_set_initialized(port, 0);
6769140d 1092 mutex_unlock(&port->mutex);
cd7b4b39 1093 info->closing = 0;
a6614999
AC		 1094 /* Right now the tty_port set is done outside of the close_end helper
1095 as we don't yet have everyone using refcounts */
1096 tty_port_close_end(port, tty);
1097 tty_port_tty_set(port, NULL);
1da177e4
LT		 1098}
1099
1100static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
1101{
1102 int c, total = 0;
1c45607a 1103 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1104 unsigned long flags;
1105
0ad9e7d1 1106 if (!info->port.xmit_buf)
8ea2c2ec 1107 return 0;
1da177e4
LT		 1108
1109 while (1) {
8ea2c2ec
JJ		 1110 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
1111 SERIAL_XMIT_SIZE - info->xmit_head));
1da177e4
LT		 1112 if (c <= 0)
1113 break;
1114
0ad9e7d1 1115 memcpy(info->port.xmit_buf + info->xmit_head, buf, c);
1da177e4 1116 spin_lock_irqsave(&info->slock, flags);
8ea2c2ec
JJ		 1117 info->xmit_head = (info->xmit_head + c) &
1118 (SERIAL_XMIT_SIZE - 1);
1da177e4
LT		 1119 info->xmit_cnt += c;
1120 spin_unlock_irqrestore(&info->slock, flags);
1121
1122 buf += c;
1123 count -= c;
1124 total += c;
1da177e4
LT		 1125 }
1126
6e94dbc7 1127 if (info->xmit_cnt && !tty->flow.stopped) {
8ea2c2ec
JJ		 1128 if (!tty->hw_stopped ||
1129 (info->type == PORT_16550A) ||
292955a7 1130 (info->board->must_hwid)) {
1da177e4 1131 spin_lock_irqsave(&info->slock, flags);
1c45607a
JS		 1132 outb(info->IER & ~UART_IER_THRI, info->ioaddr +
1133 UART_IER);
1da177e4 1134 info->IER |= UART_IER_THRI;
1c45607a 1135 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1136 spin_unlock_irqrestore(&info->slock, flags);
1137 }
1138 }
1139 return total;
1140}
1141
0be2eade 1142static int mxser_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 1143{
1c45607a 1144 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1145 unsigned long flags;
1146
0ad9e7d1 1147 if (!info->port.xmit_buf)
0be2eade 1148 return 0;
1da177e4
LT		 1149
1150 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1)
0be2eade 1151 return 0;
1da177e4
LT		 1152
1153 spin_lock_irqsave(&info->slock, flags);
0ad9e7d1 1154 info->port.xmit_buf[info->xmit_head++] = ch;
1da177e4
LT		 1155 info->xmit_head &= SERIAL_XMIT_SIZE - 1;
1156 info->xmit_cnt++;
1157 spin_unlock_irqrestore(&info->slock, flags);
6e94dbc7 1158 if (!tty->flow.stopped) {
8ea2c2ec
JJ		 1159 if (!tty->hw_stopped ||
1160 (info->type == PORT_16550A) ||
292955a7 1161 info->board->must_hwid) {
1da177e4 1162 spin_lock_irqsave(&info->slock, flags);
1c45607a 1163 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1164 info->IER |= UART_IER_THRI;
1c45607a 1165 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1166 spin_unlock_irqrestore(&info->slock, flags);
1167 }
1168 }
0be2eade 1169 return 1;
1da177e4
LT		 1170}
1171
1172
1173static void mxser_flush_chars(struct tty_struct *tty)
1174{
1c45607a 1175 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1176 unsigned long flags;
1177
6e94dbc7 1178 if (info->xmit_cnt <= 0 || tty->flow.stopped || !info->port.xmit_buf ||
ace7dd96 1179 (tty->hw_stopped && info->type != PORT_16550A &&
292955a7 1180 !info->board->must_hwid))
1da177e4
LT		 1181 return;
1182
1183 spin_lock_irqsave(&info->slock, flags);
1184
1c45607a 1185 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1186 info->IER |= UART_IER_THRI;
1c45607a 1187 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1188
1189 spin_unlock_irqrestore(&info->slock, flags);
1190}
1191
03b3b1a2 1192static unsigned int mxser_write_room(struct tty_struct *tty)
1da177e4 1193{
1c45607a 1194 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1195 int ret;
1196
1197 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
ace7dd96 1198 return ret < 0 ? 0 : ret;
1da177e4
LT		 1199}
1200
fff4ef17 1201static unsigned int mxser_chars_in_buffer(struct tty_struct *tty)
1da177e4 1202{
1c45607a 1203 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1204 return info->xmit_cnt;
1205}
1206
1c45607a
JS		 1207/*
1208 * ------------------------------------------------------------
1209 * friends of mxser_ioctl()
1210 * ------------------------------------------------------------
1211 */
216ba023 1212static int mxser_get_serial_info(struct tty_struct *tty,
6da5b587 1213 struct serial_struct *ss)
1c45607a 1214{
216ba023 1215 struct mxser_port *info = tty->driver_data;
6da5b587 1216 struct tty_port *port = &info->port;
be6cf583 1217 unsigned int closing_wait, close_delay;
6da5b587
AV		 1218
1219 if (tty->index == MXSER_PORTS)
1220 return -ENOTTY;
1221
1222 mutex_lock(&port->mutex);
be6cf583
JH		 1223
1224 close_delay = jiffies_to_msecs(info->port.close_delay) / 10;
1225 closing_wait = info->port.closing_wait;
1226 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
1227 closing_wait = jiffies_to_msecs(closing_wait) / 10;
1228
6da5b587
AV		 1229 ss->type = info->type,
1230 ss->line = tty->index,
1231 ss->port = info->ioaddr,
1232 ss->irq = info->board->irq,
1233 ss->flags = info->port.flags,
1234 ss->baud_base = info->baud_base,
be6cf583
JH		 1235 ss->close_delay = close_delay;
1236 ss->closing_wait = closing_wait;
6da5b587
AV		 1237 ss->custom_divisor = info->custom_divisor,
1238 mutex_unlock(&port->mutex);
1c45607a
JS		 1239 return 0;
1240}
1241
216ba023 1242static int mxser_set_serial_info(struct tty_struct *tty,
6da5b587 1243 struct serial_struct *ss)
1da177e4 1244{
216ba023 1245 struct mxser_port *info = tty->driver_data;
07f86c03 1246 struct tty_port *port = &info->port;
80ff8a80 1247 speed_t baud;
1c45607a 1248 unsigned long sl_flags;
be6cf583 1249 unsigned int flags, close_delay, closing_wait;
1c45607a 1250 int retval = 0;
1da177e4 1251
6da5b587
AV		 1252 if (tty->index == MXSER_PORTS)
1253 return -ENOTTY;
1254 if (tty_io_error(tty))
1255 return -EIO;
1256
1257 mutex_lock(&port->mutex);
1258 if (!info->ioaddr) {
1259 mutex_unlock(&port->mutex);
80ff8a80 1260 return -ENODEV;
6da5b587 1261 }
1da177e4 1262
6da5b587
AV		 1263 if (ss->irq != info->board->irq ||
1264 ss->port != info->ioaddr) {
1265 mutex_unlock(&port->mutex);
80ff8a80 1266 return -EINVAL;
6da5b587 1267 }
1da177e4 1268
07f86c03 1269 flags = port->flags & ASYNC_SPD_MASK;
1da177e4 1270
be6cf583
JH		 1271 close_delay = msecs_to_jiffies(ss->close_delay * 10);
1272 closing_wait = ss->closing_wait;
1273 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
1274 closing_wait = msecs_to_jiffies(closing_wait * 10);
1275
1c45607a 1276 if (!capable(CAP_SYS_ADMIN)) {
6da5b587 1277 if ((ss->baud_base != info->baud_base) ||
be6cf583 1278 (close_delay != info->port.close_delay) ||
b91cfb25 1279 (closing_wait != info->port.closing_wait) ||
6da5b587
AV		 1280 ((ss->flags & ~ASYNC_USR_MASK) != (info->port.flags & ~ASYNC_USR_MASK))) {
1281 mutex_unlock(&port->mutex);
1c45607a 1282 return -EPERM;
6da5b587 1283 }
0ad9e7d1 1284 info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) |
6da5b587 1285 (ss->flags & ASYNC_USR_MASK));
1c45607a 1286 } else {
1da177e4 1287 /*
1c45607a
JS		 1288 * OK, past this point, all the error checking has been done.
1289 * At this point, we start making changes.....
1da177e4 1290 */
07f86c03 1291 port->flags = ((port->flags & ~ASYNC_FLAGS) |
6da5b587 1292 (ss->flags & ASYNC_FLAGS));
be6cf583
JH		 1293 port->close_delay = close_delay;
1294 port->closing_wait = closing_wait;
07f86c03 1295 if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
6da5b587
AV		 1296 (ss->baud_base != info->baud_base ||
1297 ss->custom_divisor !=
80ff8a80 1298 info->custom_divisor)) {
6da5b587
AV		 1299 if (ss->custom_divisor == 0) {
1300 mutex_unlock(&port->mutex);
07f86c03 1301 return -EINVAL;
6da5b587
AV		 1302 }
1303 baud = ss->baud_base / ss->custom_divisor;
216ba023 1304 tty_encode_baud_rate(tty, baud, baud);
80ff8a80 1305 }
fc83815c 1306
b91cfb25 1307 info->type = ss->type;
1da177e4 1308
b91cfb25
JH		 1309 process_txrx_fifo(info);
1310 }
1c45607a 1311
d41861ca 1312 if (tty_port_initialized(port)) {
07f86c03 1313 if (flags != (port->flags & ASYNC_SPD_MASK)) {
1c45607a 1314 spin_lock_irqsave(&info->slock, sl_flags);
2799707f 1315 mxser_change_speed(tty);
1c45607a 1316 spin_unlock_irqrestore(&info->slock, sl_flags);
1da177e4 1317 }
6769140d 1318 } else {
07f86c03 1319 retval = mxser_activate(port, tty);
6769140d 1320 if (retval == 0)
d41861ca 1321 tty_port_set_initialized(port, 1);
6769140d 1322 }
6da5b587 1323 mutex_unlock(&port->mutex);
1c45607a
JS		 1324 return retval;
1325}
1da177e4 1326
1c45607a
JS		 1327/*
1328 * mxser_get_lsr_info - get line status register info
1329 *
1330 * Purpose: Let user call ioctl() to get info when the UART physically
1331 * is emptied. On bus types like RS485, the transmitter must
1332 * release the bus after transmitting. This must be done when
1333 * the transmit shift register is empty, not be done when the
1334 * transmit holding register is empty. This functionality
1335 * allows an RS485 driver to be written in user space.
1336 */
1337static int mxser_get_lsr_info(struct mxser_port *info,
1338 unsigned int __user *value)
1339{
1340 unsigned char status;
1341 unsigned int result;
1342 unsigned long flags;
1da177e4 1343
1c45607a
JS		 1344 spin_lock_irqsave(&info->slock, flags);
1345 status = inb(info->ioaddr + UART_LSR);
1346 spin_unlock_irqrestore(&info->slock, flags);
1347 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1348 return put_user(result, value);
1349}
1da177e4 1350
60b33c13 1351static int mxser_tiocmget(struct tty_struct *tty)
1c45607a
JS		 1352{
1353 struct mxser_port *info = tty->driver_data;
1354 unsigned char control, status;
1355 unsigned long flags;
1da177e4 1356
8ea2c2ec 1357
1c45607a
JS		 1358 if (tty->index == MXSER_PORTS)
1359 return -ENOIOCTLCMD;
18900ca6 1360 if (tty_io_error(tty))
1c45607a 1361 return -EIO;
1da177e4 1362
1c45607a 1363 control = info->MCR;
1da177e4 1364
1c45607a
JS		 1365 spin_lock_irqsave(&info->slock, flags);
1366 status = inb(info->ioaddr + UART_MSR);
1367 if (status & UART_MSR_ANY_DELTA)
216ba023 1368 mxser_check_modem_status(tty, info, status);
1c45607a
JS		 1369 spin_unlock_irqrestore(&info->slock, flags);
1370 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1371 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1372 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1373 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
1374 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1375 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1376}
1da177e4 1377
20b9d177 1378static int mxser_tiocmset(struct tty_struct *tty,
1c45607a
JS		 1379 unsigned int set, unsigned int clear)
1380{
1381 struct mxser_port *info = tty->driver_data;
1382 unsigned long flags;
1da177e4 1383
1da177e4 1384
1c45607a
JS		 1385 if (tty->index == MXSER_PORTS)
1386 return -ENOIOCTLCMD;
18900ca6 1387 if (tty_io_error(tty))
1c45607a 1388 return -EIO;
1da177e4 1389
1c45607a 1390 spin_lock_irqsave(&info->slock, flags);
1da177e4 1391
1c45607a
JS		 1392 if (set & TIOCM_RTS)
1393 info->MCR |= UART_MCR_RTS;
1394 if (set & TIOCM_DTR)
1395 info->MCR |= UART_MCR_DTR;
1da177e4 1396
1c45607a
JS		 1397 if (clear & TIOCM_RTS)
1398 info->MCR &= ~UART_MCR_RTS;
1399 if (clear & TIOCM_DTR)
1400 info->MCR &= ~UART_MCR_DTR;
8ea2c2ec 1401
1c45607a
JS		 1402 outb(info->MCR, info->ioaddr + UART_MCR);
1403 spin_unlock_irqrestore(&info->slock, flags);
1404 return 0;
1405}
1da177e4 1406
1c45607a
JS		 1407static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1408 struct async_icount *cprev)
1da177e4 1409{
1c45607a
JS		 1410 struct async_icount cnow;
1411 unsigned long flags;
1412 int ret;
1da177e4 1413
1c45607a
JS		 1414 spin_lock_irqsave(&info->slock, flags);
1415 cnow = info->icount; /* atomic copy */
1416 spin_unlock_irqrestore(&info->slock, flags);
1da177e4 1417
1c45607a
JS		 1418 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1419 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1420 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
1421 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1da177e4 1422
1c45607a
JS		 1423 *cprev = cnow;
1424
1425 return ret;
1426}
1427
6caa76b7 1428static int mxser_ioctl(struct tty_struct *tty,
1c45607a 1429 unsigned int cmd, unsigned long arg)
1da177e4 1430{
1c45607a
JS		 1431 struct mxser_port *info = tty->driver_data;
1432 struct async_icount cnow;
1c45607a
JS		 1433 unsigned long flags;
1434 void __user *argp = (void __user *)arg;
1da177e4 1435
1c45607a 1436 if (tty->index == MXSER_PORTS)
c94deae5 1437 return -ENOTTY;
1da177e4 1438
1c45607a
JS		 1439 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) {
1440 int p;
1441 unsigned long opmode;
1442 static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f };
1443 int shiftbit;
1444 unsigned char val, mask;
1da177e4 1445
292955a7 1446 if (info->board->must_hwid != MOXA_MUST_MU860_HWID)
e037f95f
MK		 1447 return -EFAULT;
1448
1c45607a
JS		 1449 p = tty->index % 4;
1450 if (cmd == MOXA_SET_OP_MODE) {
1451 if (get_user(opmode, (int __user *) argp))
1452 return -EFAULT;
1453 if (opmode != RS232_MODE &&
1454 opmode != RS485_2WIRE_MODE &&
1455 opmode != RS422_MODE &&
1456 opmode != RS485_4WIRE_MODE)
1457 return -EFAULT;
1458 mask = ModeMask[p];
1459 shiftbit = p * 2;
07f86c03 1460 spin_lock_irq(&info->slock);
1c45607a
JS		 1461 val = inb(info->opmode_ioaddr);
1462 val &= mask;
1463 val |= (opmode << shiftbit);
1464 outb(val, info->opmode_ioaddr);
07f86c03 1465 spin_unlock_irq(&info->slock);
1c45607a
JS		 1466 } else {
1467 shiftbit = p * 2;
07f86c03 1468 spin_lock_irq(&info->slock);
1c45607a 1469 opmode = inb(info->opmode_ioaddr) >> shiftbit;
07f86c03 1470 spin_unlock_irq(&info->slock);
1c45607a
JS		 1471 opmode &= OP_MODE_MASK;
1472 if (put_user(opmode, (int __user *)argp))
1473 return -EFAULT;
1474 }
1475 return 0;
1476 }
1477
6da5b587 1478 if (cmd != TIOCMIWAIT && tty_io_error(tty))
1c45607a
JS		 1479 return -EIO;
1480
1481 switch (cmd) {
1c45607a 1482 case TIOCSERGETLSR: /* Get line status register */
9d6d162d 1483 return mxser_get_lsr_info(info, argp);
1c45607a
JS		 1484 /*
1485 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1486 * - mask passed in arg for lines of interest
1487 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1488 * Caller should use TIOCGICOUNT to see which one it was
1489 */
1490 case TIOCMIWAIT:
1491 spin_lock_irqsave(&info->slock, flags);
1492 cnow = info->icount; /* note the counters on entry */
1493 spin_unlock_irqrestore(&info->slock, flags);
1494
bdc04e31 1495 return wait_event_interruptible(info->port.delta_msr_wait,
1c45607a 1496 mxser_cflags_changed(info, arg, &cnow));
1c45607a
JS		 1497 default:
1498 return -ENOIOCTLCMD;
1499 }
1500 return 0;
1501}
1502
0587102c
AC		 1503 /*
1504 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1505 * Return: write counters to the user passed counter struct
1506 * NB: both 1->0 and 0->1 transitions are counted except for
1507 * RI where only 0->1 is counted.
1508 */
1509
1510static int mxser_get_icount(struct tty_struct *tty,
1511 struct serial_icounter_struct *icount)
1512
1513{
1514 struct mxser_port *info = tty->driver_data;
1515 struct async_icount cnow;
1516 unsigned long flags;
1517
1518 spin_lock_irqsave(&info->slock, flags);
1519 cnow = info->icount;
1520 spin_unlock_irqrestore(&info->slock, flags);
1521
1522 icount->frame = cnow.frame;
1523 icount->brk = cnow.brk;
1524 icount->overrun = cnow.overrun;
1525 icount->buf_overrun = cnow.buf_overrun;
1526 icount->parity = cnow.parity;
1527 icount->rx = cnow.rx;
1528 icount->tx = cnow.tx;
1529 icount->cts = cnow.cts;
1530 icount->dsr = cnow.dsr;
1531 icount->rng = cnow.rng;
1532 icount->dcd = cnow.dcd;
1533 return 0;
1534}
1535
1c45607a
JS		 1536static void mxser_stoprx(struct tty_struct *tty)
1537{
1538 struct mxser_port *info = tty->driver_data;
1539
1540 info->ldisc_stop_rx = 1;
1541 if (I_IXOFF(tty)) {
292955a7 1542 if (info->board->must_hwid) {
1c45607a
JS		 1543 info->IER &= ~MOXA_MUST_RECV_ISR;
1544 outb(info->IER, info->ioaddr + UART_IER);
1545 } else {
1546 info->x_char = STOP_CHAR(tty);
1547 outb(0, info->ioaddr + UART_IER);
1548 info->IER |= UART_IER_THRI;
1549 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1550 }
1551 }
1552
9db276f8 1553 if (C_CRTSCTS(tty)) {
1c45607a
JS		 1554 info->MCR &= ~UART_MCR_RTS;
1555 outb(info->MCR, info->ioaddr + UART_MCR);
1da177e4
LT		 1556 }
1557}
1558
1559/*
1560 * This routine is called by the upper-layer tty layer to signal that
1561 * incoming characters should be throttled.
1562 */
1563static void mxser_throttle(struct tty_struct *tty)
1564{
1da177e4 1565 mxser_stoprx(tty);
1da177e4
LT		 1566}
1567
1568static void mxser_unthrottle(struct tty_struct *tty)
1569{
1c45607a 1570 struct mxser_port *info = tty->driver_data;
1da177e4 1571
1c45607a
JS		 1572 /* startrx */
1573 info->ldisc_stop_rx = 0;
1574 if (I_IXOFF(tty)) {
1575 if (info->x_char)
1576 info->x_char = 0;
1577 else {
292955a7 1578 if (info->board->must_hwid) {
1c45607a
JS		 1579 info->IER |= MOXA_MUST_RECV_ISR;
1580 outb(info->IER, info->ioaddr + UART_IER);
1581 } else {
1582 info->x_char = START_CHAR(tty);
1583 outb(0, info->ioaddr + UART_IER);
1584 info->IER |= UART_IER_THRI;
1585 outb(info->IER, info->ioaddr + UART_IER);
1586 }
1da177e4 1587 }
1c45607a 1588 }
1da177e4 1589
9db276f8 1590 if (C_CRTSCTS(tty)) {
1c45607a
JS		 1591 info->MCR |= UART_MCR_RTS;
1592 outb(info->MCR, info->ioaddr + UART_MCR);
1da177e4
LT		 1593 }
1594}
1595
1596/*
1597 * mxser_stop() and mxser_start()
1598 *
6e94dbc7 1599 * This routines are called before setting or resetting tty->flow.stopped.
1da177e4
LT		 1600 * They enable or disable transmitter interrupts, as necessary.
1601 */
1602static void mxser_stop(struct tty_struct *tty)
1603{
1c45607a 1604 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1605 unsigned long flags;
1606
1607 spin_lock_irqsave(&info->slock, flags);
1608 if (info->IER & UART_IER_THRI) {
1609 info->IER &= ~UART_IER_THRI;
1c45607a 1610 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1611 }
1612 spin_unlock_irqrestore(&info->slock, flags);
1613}
1614
1615static void mxser_start(struct tty_struct *tty)
1616{
1c45607a 1617 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1618 unsigned long flags;
1619
1620 spin_lock_irqsave(&info->slock, flags);
0ad9e7d1 1621 if (info->xmit_cnt && info->port.xmit_buf) {
1c45607a 1622 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1623 info->IER |= UART_IER_THRI;
1c45607a 1624 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1625 }
1626 spin_unlock_irqrestore(&info->slock, flags);
1627}
1628
1c45607a
JS		 1629static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1630{
1631 struct mxser_port *info = tty->driver_data;
1632 unsigned long flags;
1633
1634 spin_lock_irqsave(&info->slock, flags);
2799707f 1635 mxser_change_speed(tty);
1c45607a
JS		 1636 spin_unlock_irqrestore(&info->slock, flags);
1637
9db276f8 1638 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
1c45607a
JS		 1639 tty->hw_stopped = 0;
1640 mxser_start(tty);
1641 }
1642
1643 /* Handle sw stopped */
9db276f8 1644 if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) {
6e94dbc7 1645 tty->flow.stopped = 0;
1c45607a 1646
292955a7 1647 if (info->board->must_hwid) {
1c45607a 1648 spin_lock_irqsave(&info->slock, flags);
148ff86b
CH		 1649 mxser_disable_must_rx_software_flow_control(
1650 info->ioaddr);
1c45607a
JS		 1651 spin_unlock_irqrestore(&info->slock, flags);
1652 }
1653
1654 mxser_start(tty);
1655 }
1656}
1657
1da177e4
LT		 1658/*
1659 * mxser_wait_until_sent() --- wait until the transmitter is empty
1660 */
1661static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1662{
1c45607a 1663 struct mxser_port *info = tty->driver_data;
1da177e4 1664 unsigned long orig_jiffies, char_time;
07f86c03 1665 unsigned long flags;
1da177e4
LT		 1666 int lsr;
1667
1668 if (info->type == PORT_UNKNOWN)
1669 return;
1670
1671 if (info->xmit_fifo_size == 0)
1672 return; /* Just in case.... */
1673
1674 orig_jiffies = jiffies;
1675 /*
1676 * Set the check interval to be 1/5 of the estimated time to
1677 * send a single character, and make it at least 1. The check
1678 * interval should also be less than the timeout.
1679 *
1680 * Note: we have to use pretty tight timings here to satisfy
1681 * the NIST-PCTS.
1682 */
1683 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
1684 char_time = char_time / 5;
1685 if (char_time == 0)
1686 char_time = 1;
1687 if (timeout && timeout < char_time)
1688 char_time = timeout;
1689 /*
1690 * If the transmitter hasn't cleared in twice the approximate
1691 * amount of time to send the entire FIFO, it probably won't
1692 * ever clear. This assumes the UART isn't doing flow
1693 * control, which is currently the case. Hence, if it ever
1694 * takes longer than info->timeout, this is probably due to a
1695 * UART bug of some kind. So, we clamp the timeout parameter at
1696 * 2*info->timeout.
1697 */
1698 if (!timeout || timeout > 2 * info->timeout)
1699 timeout = 2 * info->timeout;
8bab534b 1700
07f86c03 1701 spin_lock_irqsave(&info->slock, flags);
1c45607a 1702 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) {
07f86c03 1703 spin_unlock_irqrestore(&info->slock, flags);
da4cd8df 1704 schedule_timeout_interruptible(char_time);
07f86c03 1705 spin_lock_irqsave(&info->slock, flags);
1da177e4 1706 if (signal_pending(current))
1c45607a
JS		 1707 break;
1708 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1709 break;
1da177e4 1710 }
07f86c03 1711 spin_unlock_irqrestore(&info->slock, flags);
1c45607a 1712 set_current_state(TASK_RUNNING);
1c45607a 1713}
1da177e4 1714
1c45607a
JS		 1715/*
1716 * This routine is called by tty_hangup() when a hangup is signaled.
1717 */
1718static void mxser_hangup(struct tty_struct *tty)
1719{
1720 struct mxser_port *info = tty->driver_data;
1da177e4 1721
1c45607a 1722 mxser_flush_buffer(tty);
3b6826b2 1723 tty_port_hangup(&info->port);
1da177e4
LT		 1724}
1725
1c45607a
JS		 1726/*
1727 * mxser_rs_break() --- routine which turns the break handling on or off
1728 */
9e98966c 1729static int mxser_rs_break(struct tty_struct *tty, int break_state)
1da177e4 1730{
1c45607a 1731 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1732 unsigned long flags;
1733
1c45607a
JS		 1734 spin_lock_irqsave(&info->slock, flags);
1735 if (break_state == -1)
1736 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
1737 info->ioaddr + UART_LCR);
1738 else
1739 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
1740 info->ioaddr + UART_LCR);
1741 spin_unlock_irqrestore(&info->slock, flags);
9e98966c 1742 return 0;
1c45607a 1743}
1da177e4 1744
e5ce1bce
JS		 1745static bool mxser_receive_chars_new(struct tty_struct *tty,
1746 struct mxser_port *port, u8 status, int *cnt)
1747{
1748 enum mxser_must_hwid hwid = port->board->must_hwid;
1749 u8 gdl;
1750
1751 if (hwid == MOXA_OTHER_UART)
1752 return false;
70640052 1753 if (status & UART_LSR_BRK_ERROR_BITS)
e5ce1bce
JS		 1754 return false;
1755 if (hwid == MOXA_MUST_MU860_HWID && (status & MOXA_MUST_LSR_RERR))
1756 return false;
1757 if (status & MOXA_MUST_LSR_RERR)
1758 return false;
1759
1760 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
1761 if (hwid == MOXA_MUST_MU150_HWID)
1762 gdl &= MOXA_MUST_GDL_MASK;
1763
1764 if (gdl >= tty->receive_room && !port->ldisc_stop_rx)
1765 mxser_stoprx(tty);
1766
1767 while (gdl--) {
1768 u8 ch = inb(port->ioaddr + UART_RX);
1769 tty_insert_flip_char(&port->port, ch, 0);
1770 (*cnt)++;
1771 }
1772
1773 return true;
1774}
1775
0c419421
JS		 1776static u8 mxser_receive_chars_old(struct tty_struct *tty,
1777 struct mxser_port *port, u8 status, int *cnt)
1c45607a 1778{
0c419421
JS		 1779 enum mxser_must_hwid hwid = port->board->must_hwid;
1780 int recv_room = tty->receive_room;
1c45607a 1781 int ignored = 0;
1c45607a 1782 int max = 256;
0c419421 1783 u8 ch;
1c45607a
JS		 1784
1785 do {
1786 if (max-- < 0)
1787 break;
1da177e4 1788
1c45607a 1789 ch = inb(port->ioaddr + UART_RX);
0c419421 1790 if (hwid && (status & UART_LSR_OE))
1c45607a 1791 outb(0x23, port->ioaddr + UART_FCR);
15517806
JS		 1792 status &= port->read_status_mask;
1793 if (status & port->ignore_status_mask) {
1c45607a
JS		 1794 if (++ignored > 100)
1795 break;
1796 } else {
1797 char flag = 0;
70640052 1798 if (status & UART_LSR_BRK_ERROR_BITS) {
15517806 1799 if (status & UART_LSR_BI) {
1c45607a
JS		 1800 flag = TTY_BREAK;
1801 port->icount.brk++;
1da177e4 1802
0ad9e7d1 1803 if (port->port.flags & ASYNC_SAK)
1c45607a 1804 do_SAK(tty);
15517806 1805 } else if (status & UART_LSR_PE) {
1c45607a
JS		 1806 flag = TTY_PARITY;
1807 port->icount.parity++;
15517806 1808 } else if (status & UART_LSR_FE) {
1c45607a
JS		 1809 flag = TTY_FRAME;
1810 port->icount.frame++;
15517806 1811 } else if (status & UART_LSR_OE) {
1c45607a
JS		 1812 flag = TTY_OVERRUN;
1813 port->icount.overrun++;
6de6e5c4 1814 }
1c45607a 1815 }
92a19f9c 1816 tty_insert_flip_char(&port->port, ch, flag);
0c419421
JS		 1817 (*cnt)++;
1818 if (*cnt >= recv_room) {
1c45607a
JS		 1819 if (!port->ldisc_stop_rx)
1820 mxser_stoprx(tty);
1821 break;
1822 }
1da177e4 1823
1c45607a 1824 }
1da177e4 1825
0c419421 1826 if (hwid)
1c45607a 1827 break;
1da177e4 1828
15517806
JS		 1829 status = inb(port->ioaddr + UART_LSR);
1830 } while (status & UART_LSR_DR);
1da177e4 1831
0c419421
JS		 1832 return status;
1833}
1834
1835static u8 mxser_receive_chars(struct tty_struct *tty,
1836 struct mxser_port *port, u8 status)
1837{
1838 int cnt = 0;
1839
1840 if (tty->receive_room == 0 && !port->ldisc_stop_rx)
1841 mxser_stoprx(tty);
1842
1843 if (!mxser_receive_chars_new(tty, port, status, &cnt))
1844 status = mxser_receive_chars_old(tty, port, status, &cnt);
1845
2e124b4a 1846 tty_flip_buffer_push(&port->port);
15517806
JS		 1847
1848 return status;
1da177e4
LT		 1849}
1850
216ba023 1851static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port)
1da177e4 1852{
1c45607a 1853 int count, cnt;
1da177e4 1854
1c45607a
JS		 1855 if (port->x_char) {
1856 outb(port->x_char, port->ioaddr + UART_TX);
1857 port->x_char = 0;
1c45607a
JS		 1858 port->icount.tx++;
1859 return;
1860 }
1da177e4 1861
0ad9e7d1 1862 if (port->port.xmit_buf == NULL)
1c45607a 1863 return;
1da177e4 1864
6e94dbc7 1865 if (port->xmit_cnt <= 0 || tty->flow.stopped ||
216ba023 1866 (tty->hw_stopped &&
1c45607a 1867 (port->type != PORT_16550A) &&
292955a7 1868 (!port->board->must_hwid))) {
1c45607a
JS		 1869 port->IER &= ~UART_IER_THRI;
1870 outb(port->IER, port->ioaddr + UART_IER);
1871 return;
1da177e4
LT		 1872 }
1873
1c45607a
JS		 1874 cnt = port->xmit_cnt;
1875 count = port->xmit_fifo_size;
1876 do {
0ad9e7d1 1877 outb(port->port.xmit_buf[port->xmit_tail++],
1c45607a
JS		 1878 port->ioaddr + UART_TX);
1879 port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1);
1880 if (--port->xmit_cnt <= 0)
1881 break;
1882 } while (--count > 0);
1da177e4 1883
1c45607a 1884 port->icount.tx += (cnt - port->xmit_cnt);
1da177e4 1885
464eb8f5 1886 if (port->xmit_cnt < WAKEUP_CHARS)
216ba023 1887 tty_wakeup(tty);
1c45607a
JS		 1888
1889 if (port->xmit_cnt <= 0) {
1890 port->IER &= ~UART_IER_THRI;
1891 outb(port->IER, port->ioaddr + UART_IER);
1da177e4 1892 }
1da177e4
LT		 1893}
1894
9e40ea1f
JS		 1895static bool mxser_port_isr(struct mxser_port *port)
1896{
1897 struct tty_struct *tty;
1898 u8 iir, msr, status;
1899 bool error = false;
1900
1901 iir = inb(port->ioaddr + UART_IIR);
1902 if (iir & UART_IIR_NO_INT)
1903 return true;
1904
1905 iir &= MOXA_MUST_IIR_MASK;
1906 tty = tty_port_tty_get(&port->port);
1907 if (!tty || port->closing || !tty_port_initialized(&port->port)) {
1908 status = inb(port->ioaddr + UART_LSR);
1909 outb(0x27, port->ioaddr + UART_FCR);
1910 inb(port->ioaddr + UART_MSR);
1911
1912 error = true;
1913 goto put_tty;
1914 }
1915
1916 status = inb(port->ioaddr + UART_LSR);
1917
9e40ea1f
JS		 1918 if (port->board->must_hwid) {
1919 if (iir == MOXA_MUST_IIR_GDA ||
1920 iir == MOXA_MUST_IIR_RDA ||
1921 iir == MOXA_MUST_IIR_RTO ||
1922 iir == MOXA_MUST_IIR_LSR)
1923 status = mxser_receive_chars(tty, port, status);
1924 } else {
1925 status &= port->read_status_mask;
1926 if (status & UART_LSR_DR)
1927 status = mxser_receive_chars(tty, port, status);
1928 }
1929
1930 msr = inb(port->ioaddr + UART_MSR);
1931 if (msr & UART_MSR_ANY_DELTA)
1932 mxser_check_modem_status(tty, port, msr);
1933
1934 if (port->board->must_hwid) {
1935 if (iir == 0x02 && (status & UART_LSR_THRE))
1936 mxser_transmit_chars(tty, port);
1937 } else {
1938 if (status & UART_LSR_THRE)
1939 mxser_transmit_chars(tty, port);
1940 }
1941
1942put_tty:
1943 tty_kref_put(tty);
1944
1945 return error;
1946}
1947
1da177e4 1948/*
1c45607a 1949 * This is the serial driver's generic interrupt routine
1da177e4 1950 */
1c45607a 1951static irqreturn_t mxser_interrupt(int irq, void *dev_id)
1da177e4 1952{
cef222cb 1953 struct mxser_board *brd = dev_id;
1c45607a 1954 struct mxser_port *port;
1c45607a 1955 unsigned int int_cnt, pass_counter = 0;
9cb5c9c3 1956 unsigned int i, max = brd->info->nports;
1c45607a 1957 int handled = IRQ_NONE;
9cb5c9c3 1958 u8 irqbits, bits, mask = BIT(max) - 1;
1da177e4 1959
1c45607a 1960 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
9cb5c9c3
JS		 1961 irqbits = inb(brd->vector) & mask;
1962 if (irqbits == mask)
1c45607a 1963 break;
1da177e4 1964
1c45607a
JS		 1965 handled = IRQ_HANDLED;
1966 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
9cb5c9c3 1967 if (irqbits == mask)
1c45607a
JS		 1968 break;
1969 if (bits & irqbits)
1970 continue;
1971 port = &brd->ports[i];
1972
1973 int_cnt = 0;
1974 spin_lock(&port->slock);
1975 do {
9e40ea1f 1976 if (mxser_port_isr(port))
1c45607a 1977 break;
1c45607a
JS		 1978 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
1979 spin_unlock(&port->slock);
1980 }
1981 }
1da177e4 1982
1c45607a
JS		 1983 return handled;
1984}
1da177e4 1985
1c45607a
JS		 1986static const struct tty_operations mxser_ops = {
1987 .open = mxser_open,
1988 .close = mxser_close,
1989 .write = mxser_write,
1990 .put_char = mxser_put_char,
1991 .flush_chars = mxser_flush_chars,
1992 .write_room = mxser_write_room,
1993 .chars_in_buffer = mxser_chars_in_buffer,
1994 .flush_buffer = mxser_flush_buffer,
1995 .ioctl = mxser_ioctl,
1996 .throttle = mxser_throttle,
1997 .unthrottle = mxser_unthrottle,
1998 .set_termios = mxser_set_termios,
1999 .stop = mxser_stop,
2000 .start = mxser_start,
2001 .hangup = mxser_hangup,
2002 .break_ctl = mxser_rs_break,
2003 .wait_until_sent = mxser_wait_until_sent,
2004 .tiocmget = mxser_tiocmget,
2005 .tiocmset = mxser_tiocmset,
6da5b587
AV		 2006 .set_serial = mxser_set_serial_info,
2007 .get_serial = mxser_get_serial_info,
0587102c 2008 .get_icount = mxser_get_icount,
1c45607a 2009};
1da177e4 2010
04b757df 2011static const struct tty_port_operations mxser_port_ops = {
31f35939 2012 .carrier_raised = mxser_carrier_raised,
fcc8ac18 2013 .dtr_rts = mxser_dtr_rts,
6769140d
AC		 2014 .activate = mxser_activate,
2015 .shutdown = mxser_shutdown_port,
31f35939
AC		 2016};
2017
1c45607a
JS		 2018/*
2019 * The MOXA Smartio/Industio serial driver boot-time initialization code!
2020 */
1da177e4 2021
2799707f 2022static int mxser_initbrd(struct mxser_board *brd)
1da177e4 2023{
1c45607a
JS		 2024 struct mxser_port *info;
2025 unsigned int i;
2026 int retval;
1da177e4 2027
1c45607a
JS		 2028 for (i = 0; i < brd->info->nports; i++) {
2029 info = &brd->ports[i];
44b7d1b3 2030 tty_port_init(&info->port);
31f35939 2031 info->port.ops = &mxser_port_ops;
1c45607a
JS		 2032 info->board = brd;
2033 info->stop_rx = 0;
2034 info->ldisc_stop_rx = 0;
1da177e4 2035
1c45607a 2036 /* Enhance mode enabled here */
292955a7 2037 if (brd->must_hwid != MOXA_OTHER_UART)
148ff86b 2038 mxser_enable_must_enchance_mode(info->ioaddr);
1da177e4 2039
58a2ddb3 2040 info->type = PORT_16550A;
1da177e4 2041
1c45607a 2042 process_txrx_fifo(info);
1da177e4 2043
1c45607a 2044 info->custom_divisor = info->baud_base * 16;
44b7d1b3
AC		 2045 info->port.close_delay = 5 * HZ / 10;
2046 info->port.closing_wait = 30 * HZ;
1c45607a 2047 info->normal_termios = mxvar_sdriver->init_termios;
1c45607a 2048 spin_lock_init(&info->slock);
1da177e4 2049
1c45607a
JS		 2050 /* before set INT ISR, disable all int */
2051 outb(inb(info->ioaddr + UART_IER) & 0xf0,
2052 info->ioaddr + UART_IER);
2053 }
1da177e4 2054
1c45607a
JS		 2055 retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser",
2056 brd);
191c5f10
JS		 2057 if (retval) {
2058 for (i = 0; i < brd->info->nports; i++)
2059 tty_port_destroy(&brd->ports[i].port);
1c45607a
JS		 2060 printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may "
2061 "conflict with another device.\n",
2062 brd->info->name, brd->irq);
191c5f10 2063 }
df480518 2064
1c45607a
JS		 2065 return retval;
2066}
1da177e4 2067
191c5f10
JS		 2068static void mxser_board_remove(struct mxser_board *brd)
2069{
2070 unsigned int i;
2071
2072 for (i = 0; i < brd->info->nports; i++) {
2073 tty_unregister_device(mxvar_sdriver, brd->idx + i);
2074 tty_port_destroy(&brd->ports[i].port);
2075 }
9e17df37 2076 free_irq(brd->irq, brd);
191c5f10
JS		 2077}
2078
9671f099 2079static int mxser_probe(struct pci_dev *pdev,
1c45607a 2080 const struct pci_device_id *ent)
1da177e4 2081{
1c45607a
JS		 2082 struct mxser_board *brd;
2083 unsigned int i, j;
2084 unsigned long ioaddress;
9e17df37 2085 struct device *tty_dev;
1c45607a 2086 int retval = -EINVAL;
1da177e4 2087
1c45607a
JS		 2088 for (i = 0; i < MXSER_BOARDS; i++)
2089 if (mxser_boards[i].info == NULL)
2090 break;
2091
2092 if (i >= MXSER_BOARDS) {
83766bc6
JS		 2093 dev_err(&pdev->dev, "too many boards found (maximum %d), board "
2094 "not configured\n", MXSER_BOARDS);
1c45607a
JS		 2095 goto err;
2096 }
2097
2098 brd = &mxser_boards[i];
2099 brd->idx = i * MXSER_PORTS_PER_BOARD;
83766bc6 2100 dev_info(&pdev->dev, "found MOXA %s board (BusNo=%d, DevNo=%d)\n",
1c45607a
JS		 2101 mxser_cards[ent->driver_data].name,
2102 pdev->bus->number, PCI_SLOT(pdev->devfn));
2103
2104 retval = pci_enable_device(pdev);
2105 if (retval) {
83766bc6 2106 dev_err(&pdev->dev, "PCI enable failed\n");
1c45607a
JS		 2107 goto err;
2108 }
2109
2110 /* io address */
2111 ioaddress = pci_resource_start(pdev, 2);
2112 retval = pci_request_region(pdev, 2, "mxser(IO)");
2113 if (retval)
df480518 2114 goto err_dis;
1c45607a
JS		 2115
2116 brd->info = &mxser_cards[ent->driver_data];
2117 for (i = 0; i < brd->info->nports; i++)
2118 brd->ports[i].ioaddr = ioaddress + 8 * i;
2119
2120 /* vector */
2121 ioaddress = pci_resource_start(pdev, 3);
2122 retval = pci_request_region(pdev, 3, "mxser(vector)");
2123 if (retval)
df480518 2124 goto err_zero;
1c45607a
JS		 2125 brd->vector = ioaddress;
2126
2127 /* irq */
2128 brd->irq = pdev->irq;
2129
292955a7 2130 brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr);
1c45607a 2131
928f9464
JS		 2132 for (j = 0; j < UART_INFO_NUM; j++) {
2133 if (Gpci_uart_info[j].type == brd->must_hwid) {
2134 brd->max_baud = Gpci_uart_info[j].max_baud;
2135
2136 /* exception....CP-102 */
2137 if (brd->info->flags & MXSER_HIGHBAUD)
2138 brd->max_baud = 921600;
2139 break;
1da177e4 2140 }
1c45607a
JS		 2141 }
2142
292955a7 2143 if (brd->must_hwid == MOXA_MUST_MU860_HWID) {
1c45607a
JS		 2144 for (i = 0; i < brd->info->nports; i++) {
2145 if (i < 4)
2146 brd->ports[i].opmode_ioaddr = ioaddress + 4;
2147 else
2148 brd->ports[i].opmode_ioaddr = ioaddress + 0x0c;
1da177e4 2149 }
1c45607a
JS		 2150 outb(0, ioaddress + 4); /* default set to RS232 mode */
2151 outb(0, ioaddress + 0x0c); /* default set to RS232 mode */
1da177e4 2152 }
1c45607a
JS		 2153
2154 for (i = 0; i < brd->info->nports; i++) {
1c45607a
JS		 2155 brd->ports[i].baud_base = 921600;
2156 }
2157
2158 /* mxser_initbrd will hook ISR. */
2799707f 2159 retval = mxser_initbrd(brd);
1c45607a 2160 if (retval)
df480518 2161 goto err_rel3;
1c45607a 2162
9e17df37
AK		 2163 for (i = 0; i < brd->info->nports; i++) {
2164 tty_dev = tty_port_register_device(&brd->ports[i].port,
2165 mxvar_sdriver, brd->idx + i, &pdev->dev);
2166 if (IS_ERR(tty_dev)) {
2167 retval = PTR_ERR(tty_dev);
1b581f17 2168 for (; i > 0; i--)
9e17df37 2169 tty_unregister_device(mxvar_sdriver,
1b581f17 2170 brd->idx + i - 1);
9e17df37
AK		 2171 goto err_relbrd;
2172 }
2173 }
1c45607a
JS		 2174
2175 pci_set_drvdata(pdev, brd);
2176
2177 return 0;
9e17df37
AK		 2178err_relbrd:
2179 for (i = 0; i < brd->info->nports; i++)
2180 tty_port_destroy(&brd->ports[i].port);
2181 free_irq(brd->irq, brd);
df480518
JS		 2182err_rel3:
2183 pci_release_region(pdev, 3);
2184err_zero:
1c45607a 2185 brd->info = NULL;
df480518
JS		 2186 pci_release_region(pdev, 2);
2187err_dis:
2188 pci_disable_device(pdev);
1c45607a
JS		 2189err:
2190 return retval;
1da177e4
LT		 2191}
2192
ae8d8a14 2193static void mxser_remove(struct pci_dev *pdev)
1da177e4 2194{
1c45607a 2195 struct mxser_board *brd = pci_get_drvdata(pdev);
1da177e4 2196
191c5f10 2197 mxser_board_remove(brd);
1da177e4 2198
df480518
JS		 2199 pci_release_region(pdev, 2);
2200 pci_release_region(pdev, 3);
2201 pci_disable_device(pdev);
1c45607a 2202 brd->info = NULL;
1da177e4
LT		 2203}
2204
1c45607a
JS		 2205static struct pci_driver mxser_driver = {
2206 .name = "mxser",
2207 .id_table = mxser_pcibrds,
2208 .probe = mxser_probe,
91116cba 2209 .remove = mxser_remove
1c45607a
JS		 2210};
2211
2212static int __init mxser_module_init(void)
1da177e4 2213{
1df00924 2214 int retval;
1da177e4 2215
1c45607a
JS		 2216 mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
2217 if (!mxvar_sdriver)
2218 return -ENOMEM;
2219
1c45607a 2220 /* Initialize the tty_driver structure */
1c45607a
JS		 2221 mxvar_sdriver->name = "ttyMI";
2222 mxvar_sdriver->major = ttymajor;
2223 mxvar_sdriver->minor_start = 0;
1c45607a
JS		 2224 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
2225 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
2226 mxvar_sdriver->init_termios = tty_std_termios;
2227 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
2228 mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV;
2229 tty_set_operations(mxvar_sdriver, &mxser_ops);
2230
2231 retval = tty_register_driver(mxvar_sdriver);
2232 if (retval) {
2233 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
2234 "tty driver !\n");
2235 goto err_put;
1da177e4 2236 }
1c45607a 2237
1c45607a
JS		 2238 retval = pci_register_driver(&mxser_driver);
2239 if (retval) {
83766bc6 2240 printk(KERN_ERR "mxser: can't register pci driver\n");
29134367 2241 goto err_unr;
1c45607a
JS		 2242 }
2243
1c45607a
JS		 2244 return 0;
2245err_unr:
2246 tty_unregister_driver(mxvar_sdriver);
2247err_put:
2248 put_tty_driver(mxvar_sdriver);
2249 return retval;
2250}
2251
2252static void __exit mxser_module_exit(void)
2253{
1c45607a 2254 pci_unregister_driver(&mxser_driver);
1c45607a
JS		 2255 tty_unregister_driver(mxvar_sdriver);
2256 put_tty_driver(mxvar_sdriver);
1da177e4
LT		 2257}
2258
2259module_init(mxser_module_init);
2260module_exit(mxser_module_exit);
Linux 6.x block layer and io_uring tree(s)