Commit | Line | Data |
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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1da177e4 LT |
2 | /* |
3 | * mxser.c -- MOXA Smartio/Industio family multiport serial driver. | |
4 | * | |
80ff8a80 JS |
5 | * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com). |
6 | * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com> | |
1da177e4 | 7 | * |
1c45607a JS |
8 | * This code is loosely based on the 1.8 moxa driver which is based on |
9 | * Linux serial driver, written by Linus Torvalds, Theodore T'so and | |
10 | * others. | |
1da177e4 | 11 | * |
1da177e4 | 12 | * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox |
8eb04cf3 AC |
13 | * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on |
14 | * www.moxa.com. | |
1da177e4 | 15 | * - Fixed x86_64 cleanness |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 | 18 | #include <linux/module.h> |
1da177e4 LT |
19 | #include <linux/errno.h> |
20 | #include <linux/signal.h> | |
21 | #include <linux/sched.h> | |
22 | #include <linux/timer.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/tty.h> | |
25 | #include <linux/tty_flip.h> | |
26 | #include <linux/serial.h> | |
27 | #include <linux/serial_reg.h> | |
28 | #include <linux/major.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/fcntl.h> | |
31 | #include <linux/ptrace.h> | |
1da177e4 LT |
32 | #include <linux/ioport.h> |
33 | #include <linux/mm.h> | |
1da177e4 LT |
34 | #include <linux/delay.h> |
35 | #include <linux/pci.h> | |
1977f032 | 36 | #include <linux/bitops.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
5a3c6b25 | 38 | #include <linux/ratelimit.h> |
1da177e4 | 39 | |
1da177e4 LT |
40 | #include <asm/io.h> |
41 | #include <asm/irq.h> | |
7c0f6ba6 | 42 | #include <linux/uaccess.h> |
1da177e4 | 43 | |
4463cc5b JS |
44 | /* |
45 | * Semi-public control interfaces | |
46 | */ | |
47 | ||
48 | /* | |
49 | * MOXA ioctls | |
50 | */ | |
51 | ||
52 | #define MOXA 0x400 | |
4463cc5b JS |
53 | #define MOXA_SET_OP_MODE (MOXA + 66) |
54 | #define MOXA_GET_OP_MODE (MOXA + 67) | |
55 | ||
56 | #define RS232_MODE 0 | |
57 | #define RS485_2WIRE_MODE 1 | |
58 | #define RS422_MODE 2 | |
59 | #define RS485_4WIRE_MODE 3 | |
60 | #define OP_MODE_MASK 3 | |
61 | ||
4463cc5b JS |
62 | /* --------------------------------------------------- */ |
63 | ||
4463cc5b JS |
64 | /* |
65 | * Follow just what Moxa Must chip defines. | |
66 | * | |
464fbf6c JS |
67 | * When LCR register (offset 0x03) is written the following value, the Must chip |
68 | * will enter enhanced mode. And a write to EFR (offset 0x02) bit 6,7 will | |
4463cc5b JS |
69 | * change bank. |
70 | */ | |
464fbf6c | 71 | #define MOXA_MUST_ENTER_ENHANCED 0xBF |
4463cc5b | 72 | |
464fbf6c | 73 | /* when enhanced mode is enabled, access to general bank register */ |
4463cc5b JS |
74 | #define MOXA_MUST_GDL_REGISTER 0x07 |
75 | #define MOXA_MUST_GDL_MASK 0x7F | |
76 | #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80 | |
77 | ||
78 | #define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */ | |
464fbf6c JS |
79 | /* enhanced register bank select and enhanced mode setting register */ |
80 | /* This works only when LCR register equals to 0xBF */ | |
4463cc5b | 81 | #define MOXA_MUST_EFR_REGISTER 0x02 |
464fbf6c JS |
82 | #define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enhanced mode enable */ |
83 | /* enhanced register bank set 0, 1, 2 */ | |
4463cc5b JS |
84 | #define MOXA_MUST_EFR_BANK0 0x00 |
85 | #define MOXA_MUST_EFR_BANK1 0x40 | |
86 | #define MOXA_MUST_EFR_BANK2 0x80 | |
87 | #define MOXA_MUST_EFR_BANK3 0xC0 | |
88 | #define MOXA_MUST_EFR_BANK_MASK 0xC0 | |
89 | ||
90 | /* set XON1 value register, when LCR=0xBF and change to bank0 */ | |
91 | #define MOXA_MUST_XON1_REGISTER 0x04 | |
92 | ||
93 | /* set XON2 value register, when LCR=0xBF and change to bank0 */ | |
94 | #define MOXA_MUST_XON2_REGISTER 0x05 | |
95 | ||
96 | /* set XOFF1 value register, when LCR=0xBF and change to bank0 */ | |
97 | #define MOXA_MUST_XOFF1_REGISTER 0x06 | |
98 | ||
99 | /* set XOFF2 value register, when LCR=0xBF and change to bank0 */ | |
100 | #define MOXA_MUST_XOFF2_REGISTER 0x07 | |
101 | ||
102 | #define MOXA_MUST_RBRTL_REGISTER 0x04 | |
103 | #define MOXA_MUST_RBRTH_REGISTER 0x05 | |
104 | #define MOXA_MUST_RBRTI_REGISTER 0x06 | |
105 | #define MOXA_MUST_THRTL_REGISTER 0x07 | |
106 | #define MOXA_MUST_ENUM_REGISTER 0x04 | |
107 | #define MOXA_MUST_HWID_REGISTER 0x05 | |
108 | #define MOXA_MUST_ECR_REGISTER 0x06 | |
109 | #define MOXA_MUST_CSR_REGISTER 0x07 | |
110 | ||
111 | #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */ | |
112 | #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */ | |
113 | ||
114 | #define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */ | |
115 | #define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */ | |
116 | #define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */ | |
117 | #define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */ | |
118 | ||
119 | #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI) | |
120 | ||
121 | /* GDA interrupt pending */ | |
122 | #define MOXA_MUST_IIR_GDA 0x1C | |
123 | #define MOXA_MUST_IIR_RDA 0x04 | |
124 | #define MOXA_MUST_IIR_RTO 0x0C | |
125 | #define MOXA_MUST_IIR_LSR 0x06 | |
126 | ||
127 | /* received Xon/Xoff or specical interrupt pending */ | |
128 | #define MOXA_MUST_IIR_XSC 0x10 | |
129 | ||
130 | /* RTS/CTS change state interrupt pending */ | |
131 | #define MOXA_MUST_IIR_RTSCTS 0x20 | |
132 | #define MOXA_MUST_IIR_MASK 0x3E | |
133 | ||
134 | #define MOXA_MUST_MCR_XON_FLAG 0x40 | |
135 | #define MOXA_MUST_MCR_XON_ANY 0x80 | |
136 | #define MOXA_MUST_MCR_TX_XON 0x08 | |
137 | ||
138 | #define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */ | |
139 | #define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */ | |
140 | #define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */ | |
141 | #define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */ | |
142 | #define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */ | |
143 | #define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */ | |
144 | #define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */ | |
145 | #define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */ | |
146 | #define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */ | |
147 | #define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */ | |
148 | #define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */ | |
1da177e4 | 149 | |
1da177e4 | 150 | #define MXSERMAJOR 174 |
1da177e4 | 151 | |
1da177e4 | 152 | #define MXSER_BOARDS 4 /* Max. boards */ |
1da177e4 | 153 | #define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */ |
1c45607a JS |
154 | #define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD) |
155 | #define MXSER_ISR_PASS_LIMIT 100 | |
1da177e4 | 156 | |
1da177e4 LT |
157 | #define WAKEUP_CHARS 256 |
158 | ||
a6970c39 | 159 | #define MXSER_BAUD_BASE 921600 |
d811b26b | 160 | #define MXSER_CUSTOM_DIVISOR (MXSER_BAUD_BASE * 16) |
a6970c39 | 161 | |
e129deff | 162 | #define PCI_DEVICE_ID_POS104UL 0x1044 |
1c45607a | 163 | #define PCI_DEVICE_ID_CB108 0x1080 |
e129deff | 164 | #define PCI_DEVICE_ID_CP102UF 0x1023 |
502f295f | 165 | #define PCI_DEVICE_ID_CP112UL 0x1120 |
1c45607a | 166 | #define PCI_DEVICE_ID_CB114 0x1142 |
80ff8a80 | 167 | #define PCI_DEVICE_ID_CP114UL 0x1143 |
1c45607a JS |
168 | #define PCI_DEVICE_ID_CB134I 0x1341 |
169 | #define PCI_DEVICE_ID_CP138U 0x1380 | |
1da177e4 | 170 | |
c24c31ff JS |
171 | #define MXSER_NPORTS(ddata) ((ddata) & 0xffU) |
172 | #define MXSER_HIGHBAUD 0x0100 | |
1da177e4 | 173 | |
e4558366 JS |
174 | enum mxser_must_hwid { |
175 | MOXA_OTHER_UART = 0x00, | |
176 | MOXA_MUST_MU150_HWID = 0x01, | |
177 | MOXA_MUST_MU860_HWID = 0x02, | |
178 | }; | |
179 | ||
1c45607a | 180 | static const struct { |
dc33f644 JS |
181 | u8 type; |
182 | u8 fifo_size; | |
183 | u8 rx_high_water; | |
184 | u8 rx_low_water; | |
185 | speed_t max_baud; | |
1c45607a | 186 | } Gpci_uart_info[] = { |
dc33f644 JS |
187 | { MOXA_OTHER_UART, 16, 14, 1, 921600 }, |
188 | { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 }, | |
189 | { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 } | |
1da177e4 | 190 | }; |
1c45607a | 191 | #define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info) |
1da177e4 | 192 | |
1da177e4 | 193 | |
1c45607a JS |
194 | /* driver_data correspond to the lines in the structure above |
195 | see also ISA probe function before you change something */ | |
3385ecf8 | 196 | static const struct pci_device_id mxser_pcibrds[] = { |
c24c31ff JS |
197 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 8 }, |
198 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 4 }, | |
15254902 | 199 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 2 }, |
c24c31ff | 200 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 4 }, |
15254902 | 201 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 4 }, |
c24c31ff JS |
202 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 2 | MXSER_HIGHBAUD }, |
203 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 4 }, | |
204 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 8 }, | |
205 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 2 }, | |
206 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 4 }, | |
207 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 4 }, | |
208 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 8 }, /* RC7000 */ | |
209 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 8 }, | |
210 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 2 }, | |
211 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 2 }, | |
212 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 8 }, | |
213 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 8 }, | |
214 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 4 }, | |
215 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 8 }, | |
216 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 4 }, | |
217 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 4 }, | |
218 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 8 }, | |
219 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 4 }, | |
220 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL), .driver_data = 4 }, | |
221 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP102UF), .driver_data = 2 }, | |
222 | { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP112UL), .driver_data = 2 }, | |
1c45607a | 223 | { } |
1da177e4 | 224 | }; |
1da177e4 LT |
225 | MODULE_DEVICE_TABLE(pci, mxser_pcibrds); |
226 | ||
1da177e4 | 227 | static int ttymajor = MXSERMAJOR; |
1da177e4 LT |
228 | |
229 | /* Variables for insmod */ | |
230 | ||
231 | MODULE_AUTHOR("Casper Yang"); | |
232 | MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver"); | |
8d3b33f6 | 233 | module_param(ttymajor, int, 0); |
1da177e4 LT |
234 | MODULE_LICENSE("GPL"); |
235 | ||
1c45607a JS |
236 | struct mxser_board; |
237 | ||
238 | struct mxser_port { | |
0ad9e7d1 | 239 | struct tty_port port; |
1c45607a | 240 | struct mxser_board *board; |
1c45607a JS |
241 | |
242 | unsigned long ioaddr; | |
243 | unsigned long opmode_ioaddr; | |
1da177e4 | 244 | |
dc33f644 JS |
245 | u8 rx_high_water; |
246 | u8 rx_low_water; | |
1da177e4 | 247 | int type; /* UART type */ |
1c45607a | 248 | |
a93963e4 JS |
249 | unsigned char x_char; /* xon/xoff character */ |
250 | u8 IER; /* Interrupt Enable Register */ | |
251 | u8 MCR; /* Modem control register */ | |
1c45607a | 252 | |
19236287 | 253 | bool ldisc_stop_rx; |
1c45607a | 254 | |
1c45607a | 255 | struct async_icount icount; /* kernel counters for 4 input interrupts */ |
104583b5 | 256 | unsigned int timeout; |
1c45607a | 257 | |
a93963e4 JS |
258 | u8 read_status_mask; |
259 | u8 ignore_status_mask; | |
dc33f644 | 260 | u8 xmit_fifo_size; |
02e43144 JS |
261 | unsigned int xmit_head; |
262 | unsigned int xmit_tail; | |
263 | unsigned int xmit_cnt; | |
cd7b4b39 | 264 | int closing; |
1c45607a | 265 | |
1da177e4 | 266 | spinlock_t slock; |
1c45607a JS |
267 | }; |
268 | ||
269 | struct mxser_board { | |
270 | unsigned int idx; | |
c24c31ff | 271 | unsigned short nports; |
1c45607a | 272 | int irq; |
1c45607a | 273 | unsigned long vector; |
1c45607a | 274 | |
e4558366 | 275 | enum mxser_must_hwid must_hwid; |
928f9464 | 276 | speed_t max_baud; |
1c45607a | 277 | |
ad1c92ff | 278 | struct mxser_port ports[]; |
1da177e4 LT |
279 | }; |
280 | ||
f8b6b327 | 281 | static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS); |
1da177e4 | 282 | static struct tty_driver *mxvar_sdriver; |
1da177e4 | 283 | |
edb7d27c JS |
284 | static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set, |
285 | bool restore_LCR) | |
148ff86b | 286 | { |
edb7d27c | 287 | u8 oldlcr, efr; |
148ff86b CH |
288 | |
289 | oldlcr = inb(baseio + UART_LCR); | |
464fbf6c | 290 | outb(MOXA_MUST_ENTER_ENHANCED, baseio + UART_LCR); |
148ff86b CH |
291 | |
292 | efr = inb(baseio + MOXA_MUST_EFR_REGISTER); | |
edb7d27c JS |
293 | efr &= ~clear; |
294 | efr |= set; | |
148ff86b CH |
295 | |
296 | outb(efr, baseio + MOXA_MUST_EFR_REGISTER); | |
148ff86b | 297 | |
edb7d27c JS |
298 | if (restore_LCR) |
299 | outb(oldlcr, baseio + UART_LCR); | |
148ff86b | 300 | |
edb7d27c | 301 | return oldlcr; |
148ff86b CH |
302 | } |
303 | ||
b286484b | 304 | static u8 mxser_must_select_bank(unsigned long baseio, u8 bank) |
148ff86b | 305 | { |
b286484b JS |
306 | return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank, |
307 | false); | |
308 | } | |
148ff86b | 309 | |
b286484b JS |
310 | static void mxser_set_must_xon1_value(unsigned long baseio, u8 value) |
311 | { | |
312 | u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); | |
148ff86b CH |
313 | outb(value, baseio + MOXA_MUST_XON1_REGISTER); |
314 | outb(oldlcr, baseio + UART_LCR); | |
315 | } | |
316 | ||
317 | static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value) | |
318 | { | |
b286484b | 319 | u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); |
148ff86b CH |
320 | outb(value, baseio + MOXA_MUST_XOFF1_REGISTER); |
321 | outb(oldlcr, baseio + UART_LCR); | |
322 | } | |
323 | ||
324 | static void mxser_set_must_fifo_value(struct mxser_port *info) | |
325 | { | |
b286484b | 326 | u8 oldlcr = mxser_must_select_bank(info->ioaddr, MOXA_MUST_EFR_BANK1); |
dc33f644 JS |
327 | outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER); |
328 | outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER); | |
329 | outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER); | |
148ff86b CH |
330 | outb(oldlcr, info->ioaddr + UART_LCR); |
331 | } | |
332 | ||
333 | static void mxser_set_must_enum_value(unsigned long baseio, u8 value) | |
334 | { | |
b286484b | 335 | u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); |
148ff86b CH |
336 | outb(value, baseio + MOXA_MUST_ENUM_REGISTER); |
337 | outb(oldlcr, baseio + UART_LCR); | |
338 | } | |
339 | ||
b286484b | 340 | static u8 mxser_get_must_hardware_id(unsigned long baseio) |
148ff86b | 341 | { |
b286484b JS |
342 | u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); |
343 | u8 id = inb(baseio + MOXA_MUST_HWID_REGISTER); | |
148ff86b | 344 | outb(oldlcr, baseio + UART_LCR); |
b286484b JS |
345 | |
346 | return id; | |
148ff86b CH |
347 | } |
348 | ||
edb7d27c JS |
349 | static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set) |
350 | { | |
351 | __mxser_must_set_EFR(baseio, clear, set, true); | |
352 | } | |
353 | ||
354 | static void mxser_must_set_enhance_mode(unsigned long baseio, bool enable) | |
355 | { | |
356 | mxser_must_set_EFR(baseio, | |
357 | enable ? 0 : MOXA_MUST_EFR_EFRB_ENABLE, | |
358 | enable ? MOXA_MUST_EFR_EFRB_ENABLE : 0); | |
359 | } | |
360 | ||
b441eb0f | 361 | static void mxser_must_no_sw_flow_control(unsigned long baseio) |
148ff86b | 362 | { |
b441eb0f | 363 | mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_MASK, 0); |
148ff86b CH |
364 | } |
365 | ||
b441eb0f | 366 | static void mxser_must_set_tx_sw_flow_control(unsigned long baseio, bool enable) |
148ff86b | 367 | { |
b441eb0f JS |
368 | mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_TX_MASK, |
369 | enable ? MOXA_MUST_EFR_SF_TX1 : 0); | |
148ff86b CH |
370 | } |
371 | ||
b441eb0f | 372 | static void mxser_must_set_rx_sw_flow_control(unsigned long baseio, bool enable) |
148ff86b | 373 | { |
b441eb0f JS |
374 | mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_RX_MASK, |
375 | enable ? MOXA_MUST_EFR_SF_RX1 : 0); | |
148ff86b CH |
376 | } |
377 | ||
e4558366 | 378 | static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io) |
1da177e4 LT |
379 | { |
380 | u8 oldmcr, hwid; | |
381 | int i; | |
382 | ||
383 | outb(0, io + UART_LCR); | |
edb7d27c | 384 | mxser_must_set_enhance_mode(io, false); |
1da177e4 LT |
385 | oldmcr = inb(io + UART_MCR); |
386 | outb(0, io + UART_MCR); | |
148ff86b | 387 | mxser_set_must_xon1_value(io, 0x11); |
1da177e4 LT |
388 | if ((hwid = inb(io + UART_MCR)) != 0) { |
389 | outb(oldmcr, io + UART_MCR); | |
8ea2c2ec | 390 | return MOXA_OTHER_UART; |
1da177e4 LT |
391 | } |
392 | ||
b286484b | 393 | hwid = mxser_get_must_hardware_id(io); |
e4558366 | 394 | for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */ |
1c45607a | 395 | if (hwid == Gpci_uart_info[i].type) |
e4558366 JS |
396 | return hwid; |
397 | ||
1da177e4 LT |
398 | return MOXA_OTHER_UART; |
399 | } | |
400 | ||
5d1ea1ad JS |
401 | static bool mxser_16550A_or_MUST(struct mxser_port *info) |
402 | { | |
403 | return info->type == PORT_16550A || info->board->must_hwid; | |
404 | } | |
405 | ||
c3db20c3 | 406 | static void mxser_process_txrx_fifo(struct mxser_port *info) |
1da177e4 | 407 | { |
c3db20c3 | 408 | unsigned int i; |
1da177e4 | 409 | |
c3db20c3 | 410 | if (info->type == PORT_16450 || info->type == PORT_8250) { |
1da177e4 LT |
411 | info->rx_high_water = 1; |
412 | info->rx_low_water = 1; | |
413 | info->xmit_fifo_size = 1; | |
c3db20c3 JS |
414 | return; |
415 | } | |
416 | ||
417 | for (i = 0; i < UART_INFO_NUM; i++) | |
418 | if (info->board->must_hwid == Gpci_uart_info[i].type) { | |
419 | info->rx_low_water = Gpci_uart_info[i].rx_low_water; | |
420 | info->rx_high_water = Gpci_uart_info[i].rx_high_water; | |
421 | info->xmit_fifo_size = Gpci_uart_info[i].fifo_size; | |
422 | break; | |
423 | } | |
1da177e4 LT |
424 | } |
425 | ||
740165f7 JS |
426 | static void __mxser_start_tx(struct mxser_port *info) |
427 | { | |
428 | outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); | |
429 | info->IER |= UART_IER_THRI; | |
430 | outb(info->IER, info->ioaddr + UART_IER); | |
431 | } | |
432 | ||
433 | static void mxser_start_tx(struct mxser_port *info) | |
434 | { | |
435 | unsigned long flags; | |
436 | ||
437 | spin_lock_irqsave(&info->slock, flags); | |
438 | __mxser_start_tx(info); | |
439 | spin_unlock_irqrestore(&info->slock, flags); | |
440 | } | |
441 | ||
442 | static void __mxser_stop_tx(struct mxser_port *info) | |
443 | { | |
444 | info->IER &= ~UART_IER_THRI; | |
445 | outb(info->IER, info->ioaddr + UART_IER); | |
446 | } | |
447 | ||
31f35939 AC |
448 | static int mxser_carrier_raised(struct tty_port *port) |
449 | { | |
450 | struct mxser_port *mp = container_of(port, struct mxser_port, port); | |
451 | return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0; | |
452 | } | |
453 | ||
fcc8ac18 | 454 | static void mxser_dtr_rts(struct tty_port *port, int on) |
5d951fb4 AC |
455 | { |
456 | struct mxser_port *mp = container_of(port, struct mxser_port, port); | |
457 | unsigned long flags; | |
007bbdc8 | 458 | u8 mcr; |
5d951fb4 AC |
459 | |
460 | spin_lock_irqsave(&mp->slock, flags); | |
007bbdc8 | 461 | mcr = inb(mp->ioaddr + UART_MCR); |
fcc8ac18 | 462 | if (on) |
007bbdc8 | 463 | mcr |= UART_MCR_DTR | UART_MCR_RTS; |
fcc8ac18 | 464 | else |
007bbdc8 JS |
465 | mcr &= ~(UART_MCR_DTR | UART_MCR_RTS); |
466 | outb(mcr, mp->ioaddr + UART_MCR); | |
5d951fb4 AC |
467 | spin_unlock_irqrestore(&mp->slock, flags); |
468 | } | |
469 | ||
dc33f644 | 470 | static int mxser_set_baud(struct tty_struct *tty, speed_t newspd) |
1da177e4 | 471 | { |
216ba023 | 472 | struct mxser_port *info = tty->driver_data; |
104583b5 | 473 | unsigned int quot = 0, baud; |
1c45607a | 474 | unsigned char cval; |
104583b5 | 475 | u64 timeout; |
1da177e4 | 476 | |
928f9464 | 477 | if (newspd > info->board->max_baud) |
1c45607a | 478 | return -1; |
1da177e4 | 479 | |
1c45607a | 480 | if (newspd == 134) { |
a6970c39 | 481 | quot = 2 * MXSER_BAUD_BASE / 269; |
216ba023 | 482 | tty_encode_baud_rate(tty, 134, 134); |
1c45607a | 483 | } else if (newspd) { |
a6970c39 | 484 | quot = MXSER_BAUD_BASE / newspd; |
1c45607a JS |
485 | if (quot == 0) |
486 | quot = 1; | |
a6970c39 | 487 | baud = MXSER_BAUD_BASE / quot; |
216ba023 | 488 | tty_encode_baud_rate(tty, baud, baud); |
1c45607a JS |
489 | } else { |
490 | quot = 0; | |
491 | } | |
1da177e4 | 492 | |
104583b5 JS |
493 | /* |
494 | * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the | |
495 | * u64 domain | |
496 | */ | |
497 | timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot; | |
a6970c39 | 498 | do_div(timeout, MXSER_BAUD_BASE); |
104583b5 | 499 | info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */ |
1da177e4 | 500 | |
1c45607a JS |
501 | if (quot) { |
502 | info->MCR |= UART_MCR_DTR; | |
503 | outb(info->MCR, info->ioaddr + UART_MCR); | |
504 | } else { | |
505 | info->MCR &= ~UART_MCR_DTR; | |
506 | outb(info->MCR, info->ioaddr + UART_MCR); | |
507 | return 0; | |
508 | } | |
1da177e4 | 509 | |
1c45607a | 510 | cval = inb(info->ioaddr + UART_LCR); |
1da177e4 | 511 | |
1c45607a | 512 | outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */ |
1da177e4 | 513 | |
1c45607a JS |
514 | outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */ |
515 | outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */ | |
516 | outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */ | |
1da177e4 | 517 | |
1c45607a | 518 | #ifdef BOTHER |
216ba023 | 519 | if (C_BAUD(tty) == BOTHER) { |
a6970c39 | 520 | quot = MXSER_BAUD_BASE % newspd; |
1c45607a JS |
521 | quot *= 8; |
522 | if (quot % newspd > newspd / 2) { | |
523 | quot /= newspd; | |
524 | quot++; | |
525 | } else | |
526 | quot /= newspd; | |
527 | ||
148ff86b | 528 | mxser_set_must_enum_value(info->ioaddr, quot); |
1c45607a JS |
529 | } else |
530 | #endif | |
148ff86b | 531 | mxser_set_must_enum_value(info->ioaddr, 0); |
1da177e4 | 532 | |
8ea2c2ec | 533 | return 0; |
1da177e4 | 534 | } |
1da177e4 | 535 | |
be486667 JS |
536 | static void mxser_handle_cts(struct tty_struct *tty, struct mxser_port *info, |
537 | u8 msr) | |
538 | { | |
539 | bool cts = msr & UART_MSR_CTS; | |
540 | ||
541 | if (tty->hw_stopped) { | |
542 | if (cts) { | |
543 | tty->hw_stopped = 0; | |
544 | ||
5d1ea1ad | 545 | if (!mxser_16550A_or_MUST(info)) |
740165f7 | 546 | __mxser_start_tx(info); |
be486667 JS |
547 | tty_wakeup(tty); |
548 | } | |
549 | return; | |
550 | } else if (cts) | |
551 | return; | |
552 | ||
553 | tty->hw_stopped = 1; | |
5d1ea1ad | 554 | if (!mxser_16550A_or_MUST(info)) |
740165f7 | 555 | __mxser_stop_tx(info); |
be486667 JS |
556 | } |
557 | ||
1c45607a JS |
558 | /* |
559 | * This routine is called to set the UART divisor registers to match | |
560 | * the specified baud rate for a serial port. | |
561 | */ | |
3fdfa165 | 562 | static void mxser_change_speed(struct tty_struct *tty, struct ktermios *old_termios) |
1da177e4 | 563 | { |
216ba023 | 564 | struct mxser_port *info = tty->driver_data; |
1c45607a | 565 | unsigned cflag, cval, fcr; |
1da177e4 | 566 | |
adc8d746 | 567 | cflag = tty->termios.c_cflag; |
1da177e4 | 568 | |
3fdfa165 JS |
569 | if (mxser_set_baud(tty, tty_get_baud_rate(tty))) { |
570 | /* Use previous rate on a failure */ | |
571 | if (old_termios) { | |
572 | speed_t baud = tty_termios_baud_rate(old_termios); | |
573 | tty_encode_baud_rate(tty, baud, baud); | |
574 | } | |
575 | } | |
1da177e4 | 576 | |
1c45607a JS |
577 | /* byte size and parity */ |
578 | switch (cflag & CSIZE) { | |
2c21832b | 579 | default: |
1c45607a | 580 | case CS5: |
2c21832b | 581 | cval = UART_LCR_WLEN5; |
1c45607a JS |
582 | break; |
583 | case CS6: | |
2c21832b | 584 | cval = UART_LCR_WLEN6; |
1c45607a JS |
585 | break; |
586 | case CS7: | |
2c21832b | 587 | cval = UART_LCR_WLEN7; |
1c45607a JS |
588 | break; |
589 | case CS8: | |
2c21832b | 590 | cval = UART_LCR_WLEN8; |
1c45607a | 591 | break; |
1c45607a | 592 | } |
2c21832b | 593 | |
1c45607a | 594 | if (cflag & CSTOPB) |
2c21832b | 595 | cval |= UART_LCR_STOP; |
1c45607a JS |
596 | if (cflag & PARENB) |
597 | cval |= UART_LCR_PARITY; | |
598 | if (!(cflag & PARODD)) | |
599 | cval |= UART_LCR_EPAR; | |
600 | if (cflag & CMSPAR) | |
601 | cval |= UART_LCR_SPAR; | |
1da177e4 | 602 | |
1c45607a | 603 | if ((info->type == PORT_8250) || (info->type == PORT_16450)) { |
292955a7 | 604 | if (info->board->must_hwid) { |
1c45607a JS |
605 | fcr = UART_FCR_ENABLE_FIFO; |
606 | fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; | |
148ff86b | 607 | mxser_set_must_fifo_value(info); |
1c45607a JS |
608 | } else |
609 | fcr = 0; | |
610 | } else { | |
611 | fcr = UART_FCR_ENABLE_FIFO; | |
292955a7 | 612 | if (info->board->must_hwid) { |
1c45607a | 613 | fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; |
148ff86b | 614 | mxser_set_must_fifo_value(info); |
1c45607a | 615 | } else { |
dc33f644 | 616 | switch (info->rx_high_water) { |
1c45607a JS |
617 | case 1: |
618 | fcr |= UART_FCR_TRIGGER_1; | |
619 | break; | |
620 | case 4: | |
621 | fcr |= UART_FCR_TRIGGER_4; | |
622 | break; | |
623 | case 8: | |
624 | fcr |= UART_FCR_TRIGGER_8; | |
625 | break; | |
626 | default: | |
627 | fcr |= UART_FCR_TRIGGER_14; | |
628 | break; | |
629 | } | |
1da177e4 | 630 | } |
1da177e4 LT |
631 | } |
632 | ||
1c45607a JS |
633 | /* CTS flow control flag and modem status interrupts */ |
634 | info->IER &= ~UART_IER_MSI; | |
635 | info->MCR &= ~UART_MCR_AFE; | |
5604a98e | 636 | tty_port_set_cts_flow(&info->port, cflag & CRTSCTS); |
1c45607a | 637 | if (cflag & CRTSCTS) { |
1c45607a | 638 | info->IER |= UART_IER_MSI; |
5d1ea1ad | 639 | if (mxser_16550A_or_MUST(info)) { |
1c45607a JS |
640 | info->MCR |= UART_MCR_AFE; |
641 | } else { | |
be486667 JS |
642 | mxser_handle_cts(tty, info, |
643 | inb(info->ioaddr + UART_MSR)); | |
1da177e4 | 644 | } |
1c45607a JS |
645 | } |
646 | outb(info->MCR, info->ioaddr + UART_MCR); | |
2d68655d PH |
647 | tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL); |
648 | if (~cflag & CLOCAL) | |
1c45607a | 649 | info->IER |= UART_IER_MSI; |
1c45607a JS |
650 | outb(info->IER, info->ioaddr + UART_IER); |
651 | ||
652 | /* | |
653 | * Set up parity check flag | |
654 | */ | |
655 | info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
216ba023 | 656 | if (I_INPCK(tty)) |
1c45607a | 657 | info->read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
216ba023 | 658 | if (I_BRKINT(tty) || I_PARMRK(tty)) |
1c45607a | 659 | info->read_status_mask |= UART_LSR_BI; |
1da177e4 | 660 | |
1c45607a | 661 | info->ignore_status_mask = 0; |
1da177e4 | 662 | |
216ba023 | 663 | if (I_IGNBRK(tty)) { |
1c45607a JS |
664 | info->ignore_status_mask |= UART_LSR_BI; |
665 | info->read_status_mask |= UART_LSR_BI; | |
8ea2c2ec | 666 | /* |
1c45607a JS |
667 | * If we're ignore parity and break indicators, ignore |
668 | * overruns too. (For real raw support). | |
8ea2c2ec | 669 | */ |
216ba023 | 670 | if (I_IGNPAR(tty)) { |
1c45607a JS |
671 | info->ignore_status_mask |= |
672 | UART_LSR_OE | | |
673 | UART_LSR_PE | | |
674 | UART_LSR_FE; | |
675 | info->read_status_mask |= | |
676 | UART_LSR_OE | | |
677 | UART_LSR_PE | | |
678 | UART_LSR_FE; | |
679 | } | |
1da177e4 | 680 | } |
292955a7 | 681 | if (info->board->must_hwid) { |
216ba023 AC |
682 | mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty)); |
683 | mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty)); | |
b441eb0f JS |
684 | mxser_must_set_rx_sw_flow_control(info->ioaddr, I_IXON(tty)); |
685 | mxser_must_set_tx_sw_flow_control(info->ioaddr, I_IXOFF(tty)); | |
1da177e4 | 686 | } |
1da177e4 | 687 | |
1da177e4 | 688 | |
1c45607a JS |
689 | outb(fcr, info->ioaddr + UART_FCR); /* set fcr */ |
690 | outb(cval, info->ioaddr + UART_LCR); | |
1da177e4 LT |
691 | } |
692 | ||
216ba023 AC |
693 | static void mxser_check_modem_status(struct tty_struct *tty, |
694 | struct mxser_port *port, int status) | |
1da177e4 | 695 | { |
1c45607a JS |
696 | /* update input line counters */ |
697 | if (status & UART_MSR_TERI) | |
698 | port->icount.rng++; | |
699 | if (status & UART_MSR_DDSR) | |
700 | port->icount.dsr++; | |
701 | if (status & UART_MSR_DDCD) | |
702 | port->icount.dcd++; | |
703 | if (status & UART_MSR_DCTS) | |
704 | port->icount.cts++; | |
bdc04e31 | 705 | wake_up_interruptible(&port->port.delta_msr_wait); |
1da177e4 | 706 | |
2d68655d | 707 | if (tty_port_check_carrier(&port->port) && (status & UART_MSR_DDCD)) { |
1c45607a | 708 | if (status & UART_MSR_DCD) |
0ad9e7d1 | 709 | wake_up_interruptible(&port->port.open_wait); |
1c45607a | 710 | } |
1da177e4 | 711 | |
be486667 JS |
712 | if (tty_port_cts_enabled(&port->port)) |
713 | mxser_handle_cts(tty, port, status); | |
1da177e4 LT |
714 | } |
715 | ||
6769140d | 716 | static int mxser_activate(struct tty_port *port, struct tty_struct *tty) |
1da177e4 | 717 | { |
6769140d | 718 | struct mxser_port *info = container_of(port, struct mxser_port, port); |
1c45607a JS |
719 | unsigned long page; |
720 | unsigned long flags; | |
1da177e4 | 721 | |
1c45607a JS |
722 | page = __get_free_page(GFP_KERNEL); |
723 | if (!page) | |
724 | return -ENOMEM; | |
1da177e4 | 725 | |
1c45607a | 726 | spin_lock_irqsave(&info->slock, flags); |
1da177e4 | 727 | |
987a4cfe | 728 | if (!info->type) { |
216ba023 | 729 | set_bit(TTY_IO_ERROR, &tty->flags); |
1c45607a JS |
730 | free_page(page); |
731 | spin_unlock_irqrestore(&info->slock, flags); | |
1da177e4 | 732 | return 0; |
1c45607a | 733 | } |
6769140d | 734 | info->port.xmit_buf = (unsigned char *) page; |
1da177e4 | 735 | |
1da177e4 | 736 | /* |
1c45607a JS |
737 | * Clear the FIFO buffers and disable them |
738 | * (they will be reenabled in mxser_change_speed()) | |
1da177e4 | 739 | */ |
292955a7 | 740 | if (info->board->must_hwid) |
1c45607a JS |
741 | outb((UART_FCR_CLEAR_RCVR | |
742 | UART_FCR_CLEAR_XMIT | | |
743 | MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR); | |
744 | else | |
745 | outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), | |
746 | info->ioaddr + UART_FCR); | |
1da177e4 | 747 | |
1c45607a JS |
748 | /* |
749 | * At this point there's no way the LSR could still be 0xFF; | |
750 | * if it is, then bail out, because there's likely no UART | |
751 | * here. | |
752 | */ | |
753 | if (inb(info->ioaddr + UART_LSR) == 0xff) { | |
754 | spin_unlock_irqrestore(&info->slock, flags); | |
755 | if (capable(CAP_SYS_ADMIN)) { | |
f43a510d | 756 | set_bit(TTY_IO_ERROR, &tty->flags); |
1c45607a JS |
757 | return 0; |
758 | } else | |
759 | return -ENODEV; | |
760 | } | |
1da177e4 | 761 | |
1c45607a JS |
762 | /* |
763 | * Clear the interrupt registers. | |
764 | */ | |
765 | (void) inb(info->ioaddr + UART_LSR); | |
766 | (void) inb(info->ioaddr + UART_RX); | |
767 | (void) inb(info->ioaddr + UART_IIR); | |
768 | (void) inb(info->ioaddr + UART_MSR); | |
769 | ||
770 | /* | |
771 | * Now, initialize the UART | |
772 | */ | |
773 | outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */ | |
774 | info->MCR = UART_MCR_DTR | UART_MCR_RTS; | |
775 | outb(info->MCR, info->ioaddr + UART_MCR); | |
776 | ||
777 | /* | |
778 | * Finally, enable interrupts | |
779 | */ | |
780 | info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; | |
781 | ||
292955a7 | 782 | if (info->board->must_hwid) |
1c45607a JS |
783 | info->IER |= MOXA_MUST_IER_EGDAI; |
784 | outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */ | |
785 | ||
786 | /* | |
787 | * And clear the interrupt registers again for luck. | |
788 | */ | |
789 | (void) inb(info->ioaddr + UART_LSR); | |
790 | (void) inb(info->ioaddr + UART_RX); | |
791 | (void) inb(info->ioaddr + UART_IIR); | |
792 | (void) inb(info->ioaddr + UART_MSR); | |
793 | ||
216ba023 | 794 | clear_bit(TTY_IO_ERROR, &tty->flags); |
1c45607a JS |
795 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; |
796 | ||
797 | /* | |
798 | * and set the speed of the serial port | |
799 | */ | |
3fdfa165 | 800 | mxser_change_speed(tty, NULL); |
1c45607a JS |
801 | spin_unlock_irqrestore(&info->slock, flags); |
802 | ||
803 | return 0; | |
804 | } | |
805 | ||
806 | /* | |
6769140d | 807 | * This routine will shutdown a serial port |
1c45607a | 808 | */ |
6769140d | 809 | static void mxser_shutdown_port(struct tty_port *port) |
1c45607a | 810 | { |
6769140d | 811 | struct mxser_port *info = container_of(port, struct mxser_port, port); |
1c45607a JS |
812 | unsigned long flags; |
813 | ||
1c45607a JS |
814 | spin_lock_irqsave(&info->slock, flags); |
815 | ||
816 | /* | |
817 | * clear delta_msr_wait queue to avoid mem leaks: we may free the irq | |
818 | * here so the queue might never be waken up | |
819 | */ | |
bdc04e31 | 820 | wake_up_interruptible(&info->port.delta_msr_wait); |
1c45607a JS |
821 | |
822 | /* | |
6769140d | 823 | * Free the xmit buffer, if necessary |
1c45607a | 824 | */ |
0ad9e7d1 AC |
825 | if (info->port.xmit_buf) { |
826 | free_page((unsigned long) info->port.xmit_buf); | |
827 | info->port.xmit_buf = NULL; | |
1da177e4 LT |
828 | } |
829 | ||
1c45607a JS |
830 | info->IER = 0; |
831 | outb(0x00, info->ioaddr + UART_IER); | |
832 | ||
1c45607a | 833 | /* clear Rx/Tx FIFO's */ |
292955a7 | 834 | if (info->board->must_hwid) |
1c45607a JS |
835 | outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | |
836 | MOXA_MUST_FCR_GDA_MODE_ENABLE, | |
837 | info->ioaddr + UART_FCR); | |
838 | else | |
839 | outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, | |
840 | info->ioaddr + UART_FCR); | |
841 | ||
842 | /* read data port to reset things */ | |
843 | (void) inb(info->ioaddr + UART_RX); | |
844 | ||
1c45607a | 845 | |
292955a7 | 846 | if (info->board->must_hwid) |
b441eb0f | 847 | mxser_must_no_sw_flow_control(info->ioaddr); |
1c45607a JS |
848 | |
849 | spin_unlock_irqrestore(&info->slock, flags); | |
850 | } | |
851 | ||
852 | /* | |
853 | * This routine is called whenever a serial port is opened. It | |
854 | * enables interrupts for a serial port, linking in its async structure into | |
855 | * the IRQ chain. It also performs the serial-specific | |
856 | * initialization for the tty structure. | |
857 | */ | |
858 | static int mxser_open(struct tty_struct *tty, struct file *filp) | |
859 | { | |
42ad25fc JS |
860 | struct tty_port *tport = tty->port; |
861 | struct mxser_port *port = container_of(tport, struct mxser_port, port); | |
1c45607a | 862 | |
42ad25fc | 863 | tty->driver_data = port; |
1c45607a | 864 | |
42ad25fc | 865 | return tty_port_open(tport, tty, filp); |
1da177e4 LT |
866 | } |
867 | ||
978e595f AC |
868 | static void mxser_flush_buffer(struct tty_struct *tty) |
869 | { | |
870 | struct mxser_port *info = tty->driver_data; | |
871 | char fcr; | |
872 | unsigned long flags; | |
873 | ||
874 | ||
875 | spin_lock_irqsave(&info->slock, flags); | |
876 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; | |
877 | ||
878 | fcr = inb(info->ioaddr + UART_FCR); | |
879 | outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), | |
880 | info->ioaddr + UART_FCR); | |
881 | outb(fcr, info->ioaddr + UART_FCR); | |
882 | ||
883 | spin_unlock_irqrestore(&info->slock, flags); | |
884 | ||
885 | tty_wakeup(tty); | |
886 | } | |
887 | ||
888 | ||
6769140d | 889 | static void mxser_close_port(struct tty_port *port) |
1da177e4 | 890 | { |
1e2b0254 | 891 | struct mxser_port *info = container_of(port, struct mxser_port, port); |
1da177e4 | 892 | unsigned long timeout; |
1da177e4 LT |
893 | /* |
894 | * At this point we stop accepting input. To do this, we | |
895 | * disable the receive line status interrupts, and tell the | |
896 | * interrupt driver to stop checking the data ready bit in the | |
897 | * line status register. | |
898 | */ | |
899 | info->IER &= ~UART_IER_RLSI; | |
292955a7 | 900 | if (info->board->must_hwid) |
1da177e4 | 901 | info->IER &= ~MOXA_MUST_RECV_ISR; |
1c45607a | 902 | |
6769140d AC |
903 | outb(info->IER, info->ioaddr + UART_IER); |
904 | /* | |
905 | * Before we drop DTR, make sure the UART transmitter | |
906 | * has completely drained; this is especially | |
907 | * important if there is a transmit FIFO! | |
908 | */ | |
909 | timeout = jiffies + HZ; | |
910 | while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) { | |
911 | schedule_timeout_interruptible(5); | |
912 | if (time_after(jiffies, timeout)) | |
913 | break; | |
1da177e4 | 914 | } |
1e2b0254 AC |
915 | } |
916 | ||
917 | /* | |
918 | * This routine is called when the serial port gets closed. First, we | |
919 | * wait for the last remaining data to be sent. Then, we unlink its | |
920 | * async structure from the interrupt chain if necessary, and we free | |
921 | * that IRQ if nothing is left in the chain. | |
922 | */ | |
923 | static void mxser_close(struct tty_struct *tty, struct file *filp) | |
924 | { | |
925 | struct mxser_port *info = tty->driver_data; | |
926 | struct tty_port *port = &info->port; | |
927 | ||
389fc82e | 928 | if (info == NULL) |
1e2b0254 AC |
929 | return; |
930 | if (tty_port_close_start(port, tty, filp) == 0) | |
931 | return; | |
cd7b4b39 | 932 | info->closing = 1; |
6769140d AC |
933 | mutex_lock(&port->mutex); |
934 | mxser_close_port(port); | |
1e2b0254 | 935 | mxser_flush_buffer(tty); |
d41861ca PH |
936 | if (tty_port_initialized(port) && C_HUPCL(tty)) |
937 | tty_port_lower_dtr_rts(port); | |
6769140d | 938 | mxser_shutdown_port(port); |
d41861ca | 939 | tty_port_set_initialized(port, 0); |
6769140d | 940 | mutex_unlock(&port->mutex); |
cd7b4b39 | 941 | info->closing = 0; |
a6614999 AC |
942 | /* Right now the tty_port set is done outside of the close_end helper |
943 | as we don't yet have everyone using refcounts */ | |
944 | tty_port_close_end(port, tty); | |
945 | tty_port_tty_set(port, NULL); | |
1da177e4 LT |
946 | } |
947 | ||
948 | static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count) | |
949 | { | |
950 | int c, total = 0; | |
1c45607a | 951 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
952 | unsigned long flags; |
953 | ||
0ad9e7d1 | 954 | if (!info->port.xmit_buf) |
8ea2c2ec | 955 | return 0; |
1da177e4 LT |
956 | |
957 | while (1) { | |
8ea2c2ec JJ |
958 | c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, |
959 | SERIAL_XMIT_SIZE - info->xmit_head)); | |
1da177e4 LT |
960 | if (c <= 0) |
961 | break; | |
962 | ||
0ad9e7d1 | 963 | memcpy(info->port.xmit_buf + info->xmit_head, buf, c); |
1da177e4 | 964 | spin_lock_irqsave(&info->slock, flags); |
8ea2c2ec JJ |
965 | info->xmit_head = (info->xmit_head + c) & |
966 | (SERIAL_XMIT_SIZE - 1); | |
1da177e4 LT |
967 | info->xmit_cnt += c; |
968 | spin_unlock_irqrestore(&info->slock, flags); | |
969 | ||
970 | buf += c; | |
971 | count -= c; | |
972 | total += c; | |
1da177e4 LT |
973 | } |
974 | ||
5d1ea1ad JS |
975 | if (info->xmit_cnt && !tty->flow.stopped) |
976 | if (!tty->hw_stopped || mxser_16550A_or_MUST(info)) | |
740165f7 | 977 | mxser_start_tx(info); |
5d1ea1ad | 978 | |
1da177e4 LT |
979 | return total; |
980 | } | |
981 | ||
0be2eade | 982 | static int mxser_put_char(struct tty_struct *tty, unsigned char ch) |
1da177e4 | 983 | { |
1c45607a | 984 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
985 | unsigned long flags; |
986 | ||
0ad9e7d1 | 987 | if (!info->port.xmit_buf) |
0be2eade | 988 | return 0; |
1da177e4 LT |
989 | |
990 | if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1) | |
0be2eade | 991 | return 0; |
1da177e4 LT |
992 | |
993 | spin_lock_irqsave(&info->slock, flags); | |
0ad9e7d1 | 994 | info->port.xmit_buf[info->xmit_head++] = ch; |
1da177e4 LT |
995 | info->xmit_head &= SERIAL_XMIT_SIZE - 1; |
996 | info->xmit_cnt++; | |
997 | spin_unlock_irqrestore(&info->slock, flags); | |
8aff64e0 | 998 | |
0be2eade | 999 | return 1; |
1da177e4 LT |
1000 | } |
1001 | ||
1002 | ||
1003 | static void mxser_flush_chars(struct tty_struct *tty) | |
1004 | { | |
1c45607a | 1005 | struct mxser_port *info = tty->driver_data; |
1da177e4 | 1006 | |
265ceff7 | 1007 | if (!info->xmit_cnt || tty->flow.stopped || !info->port.xmit_buf || |
5d1ea1ad | 1008 | (tty->hw_stopped && !mxser_16550A_or_MUST(info))) |
1da177e4 LT |
1009 | return; |
1010 | ||
740165f7 | 1011 | mxser_start_tx(info); |
1da177e4 LT |
1012 | } |
1013 | ||
03b3b1a2 | 1014 | static unsigned int mxser_write_room(struct tty_struct *tty) |
1da177e4 | 1015 | { |
1c45607a | 1016 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
1017 | int ret; |
1018 | ||
1019 | ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1; | |
ace7dd96 | 1020 | return ret < 0 ? 0 : ret; |
1da177e4 LT |
1021 | } |
1022 | ||
fff4ef17 | 1023 | static unsigned int mxser_chars_in_buffer(struct tty_struct *tty) |
1da177e4 | 1024 | { |
1c45607a | 1025 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
1026 | return info->xmit_cnt; |
1027 | } | |
1028 | ||
1c45607a JS |
1029 | /* |
1030 | * ------------------------------------------------------------ | |
1031 | * friends of mxser_ioctl() | |
1032 | * ------------------------------------------------------------ | |
1033 | */ | |
216ba023 | 1034 | static int mxser_get_serial_info(struct tty_struct *tty, |
6da5b587 | 1035 | struct serial_struct *ss) |
1c45607a | 1036 | { |
216ba023 | 1037 | struct mxser_port *info = tty->driver_data; |
6da5b587 | 1038 | struct tty_port *port = &info->port; |
be6cf583 | 1039 | unsigned int closing_wait, close_delay; |
6da5b587 | 1040 | |
6da5b587 | 1041 | mutex_lock(&port->mutex); |
be6cf583 JH |
1042 | |
1043 | close_delay = jiffies_to_msecs(info->port.close_delay) / 10; | |
1044 | closing_wait = info->port.closing_wait; | |
1045 | if (closing_wait != ASYNC_CLOSING_WAIT_NONE) | |
1046 | closing_wait = jiffies_to_msecs(closing_wait) / 10; | |
1047 | ||
2285c496 DC |
1048 | ss->type = info->type; |
1049 | ss->line = tty->index; | |
1050 | ss->port = info->ioaddr; | |
1051 | ss->irq = info->board->irq; | |
1052 | ss->flags = info->port.flags; | |
1053 | ss->baud_base = MXSER_BAUD_BASE; | |
be6cf583 JH |
1054 | ss->close_delay = close_delay; |
1055 | ss->closing_wait = closing_wait; | |
d811b26b | 1056 | ss->custom_divisor = MXSER_CUSTOM_DIVISOR, |
6da5b587 | 1057 | mutex_unlock(&port->mutex); |
1c45607a JS |
1058 | return 0; |
1059 | } | |
1060 | ||
216ba023 | 1061 | static int mxser_set_serial_info(struct tty_struct *tty, |
6da5b587 | 1062 | struct serial_struct *ss) |
1da177e4 | 1063 | { |
216ba023 | 1064 | struct mxser_port *info = tty->driver_data; |
07f86c03 | 1065 | struct tty_port *port = &info->port; |
80ff8a80 | 1066 | speed_t baud; |
1c45607a | 1067 | unsigned long sl_flags; |
06cc52ef | 1068 | unsigned int old_speed, close_delay, closing_wait; |
1c45607a | 1069 | int retval = 0; |
1da177e4 | 1070 | |
6da5b587 AV |
1071 | if (tty_io_error(tty)) |
1072 | return -EIO; | |
1073 | ||
1074 | mutex_lock(&port->mutex); | |
1da177e4 | 1075 | |
6da5b587 AV |
1076 | if (ss->irq != info->board->irq || |
1077 | ss->port != info->ioaddr) { | |
1078 | mutex_unlock(&port->mutex); | |
80ff8a80 | 1079 | return -EINVAL; |
6da5b587 | 1080 | } |
1da177e4 | 1081 | |
06cc52ef | 1082 | old_speed = port->flags & ASYNC_SPD_MASK; |
1da177e4 | 1083 | |
be6cf583 JH |
1084 | close_delay = msecs_to_jiffies(ss->close_delay * 10); |
1085 | closing_wait = ss->closing_wait; | |
1086 | if (closing_wait != ASYNC_CLOSING_WAIT_NONE) | |
1087 | closing_wait = msecs_to_jiffies(closing_wait * 10); | |
1088 | ||
1c45607a | 1089 | if (!capable(CAP_SYS_ADMIN)) { |
a6970c39 | 1090 | if ((ss->baud_base != MXSER_BAUD_BASE) || |
1b3086b6 JS |
1091 | (close_delay != port->close_delay) || |
1092 | (closing_wait != port->closing_wait) || | |
1093 | ((ss->flags & ~ASYNC_USR_MASK) != (port->flags & ~ASYNC_USR_MASK))) { | |
6da5b587 | 1094 | mutex_unlock(&port->mutex); |
1c45607a | 1095 | return -EPERM; |
6da5b587 | 1096 | } |
1b3086b6 JS |
1097 | port->flags = (port->flags & ~ASYNC_USR_MASK) | |
1098 | (ss->flags & ASYNC_USR_MASK); | |
1c45607a | 1099 | } else { |
1da177e4 | 1100 | /* |
1c45607a JS |
1101 | * OK, past this point, all the error checking has been done. |
1102 | * At this point, we start making changes..... | |
1da177e4 | 1103 | */ |
07f86c03 | 1104 | port->flags = ((port->flags & ~ASYNC_FLAGS) | |
6da5b587 | 1105 | (ss->flags & ASYNC_FLAGS)); |
be6cf583 JH |
1106 | port->close_delay = close_delay; |
1107 | port->closing_wait = closing_wait; | |
07f86c03 | 1108 | if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST && |
a6970c39 | 1109 | (ss->baud_base != MXSER_BAUD_BASE || |
6da5b587 | 1110 | ss->custom_divisor != |
d811b26b | 1111 | MXSER_CUSTOM_DIVISOR)) { |
6da5b587 AV |
1112 | if (ss->custom_divisor == 0) { |
1113 | mutex_unlock(&port->mutex); | |
07f86c03 | 1114 | return -EINVAL; |
6da5b587 AV |
1115 | } |
1116 | baud = ss->baud_base / ss->custom_divisor; | |
216ba023 | 1117 | tty_encode_baud_rate(tty, baud, baud); |
80ff8a80 | 1118 | } |
fc83815c | 1119 | |
b91cfb25 | 1120 | info->type = ss->type; |
1da177e4 | 1121 | |
c3db20c3 | 1122 | mxser_process_txrx_fifo(info); |
b91cfb25 | 1123 | } |
1c45607a | 1124 | |
d41861ca | 1125 | if (tty_port_initialized(port)) { |
06cc52ef | 1126 | if (old_speed != (port->flags & ASYNC_SPD_MASK)) { |
1c45607a | 1127 | spin_lock_irqsave(&info->slock, sl_flags); |
3fdfa165 | 1128 | mxser_change_speed(tty, NULL); |
1c45607a | 1129 | spin_unlock_irqrestore(&info->slock, sl_flags); |
1da177e4 | 1130 | } |
6769140d | 1131 | } else { |
07f86c03 | 1132 | retval = mxser_activate(port, tty); |
6769140d | 1133 | if (retval == 0) |
d41861ca | 1134 | tty_port_set_initialized(port, 1); |
6769140d | 1135 | } |
6da5b587 | 1136 | mutex_unlock(&port->mutex); |
1c45607a JS |
1137 | return retval; |
1138 | } | |
1da177e4 | 1139 | |
1c45607a JS |
1140 | /* |
1141 | * mxser_get_lsr_info - get line status register info | |
1142 | * | |
1143 | * Purpose: Let user call ioctl() to get info when the UART physically | |
1144 | * is emptied. On bus types like RS485, the transmitter must | |
1145 | * release the bus after transmitting. This must be done when | |
1146 | * the transmit shift register is empty, not be done when the | |
1147 | * transmit holding register is empty. This functionality | |
1148 | * allows an RS485 driver to be written in user space. | |
1149 | */ | |
1150 | static int mxser_get_lsr_info(struct mxser_port *info, | |
1151 | unsigned int __user *value) | |
1152 | { | |
1153 | unsigned char status; | |
1154 | unsigned int result; | |
1155 | unsigned long flags; | |
1da177e4 | 1156 | |
1c45607a JS |
1157 | spin_lock_irqsave(&info->slock, flags); |
1158 | status = inb(info->ioaddr + UART_LSR); | |
1159 | spin_unlock_irqrestore(&info->slock, flags); | |
1160 | result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0); | |
1161 | return put_user(result, value); | |
1162 | } | |
1da177e4 | 1163 | |
60b33c13 | 1164 | static int mxser_tiocmget(struct tty_struct *tty) |
1c45607a JS |
1165 | { |
1166 | struct mxser_port *info = tty->driver_data; | |
1167 | unsigned char control, status; | |
1168 | unsigned long flags; | |
1da177e4 | 1169 | |
18900ca6 | 1170 | if (tty_io_error(tty)) |
1c45607a | 1171 | return -EIO; |
1da177e4 | 1172 | |
1c45607a | 1173 | spin_lock_irqsave(&info->slock, flags); |
202acdaa | 1174 | control = info->MCR; |
1c45607a JS |
1175 | status = inb(info->ioaddr + UART_MSR); |
1176 | if (status & UART_MSR_ANY_DELTA) | |
216ba023 | 1177 | mxser_check_modem_status(tty, info, status); |
1c45607a | 1178 | spin_unlock_irqrestore(&info->slock, flags); |
202acdaa | 1179 | |
1c45607a JS |
1180 | return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) | |
1181 | ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) | | |
1182 | ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) | | |
1183 | ((status & UART_MSR_RI) ? TIOCM_RNG : 0) | | |
1184 | ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) | | |
1185 | ((status & UART_MSR_CTS) ? TIOCM_CTS : 0); | |
1186 | } | |
1da177e4 | 1187 | |
20b9d177 | 1188 | static int mxser_tiocmset(struct tty_struct *tty, |
1c45607a JS |
1189 | unsigned int set, unsigned int clear) |
1190 | { | |
1191 | struct mxser_port *info = tty->driver_data; | |
1192 | unsigned long flags; | |
1da177e4 | 1193 | |
18900ca6 | 1194 | if (tty_io_error(tty)) |
1c45607a | 1195 | return -EIO; |
1da177e4 | 1196 | |
1c45607a | 1197 | spin_lock_irqsave(&info->slock, flags); |
1da177e4 | 1198 | |
1c45607a JS |
1199 | if (set & TIOCM_RTS) |
1200 | info->MCR |= UART_MCR_RTS; | |
1201 | if (set & TIOCM_DTR) | |
1202 | info->MCR |= UART_MCR_DTR; | |
1da177e4 | 1203 | |
1c45607a JS |
1204 | if (clear & TIOCM_RTS) |
1205 | info->MCR &= ~UART_MCR_RTS; | |
1206 | if (clear & TIOCM_DTR) | |
1207 | info->MCR &= ~UART_MCR_DTR; | |
8ea2c2ec | 1208 | |
1c45607a JS |
1209 | outb(info->MCR, info->ioaddr + UART_MCR); |
1210 | spin_unlock_irqrestore(&info->slock, flags); | |
1211 | return 0; | |
1212 | } | |
1da177e4 | 1213 | |
1c45607a JS |
1214 | static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg, |
1215 | struct async_icount *cprev) | |
1da177e4 | 1216 | { |
1c45607a JS |
1217 | struct async_icount cnow; |
1218 | unsigned long flags; | |
1219 | int ret; | |
1da177e4 | 1220 | |
1c45607a JS |
1221 | spin_lock_irqsave(&info->slock, flags); |
1222 | cnow = info->icount; /* atomic copy */ | |
1223 | spin_unlock_irqrestore(&info->slock, flags); | |
1da177e4 | 1224 | |
1c45607a JS |
1225 | ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) || |
1226 | ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) || | |
1227 | ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) || | |
1228 | ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts)); | |
1da177e4 | 1229 | |
1c45607a JS |
1230 | *cprev = cnow; |
1231 | ||
1232 | return ret; | |
1233 | } | |
1234 | ||
9fae5f85 JS |
1235 | /* We should likely switch to TIOCGRS485/TIOCSRS485. */ |
1236 | static int mxser_ioctl_op_mode(struct mxser_port *port, int index, bool set, | |
1237 | int __user *u_opmode) | |
1238 | { | |
9fae5f85 JS |
1239 | int opmode, p = index % 4; |
1240 | int shiftbit = p * 2; | |
238d117d | 1241 | u8 val; |
9fae5f85 JS |
1242 | |
1243 | if (port->board->must_hwid != MOXA_MUST_MU860_HWID) | |
1244 | return -EFAULT; | |
1245 | ||
1246 | if (set) { | |
1247 | if (get_user(opmode, u_opmode)) | |
1248 | return -EFAULT; | |
1249 | ||
238d117d JS |
1250 | if (opmode & ~OP_MODE_MASK) |
1251 | return -EINVAL; | |
9fae5f85 JS |
1252 | |
1253 | spin_lock_irq(&port->slock); | |
1254 | val = inb(port->opmode_ioaddr); | |
238d117d | 1255 | val &= ~(OP_MODE_MASK << shiftbit); |
9fae5f85 JS |
1256 | val |= (opmode << shiftbit); |
1257 | outb(val, port->opmode_ioaddr); | |
1258 | spin_unlock_irq(&port->slock); | |
9fae5f85 | 1259 | |
238d117d | 1260 | return 0; |
9fae5f85 JS |
1261 | } |
1262 | ||
238d117d JS |
1263 | spin_lock_irq(&port->slock); |
1264 | opmode = inb(port->opmode_ioaddr) >> shiftbit; | |
1265 | spin_unlock_irq(&port->slock); | |
1266 | ||
1267 | return put_user(opmode & OP_MODE_MASK, u_opmode); | |
9fae5f85 JS |
1268 | } |
1269 | ||
6caa76b7 | 1270 | static int mxser_ioctl(struct tty_struct *tty, |
1c45607a | 1271 | unsigned int cmd, unsigned long arg) |
1da177e4 | 1272 | { |
1c45607a JS |
1273 | struct mxser_port *info = tty->driver_data; |
1274 | struct async_icount cnow; | |
1c45607a JS |
1275 | unsigned long flags; |
1276 | void __user *argp = (void __user *)arg; | |
1da177e4 | 1277 | |
9fae5f85 JS |
1278 | if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) |
1279 | return mxser_ioctl_op_mode(info, tty->index, | |
1280 | cmd == MOXA_SET_OP_MODE, argp); | |
1c45607a | 1281 | |
6da5b587 | 1282 | if (cmd != TIOCMIWAIT && tty_io_error(tty)) |
1c45607a JS |
1283 | return -EIO; |
1284 | ||
1285 | switch (cmd) { | |
1c45607a | 1286 | case TIOCSERGETLSR: /* Get line status register */ |
9d6d162d | 1287 | return mxser_get_lsr_info(info, argp); |
1c45607a JS |
1288 | /* |
1289 | * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change | |
1290 | * - mask passed in arg for lines of interest | |
1291 | * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) | |
1292 | * Caller should use TIOCGICOUNT to see which one it was | |
1293 | */ | |
1294 | case TIOCMIWAIT: | |
1295 | spin_lock_irqsave(&info->slock, flags); | |
1296 | cnow = info->icount; /* note the counters on entry */ | |
1297 | spin_unlock_irqrestore(&info->slock, flags); | |
1298 | ||
bdc04e31 | 1299 | return wait_event_interruptible(info->port.delta_msr_wait, |
1c45607a | 1300 | mxser_cflags_changed(info, arg, &cnow)); |
1c45607a JS |
1301 | default: |
1302 | return -ENOIOCTLCMD; | |
1303 | } | |
1304 | return 0; | |
1305 | } | |
1306 | ||
0587102c AC |
1307 | /* |
1308 | * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) | |
1309 | * Return: write counters to the user passed counter struct | |
1310 | * NB: both 1->0 and 0->1 transitions are counted except for | |
1311 | * RI where only 0->1 is counted. | |
1312 | */ | |
1313 | ||
1314 | static int mxser_get_icount(struct tty_struct *tty, | |
1315 | struct serial_icounter_struct *icount) | |
1316 | ||
1317 | { | |
1318 | struct mxser_port *info = tty->driver_data; | |
1319 | struct async_icount cnow; | |
1320 | unsigned long flags; | |
1321 | ||
1322 | spin_lock_irqsave(&info->slock, flags); | |
1323 | cnow = info->icount; | |
1324 | spin_unlock_irqrestore(&info->slock, flags); | |
1325 | ||
1326 | icount->frame = cnow.frame; | |
1327 | icount->brk = cnow.brk; | |
1328 | icount->overrun = cnow.overrun; | |
1329 | icount->buf_overrun = cnow.buf_overrun; | |
1330 | icount->parity = cnow.parity; | |
1331 | icount->rx = cnow.rx; | |
1332 | icount->tx = cnow.tx; | |
1333 | icount->cts = cnow.cts; | |
1334 | icount->dsr = cnow.dsr; | |
1335 | icount->rng = cnow.rng; | |
1336 | icount->dcd = cnow.dcd; | |
1337 | return 0; | |
1338 | } | |
1339 | ||
1c45607a JS |
1340 | static void mxser_stoprx(struct tty_struct *tty) |
1341 | { | |
1342 | struct mxser_port *info = tty->driver_data; | |
1343 | ||
19236287 | 1344 | info->ldisc_stop_rx = true; |
1c45607a | 1345 | if (I_IXOFF(tty)) { |
292955a7 | 1346 | if (info->board->must_hwid) { |
1c45607a JS |
1347 | info->IER &= ~MOXA_MUST_RECV_ISR; |
1348 | outb(info->IER, info->ioaddr + UART_IER); | |
1349 | } else { | |
1350 | info->x_char = STOP_CHAR(tty); | |
1351 | outb(0, info->ioaddr + UART_IER); | |
1352 | info->IER |= UART_IER_THRI; | |
1353 | outb(info->IER, info->ioaddr + UART_IER); | |
1da177e4 LT |
1354 | } |
1355 | } | |
1356 | ||
9db276f8 | 1357 | if (C_CRTSCTS(tty)) { |
1c45607a JS |
1358 | info->MCR &= ~UART_MCR_RTS; |
1359 | outb(info->MCR, info->ioaddr + UART_MCR); | |
1da177e4 LT |
1360 | } |
1361 | } | |
1362 | ||
1363 | /* | |
1364 | * This routine is called by the upper-layer tty layer to signal that | |
1365 | * incoming characters should be throttled. | |
1366 | */ | |
1367 | static void mxser_throttle(struct tty_struct *tty) | |
1368 | { | |
1da177e4 | 1369 | mxser_stoprx(tty); |
1da177e4 LT |
1370 | } |
1371 | ||
1372 | static void mxser_unthrottle(struct tty_struct *tty) | |
1373 | { | |
1c45607a | 1374 | struct mxser_port *info = tty->driver_data; |
1da177e4 | 1375 | |
1c45607a | 1376 | /* startrx */ |
19236287 | 1377 | info->ldisc_stop_rx = false; |
1c45607a JS |
1378 | if (I_IXOFF(tty)) { |
1379 | if (info->x_char) | |
1380 | info->x_char = 0; | |
1381 | else { | |
292955a7 | 1382 | if (info->board->must_hwid) { |
1c45607a JS |
1383 | info->IER |= MOXA_MUST_RECV_ISR; |
1384 | outb(info->IER, info->ioaddr + UART_IER); | |
1385 | } else { | |
1386 | info->x_char = START_CHAR(tty); | |
1387 | outb(0, info->ioaddr + UART_IER); | |
1388 | info->IER |= UART_IER_THRI; | |
1389 | outb(info->IER, info->ioaddr + UART_IER); | |
1390 | } | |
1da177e4 | 1391 | } |
1c45607a | 1392 | } |
1da177e4 | 1393 | |
9db276f8 | 1394 | if (C_CRTSCTS(tty)) { |
1c45607a JS |
1395 | info->MCR |= UART_MCR_RTS; |
1396 | outb(info->MCR, info->ioaddr + UART_MCR); | |
1da177e4 LT |
1397 | } |
1398 | } | |
1399 | ||
1400 | /* | |
1401 | * mxser_stop() and mxser_start() | |
1402 | * | |
6e94dbc7 | 1403 | * This routines are called before setting or resetting tty->flow.stopped. |
1da177e4 LT |
1404 | * They enable or disable transmitter interrupts, as necessary. |
1405 | */ | |
1406 | static void mxser_stop(struct tty_struct *tty) | |
1407 | { | |
1c45607a | 1408 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
1409 | unsigned long flags; |
1410 | ||
1411 | spin_lock_irqsave(&info->slock, flags); | |
740165f7 JS |
1412 | if (info->IER & UART_IER_THRI) |
1413 | __mxser_stop_tx(info); | |
1da177e4 LT |
1414 | spin_unlock_irqrestore(&info->slock, flags); |
1415 | } | |
1416 | ||
1417 | static void mxser_start(struct tty_struct *tty) | |
1418 | { | |
1c45607a | 1419 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
1420 | unsigned long flags; |
1421 | ||
1422 | spin_lock_irqsave(&info->slock, flags); | |
740165f7 JS |
1423 | if (info->xmit_cnt && info->port.xmit_buf) |
1424 | __mxser_start_tx(info); | |
1da177e4 LT |
1425 | spin_unlock_irqrestore(&info->slock, flags); |
1426 | } | |
1427 | ||
1c45607a JS |
1428 | static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios) |
1429 | { | |
1430 | struct mxser_port *info = tty->driver_data; | |
1431 | unsigned long flags; | |
1432 | ||
1433 | spin_lock_irqsave(&info->slock, flags); | |
3fdfa165 | 1434 | mxser_change_speed(tty, old_termios); |
1c45607a JS |
1435 | spin_unlock_irqrestore(&info->slock, flags); |
1436 | ||
9db276f8 | 1437 | if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) { |
1c45607a JS |
1438 | tty->hw_stopped = 0; |
1439 | mxser_start(tty); | |
1440 | } | |
1441 | ||
1442 | /* Handle sw stopped */ | |
9db276f8 | 1443 | if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) { |
6e94dbc7 | 1444 | tty->flow.stopped = 0; |
1c45607a | 1445 | |
292955a7 | 1446 | if (info->board->must_hwid) { |
1c45607a | 1447 | spin_lock_irqsave(&info->slock, flags); |
b441eb0f | 1448 | mxser_must_set_rx_sw_flow_control(info->ioaddr, false); |
1c45607a JS |
1449 | spin_unlock_irqrestore(&info->slock, flags); |
1450 | } | |
1451 | ||
1452 | mxser_start(tty); | |
1453 | } | |
1454 | } | |
1455 | ||
1da177e4 LT |
1456 | /* |
1457 | * mxser_wait_until_sent() --- wait until the transmitter is empty | |
1458 | */ | |
1459 | static void mxser_wait_until_sent(struct tty_struct *tty, int timeout) | |
1460 | { | |
1c45607a | 1461 | struct mxser_port *info = tty->driver_data; |
1da177e4 | 1462 | unsigned long orig_jiffies, char_time; |
07f86c03 | 1463 | unsigned long flags; |
1da177e4 LT |
1464 | int lsr; |
1465 | ||
1466 | if (info->type == PORT_UNKNOWN) | |
1467 | return; | |
1468 | ||
1469 | if (info->xmit_fifo_size == 0) | |
1470 | return; /* Just in case.... */ | |
1471 | ||
1472 | orig_jiffies = jiffies; | |
1473 | /* | |
1474 | * Set the check interval to be 1/5 of the estimated time to | |
1475 | * send a single character, and make it at least 1. The check | |
1476 | * interval should also be less than the timeout. | |
1477 | * | |
1478 | * Note: we have to use pretty tight timings here to satisfy | |
1479 | * the NIST-PCTS. | |
1480 | */ | |
1481 | char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size; | |
1482 | char_time = char_time / 5; | |
1483 | if (char_time == 0) | |
1484 | char_time = 1; | |
1485 | if (timeout && timeout < char_time) | |
1486 | char_time = timeout; | |
1487 | /* | |
1488 | * If the transmitter hasn't cleared in twice the approximate | |
1489 | * amount of time to send the entire FIFO, it probably won't | |
1490 | * ever clear. This assumes the UART isn't doing flow | |
1491 | * control, which is currently the case. Hence, if it ever | |
1492 | * takes longer than info->timeout, this is probably due to a | |
1493 | * UART bug of some kind. So, we clamp the timeout parameter at | |
1494 | * 2*info->timeout. | |
1495 | */ | |
1496 | if (!timeout || timeout > 2 * info->timeout) | |
1497 | timeout = 2 * info->timeout; | |
8bab534b | 1498 | |
07f86c03 | 1499 | spin_lock_irqsave(&info->slock, flags); |
1c45607a | 1500 | while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) { |
07f86c03 | 1501 | spin_unlock_irqrestore(&info->slock, flags); |
da4cd8df | 1502 | schedule_timeout_interruptible(char_time); |
07f86c03 | 1503 | spin_lock_irqsave(&info->slock, flags); |
1da177e4 | 1504 | if (signal_pending(current)) |
1c45607a JS |
1505 | break; |
1506 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
1507 | break; | |
1da177e4 | 1508 | } |
07f86c03 | 1509 | spin_unlock_irqrestore(&info->slock, flags); |
1c45607a | 1510 | set_current_state(TASK_RUNNING); |
1c45607a | 1511 | } |
1da177e4 | 1512 | |
1c45607a JS |
1513 | /* |
1514 | * This routine is called by tty_hangup() when a hangup is signaled. | |
1515 | */ | |
1516 | static void mxser_hangup(struct tty_struct *tty) | |
1517 | { | |
1518 | struct mxser_port *info = tty->driver_data; | |
1da177e4 | 1519 | |
1c45607a | 1520 | mxser_flush_buffer(tty); |
3b6826b2 | 1521 | tty_port_hangup(&info->port); |
1da177e4 LT |
1522 | } |
1523 | ||
1c45607a JS |
1524 | /* |
1525 | * mxser_rs_break() --- routine which turns the break handling on or off | |
1526 | */ | |
9e98966c | 1527 | static int mxser_rs_break(struct tty_struct *tty, int break_state) |
1da177e4 | 1528 | { |
1c45607a | 1529 | struct mxser_port *info = tty->driver_data; |
1da177e4 | 1530 | unsigned long flags; |
59908433 | 1531 | u8 lcr; |
1da177e4 | 1532 | |
1c45607a | 1533 | spin_lock_irqsave(&info->slock, flags); |
59908433 | 1534 | lcr = inb(info->ioaddr + UART_LCR); |
1c45607a | 1535 | if (break_state == -1) |
59908433 | 1536 | lcr |= UART_LCR_SBC; |
1c45607a | 1537 | else |
59908433 JS |
1538 | lcr &= ~UART_LCR_SBC; |
1539 | outb(lcr, info->ioaddr + UART_LCR); | |
1c45607a | 1540 | spin_unlock_irqrestore(&info->slock, flags); |
59908433 | 1541 | |
9e98966c | 1542 | return 0; |
1c45607a | 1543 | } |
1da177e4 | 1544 | |
e5ce1bce | 1545 | static bool mxser_receive_chars_new(struct tty_struct *tty, |
95b3ea4c | 1546 | struct mxser_port *port, u8 status) |
e5ce1bce JS |
1547 | { |
1548 | enum mxser_must_hwid hwid = port->board->must_hwid; | |
1549 | u8 gdl; | |
1550 | ||
1551 | if (hwid == MOXA_OTHER_UART) | |
1552 | return false; | |
7d5006d5 | 1553 | if (status & (UART_LSR_BRK_ERROR_BITS | MOXA_MUST_LSR_RERR)) |
e5ce1bce JS |
1554 | return false; |
1555 | ||
1556 | gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER); | |
1557 | if (hwid == MOXA_MUST_MU150_HWID) | |
1558 | gdl &= MOXA_MUST_GDL_MASK; | |
1559 | ||
1560 | if (gdl >= tty->receive_room && !port->ldisc_stop_rx) | |
1561 | mxser_stoprx(tty); | |
1562 | ||
1563 | while (gdl--) { | |
1564 | u8 ch = inb(port->ioaddr + UART_RX); | |
1565 | tty_insert_flip_char(&port->port, ch, 0); | |
e5ce1bce JS |
1566 | } |
1567 | ||
1568 | return true; | |
1569 | } | |
1570 | ||
0c419421 | 1571 | static u8 mxser_receive_chars_old(struct tty_struct *tty, |
95b3ea4c | 1572 | struct mxser_port *port, u8 status) |
1c45607a | 1573 | { |
0c419421 JS |
1574 | enum mxser_must_hwid hwid = port->board->must_hwid; |
1575 | int recv_room = tty->receive_room; | |
1c45607a | 1576 | int ignored = 0; |
1c45607a | 1577 | int max = 256; |
95b3ea4c | 1578 | int cnt = 0; |
0c419421 | 1579 | u8 ch; |
1c45607a JS |
1580 | |
1581 | do { | |
1582 | if (max-- < 0) | |
1583 | break; | |
1da177e4 | 1584 | |
1c45607a | 1585 | ch = inb(port->ioaddr + UART_RX); |
0c419421 | 1586 | if (hwid && (status & UART_LSR_OE)) |
aaa28e9f JS |
1587 | outb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | |
1588 | MOXA_MUST_FCR_GDA_MODE_ENABLE, | |
1589 | port->ioaddr + UART_FCR); | |
15517806 JS |
1590 | status &= port->read_status_mask; |
1591 | if (status & port->ignore_status_mask) { | |
1c45607a JS |
1592 | if (++ignored > 100) |
1593 | break; | |
1594 | } else { | |
1595 | char flag = 0; | |
70640052 | 1596 | if (status & UART_LSR_BRK_ERROR_BITS) { |
15517806 | 1597 | if (status & UART_LSR_BI) { |
1c45607a JS |
1598 | flag = TTY_BREAK; |
1599 | port->icount.brk++; | |
1da177e4 | 1600 | |
0ad9e7d1 | 1601 | if (port->port.flags & ASYNC_SAK) |
1c45607a | 1602 | do_SAK(tty); |
15517806 | 1603 | } else if (status & UART_LSR_PE) { |
1c45607a JS |
1604 | flag = TTY_PARITY; |
1605 | port->icount.parity++; | |
15517806 | 1606 | } else if (status & UART_LSR_FE) { |
1c45607a JS |
1607 | flag = TTY_FRAME; |
1608 | port->icount.frame++; | |
15517806 | 1609 | } else if (status & UART_LSR_OE) { |
1c45607a JS |
1610 | flag = TTY_OVERRUN; |
1611 | port->icount.overrun++; | |
6de6e5c4 | 1612 | } |
1c45607a | 1613 | } |
92a19f9c | 1614 | tty_insert_flip_char(&port->port, ch, flag); |
95b3ea4c JS |
1615 | cnt++; |
1616 | if (cnt >= recv_room) { | |
1c45607a JS |
1617 | if (!port->ldisc_stop_rx) |
1618 | mxser_stoprx(tty); | |
1619 | break; | |
1620 | } | |
1da177e4 | 1621 | |
1c45607a | 1622 | } |
1da177e4 | 1623 | |
0c419421 | 1624 | if (hwid) |
1c45607a | 1625 | break; |
1da177e4 | 1626 | |
15517806 JS |
1627 | status = inb(port->ioaddr + UART_LSR); |
1628 | } while (status & UART_LSR_DR); | |
1da177e4 | 1629 | |
0c419421 JS |
1630 | return status; |
1631 | } | |
1632 | ||
1633 | static u8 mxser_receive_chars(struct tty_struct *tty, | |
1634 | struct mxser_port *port, u8 status) | |
1635 | { | |
0c419421 JS |
1636 | if (tty->receive_room == 0 && !port->ldisc_stop_rx) |
1637 | mxser_stoprx(tty); | |
1638 | ||
95b3ea4c JS |
1639 | if (!mxser_receive_chars_new(tty, port, status)) |
1640 | status = mxser_receive_chars_old(tty, port, status); | |
0c419421 | 1641 | |
2e124b4a | 1642 | tty_flip_buffer_push(&port->port); |
15517806 JS |
1643 | |
1644 | return status; | |
1da177e4 LT |
1645 | } |
1646 | ||
216ba023 | 1647 | static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port) |
1da177e4 | 1648 | { |
1c45607a | 1649 | int count, cnt; |
1da177e4 | 1650 | |
1c45607a JS |
1651 | if (port->x_char) { |
1652 | outb(port->x_char, port->ioaddr + UART_TX); | |
1653 | port->x_char = 0; | |
1c45607a JS |
1654 | port->icount.tx++; |
1655 | return; | |
1656 | } | |
1da177e4 | 1657 | |
0ad9e7d1 | 1658 | if (port->port.xmit_buf == NULL) |
1c45607a | 1659 | return; |
1da177e4 | 1660 | |
265ceff7 | 1661 | if (!port->xmit_cnt || tty->flow.stopped || |
5d1ea1ad | 1662 | (tty->hw_stopped && !mxser_16550A_or_MUST(port))) { |
740165f7 | 1663 | __mxser_stop_tx(port); |
1c45607a | 1664 | return; |
1da177e4 LT |
1665 | } |
1666 | ||
1c45607a JS |
1667 | cnt = port->xmit_cnt; |
1668 | count = port->xmit_fifo_size; | |
1669 | do { | |
0ad9e7d1 | 1670 | outb(port->port.xmit_buf[port->xmit_tail++], |
1c45607a JS |
1671 | port->ioaddr + UART_TX); |
1672 | port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1); | |
265ceff7 | 1673 | if (!--port->xmit_cnt) |
1c45607a JS |
1674 | break; |
1675 | } while (--count > 0); | |
1da177e4 | 1676 | |
1c45607a | 1677 | port->icount.tx += (cnt - port->xmit_cnt); |
1da177e4 | 1678 | |
464eb8f5 | 1679 | if (port->xmit_cnt < WAKEUP_CHARS) |
216ba023 | 1680 | tty_wakeup(tty); |
1c45607a | 1681 | |
265ceff7 | 1682 | if (!port->xmit_cnt) |
740165f7 | 1683 | __mxser_stop_tx(port); |
1da177e4 LT |
1684 | } |
1685 | ||
9e40ea1f JS |
1686 | static bool mxser_port_isr(struct mxser_port *port) |
1687 | { | |
1688 | struct tty_struct *tty; | |
1689 | u8 iir, msr, status; | |
1690 | bool error = false; | |
1691 | ||
1692 | iir = inb(port->ioaddr + UART_IIR); | |
1693 | if (iir & UART_IIR_NO_INT) | |
1694 | return true; | |
1695 | ||
1696 | iir &= MOXA_MUST_IIR_MASK; | |
1697 | tty = tty_port_tty_get(&port->port); | |
1698 | if (!tty || port->closing || !tty_port_initialized(&port->port)) { | |
1699 | status = inb(port->ioaddr + UART_LSR); | |
aaa28e9f JS |
1700 | outb(MOXA_MUST_FCR_GDA_MODE_ENABLE | UART_FCR_ENABLE_FIFO | |
1701 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, | |
1702 | port->ioaddr + UART_FCR); | |
9e40ea1f JS |
1703 | inb(port->ioaddr + UART_MSR); |
1704 | ||
1705 | error = true; | |
1706 | goto put_tty; | |
1707 | } | |
1708 | ||
1709 | status = inb(port->ioaddr + UART_LSR); | |
1710 | ||
9e40ea1f JS |
1711 | if (port->board->must_hwid) { |
1712 | if (iir == MOXA_MUST_IIR_GDA || | |
1713 | iir == MOXA_MUST_IIR_RDA || | |
1714 | iir == MOXA_MUST_IIR_RTO || | |
1715 | iir == MOXA_MUST_IIR_LSR) | |
1716 | status = mxser_receive_chars(tty, port, status); | |
1717 | } else { | |
1718 | status &= port->read_status_mask; | |
1719 | if (status & UART_LSR_DR) | |
1720 | status = mxser_receive_chars(tty, port, status); | |
1721 | } | |
1722 | ||
1723 | msr = inb(port->ioaddr + UART_MSR); | |
1724 | if (msr & UART_MSR_ANY_DELTA) | |
1725 | mxser_check_modem_status(tty, port, msr); | |
1726 | ||
1727 | if (port->board->must_hwid) { | |
1728 | if (iir == 0x02 && (status & UART_LSR_THRE)) | |
1729 | mxser_transmit_chars(tty, port); | |
1730 | } else { | |
1731 | if (status & UART_LSR_THRE) | |
1732 | mxser_transmit_chars(tty, port); | |
1733 | } | |
1734 | ||
1735 | put_tty: | |
1736 | tty_kref_put(tty); | |
1737 | ||
1738 | return error; | |
1739 | } | |
1740 | ||
1da177e4 | 1741 | /* |
1c45607a | 1742 | * This is the serial driver's generic interrupt routine |
1da177e4 | 1743 | */ |
1c45607a | 1744 | static irqreturn_t mxser_interrupt(int irq, void *dev_id) |
1da177e4 | 1745 | { |
cef222cb | 1746 | struct mxser_board *brd = dev_id; |
1c45607a | 1747 | struct mxser_port *port; |
1c45607a | 1748 | unsigned int int_cnt, pass_counter = 0; |
c24c31ff | 1749 | unsigned int i, max = brd->nports; |
1c45607a | 1750 | int handled = IRQ_NONE; |
9cb5c9c3 | 1751 | u8 irqbits, bits, mask = BIT(max) - 1; |
1da177e4 | 1752 | |
1c45607a | 1753 | while (pass_counter++ < MXSER_ISR_PASS_LIMIT) { |
9cb5c9c3 JS |
1754 | irqbits = inb(brd->vector) & mask; |
1755 | if (irqbits == mask) | |
1c45607a | 1756 | break; |
1da177e4 | 1757 | |
1c45607a JS |
1758 | handled = IRQ_HANDLED; |
1759 | for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) { | |
9cb5c9c3 | 1760 | if (irqbits == mask) |
1c45607a JS |
1761 | break; |
1762 | if (bits & irqbits) | |
1763 | continue; | |
1764 | port = &brd->ports[i]; | |
1765 | ||
1766 | int_cnt = 0; | |
1767 | spin_lock(&port->slock); | |
1768 | do { | |
9e40ea1f | 1769 | if (mxser_port_isr(port)) |
1c45607a | 1770 | break; |
1c45607a JS |
1771 | } while (int_cnt++ < MXSER_ISR_PASS_LIMIT); |
1772 | spin_unlock(&port->slock); | |
1773 | } | |
1774 | } | |
1da177e4 | 1775 | |
1c45607a JS |
1776 | return handled; |
1777 | } | |
1da177e4 | 1778 | |
1c45607a JS |
1779 | static const struct tty_operations mxser_ops = { |
1780 | .open = mxser_open, | |
1781 | .close = mxser_close, | |
1782 | .write = mxser_write, | |
1783 | .put_char = mxser_put_char, | |
1784 | .flush_chars = mxser_flush_chars, | |
1785 | .write_room = mxser_write_room, | |
1786 | .chars_in_buffer = mxser_chars_in_buffer, | |
1787 | .flush_buffer = mxser_flush_buffer, | |
1788 | .ioctl = mxser_ioctl, | |
1789 | .throttle = mxser_throttle, | |
1790 | .unthrottle = mxser_unthrottle, | |
1791 | .set_termios = mxser_set_termios, | |
1792 | .stop = mxser_stop, | |
1793 | .start = mxser_start, | |
1794 | .hangup = mxser_hangup, | |
1795 | .break_ctl = mxser_rs_break, | |
1796 | .wait_until_sent = mxser_wait_until_sent, | |
1797 | .tiocmget = mxser_tiocmget, | |
1798 | .tiocmset = mxser_tiocmset, | |
6da5b587 AV |
1799 | .set_serial = mxser_set_serial_info, |
1800 | .get_serial = mxser_get_serial_info, | |
0587102c | 1801 | .get_icount = mxser_get_icount, |
1c45607a | 1802 | }; |
1da177e4 | 1803 | |
04b757df | 1804 | static const struct tty_port_operations mxser_port_ops = { |
31f35939 | 1805 | .carrier_raised = mxser_carrier_raised, |
fcc8ac18 | 1806 | .dtr_rts = mxser_dtr_rts, |
6769140d AC |
1807 | .activate = mxser_activate, |
1808 | .shutdown = mxser_shutdown_port, | |
31f35939 AC |
1809 | }; |
1810 | ||
1c45607a JS |
1811 | /* |
1812 | * The MOXA Smartio/Industio serial driver boot-time initialization code! | |
1813 | */ | |
1da177e4 | 1814 | |
c24c31ff | 1815 | static void mxser_initbrd(struct mxser_board *brd, bool high_baud) |
1da177e4 | 1816 | { |
1c45607a JS |
1817 | struct mxser_port *info; |
1818 | unsigned int i; | |
57faa7d6 JS |
1819 | bool is_mu860; |
1820 | ||
1821 | brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr); | |
1822 | is_mu860 = brd->must_hwid == MOXA_MUST_MU860_HWID; | |
1823 | ||
1824 | for (i = 0; i < UART_INFO_NUM; i++) { | |
1825 | if (Gpci_uart_info[i].type == brd->must_hwid) { | |
1826 | brd->max_baud = Gpci_uart_info[i].max_baud; | |
1827 | ||
1828 | /* exception....CP-102 */ | |
c24c31ff | 1829 | if (high_baud) |
57faa7d6 JS |
1830 | brd->max_baud = 921600; |
1831 | break; | |
1832 | } | |
1833 | } | |
1834 | ||
1835 | if (is_mu860) { | |
1836 | /* set to RS232 mode by default */ | |
1837 | outb(0, brd->vector + 4); | |
1838 | outb(0, brd->vector + 0x0c); | |
1839 | } | |
1da177e4 | 1840 | |
c24c31ff | 1841 | for (i = 0; i < brd->nports; i++) { |
1c45607a | 1842 | info = &brd->ports[i]; |
57faa7d6 JS |
1843 | if (is_mu860) { |
1844 | if (i < 4) | |
1845 | info->opmode_ioaddr = brd->vector + 4; | |
1846 | else | |
1847 | info->opmode_ioaddr = brd->vector + 0x0c; | |
1848 | } | |
44b7d1b3 | 1849 | tty_port_init(&info->port); |
31f35939 | 1850 | info->port.ops = &mxser_port_ops; |
1c45607a | 1851 | info->board = brd; |
19236287 | 1852 | info->ldisc_stop_rx = false; |
1da177e4 | 1853 | |
1c45607a | 1854 | /* Enhance mode enabled here */ |
292955a7 | 1855 | if (brd->must_hwid != MOXA_OTHER_UART) |
edb7d27c | 1856 | mxser_must_set_enhance_mode(info->ioaddr, true); |
1da177e4 | 1857 | |
58a2ddb3 | 1858 | info->type = PORT_16550A; |
1da177e4 | 1859 | |
c3db20c3 | 1860 | mxser_process_txrx_fifo(info); |
1da177e4 | 1861 | |
44b7d1b3 AC |
1862 | info->port.close_delay = 5 * HZ / 10; |
1863 | info->port.closing_wait = 30 * HZ; | |
1c45607a | 1864 | spin_lock_init(&info->slock); |
1da177e4 | 1865 | |
1c45607a JS |
1866 | /* before set INT ISR, disable all int */ |
1867 | outb(inb(info->ioaddr + UART_IER) & 0xf0, | |
1868 | info->ioaddr + UART_IER); | |
1869 | } | |
1c45607a | 1870 | } |
1da177e4 | 1871 | |
9671f099 | 1872 | static int mxser_probe(struct pci_dev *pdev, |
1c45607a | 1873 | const struct pci_device_id *ent) |
1da177e4 | 1874 | { |
1c45607a | 1875 | struct mxser_board *brd; |
13d4aba8 | 1876 | unsigned int i, base; |
1c45607a | 1877 | unsigned long ioaddress; |
c24c31ff | 1878 | unsigned short nports = MXSER_NPORTS(ent->driver_data); |
9e17df37 | 1879 | struct device *tty_dev; |
1c45607a | 1880 | int retval = -EINVAL; |
1da177e4 | 1881 | |
f8b6b327 | 1882 | i = find_first_zero_bit(mxser_boards, MXSER_BOARDS); |
1c45607a | 1883 | if (i >= MXSER_BOARDS) { |
83766bc6 JS |
1884 | dev_err(&pdev->dev, "too many boards found (maximum %d), board " |
1885 | "not configured\n", MXSER_BOARDS); | |
1c45607a JS |
1886 | goto err; |
1887 | } | |
1888 | ||
ad1c92ff JS |
1889 | brd = devm_kzalloc(&pdev->dev, struct_size(brd, ports, nports), |
1890 | GFP_KERNEL); | |
f8b6b327 JS |
1891 | if (!brd) |
1892 | goto err; | |
1893 | ||
13d4aba8 | 1894 | brd->idx = i; |
f8b6b327 | 1895 | __set_bit(brd->idx, mxser_boards); |
13d4aba8 | 1896 | base = i * MXSER_PORTS_PER_BOARD; |
1c45607a | 1897 | |
dcb04e21 | 1898 | retval = pcim_enable_device(pdev); |
1c45607a | 1899 | if (retval) { |
83766bc6 | 1900 | dev_err(&pdev->dev, "PCI enable failed\n"); |
f8b6b327 | 1901 | goto err_zero; |
1c45607a JS |
1902 | } |
1903 | ||
1904 | /* io address */ | |
1905 | ioaddress = pci_resource_start(pdev, 2); | |
1906 | retval = pci_request_region(pdev, 2, "mxser(IO)"); | |
1907 | if (retval) | |
f8b6b327 | 1908 | goto err_zero; |
1c45607a | 1909 | |
c24c31ff JS |
1910 | brd->nports = nports; |
1911 | for (i = 0; i < nports; i++) | |
1c45607a JS |
1912 | brd->ports[i].ioaddr = ioaddress + 8 * i; |
1913 | ||
1914 | /* vector */ | |
1915 | ioaddress = pci_resource_start(pdev, 3); | |
1916 | retval = pci_request_region(pdev, 3, "mxser(vector)"); | |
1917 | if (retval) | |
df480518 | 1918 | goto err_zero; |
1c45607a JS |
1919 | brd->vector = ioaddress; |
1920 | ||
1921 | /* irq */ | |
1922 | brd->irq = pdev->irq; | |
1923 | ||
c24c31ff | 1924 | mxser_initbrd(brd, ent->driver_data & MXSER_HIGHBAUD); |
7f0e79dc JS |
1925 | |
1926 | retval = devm_request_irq(&pdev->dev, brd->irq, mxser_interrupt, | |
1927 | IRQF_SHARED, "mxser", brd); | |
1928 | if (retval) { | |
1929 | dev_err(&pdev->dev, "request irq failed"); | |
1930 | goto err_relbrd; | |
1931 | } | |
1c45607a | 1932 | |
c24c31ff | 1933 | for (i = 0; i < nports; i++) { |
9e17df37 | 1934 | tty_dev = tty_port_register_device(&brd->ports[i].port, |
13d4aba8 | 1935 | mxvar_sdriver, base + i, &pdev->dev); |
9e17df37 AK |
1936 | if (IS_ERR(tty_dev)) { |
1937 | retval = PTR_ERR(tty_dev); | |
1b581f17 | 1938 | for (; i > 0; i--) |
9e17df37 | 1939 | tty_unregister_device(mxvar_sdriver, |
13d4aba8 | 1940 | base + i - 1); |
9e17df37 AK |
1941 | goto err_relbrd; |
1942 | } | |
1943 | } | |
1c45607a JS |
1944 | |
1945 | pci_set_drvdata(pdev, brd); | |
1946 | ||
1947 | return 0; | |
9e17df37 | 1948 | err_relbrd: |
c24c31ff | 1949 | for (i = 0; i < nports; i++) |
9e17df37 | 1950 | tty_port_destroy(&brd->ports[i].port); |
df480518 | 1951 | err_zero: |
f8b6b327 | 1952 | __clear_bit(brd->idx, mxser_boards); |
1c45607a JS |
1953 | err: |
1954 | return retval; | |
1da177e4 LT |
1955 | } |
1956 | ||
ae8d8a14 | 1957 | static void mxser_remove(struct pci_dev *pdev) |
1da177e4 | 1958 | { |
1c45607a | 1959 | struct mxser_board *brd = pci_get_drvdata(pdev); |
13d4aba8 | 1960 | unsigned int i, base = brd->idx * MXSER_PORTS_PER_BOARD; |
d450f085 | 1961 | |
c24c31ff | 1962 | for (i = 0; i < brd->nports; i++) { |
13d4aba8 | 1963 | tty_unregister_device(mxvar_sdriver, base + i); |
d450f085 JS |
1964 | tty_port_destroy(&brd->ports[i].port); |
1965 | } | |
1da177e4 | 1966 | |
f8b6b327 | 1967 | __clear_bit(brd->idx, mxser_boards); |
1da177e4 LT |
1968 | } |
1969 | ||
1c45607a JS |
1970 | static struct pci_driver mxser_driver = { |
1971 | .name = "mxser", | |
1972 | .id_table = mxser_pcibrds, | |
1973 | .probe = mxser_probe, | |
91116cba | 1974 | .remove = mxser_remove |
1c45607a JS |
1975 | }; |
1976 | ||
1977 | static int __init mxser_module_init(void) | |
1da177e4 | 1978 | { |
1df00924 | 1979 | int retval; |
1da177e4 | 1980 | |
39b7b42b JS |
1981 | mxvar_sdriver = tty_alloc_driver(MXSER_PORTS, TTY_DRIVER_REAL_RAW | |
1982 | TTY_DRIVER_DYNAMIC_DEV); | |
1983 | if (IS_ERR(mxvar_sdriver)) | |
1984 | return PTR_ERR(mxvar_sdriver); | |
1c45607a | 1985 | |
1c45607a | 1986 | /* Initialize the tty_driver structure */ |
1c45607a JS |
1987 | mxvar_sdriver->name = "ttyMI"; |
1988 | mxvar_sdriver->major = ttymajor; | |
1989 | mxvar_sdriver->minor_start = 0; | |
1c45607a JS |
1990 | mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL; |
1991 | mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL; | |
1992 | mxvar_sdriver->init_termios = tty_std_termios; | |
1993 | mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL; | |
1c45607a JS |
1994 | tty_set_operations(mxvar_sdriver, &mxser_ops); |
1995 | ||
1996 | retval = tty_register_driver(mxvar_sdriver); | |
1997 | if (retval) { | |
1998 | printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family " | |
1999 | "tty driver !\n"); | |
2000 | goto err_put; | |
1da177e4 | 2001 | } |
1c45607a | 2002 | |
1c45607a JS |
2003 | retval = pci_register_driver(&mxser_driver); |
2004 | if (retval) { | |
83766bc6 | 2005 | printk(KERN_ERR "mxser: can't register pci driver\n"); |
29134367 | 2006 | goto err_unr; |
1c45607a JS |
2007 | } |
2008 | ||
1c45607a JS |
2009 | return 0; |
2010 | err_unr: | |
2011 | tty_unregister_driver(mxvar_sdriver); | |
2012 | err_put: | |
9f90a4dd | 2013 | tty_driver_kref_put(mxvar_sdriver); |
1c45607a JS |
2014 | return retval; |
2015 | } | |
2016 | ||
2017 | static void __exit mxser_module_exit(void) | |
2018 | { | |
1c45607a | 2019 | pci_unregister_driver(&mxser_driver); |
1c45607a | 2020 | tty_unregister_driver(mxvar_sdriver); |
9f90a4dd | 2021 | tty_driver_kref_put(mxvar_sdriver); |
1da177e4 LT |
2022 | } |
2023 | ||
2024 | module_init(mxser_module_init); | |
2025 | module_exit(mxser_module_exit); |