Commit | Line | Data |
---|---|---|
e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1da177e4 LT |
2 | /* |
3 | * mxser.c -- MOXA Smartio/Industio family multiport serial driver. | |
4 | * | |
80ff8a80 JS |
5 | * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com). |
6 | * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com> | |
1da177e4 | 7 | * |
1c45607a JS |
8 | * This code is loosely based on the 1.8 moxa driver which is based on |
9 | * Linux serial driver, written by Linus Torvalds, Theodore T'so and | |
10 | * others. | |
1da177e4 | 11 | * |
1da177e4 | 12 | * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox |
8eb04cf3 AC |
13 | * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on |
14 | * www.moxa.com. | |
1da177e4 | 15 | * - Fixed x86_64 cleanness |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 | 18 | #include <linux/module.h> |
1da177e4 LT |
19 | #include <linux/errno.h> |
20 | #include <linux/signal.h> | |
21 | #include <linux/sched.h> | |
22 | #include <linux/timer.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/tty.h> | |
25 | #include <linux/tty_flip.h> | |
26 | #include <linux/serial.h> | |
27 | #include <linux/serial_reg.h> | |
28 | #include <linux/major.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/fcntl.h> | |
31 | #include <linux/ptrace.h> | |
1da177e4 LT |
32 | #include <linux/ioport.h> |
33 | #include <linux/mm.h> | |
1da177e4 LT |
34 | #include <linux/delay.h> |
35 | #include <linux/pci.h> | |
1977f032 | 36 | #include <linux/bitops.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
5a3c6b25 | 38 | #include <linux/ratelimit.h> |
1da177e4 | 39 | |
1da177e4 LT |
40 | #include <asm/io.h> |
41 | #include <asm/irq.h> | |
7c0f6ba6 | 42 | #include <linux/uaccess.h> |
1da177e4 | 43 | |
4463cc5b JS |
44 | /* |
45 | * Semi-public control interfaces | |
46 | */ | |
47 | ||
48 | /* | |
49 | * MOXA ioctls | |
50 | */ | |
51 | ||
52 | #define MOXA 0x400 | |
4463cc5b JS |
53 | #define MOXA_SET_OP_MODE (MOXA + 66) |
54 | #define MOXA_GET_OP_MODE (MOXA + 67) | |
55 | ||
56 | #define RS232_MODE 0 | |
57 | #define RS485_2WIRE_MODE 1 | |
58 | #define RS422_MODE 2 | |
59 | #define RS485_4WIRE_MODE 3 | |
60 | #define OP_MODE_MASK 3 | |
61 | ||
4463cc5b JS |
62 | /* --------------------------------------------------- */ |
63 | ||
4463cc5b JS |
64 | /* |
65 | * Follow just what Moxa Must chip defines. | |
66 | * | |
464fbf6c JS |
67 | * When LCR register (offset 0x03) is written the following value, the Must chip |
68 | * will enter enhanced mode. And a write to EFR (offset 0x02) bit 6,7 will | |
4463cc5b JS |
69 | * change bank. |
70 | */ | |
464fbf6c | 71 | #define MOXA_MUST_ENTER_ENHANCED 0xBF |
4463cc5b | 72 | |
464fbf6c | 73 | /* when enhanced mode is enabled, access to general bank register */ |
4463cc5b JS |
74 | #define MOXA_MUST_GDL_REGISTER 0x07 |
75 | #define MOXA_MUST_GDL_MASK 0x7F | |
76 | #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80 | |
77 | ||
78 | #define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */ | |
464fbf6c JS |
79 | /* enhanced register bank select and enhanced mode setting register */ |
80 | /* This works only when LCR register equals to 0xBF */ | |
4463cc5b | 81 | #define MOXA_MUST_EFR_REGISTER 0x02 |
464fbf6c JS |
82 | #define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enhanced mode enable */ |
83 | /* enhanced register bank set 0, 1, 2 */ | |
4463cc5b JS |
84 | #define MOXA_MUST_EFR_BANK0 0x00 |
85 | #define MOXA_MUST_EFR_BANK1 0x40 | |
86 | #define MOXA_MUST_EFR_BANK2 0x80 | |
87 | #define MOXA_MUST_EFR_BANK3 0xC0 | |
88 | #define MOXA_MUST_EFR_BANK_MASK 0xC0 | |
89 | ||
90 | /* set XON1 value register, when LCR=0xBF and change to bank0 */ | |
91 | #define MOXA_MUST_XON1_REGISTER 0x04 | |
92 | ||
93 | /* set XON2 value register, when LCR=0xBF and change to bank0 */ | |
94 | #define MOXA_MUST_XON2_REGISTER 0x05 | |
95 | ||
96 | /* set XOFF1 value register, when LCR=0xBF and change to bank0 */ | |
97 | #define MOXA_MUST_XOFF1_REGISTER 0x06 | |
98 | ||
99 | /* set XOFF2 value register, when LCR=0xBF and change to bank0 */ | |
100 | #define MOXA_MUST_XOFF2_REGISTER 0x07 | |
101 | ||
102 | #define MOXA_MUST_RBRTL_REGISTER 0x04 | |
103 | #define MOXA_MUST_RBRTH_REGISTER 0x05 | |
104 | #define MOXA_MUST_RBRTI_REGISTER 0x06 | |
105 | #define MOXA_MUST_THRTL_REGISTER 0x07 | |
106 | #define MOXA_MUST_ENUM_REGISTER 0x04 | |
107 | #define MOXA_MUST_HWID_REGISTER 0x05 | |
108 | #define MOXA_MUST_ECR_REGISTER 0x06 | |
109 | #define MOXA_MUST_CSR_REGISTER 0x07 | |
110 | ||
111 | #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */ | |
112 | #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */ | |
113 | ||
114 | #define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */ | |
115 | #define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */ | |
116 | #define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */ | |
117 | #define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */ | |
118 | ||
119 | #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI) | |
120 | ||
121 | /* GDA interrupt pending */ | |
122 | #define MOXA_MUST_IIR_GDA 0x1C | |
123 | #define MOXA_MUST_IIR_RDA 0x04 | |
124 | #define MOXA_MUST_IIR_RTO 0x0C | |
125 | #define MOXA_MUST_IIR_LSR 0x06 | |
126 | ||
127 | /* received Xon/Xoff or specical interrupt pending */ | |
128 | #define MOXA_MUST_IIR_XSC 0x10 | |
129 | ||
130 | /* RTS/CTS change state interrupt pending */ | |
131 | #define MOXA_MUST_IIR_RTSCTS 0x20 | |
132 | #define MOXA_MUST_IIR_MASK 0x3E | |
133 | ||
134 | #define MOXA_MUST_MCR_XON_FLAG 0x40 | |
135 | #define MOXA_MUST_MCR_XON_ANY 0x80 | |
136 | #define MOXA_MUST_MCR_TX_XON 0x08 | |
137 | ||
138 | #define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */ | |
139 | #define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */ | |
140 | #define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */ | |
141 | #define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */ | |
142 | #define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */ | |
143 | #define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */ | |
144 | #define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */ | |
145 | #define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */ | |
146 | #define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */ | |
147 | #define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */ | |
148 | #define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */ | |
1da177e4 | 149 | |
1da177e4 | 150 | #define MXSERMAJOR 174 |
1da177e4 | 151 | |
1da177e4 | 152 | #define MXSER_BOARDS 4 /* Max. boards */ |
1da177e4 | 153 | #define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */ |
1c45607a JS |
154 | #define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD) |
155 | #define MXSER_ISR_PASS_LIMIT 100 | |
1da177e4 | 156 | |
1da177e4 LT |
157 | #define WAKEUP_CHARS 256 |
158 | ||
a6970c39 | 159 | #define MXSER_BAUD_BASE 921600 |
d811b26b | 160 | #define MXSER_CUSTOM_DIVISOR (MXSER_BAUD_BASE * 16) |
a6970c39 | 161 | |
4167bd25 JS |
162 | #define PCI_DEVICE_ID_MOXA_RC7000 0x0001 |
163 | #define PCI_DEVICE_ID_MOXA_CP102 0x1020 | |
164 | #define PCI_DEVICE_ID_MOXA_CP102UL 0x1021 | |
165 | #define PCI_DEVICE_ID_MOXA_CP102U 0x1022 | |
166 | #define PCI_DEVICE_ID_MOXA_CP102UF 0x1023 | |
167 | #define PCI_DEVICE_ID_MOXA_C104 0x1040 | |
168 | #define PCI_DEVICE_ID_MOXA_CP104U 0x1041 | |
169 | #define PCI_DEVICE_ID_MOXA_CP104JU 0x1042 | |
170 | #define PCI_DEVICE_ID_MOXA_CP104EL 0x1043 | |
16add04f JS |
171 | #define PCI_DEVICE_ID_MOXA_POS104UL 0x1044 |
172 | #define PCI_DEVICE_ID_MOXA_CB108 0x1080 | |
16add04f | 173 | #define PCI_DEVICE_ID_MOXA_CP112UL 0x1120 |
4167bd25 JS |
174 | #define PCI_DEVICE_ID_MOXA_CT114 0x1140 |
175 | #define PCI_DEVICE_ID_MOXA_CP114 0x1141 | |
16add04f JS |
176 | #define PCI_DEVICE_ID_MOXA_CB114 0x1142 |
177 | #define PCI_DEVICE_ID_MOXA_CP114UL 0x1143 | |
4167bd25 JS |
178 | #define PCI_DEVICE_ID_MOXA_CP118U 0x1180 |
179 | #define PCI_DEVICE_ID_MOXA_CP118EL 0x1181 | |
180 | #define PCI_DEVICE_ID_MOXA_CP132 0x1320 | |
181 | #define PCI_DEVICE_ID_MOXA_CP132U 0x1321 | |
182 | #define PCI_DEVICE_ID_MOXA_CP134U 0x1340 | |
16add04f JS |
183 | #define PCI_DEVICE_ID_MOXA_CB134I 0x1341 |
184 | #define PCI_DEVICE_ID_MOXA_CP138U 0x1380 | |
4167bd25 JS |
185 | #define PCI_DEVICE_ID_MOXA_C168 0x1680 |
186 | #define PCI_DEVICE_ID_MOXA_CP168U 0x1681 | |
187 | #define PCI_DEVICE_ID_MOXA_CP168EL 0x1682 | |
1da177e4 | 188 | |
c24c31ff JS |
189 | #define MXSER_NPORTS(ddata) ((ddata) & 0xffU) |
190 | #define MXSER_HIGHBAUD 0x0100 | |
1da177e4 | 191 | |
e4558366 JS |
192 | enum mxser_must_hwid { |
193 | MOXA_OTHER_UART = 0x00, | |
194 | MOXA_MUST_MU150_HWID = 0x01, | |
195 | MOXA_MUST_MU860_HWID = 0x02, | |
196 | }; | |
197 | ||
1c45607a | 198 | static const struct { |
dc33f644 JS |
199 | u8 type; |
200 | u8 fifo_size; | |
201 | u8 rx_high_water; | |
202 | u8 rx_low_water; | |
203 | speed_t max_baud; | |
1c45607a | 204 | } Gpci_uart_info[] = { |
dc33f644 JS |
205 | { MOXA_OTHER_UART, 16, 14, 1, 921600 }, |
206 | { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 }, | |
207 | { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 } | |
1da177e4 | 208 | }; |
1c45607a | 209 | #define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info) |
1da177e4 | 210 | |
1da177e4 | 211 | |
1c45607a JS |
212 | /* driver_data correspond to the lines in the structure above |
213 | see also ISA probe function before you change something */ | |
3385ecf8 | 214 | static const struct pci_device_id mxser_pcibrds[] = { |
c668d567 JS |
215 | { PCI_DEVICE_DATA(MOXA, C168, 8) }, |
216 | { PCI_DEVICE_DATA(MOXA, C104, 4) }, | |
217 | { PCI_DEVICE_DATA(MOXA, CP132, 2) }, | |
218 | { PCI_DEVICE_DATA(MOXA, CP114, 4) }, | |
219 | { PCI_DEVICE_DATA(MOXA, CT114, 4) }, | |
220 | { PCI_DEVICE_DATA(MOXA, CP102, 2 | MXSER_HIGHBAUD) }, | |
221 | { PCI_DEVICE_DATA(MOXA, CP104U, 4) }, | |
222 | { PCI_DEVICE_DATA(MOXA, CP168U, 8) }, | |
223 | { PCI_DEVICE_DATA(MOXA, CP132U, 2) }, | |
224 | { PCI_DEVICE_DATA(MOXA, CP134U, 4) }, | |
225 | { PCI_DEVICE_DATA(MOXA, CP104JU, 4) }, | |
226 | { PCI_DEVICE_DATA(MOXA, RC7000, 8) }, /* RC7000 */ | |
227 | { PCI_DEVICE_DATA(MOXA, CP118U, 8) }, | |
228 | { PCI_DEVICE_DATA(MOXA, CP102UL, 2) }, | |
229 | { PCI_DEVICE_DATA(MOXA, CP102U, 2) }, | |
230 | { PCI_DEVICE_DATA(MOXA, CP118EL, 8) }, | |
231 | { PCI_DEVICE_DATA(MOXA, CP168EL, 8) }, | |
232 | { PCI_DEVICE_DATA(MOXA, CP104EL, 4) }, | |
233 | { PCI_DEVICE_DATA(MOXA, CB108, 8) }, | |
234 | { PCI_DEVICE_DATA(MOXA, CB114, 4) }, | |
235 | { PCI_DEVICE_DATA(MOXA, CB134I, 4) }, | |
236 | { PCI_DEVICE_DATA(MOXA, CP138U, 8) }, | |
237 | { PCI_DEVICE_DATA(MOXA, POS104UL, 4) }, | |
238 | { PCI_DEVICE_DATA(MOXA, CP114UL, 4) }, | |
239 | { PCI_DEVICE_DATA(MOXA, CP102UF, 2) }, | |
240 | { PCI_DEVICE_DATA(MOXA, CP112UL, 2) }, | |
1c45607a | 241 | { } |
1da177e4 | 242 | }; |
1da177e4 LT |
243 | MODULE_DEVICE_TABLE(pci, mxser_pcibrds); |
244 | ||
1da177e4 | 245 | static int ttymajor = MXSERMAJOR; |
1da177e4 LT |
246 | |
247 | /* Variables for insmod */ | |
248 | ||
249 | MODULE_AUTHOR("Casper Yang"); | |
250 | MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver"); | |
8d3b33f6 | 251 | module_param(ttymajor, int, 0); |
1da177e4 LT |
252 | MODULE_LICENSE("GPL"); |
253 | ||
1c45607a JS |
254 | struct mxser_board; |
255 | ||
256 | struct mxser_port { | |
0ad9e7d1 | 257 | struct tty_port port; |
1c45607a | 258 | struct mxser_board *board; |
1c45607a JS |
259 | |
260 | unsigned long ioaddr; | |
261 | unsigned long opmode_ioaddr; | |
1da177e4 | 262 | |
dc33f644 JS |
263 | u8 rx_high_water; |
264 | u8 rx_low_water; | |
1da177e4 | 265 | int type; /* UART type */ |
1c45607a | 266 | |
a93963e4 JS |
267 | unsigned char x_char; /* xon/xoff character */ |
268 | u8 IER; /* Interrupt Enable Register */ | |
269 | u8 MCR; /* Modem control register */ | |
d249e662 | 270 | u8 FCR; /* FIFO control register */ |
1c45607a | 271 | |
1c45607a | 272 | struct async_icount icount; /* kernel counters for 4 input interrupts */ |
104583b5 | 273 | unsigned int timeout; |
1c45607a | 274 | |
a93963e4 JS |
275 | u8 read_status_mask; |
276 | u8 ignore_status_mask; | |
dc33f644 | 277 | u8 xmit_fifo_size; |
02e43144 JS |
278 | unsigned int xmit_head; |
279 | unsigned int xmit_tail; | |
280 | unsigned int xmit_cnt; | |
1c45607a | 281 | |
1da177e4 | 282 | spinlock_t slock; |
1c45607a JS |
283 | }; |
284 | ||
285 | struct mxser_board { | |
286 | unsigned int idx; | |
c24c31ff | 287 | unsigned short nports; |
1c45607a | 288 | int irq; |
1c45607a | 289 | unsigned long vector; |
1c45607a | 290 | |
e4558366 | 291 | enum mxser_must_hwid must_hwid; |
928f9464 | 292 | speed_t max_baud; |
1c45607a | 293 | |
ad1c92ff | 294 | struct mxser_port ports[]; |
1da177e4 LT |
295 | }; |
296 | ||
f8b6b327 | 297 | static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS); |
1da177e4 | 298 | static struct tty_driver *mxvar_sdriver; |
1da177e4 | 299 | |
edb7d27c JS |
300 | static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set, |
301 | bool restore_LCR) | |
148ff86b | 302 | { |
edb7d27c | 303 | u8 oldlcr, efr; |
148ff86b CH |
304 | |
305 | oldlcr = inb(baseio + UART_LCR); | |
464fbf6c | 306 | outb(MOXA_MUST_ENTER_ENHANCED, baseio + UART_LCR); |
148ff86b CH |
307 | |
308 | efr = inb(baseio + MOXA_MUST_EFR_REGISTER); | |
edb7d27c JS |
309 | efr &= ~clear; |
310 | efr |= set; | |
148ff86b CH |
311 | |
312 | outb(efr, baseio + MOXA_MUST_EFR_REGISTER); | |
148ff86b | 313 | |
edb7d27c JS |
314 | if (restore_LCR) |
315 | outb(oldlcr, baseio + UART_LCR); | |
148ff86b | 316 | |
edb7d27c | 317 | return oldlcr; |
148ff86b CH |
318 | } |
319 | ||
b286484b | 320 | static u8 mxser_must_select_bank(unsigned long baseio, u8 bank) |
148ff86b | 321 | { |
b286484b JS |
322 | return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank, |
323 | false); | |
324 | } | |
148ff86b | 325 | |
b286484b JS |
326 | static void mxser_set_must_xon1_value(unsigned long baseio, u8 value) |
327 | { | |
328 | u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); | |
148ff86b CH |
329 | outb(value, baseio + MOXA_MUST_XON1_REGISTER); |
330 | outb(oldlcr, baseio + UART_LCR); | |
331 | } | |
332 | ||
333 | static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value) | |
334 | { | |
b286484b | 335 | u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); |
148ff86b CH |
336 | outb(value, baseio + MOXA_MUST_XOFF1_REGISTER); |
337 | outb(oldlcr, baseio + UART_LCR); | |
338 | } | |
339 | ||
340 | static void mxser_set_must_fifo_value(struct mxser_port *info) | |
341 | { | |
b286484b | 342 | u8 oldlcr = mxser_must_select_bank(info->ioaddr, MOXA_MUST_EFR_BANK1); |
dc33f644 JS |
343 | outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER); |
344 | outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER); | |
345 | outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER); | |
148ff86b CH |
346 | outb(oldlcr, info->ioaddr + UART_LCR); |
347 | } | |
348 | ||
349 | static void mxser_set_must_enum_value(unsigned long baseio, u8 value) | |
350 | { | |
b286484b | 351 | u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); |
148ff86b CH |
352 | outb(value, baseio + MOXA_MUST_ENUM_REGISTER); |
353 | outb(oldlcr, baseio + UART_LCR); | |
354 | } | |
355 | ||
b286484b | 356 | static u8 mxser_get_must_hardware_id(unsigned long baseio) |
148ff86b | 357 | { |
b286484b JS |
358 | u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); |
359 | u8 id = inb(baseio + MOXA_MUST_HWID_REGISTER); | |
148ff86b | 360 | outb(oldlcr, baseio + UART_LCR); |
b286484b JS |
361 | |
362 | return id; | |
148ff86b CH |
363 | } |
364 | ||
edb7d27c JS |
365 | static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set) |
366 | { | |
367 | __mxser_must_set_EFR(baseio, clear, set, true); | |
368 | } | |
369 | ||
370 | static void mxser_must_set_enhance_mode(unsigned long baseio, bool enable) | |
371 | { | |
372 | mxser_must_set_EFR(baseio, | |
373 | enable ? 0 : MOXA_MUST_EFR_EFRB_ENABLE, | |
374 | enable ? MOXA_MUST_EFR_EFRB_ENABLE : 0); | |
375 | } | |
376 | ||
b441eb0f | 377 | static void mxser_must_no_sw_flow_control(unsigned long baseio) |
148ff86b | 378 | { |
b441eb0f | 379 | mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_MASK, 0); |
148ff86b CH |
380 | } |
381 | ||
b441eb0f | 382 | static void mxser_must_set_tx_sw_flow_control(unsigned long baseio, bool enable) |
148ff86b | 383 | { |
b441eb0f JS |
384 | mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_TX_MASK, |
385 | enable ? MOXA_MUST_EFR_SF_TX1 : 0); | |
148ff86b CH |
386 | } |
387 | ||
b441eb0f | 388 | static void mxser_must_set_rx_sw_flow_control(unsigned long baseio, bool enable) |
148ff86b | 389 | { |
b441eb0f JS |
390 | mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_RX_MASK, |
391 | enable ? MOXA_MUST_EFR_SF_RX1 : 0); | |
148ff86b CH |
392 | } |
393 | ||
e4558366 | 394 | static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io) |
1da177e4 LT |
395 | { |
396 | u8 oldmcr, hwid; | |
397 | int i; | |
398 | ||
399 | outb(0, io + UART_LCR); | |
edb7d27c | 400 | mxser_must_set_enhance_mode(io, false); |
1da177e4 LT |
401 | oldmcr = inb(io + UART_MCR); |
402 | outb(0, io + UART_MCR); | |
148ff86b | 403 | mxser_set_must_xon1_value(io, 0x11); |
1da177e4 LT |
404 | if ((hwid = inb(io + UART_MCR)) != 0) { |
405 | outb(oldmcr, io + UART_MCR); | |
8ea2c2ec | 406 | return MOXA_OTHER_UART; |
1da177e4 LT |
407 | } |
408 | ||
b286484b | 409 | hwid = mxser_get_must_hardware_id(io); |
e4558366 | 410 | for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */ |
1c45607a | 411 | if (hwid == Gpci_uart_info[i].type) |
e4558366 JS |
412 | return hwid; |
413 | ||
1da177e4 LT |
414 | return MOXA_OTHER_UART; |
415 | } | |
416 | ||
5d1ea1ad JS |
417 | static bool mxser_16550A_or_MUST(struct mxser_port *info) |
418 | { | |
419 | return info->type == PORT_16550A || info->board->must_hwid; | |
420 | } | |
421 | ||
c3db20c3 | 422 | static void mxser_process_txrx_fifo(struct mxser_port *info) |
1da177e4 | 423 | { |
c3db20c3 | 424 | unsigned int i; |
1da177e4 | 425 | |
c3db20c3 | 426 | if (info->type == PORT_16450 || info->type == PORT_8250) { |
1da177e4 LT |
427 | info->rx_high_water = 1; |
428 | info->rx_low_water = 1; | |
429 | info->xmit_fifo_size = 1; | |
c3db20c3 JS |
430 | return; |
431 | } | |
432 | ||
433 | for (i = 0; i < UART_INFO_NUM; i++) | |
434 | if (info->board->must_hwid == Gpci_uart_info[i].type) { | |
435 | info->rx_low_water = Gpci_uart_info[i].rx_low_water; | |
436 | info->rx_high_water = Gpci_uart_info[i].rx_high_water; | |
437 | info->xmit_fifo_size = Gpci_uart_info[i].fifo_size; | |
438 | break; | |
439 | } | |
1da177e4 LT |
440 | } |
441 | ||
740165f7 JS |
442 | static void __mxser_start_tx(struct mxser_port *info) |
443 | { | |
444 | outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); | |
445 | info->IER |= UART_IER_THRI; | |
446 | outb(info->IER, info->ioaddr + UART_IER); | |
447 | } | |
448 | ||
449 | static void mxser_start_tx(struct mxser_port *info) | |
450 | { | |
451 | unsigned long flags; | |
452 | ||
453 | spin_lock_irqsave(&info->slock, flags); | |
454 | __mxser_start_tx(info); | |
455 | spin_unlock_irqrestore(&info->slock, flags); | |
456 | } | |
457 | ||
458 | static void __mxser_stop_tx(struct mxser_port *info) | |
459 | { | |
460 | info->IER &= ~UART_IER_THRI; | |
461 | outb(info->IER, info->ioaddr + UART_IER); | |
462 | } | |
463 | ||
31f35939 AC |
464 | static int mxser_carrier_raised(struct tty_port *port) |
465 | { | |
466 | struct mxser_port *mp = container_of(port, struct mxser_port, port); | |
467 | return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0; | |
468 | } | |
469 | ||
fcc8ac18 | 470 | static void mxser_dtr_rts(struct tty_port *port, int on) |
5d951fb4 AC |
471 | { |
472 | struct mxser_port *mp = container_of(port, struct mxser_port, port); | |
473 | unsigned long flags; | |
007bbdc8 | 474 | u8 mcr; |
5d951fb4 AC |
475 | |
476 | spin_lock_irqsave(&mp->slock, flags); | |
007bbdc8 | 477 | mcr = inb(mp->ioaddr + UART_MCR); |
fcc8ac18 | 478 | if (on) |
007bbdc8 | 479 | mcr |= UART_MCR_DTR | UART_MCR_RTS; |
fcc8ac18 | 480 | else |
007bbdc8 JS |
481 | mcr &= ~(UART_MCR_DTR | UART_MCR_RTS); |
482 | outb(mcr, mp->ioaddr + UART_MCR); | |
5d951fb4 AC |
483 | spin_unlock_irqrestore(&mp->slock, flags); |
484 | } | |
485 | ||
dc33f644 | 486 | static int mxser_set_baud(struct tty_struct *tty, speed_t newspd) |
1da177e4 | 487 | { |
216ba023 | 488 | struct mxser_port *info = tty->driver_data; |
104583b5 | 489 | unsigned int quot = 0, baud; |
1c45607a | 490 | unsigned char cval; |
104583b5 | 491 | u64 timeout; |
1da177e4 | 492 | |
928f9464 | 493 | if (newspd > info->board->max_baud) |
1c45607a | 494 | return -1; |
1da177e4 | 495 | |
1c45607a | 496 | if (newspd == 134) { |
a6970c39 | 497 | quot = 2 * MXSER_BAUD_BASE / 269; |
216ba023 | 498 | tty_encode_baud_rate(tty, 134, 134); |
1c45607a | 499 | } else if (newspd) { |
a6970c39 | 500 | quot = MXSER_BAUD_BASE / newspd; |
1c45607a JS |
501 | if (quot == 0) |
502 | quot = 1; | |
a6970c39 | 503 | baud = MXSER_BAUD_BASE / quot; |
216ba023 | 504 | tty_encode_baud_rate(tty, baud, baud); |
1c45607a JS |
505 | } else { |
506 | quot = 0; | |
507 | } | |
1da177e4 | 508 | |
104583b5 JS |
509 | /* |
510 | * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the | |
511 | * u64 domain | |
512 | */ | |
513 | timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot; | |
a6970c39 | 514 | do_div(timeout, MXSER_BAUD_BASE); |
104583b5 | 515 | info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */ |
1da177e4 | 516 | |
1c45607a JS |
517 | if (quot) { |
518 | info->MCR |= UART_MCR_DTR; | |
519 | outb(info->MCR, info->ioaddr + UART_MCR); | |
520 | } else { | |
521 | info->MCR &= ~UART_MCR_DTR; | |
522 | outb(info->MCR, info->ioaddr + UART_MCR); | |
523 | return 0; | |
524 | } | |
1da177e4 | 525 | |
1c45607a | 526 | cval = inb(info->ioaddr + UART_LCR); |
1da177e4 | 527 | |
1c45607a | 528 | outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */ |
1da177e4 | 529 | |
1c45607a JS |
530 | outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */ |
531 | outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */ | |
532 | outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */ | |
1da177e4 | 533 | |
1c45607a | 534 | #ifdef BOTHER |
216ba023 | 535 | if (C_BAUD(tty) == BOTHER) { |
a6970c39 | 536 | quot = MXSER_BAUD_BASE % newspd; |
1c45607a JS |
537 | quot *= 8; |
538 | if (quot % newspd > newspd / 2) { | |
539 | quot /= newspd; | |
540 | quot++; | |
541 | } else | |
542 | quot /= newspd; | |
543 | ||
148ff86b | 544 | mxser_set_must_enum_value(info->ioaddr, quot); |
1c45607a JS |
545 | } else |
546 | #endif | |
148ff86b | 547 | mxser_set_must_enum_value(info->ioaddr, 0); |
1da177e4 | 548 | |
8ea2c2ec | 549 | return 0; |
1da177e4 | 550 | } |
1da177e4 | 551 | |
be486667 JS |
552 | static void mxser_handle_cts(struct tty_struct *tty, struct mxser_port *info, |
553 | u8 msr) | |
554 | { | |
555 | bool cts = msr & UART_MSR_CTS; | |
556 | ||
557 | if (tty->hw_stopped) { | |
558 | if (cts) { | |
559 | tty->hw_stopped = 0; | |
560 | ||
5d1ea1ad | 561 | if (!mxser_16550A_or_MUST(info)) |
740165f7 | 562 | __mxser_start_tx(info); |
be486667 JS |
563 | tty_wakeup(tty); |
564 | } | |
565 | return; | |
566 | } else if (cts) | |
567 | return; | |
568 | ||
569 | tty->hw_stopped = 1; | |
5d1ea1ad | 570 | if (!mxser_16550A_or_MUST(info)) |
740165f7 | 571 | __mxser_stop_tx(info); |
be486667 JS |
572 | } |
573 | ||
1c45607a JS |
574 | /* |
575 | * This routine is called to set the UART divisor registers to match | |
576 | * the specified baud rate for a serial port. | |
577 | */ | |
3fdfa165 | 578 | static void mxser_change_speed(struct tty_struct *tty, struct ktermios *old_termios) |
1da177e4 | 579 | { |
216ba023 | 580 | struct mxser_port *info = tty->driver_data; |
d249e662 | 581 | unsigned cflag, cval; |
1da177e4 | 582 | |
adc8d746 | 583 | cflag = tty->termios.c_cflag; |
1da177e4 | 584 | |
3fdfa165 JS |
585 | if (mxser_set_baud(tty, tty_get_baud_rate(tty))) { |
586 | /* Use previous rate on a failure */ | |
587 | if (old_termios) { | |
588 | speed_t baud = tty_termios_baud_rate(old_termios); | |
589 | tty_encode_baud_rate(tty, baud, baud); | |
590 | } | |
591 | } | |
1da177e4 | 592 | |
1c45607a JS |
593 | /* byte size and parity */ |
594 | switch (cflag & CSIZE) { | |
2c21832b | 595 | default: |
1c45607a | 596 | case CS5: |
2c21832b | 597 | cval = UART_LCR_WLEN5; |
1c45607a JS |
598 | break; |
599 | case CS6: | |
2c21832b | 600 | cval = UART_LCR_WLEN6; |
1c45607a JS |
601 | break; |
602 | case CS7: | |
2c21832b | 603 | cval = UART_LCR_WLEN7; |
1c45607a JS |
604 | break; |
605 | case CS8: | |
2c21832b | 606 | cval = UART_LCR_WLEN8; |
1c45607a | 607 | break; |
1c45607a | 608 | } |
2c21832b | 609 | |
1c45607a | 610 | if (cflag & CSTOPB) |
2c21832b | 611 | cval |= UART_LCR_STOP; |
1c45607a JS |
612 | if (cflag & PARENB) |
613 | cval |= UART_LCR_PARITY; | |
614 | if (!(cflag & PARODD)) | |
615 | cval |= UART_LCR_EPAR; | |
616 | if (cflag & CMSPAR) | |
617 | cval |= UART_LCR_SPAR; | |
1da177e4 | 618 | |
d249e662 | 619 | info->FCR = 0; |
bf1434c1 | 620 | if (info->board->must_hwid) { |
d249e662 | 621 | info->FCR |= UART_FCR_ENABLE_FIFO | |
bf1434c1 JS |
622 | MOXA_MUST_FCR_GDA_MODE_ENABLE; |
623 | mxser_set_must_fifo_value(info); | |
624 | } else if (info->type != PORT_8250 && info->type != PORT_16450) { | |
d249e662 | 625 | info->FCR |= UART_FCR_ENABLE_FIFO; |
bf1434c1 JS |
626 | switch (info->rx_high_water) { |
627 | case 1: | |
d249e662 | 628 | info->FCR |= UART_FCR_TRIGGER_1; |
bf1434c1 JS |
629 | break; |
630 | case 4: | |
d249e662 | 631 | info->FCR |= UART_FCR_TRIGGER_4; |
bf1434c1 JS |
632 | break; |
633 | case 8: | |
d249e662 | 634 | info->FCR |= UART_FCR_TRIGGER_8; |
bf1434c1 JS |
635 | break; |
636 | default: | |
d249e662 | 637 | info->FCR |= UART_FCR_TRIGGER_14; |
bf1434c1 | 638 | break; |
1da177e4 | 639 | } |
1da177e4 LT |
640 | } |
641 | ||
1c45607a JS |
642 | /* CTS flow control flag and modem status interrupts */ |
643 | info->IER &= ~UART_IER_MSI; | |
644 | info->MCR &= ~UART_MCR_AFE; | |
5604a98e | 645 | tty_port_set_cts_flow(&info->port, cflag & CRTSCTS); |
1c45607a | 646 | if (cflag & CRTSCTS) { |
1c45607a | 647 | info->IER |= UART_IER_MSI; |
5d1ea1ad | 648 | if (mxser_16550A_or_MUST(info)) { |
1c45607a JS |
649 | info->MCR |= UART_MCR_AFE; |
650 | } else { | |
be486667 JS |
651 | mxser_handle_cts(tty, info, |
652 | inb(info->ioaddr + UART_MSR)); | |
1da177e4 | 653 | } |
1c45607a JS |
654 | } |
655 | outb(info->MCR, info->ioaddr + UART_MCR); | |
2d68655d PH |
656 | tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL); |
657 | if (~cflag & CLOCAL) | |
1c45607a | 658 | info->IER |= UART_IER_MSI; |
1c45607a JS |
659 | outb(info->IER, info->ioaddr + UART_IER); |
660 | ||
661 | /* | |
662 | * Set up parity check flag | |
663 | */ | |
664 | info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
216ba023 | 665 | if (I_INPCK(tty)) |
1c45607a | 666 | info->read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
216ba023 | 667 | if (I_BRKINT(tty) || I_PARMRK(tty)) |
1c45607a | 668 | info->read_status_mask |= UART_LSR_BI; |
1da177e4 | 669 | |
1c45607a | 670 | info->ignore_status_mask = 0; |
1da177e4 | 671 | |
216ba023 | 672 | if (I_IGNBRK(tty)) { |
1c45607a JS |
673 | info->ignore_status_mask |= UART_LSR_BI; |
674 | info->read_status_mask |= UART_LSR_BI; | |
8ea2c2ec | 675 | /* |
1c45607a JS |
676 | * If we're ignore parity and break indicators, ignore |
677 | * overruns too. (For real raw support). | |
8ea2c2ec | 678 | */ |
216ba023 | 679 | if (I_IGNPAR(tty)) { |
1c45607a JS |
680 | info->ignore_status_mask |= |
681 | UART_LSR_OE | | |
682 | UART_LSR_PE | | |
683 | UART_LSR_FE; | |
684 | info->read_status_mask |= | |
685 | UART_LSR_OE | | |
686 | UART_LSR_PE | | |
687 | UART_LSR_FE; | |
688 | } | |
1da177e4 | 689 | } |
292955a7 | 690 | if (info->board->must_hwid) { |
216ba023 AC |
691 | mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty)); |
692 | mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty)); | |
b441eb0f JS |
693 | mxser_must_set_rx_sw_flow_control(info->ioaddr, I_IXON(tty)); |
694 | mxser_must_set_tx_sw_flow_control(info->ioaddr, I_IXOFF(tty)); | |
1da177e4 | 695 | } |
1da177e4 | 696 | |
1da177e4 | 697 | |
d249e662 | 698 | outb(info->FCR, info->ioaddr + UART_FCR); |
1c45607a | 699 | outb(cval, info->ioaddr + UART_LCR); |
1da177e4 LT |
700 | } |
701 | ||
30f6027f JS |
702 | static u8 mxser_check_modem_status(struct tty_struct *tty, |
703 | struct mxser_port *port) | |
1da177e4 | 704 | { |
30f6027f JS |
705 | u8 msr = inb(port->ioaddr + UART_MSR); |
706 | ||
707 | if (!(msr & UART_MSR_ANY_DELTA)) | |
708 | return msr; | |
709 | ||
1c45607a | 710 | /* update input line counters */ |
30f6027f | 711 | if (msr & UART_MSR_TERI) |
1c45607a | 712 | port->icount.rng++; |
30f6027f | 713 | if (msr & UART_MSR_DDSR) |
1c45607a | 714 | port->icount.dsr++; |
30f6027f | 715 | if (msr & UART_MSR_DDCD) |
1c45607a | 716 | port->icount.dcd++; |
30f6027f | 717 | if (msr & UART_MSR_DCTS) |
1c45607a | 718 | port->icount.cts++; |
bdc04e31 | 719 | wake_up_interruptible(&port->port.delta_msr_wait); |
1da177e4 | 720 | |
30f6027f JS |
721 | if (tty_port_check_carrier(&port->port) && (msr & UART_MSR_DDCD)) { |
722 | if (msr & UART_MSR_DCD) | |
0ad9e7d1 | 723 | wake_up_interruptible(&port->port.open_wait); |
1c45607a | 724 | } |
1da177e4 | 725 | |
be486667 | 726 | if (tty_port_cts_enabled(&port->port)) |
30f6027f JS |
727 | mxser_handle_cts(tty, port, msr); |
728 | ||
729 | return msr; | |
1da177e4 LT |
730 | } |
731 | ||
ee7e5e66 JS |
732 | static void mxser_disable_and_clear_FIFO(struct mxser_port *info) |
733 | { | |
734 | u8 fcr = UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT; | |
735 | ||
736 | if (info->board->must_hwid) | |
737 | fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; | |
738 | ||
739 | outb(fcr, info->ioaddr + UART_FCR); | |
740 | } | |
741 | ||
6769140d | 742 | static int mxser_activate(struct tty_port *port, struct tty_struct *tty) |
1da177e4 | 743 | { |
6769140d | 744 | struct mxser_port *info = container_of(port, struct mxser_port, port); |
1c45607a JS |
745 | unsigned long page; |
746 | unsigned long flags; | |
1da177e4 | 747 | |
1c45607a JS |
748 | page = __get_free_page(GFP_KERNEL); |
749 | if (!page) | |
750 | return -ENOMEM; | |
1da177e4 | 751 | |
1c45607a | 752 | spin_lock_irqsave(&info->slock, flags); |
1da177e4 | 753 | |
987a4cfe | 754 | if (!info->type) { |
216ba023 | 755 | set_bit(TTY_IO_ERROR, &tty->flags); |
1c45607a JS |
756 | free_page(page); |
757 | spin_unlock_irqrestore(&info->slock, flags); | |
1da177e4 | 758 | return 0; |
1c45607a | 759 | } |
6769140d | 760 | info->port.xmit_buf = (unsigned char *) page; |
1da177e4 | 761 | |
1da177e4 | 762 | /* |
1c45607a JS |
763 | * Clear the FIFO buffers and disable them |
764 | * (they will be reenabled in mxser_change_speed()) | |
1da177e4 | 765 | */ |
ee7e5e66 | 766 | mxser_disable_and_clear_FIFO(info); |
1da177e4 | 767 | |
1c45607a JS |
768 | /* |
769 | * At this point there's no way the LSR could still be 0xFF; | |
770 | * if it is, then bail out, because there's likely no UART | |
771 | * here. | |
772 | */ | |
773 | if (inb(info->ioaddr + UART_LSR) == 0xff) { | |
774 | spin_unlock_irqrestore(&info->slock, flags); | |
775 | if (capable(CAP_SYS_ADMIN)) { | |
f43a510d | 776 | set_bit(TTY_IO_ERROR, &tty->flags); |
1c45607a JS |
777 | return 0; |
778 | } else | |
779 | return -ENODEV; | |
780 | } | |
1da177e4 | 781 | |
1c45607a JS |
782 | /* |
783 | * Clear the interrupt registers. | |
784 | */ | |
785 | (void) inb(info->ioaddr + UART_LSR); | |
786 | (void) inb(info->ioaddr + UART_RX); | |
787 | (void) inb(info->ioaddr + UART_IIR); | |
788 | (void) inb(info->ioaddr + UART_MSR); | |
789 | ||
790 | /* | |
791 | * Now, initialize the UART | |
792 | */ | |
793 | outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */ | |
794 | info->MCR = UART_MCR_DTR | UART_MCR_RTS; | |
795 | outb(info->MCR, info->ioaddr + UART_MCR); | |
796 | ||
797 | /* | |
798 | * Finally, enable interrupts | |
799 | */ | |
800 | info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; | |
801 | ||
292955a7 | 802 | if (info->board->must_hwid) |
1c45607a JS |
803 | info->IER |= MOXA_MUST_IER_EGDAI; |
804 | outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */ | |
805 | ||
806 | /* | |
807 | * And clear the interrupt registers again for luck. | |
808 | */ | |
809 | (void) inb(info->ioaddr + UART_LSR); | |
810 | (void) inb(info->ioaddr + UART_RX); | |
811 | (void) inb(info->ioaddr + UART_IIR); | |
812 | (void) inb(info->ioaddr + UART_MSR); | |
813 | ||
216ba023 | 814 | clear_bit(TTY_IO_ERROR, &tty->flags); |
1c45607a JS |
815 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; |
816 | ||
817 | /* | |
818 | * and set the speed of the serial port | |
819 | */ | |
3fdfa165 | 820 | mxser_change_speed(tty, NULL); |
1c45607a JS |
821 | spin_unlock_irqrestore(&info->slock, flags); |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
47b722d4 JS |
826 | /* |
827 | * To stop accepting input, we disable the receive line status interrupts, and | |
828 | * tell the interrupt driver to stop checking the data ready bit in the line | |
829 | * status register. | |
830 | */ | |
831 | static void mxser_stop_rx(struct mxser_port *info) | |
832 | { | |
833 | info->IER &= ~UART_IER_RLSI; | |
834 | if (info->board->must_hwid) | |
835 | info->IER &= ~MOXA_MUST_RECV_ISR; | |
836 | ||
837 | outb(info->IER, info->ioaddr + UART_IER); | |
838 | } | |
839 | ||
1c45607a | 840 | /* |
6769140d | 841 | * This routine will shutdown a serial port |
1c45607a | 842 | */ |
6769140d | 843 | static void mxser_shutdown_port(struct tty_port *port) |
1c45607a | 844 | { |
6769140d | 845 | struct mxser_port *info = container_of(port, struct mxser_port, port); |
1c45607a JS |
846 | unsigned long flags; |
847 | ||
1c45607a JS |
848 | spin_lock_irqsave(&info->slock, flags); |
849 | ||
47b722d4 JS |
850 | mxser_stop_rx(info); |
851 | ||
1c45607a JS |
852 | /* |
853 | * clear delta_msr_wait queue to avoid mem leaks: we may free the irq | |
854 | * here so the queue might never be waken up | |
855 | */ | |
bdc04e31 | 856 | wake_up_interruptible(&info->port.delta_msr_wait); |
1c45607a JS |
857 | |
858 | /* | |
6769140d | 859 | * Free the xmit buffer, if necessary |
1c45607a | 860 | */ |
0ad9e7d1 AC |
861 | if (info->port.xmit_buf) { |
862 | free_page((unsigned long) info->port.xmit_buf); | |
863 | info->port.xmit_buf = NULL; | |
1da177e4 LT |
864 | } |
865 | ||
1c45607a JS |
866 | info->IER = 0; |
867 | outb(0x00, info->ioaddr + UART_IER); | |
868 | ||
1c45607a | 869 | /* clear Rx/Tx FIFO's */ |
ee7e5e66 | 870 | mxser_disable_and_clear_FIFO(info); |
1c45607a JS |
871 | |
872 | /* read data port to reset things */ | |
873 | (void) inb(info->ioaddr + UART_RX); | |
874 | ||
1c45607a | 875 | |
292955a7 | 876 | if (info->board->must_hwid) |
b441eb0f | 877 | mxser_must_no_sw_flow_control(info->ioaddr); |
1c45607a JS |
878 | |
879 | spin_unlock_irqrestore(&info->slock, flags); | |
880 | } | |
881 | ||
882 | /* | |
883 | * This routine is called whenever a serial port is opened. It | |
884 | * enables interrupts for a serial port, linking in its async structure into | |
885 | * the IRQ chain. It also performs the serial-specific | |
886 | * initialization for the tty structure. | |
887 | */ | |
888 | static int mxser_open(struct tty_struct *tty, struct file *filp) | |
889 | { | |
42ad25fc JS |
890 | struct tty_port *tport = tty->port; |
891 | struct mxser_port *port = container_of(tport, struct mxser_port, port); | |
1c45607a | 892 | |
42ad25fc | 893 | tty->driver_data = port; |
1c45607a | 894 | |
42ad25fc | 895 | return tty_port_open(tport, tty, filp); |
1da177e4 LT |
896 | } |
897 | ||
978e595f AC |
898 | static void mxser_flush_buffer(struct tty_struct *tty) |
899 | { | |
900 | struct mxser_port *info = tty->driver_data; | |
978e595f AC |
901 | unsigned long flags; |
902 | ||
903 | ||
904 | spin_lock_irqsave(&info->slock, flags); | |
905 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; | |
906 | ||
d249e662 | 907 | outb(info->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, |
978e595f | 908 | info->ioaddr + UART_FCR); |
978e595f AC |
909 | |
910 | spin_unlock_irqrestore(&info->slock, flags); | |
911 | ||
912 | tty_wakeup(tty); | |
913 | } | |
914 | ||
1e2b0254 AC |
915 | static void mxser_close(struct tty_struct *tty, struct file *filp) |
916 | { | |
c7ec012f | 917 | tty_port_close(tty->port, tty, filp); |
1da177e4 LT |
918 | } |
919 | ||
920 | static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count) | |
921 | { | |
922 | int c, total = 0; | |
1c45607a | 923 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
924 | unsigned long flags; |
925 | ||
1da177e4 | 926 | while (1) { |
8ea2c2ec JJ |
927 | c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, |
928 | SERIAL_XMIT_SIZE - info->xmit_head)); | |
1da177e4 LT |
929 | if (c <= 0) |
930 | break; | |
931 | ||
0ad9e7d1 | 932 | memcpy(info->port.xmit_buf + info->xmit_head, buf, c); |
1da177e4 | 933 | spin_lock_irqsave(&info->slock, flags); |
8ea2c2ec JJ |
934 | info->xmit_head = (info->xmit_head + c) & |
935 | (SERIAL_XMIT_SIZE - 1); | |
1da177e4 LT |
936 | info->xmit_cnt += c; |
937 | spin_unlock_irqrestore(&info->slock, flags); | |
938 | ||
939 | buf += c; | |
940 | count -= c; | |
941 | total += c; | |
1da177e4 LT |
942 | } |
943 | ||
5d1ea1ad JS |
944 | if (info->xmit_cnt && !tty->flow.stopped) |
945 | if (!tty->hw_stopped || mxser_16550A_or_MUST(info)) | |
740165f7 | 946 | mxser_start_tx(info); |
5d1ea1ad | 947 | |
1da177e4 LT |
948 | return total; |
949 | } | |
950 | ||
0be2eade | 951 | static int mxser_put_char(struct tty_struct *tty, unsigned char ch) |
1da177e4 | 952 | { |
1c45607a | 953 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
954 | unsigned long flags; |
955 | ||
1da177e4 | 956 | if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1) |
0be2eade | 957 | return 0; |
1da177e4 LT |
958 | |
959 | spin_lock_irqsave(&info->slock, flags); | |
0ad9e7d1 | 960 | info->port.xmit_buf[info->xmit_head++] = ch; |
1da177e4 LT |
961 | info->xmit_head &= SERIAL_XMIT_SIZE - 1; |
962 | info->xmit_cnt++; | |
963 | spin_unlock_irqrestore(&info->slock, flags); | |
8aff64e0 | 964 | |
0be2eade | 965 | return 1; |
1da177e4 LT |
966 | } |
967 | ||
968 | ||
969 | static void mxser_flush_chars(struct tty_struct *tty) | |
970 | { | |
1c45607a | 971 | struct mxser_port *info = tty->driver_data; |
1da177e4 | 972 | |
5c338fbf | 973 | if (!info->xmit_cnt || tty->flow.stopped || |
5d1ea1ad | 974 | (tty->hw_stopped && !mxser_16550A_or_MUST(info))) |
1da177e4 LT |
975 | return; |
976 | ||
740165f7 | 977 | mxser_start_tx(info); |
1da177e4 LT |
978 | } |
979 | ||
03b3b1a2 | 980 | static unsigned int mxser_write_room(struct tty_struct *tty) |
1da177e4 | 981 | { |
1c45607a | 982 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
983 | int ret; |
984 | ||
985 | ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1; | |
ace7dd96 | 986 | return ret < 0 ? 0 : ret; |
1da177e4 LT |
987 | } |
988 | ||
fff4ef17 | 989 | static unsigned int mxser_chars_in_buffer(struct tty_struct *tty) |
1da177e4 | 990 | { |
1c45607a | 991 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
992 | return info->xmit_cnt; |
993 | } | |
994 | ||
1c45607a JS |
995 | /* |
996 | * ------------------------------------------------------------ | |
997 | * friends of mxser_ioctl() | |
998 | * ------------------------------------------------------------ | |
999 | */ | |
216ba023 | 1000 | static int mxser_get_serial_info(struct tty_struct *tty, |
6da5b587 | 1001 | struct serial_struct *ss) |
1c45607a | 1002 | { |
216ba023 | 1003 | struct mxser_port *info = tty->driver_data; |
6da5b587 | 1004 | struct tty_port *port = &info->port; |
be6cf583 | 1005 | unsigned int closing_wait, close_delay; |
6da5b587 | 1006 | |
6da5b587 | 1007 | mutex_lock(&port->mutex); |
be6cf583 JH |
1008 | |
1009 | close_delay = jiffies_to_msecs(info->port.close_delay) / 10; | |
1010 | closing_wait = info->port.closing_wait; | |
1011 | if (closing_wait != ASYNC_CLOSING_WAIT_NONE) | |
1012 | closing_wait = jiffies_to_msecs(closing_wait) / 10; | |
1013 | ||
2285c496 DC |
1014 | ss->type = info->type; |
1015 | ss->line = tty->index; | |
1016 | ss->port = info->ioaddr; | |
1017 | ss->irq = info->board->irq; | |
1018 | ss->flags = info->port.flags; | |
1019 | ss->baud_base = MXSER_BAUD_BASE; | |
be6cf583 JH |
1020 | ss->close_delay = close_delay; |
1021 | ss->closing_wait = closing_wait; | |
d811b26b | 1022 | ss->custom_divisor = MXSER_CUSTOM_DIVISOR, |
6da5b587 | 1023 | mutex_unlock(&port->mutex); |
1c45607a JS |
1024 | return 0; |
1025 | } | |
1026 | ||
216ba023 | 1027 | static int mxser_set_serial_info(struct tty_struct *tty, |
6da5b587 | 1028 | struct serial_struct *ss) |
1da177e4 | 1029 | { |
216ba023 | 1030 | struct mxser_port *info = tty->driver_data; |
07f86c03 | 1031 | struct tty_port *port = &info->port; |
80ff8a80 | 1032 | speed_t baud; |
1c45607a | 1033 | unsigned long sl_flags; |
06cc52ef | 1034 | unsigned int old_speed, close_delay, closing_wait; |
1c45607a | 1035 | int retval = 0; |
1da177e4 | 1036 | |
6da5b587 AV |
1037 | if (tty_io_error(tty)) |
1038 | return -EIO; | |
1039 | ||
1040 | mutex_lock(&port->mutex); | |
1da177e4 | 1041 | |
6da5b587 AV |
1042 | if (ss->irq != info->board->irq || |
1043 | ss->port != info->ioaddr) { | |
1044 | mutex_unlock(&port->mutex); | |
80ff8a80 | 1045 | return -EINVAL; |
6da5b587 | 1046 | } |
1da177e4 | 1047 | |
06cc52ef | 1048 | old_speed = port->flags & ASYNC_SPD_MASK; |
1da177e4 | 1049 | |
be6cf583 JH |
1050 | close_delay = msecs_to_jiffies(ss->close_delay * 10); |
1051 | closing_wait = ss->closing_wait; | |
1052 | if (closing_wait != ASYNC_CLOSING_WAIT_NONE) | |
1053 | closing_wait = msecs_to_jiffies(closing_wait * 10); | |
1054 | ||
1c45607a | 1055 | if (!capable(CAP_SYS_ADMIN)) { |
a6970c39 | 1056 | if ((ss->baud_base != MXSER_BAUD_BASE) || |
1b3086b6 JS |
1057 | (close_delay != port->close_delay) || |
1058 | (closing_wait != port->closing_wait) || | |
1059 | ((ss->flags & ~ASYNC_USR_MASK) != (port->flags & ~ASYNC_USR_MASK))) { | |
6da5b587 | 1060 | mutex_unlock(&port->mutex); |
1c45607a | 1061 | return -EPERM; |
6da5b587 | 1062 | } |
1b3086b6 JS |
1063 | port->flags = (port->flags & ~ASYNC_USR_MASK) | |
1064 | (ss->flags & ASYNC_USR_MASK); | |
1c45607a | 1065 | } else { |
1da177e4 | 1066 | /* |
1c45607a JS |
1067 | * OK, past this point, all the error checking has been done. |
1068 | * At this point, we start making changes..... | |
1da177e4 | 1069 | */ |
07f86c03 | 1070 | port->flags = ((port->flags & ~ASYNC_FLAGS) | |
6da5b587 | 1071 | (ss->flags & ASYNC_FLAGS)); |
be6cf583 JH |
1072 | port->close_delay = close_delay; |
1073 | port->closing_wait = closing_wait; | |
07f86c03 | 1074 | if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST && |
a6970c39 | 1075 | (ss->baud_base != MXSER_BAUD_BASE || |
6da5b587 | 1076 | ss->custom_divisor != |
d811b26b | 1077 | MXSER_CUSTOM_DIVISOR)) { |
6da5b587 AV |
1078 | if (ss->custom_divisor == 0) { |
1079 | mutex_unlock(&port->mutex); | |
07f86c03 | 1080 | return -EINVAL; |
6da5b587 AV |
1081 | } |
1082 | baud = ss->baud_base / ss->custom_divisor; | |
216ba023 | 1083 | tty_encode_baud_rate(tty, baud, baud); |
80ff8a80 | 1084 | } |
fc83815c | 1085 | |
b91cfb25 | 1086 | info->type = ss->type; |
1da177e4 | 1087 | |
c3db20c3 | 1088 | mxser_process_txrx_fifo(info); |
b91cfb25 | 1089 | } |
1c45607a | 1090 | |
d41861ca | 1091 | if (tty_port_initialized(port)) { |
06cc52ef | 1092 | if (old_speed != (port->flags & ASYNC_SPD_MASK)) { |
1c45607a | 1093 | spin_lock_irqsave(&info->slock, sl_flags); |
3fdfa165 | 1094 | mxser_change_speed(tty, NULL); |
1c45607a | 1095 | spin_unlock_irqrestore(&info->slock, sl_flags); |
1da177e4 | 1096 | } |
6769140d | 1097 | } else { |
07f86c03 | 1098 | retval = mxser_activate(port, tty); |
6769140d | 1099 | if (retval == 0) |
d41861ca | 1100 | tty_port_set_initialized(port, 1); |
6769140d | 1101 | } |
6da5b587 | 1102 | mutex_unlock(&port->mutex); |
1c45607a JS |
1103 | return retval; |
1104 | } | |
1da177e4 | 1105 | |
1c45607a JS |
1106 | /* |
1107 | * mxser_get_lsr_info - get line status register info | |
1108 | * | |
1109 | * Purpose: Let user call ioctl() to get info when the UART physically | |
1110 | * is emptied. On bus types like RS485, the transmitter must | |
1111 | * release the bus after transmitting. This must be done when | |
1112 | * the transmit shift register is empty, not be done when the | |
1113 | * transmit holding register is empty. This functionality | |
1114 | * allows an RS485 driver to be written in user space. | |
1115 | */ | |
1116 | static int mxser_get_lsr_info(struct mxser_port *info, | |
1117 | unsigned int __user *value) | |
1118 | { | |
1119 | unsigned char status; | |
1120 | unsigned int result; | |
1121 | unsigned long flags; | |
1da177e4 | 1122 | |
1c45607a JS |
1123 | spin_lock_irqsave(&info->slock, flags); |
1124 | status = inb(info->ioaddr + UART_LSR); | |
1125 | spin_unlock_irqrestore(&info->slock, flags); | |
1126 | result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0); | |
1127 | return put_user(result, value); | |
1128 | } | |
1da177e4 | 1129 | |
60b33c13 | 1130 | static int mxser_tiocmget(struct tty_struct *tty) |
1c45607a JS |
1131 | { |
1132 | struct mxser_port *info = tty->driver_data; | |
30f6027f | 1133 | unsigned char control; |
1c45607a | 1134 | unsigned long flags; |
30f6027f | 1135 | u8 msr; |
1da177e4 | 1136 | |
18900ca6 | 1137 | if (tty_io_error(tty)) |
1c45607a | 1138 | return -EIO; |
1da177e4 | 1139 | |
1c45607a | 1140 | spin_lock_irqsave(&info->slock, flags); |
202acdaa | 1141 | control = info->MCR; |
30f6027f | 1142 | msr = mxser_check_modem_status(tty, info); |
1c45607a | 1143 | spin_unlock_irqrestore(&info->slock, flags); |
202acdaa | 1144 | |
1c45607a JS |
1145 | return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) | |
1146 | ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) | | |
30f6027f JS |
1147 | ((msr & UART_MSR_DCD) ? TIOCM_CAR : 0) | |
1148 | ((msr & UART_MSR_RI) ? TIOCM_RNG : 0) | | |
1149 | ((msr & UART_MSR_DSR) ? TIOCM_DSR : 0) | | |
1150 | ((msr & UART_MSR_CTS) ? TIOCM_CTS : 0); | |
1c45607a | 1151 | } |
1da177e4 | 1152 | |
20b9d177 | 1153 | static int mxser_tiocmset(struct tty_struct *tty, |
1c45607a JS |
1154 | unsigned int set, unsigned int clear) |
1155 | { | |
1156 | struct mxser_port *info = tty->driver_data; | |
1157 | unsigned long flags; | |
1da177e4 | 1158 | |
18900ca6 | 1159 | if (tty_io_error(tty)) |
1c45607a | 1160 | return -EIO; |
1da177e4 | 1161 | |
1c45607a | 1162 | spin_lock_irqsave(&info->slock, flags); |
1da177e4 | 1163 | |
1c45607a JS |
1164 | if (set & TIOCM_RTS) |
1165 | info->MCR |= UART_MCR_RTS; | |
1166 | if (set & TIOCM_DTR) | |
1167 | info->MCR |= UART_MCR_DTR; | |
1da177e4 | 1168 | |
1c45607a JS |
1169 | if (clear & TIOCM_RTS) |
1170 | info->MCR &= ~UART_MCR_RTS; | |
1171 | if (clear & TIOCM_DTR) | |
1172 | info->MCR &= ~UART_MCR_DTR; | |
8ea2c2ec | 1173 | |
1c45607a JS |
1174 | outb(info->MCR, info->ioaddr + UART_MCR); |
1175 | spin_unlock_irqrestore(&info->slock, flags); | |
1176 | return 0; | |
1177 | } | |
1da177e4 | 1178 | |
1c45607a JS |
1179 | static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg, |
1180 | struct async_icount *cprev) | |
1da177e4 | 1181 | { |
1c45607a JS |
1182 | struct async_icount cnow; |
1183 | unsigned long flags; | |
1184 | int ret; | |
1da177e4 | 1185 | |
1c45607a JS |
1186 | spin_lock_irqsave(&info->slock, flags); |
1187 | cnow = info->icount; /* atomic copy */ | |
1188 | spin_unlock_irqrestore(&info->slock, flags); | |
1da177e4 | 1189 | |
1c45607a JS |
1190 | ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) || |
1191 | ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) || | |
1192 | ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) || | |
1193 | ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts)); | |
1da177e4 | 1194 | |
1c45607a JS |
1195 | *cprev = cnow; |
1196 | ||
1197 | return ret; | |
1198 | } | |
1199 | ||
9fae5f85 JS |
1200 | /* We should likely switch to TIOCGRS485/TIOCSRS485. */ |
1201 | static int mxser_ioctl_op_mode(struct mxser_port *port, int index, bool set, | |
1202 | int __user *u_opmode) | |
1203 | { | |
9fae5f85 JS |
1204 | int opmode, p = index % 4; |
1205 | int shiftbit = p * 2; | |
238d117d | 1206 | u8 val; |
9fae5f85 JS |
1207 | |
1208 | if (port->board->must_hwid != MOXA_MUST_MU860_HWID) | |
1209 | return -EFAULT; | |
1210 | ||
1211 | if (set) { | |
1212 | if (get_user(opmode, u_opmode)) | |
1213 | return -EFAULT; | |
1214 | ||
238d117d JS |
1215 | if (opmode & ~OP_MODE_MASK) |
1216 | return -EINVAL; | |
9fae5f85 JS |
1217 | |
1218 | spin_lock_irq(&port->slock); | |
1219 | val = inb(port->opmode_ioaddr); | |
238d117d | 1220 | val &= ~(OP_MODE_MASK << shiftbit); |
9fae5f85 JS |
1221 | val |= (opmode << shiftbit); |
1222 | outb(val, port->opmode_ioaddr); | |
1223 | spin_unlock_irq(&port->slock); | |
9fae5f85 | 1224 | |
238d117d | 1225 | return 0; |
9fae5f85 JS |
1226 | } |
1227 | ||
238d117d JS |
1228 | spin_lock_irq(&port->slock); |
1229 | opmode = inb(port->opmode_ioaddr) >> shiftbit; | |
1230 | spin_unlock_irq(&port->slock); | |
1231 | ||
1232 | return put_user(opmode & OP_MODE_MASK, u_opmode); | |
9fae5f85 JS |
1233 | } |
1234 | ||
6caa76b7 | 1235 | static int mxser_ioctl(struct tty_struct *tty, |
1c45607a | 1236 | unsigned int cmd, unsigned long arg) |
1da177e4 | 1237 | { |
1c45607a JS |
1238 | struct mxser_port *info = tty->driver_data; |
1239 | struct async_icount cnow; | |
1c45607a JS |
1240 | unsigned long flags; |
1241 | void __user *argp = (void __user *)arg; | |
1da177e4 | 1242 | |
9fae5f85 JS |
1243 | if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) |
1244 | return mxser_ioctl_op_mode(info, tty->index, | |
1245 | cmd == MOXA_SET_OP_MODE, argp); | |
1c45607a | 1246 | |
6da5b587 | 1247 | if (cmd != TIOCMIWAIT && tty_io_error(tty)) |
1c45607a JS |
1248 | return -EIO; |
1249 | ||
1250 | switch (cmd) { | |
1c45607a | 1251 | case TIOCSERGETLSR: /* Get line status register */ |
9d6d162d | 1252 | return mxser_get_lsr_info(info, argp); |
1c45607a JS |
1253 | /* |
1254 | * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change | |
1255 | * - mask passed in arg for lines of interest | |
1256 | * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) | |
1257 | * Caller should use TIOCGICOUNT to see which one it was | |
1258 | */ | |
1259 | case TIOCMIWAIT: | |
1260 | spin_lock_irqsave(&info->slock, flags); | |
1261 | cnow = info->icount; /* note the counters on entry */ | |
1262 | spin_unlock_irqrestore(&info->slock, flags); | |
1263 | ||
bdc04e31 | 1264 | return wait_event_interruptible(info->port.delta_msr_wait, |
1c45607a | 1265 | mxser_cflags_changed(info, arg, &cnow)); |
1c45607a JS |
1266 | default: |
1267 | return -ENOIOCTLCMD; | |
1268 | } | |
1269 | return 0; | |
1270 | } | |
1271 | ||
0587102c AC |
1272 | /* |
1273 | * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) | |
1274 | * Return: write counters to the user passed counter struct | |
1275 | * NB: both 1->0 and 0->1 transitions are counted except for | |
1276 | * RI where only 0->1 is counted. | |
1277 | */ | |
1278 | ||
1279 | static int mxser_get_icount(struct tty_struct *tty, | |
1280 | struct serial_icounter_struct *icount) | |
1281 | ||
1282 | { | |
1283 | struct mxser_port *info = tty->driver_data; | |
1284 | struct async_icount cnow; | |
1285 | unsigned long flags; | |
1286 | ||
1287 | spin_lock_irqsave(&info->slock, flags); | |
1288 | cnow = info->icount; | |
1289 | spin_unlock_irqrestore(&info->slock, flags); | |
1290 | ||
1291 | icount->frame = cnow.frame; | |
1292 | icount->brk = cnow.brk; | |
1293 | icount->overrun = cnow.overrun; | |
1294 | icount->buf_overrun = cnow.buf_overrun; | |
1295 | icount->parity = cnow.parity; | |
1296 | icount->rx = cnow.rx; | |
1297 | icount->tx = cnow.tx; | |
1298 | icount->cts = cnow.cts; | |
1299 | icount->dsr = cnow.dsr; | |
1300 | icount->rng = cnow.rng; | |
1301 | icount->dcd = cnow.dcd; | |
1302 | return 0; | |
1303 | } | |
1304 | ||
c6693e6e JS |
1305 | /* |
1306 | * This routine is called by the upper-layer tty layer to signal that | |
1307 | * incoming characters should be throttled. | |
1308 | */ | |
1309 | static void mxser_throttle(struct tty_struct *tty) | |
1c45607a JS |
1310 | { |
1311 | struct mxser_port *info = tty->driver_data; | |
1312 | ||
1c45607a | 1313 | if (I_IXOFF(tty)) { |
292955a7 | 1314 | if (info->board->must_hwid) { |
1c45607a JS |
1315 | info->IER &= ~MOXA_MUST_RECV_ISR; |
1316 | outb(info->IER, info->ioaddr + UART_IER); | |
1317 | } else { | |
1318 | info->x_char = STOP_CHAR(tty); | |
1319 | outb(0, info->ioaddr + UART_IER); | |
1320 | info->IER |= UART_IER_THRI; | |
1321 | outb(info->IER, info->ioaddr + UART_IER); | |
1da177e4 LT |
1322 | } |
1323 | } | |
1324 | ||
9db276f8 | 1325 | if (C_CRTSCTS(tty)) { |
1c45607a JS |
1326 | info->MCR &= ~UART_MCR_RTS; |
1327 | outb(info->MCR, info->ioaddr + UART_MCR); | |
1da177e4 LT |
1328 | } |
1329 | } | |
1330 | ||
1da177e4 LT |
1331 | static void mxser_unthrottle(struct tty_struct *tty) |
1332 | { | |
1c45607a | 1333 | struct mxser_port *info = tty->driver_data; |
1da177e4 | 1334 | |
1c45607a | 1335 | /* startrx */ |
1c45607a JS |
1336 | if (I_IXOFF(tty)) { |
1337 | if (info->x_char) | |
1338 | info->x_char = 0; | |
1339 | else { | |
292955a7 | 1340 | if (info->board->must_hwid) { |
1c45607a JS |
1341 | info->IER |= MOXA_MUST_RECV_ISR; |
1342 | outb(info->IER, info->ioaddr + UART_IER); | |
1343 | } else { | |
1344 | info->x_char = START_CHAR(tty); | |
1345 | outb(0, info->ioaddr + UART_IER); | |
1346 | info->IER |= UART_IER_THRI; | |
1347 | outb(info->IER, info->ioaddr + UART_IER); | |
1348 | } | |
1da177e4 | 1349 | } |
1c45607a | 1350 | } |
1da177e4 | 1351 | |
9db276f8 | 1352 | if (C_CRTSCTS(tty)) { |
1c45607a JS |
1353 | info->MCR |= UART_MCR_RTS; |
1354 | outb(info->MCR, info->ioaddr + UART_MCR); | |
1da177e4 LT |
1355 | } |
1356 | } | |
1357 | ||
1358 | /* | |
1359 | * mxser_stop() and mxser_start() | |
1360 | * | |
6e94dbc7 | 1361 | * This routines are called before setting or resetting tty->flow.stopped. |
1da177e4 LT |
1362 | * They enable or disable transmitter interrupts, as necessary. |
1363 | */ | |
1364 | static void mxser_stop(struct tty_struct *tty) | |
1365 | { | |
1c45607a | 1366 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
1367 | unsigned long flags; |
1368 | ||
1369 | spin_lock_irqsave(&info->slock, flags); | |
740165f7 JS |
1370 | if (info->IER & UART_IER_THRI) |
1371 | __mxser_stop_tx(info); | |
1da177e4 LT |
1372 | spin_unlock_irqrestore(&info->slock, flags); |
1373 | } | |
1374 | ||
1375 | static void mxser_start(struct tty_struct *tty) | |
1376 | { | |
1c45607a | 1377 | struct mxser_port *info = tty->driver_data; |
1da177e4 LT |
1378 | unsigned long flags; |
1379 | ||
1380 | spin_lock_irqsave(&info->slock, flags); | |
5c338fbf | 1381 | if (info->xmit_cnt) |
740165f7 | 1382 | __mxser_start_tx(info); |
1da177e4 LT |
1383 | spin_unlock_irqrestore(&info->slock, flags); |
1384 | } | |
1385 | ||
1c45607a JS |
1386 | static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios) |
1387 | { | |
1388 | struct mxser_port *info = tty->driver_data; | |
1389 | unsigned long flags; | |
1390 | ||
1391 | spin_lock_irqsave(&info->slock, flags); | |
3fdfa165 | 1392 | mxser_change_speed(tty, old_termios); |
1c45607a JS |
1393 | spin_unlock_irqrestore(&info->slock, flags); |
1394 | ||
9db276f8 | 1395 | if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) { |
1c45607a JS |
1396 | tty->hw_stopped = 0; |
1397 | mxser_start(tty); | |
1398 | } | |
1399 | ||
1400 | /* Handle sw stopped */ | |
9db276f8 | 1401 | if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) { |
6e94dbc7 | 1402 | tty->flow.stopped = 0; |
1c45607a | 1403 | |
292955a7 | 1404 | if (info->board->must_hwid) { |
1c45607a | 1405 | spin_lock_irqsave(&info->slock, flags); |
b441eb0f | 1406 | mxser_must_set_rx_sw_flow_control(info->ioaddr, false); |
1c45607a JS |
1407 | spin_unlock_irqrestore(&info->slock, flags); |
1408 | } | |
1409 | ||
1410 | mxser_start(tty); | |
1411 | } | |
1412 | } | |
1413 | ||
239ef19e JS |
1414 | static bool mxser_tx_empty(struct mxser_port *info) |
1415 | { | |
1416 | unsigned long flags; | |
1417 | u8 lsr; | |
1418 | ||
1419 | spin_lock_irqsave(&info->slock, flags); | |
1420 | lsr = inb(info->ioaddr + UART_LSR); | |
1421 | spin_unlock_irqrestore(&info->slock, flags); | |
1422 | ||
1423 | return !(lsr & UART_LSR_TEMT); | |
1424 | } | |
1425 | ||
1da177e4 LT |
1426 | /* |
1427 | * mxser_wait_until_sent() --- wait until the transmitter is empty | |
1428 | */ | |
1429 | static void mxser_wait_until_sent(struct tty_struct *tty, int timeout) | |
1430 | { | |
1c45607a | 1431 | struct mxser_port *info = tty->driver_data; |
49b798a6 | 1432 | unsigned long expire, char_time; |
1da177e4 LT |
1433 | |
1434 | if (info->type == PORT_UNKNOWN) | |
1435 | return; | |
1436 | ||
1437 | if (info->xmit_fifo_size == 0) | |
1438 | return; /* Just in case.... */ | |
1439 | ||
1da177e4 LT |
1440 | /* |
1441 | * Set the check interval to be 1/5 of the estimated time to | |
1442 | * send a single character, and make it at least 1. The check | |
1443 | * interval should also be less than the timeout. | |
1444 | * | |
1445 | * Note: we have to use pretty tight timings here to satisfy | |
1446 | * the NIST-PCTS. | |
1447 | */ | |
1448 | char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size; | |
1449 | char_time = char_time / 5; | |
1450 | if (char_time == 0) | |
1451 | char_time = 1; | |
1452 | if (timeout && timeout < char_time) | |
1453 | char_time = timeout; | |
fe74bc61 JS |
1454 | |
1455 | char_time = jiffies_to_msecs(char_time); | |
1456 | ||
1da177e4 LT |
1457 | /* |
1458 | * If the transmitter hasn't cleared in twice the approximate | |
1459 | * amount of time to send the entire FIFO, it probably won't | |
1460 | * ever clear. This assumes the UART isn't doing flow | |
1461 | * control, which is currently the case. Hence, if it ever | |
1462 | * takes longer than info->timeout, this is probably due to a | |
1463 | * UART bug of some kind. So, we clamp the timeout parameter at | |
1464 | * 2*info->timeout. | |
1465 | */ | |
1466 | if (!timeout || timeout > 2 * info->timeout) | |
1467 | timeout = 2 * info->timeout; | |
8bab534b | 1468 | |
49b798a6 JS |
1469 | expire = jiffies + timeout; |
1470 | ||
239ef19e | 1471 | while (mxser_tx_empty(info)) { |
fe74bc61 | 1472 | msleep_interruptible(char_time); |
1da177e4 | 1473 | if (signal_pending(current)) |
1c45607a | 1474 | break; |
49b798a6 | 1475 | if (time_after(jiffies, expire)) |
1c45607a | 1476 | break; |
1da177e4 | 1477 | } |
1c45607a | 1478 | } |
1da177e4 | 1479 | |
1c45607a JS |
1480 | /* |
1481 | * This routine is called by tty_hangup() when a hangup is signaled. | |
1482 | */ | |
1483 | static void mxser_hangup(struct tty_struct *tty) | |
1484 | { | |
1485 | struct mxser_port *info = tty->driver_data; | |
1da177e4 | 1486 | |
1c45607a | 1487 | mxser_flush_buffer(tty); |
3b6826b2 | 1488 | tty_port_hangup(&info->port); |
1da177e4 LT |
1489 | } |
1490 | ||
1c45607a JS |
1491 | /* |
1492 | * mxser_rs_break() --- routine which turns the break handling on or off | |
1493 | */ | |
9e98966c | 1494 | static int mxser_rs_break(struct tty_struct *tty, int break_state) |
1da177e4 | 1495 | { |
1c45607a | 1496 | struct mxser_port *info = tty->driver_data; |
1da177e4 | 1497 | unsigned long flags; |
59908433 | 1498 | u8 lcr; |
1da177e4 | 1499 | |
1c45607a | 1500 | spin_lock_irqsave(&info->slock, flags); |
59908433 | 1501 | lcr = inb(info->ioaddr + UART_LCR); |
1c45607a | 1502 | if (break_state == -1) |
59908433 | 1503 | lcr |= UART_LCR_SBC; |
1c45607a | 1504 | else |
59908433 JS |
1505 | lcr &= ~UART_LCR_SBC; |
1506 | outb(lcr, info->ioaddr + UART_LCR); | |
1c45607a | 1507 | spin_unlock_irqrestore(&info->slock, flags); |
59908433 | 1508 | |
9e98966c | 1509 | return 0; |
1c45607a | 1510 | } |
1da177e4 | 1511 | |
9dd6f306 | 1512 | static bool mxser_receive_chars_new(struct mxser_port *port, u8 status) |
e5ce1bce JS |
1513 | { |
1514 | enum mxser_must_hwid hwid = port->board->must_hwid; | |
1515 | u8 gdl; | |
1516 | ||
1517 | if (hwid == MOXA_OTHER_UART) | |
1518 | return false; | |
7d5006d5 | 1519 | if (status & (UART_LSR_BRK_ERROR_BITS | MOXA_MUST_LSR_RERR)) |
e5ce1bce JS |
1520 | return false; |
1521 | ||
1522 | gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER); | |
1523 | if (hwid == MOXA_MUST_MU150_HWID) | |
1524 | gdl &= MOXA_MUST_GDL_MASK; | |
1525 | ||
e5ce1bce JS |
1526 | while (gdl--) { |
1527 | u8 ch = inb(port->ioaddr + UART_RX); | |
eb68ac04 JS |
1528 | if (!tty_insert_flip_char(&port->port, ch, 0)) |
1529 | port->icount.buf_overrun++; | |
e5ce1bce JS |
1530 | } |
1531 | ||
1532 | return true; | |
1533 | } | |
1534 | ||
0c419421 | 1535 | static u8 mxser_receive_chars_old(struct tty_struct *tty, |
95b3ea4c | 1536 | struct mxser_port *port, u8 status) |
1c45607a | 1537 | { |
0c419421 | 1538 | enum mxser_must_hwid hwid = port->board->must_hwid; |
1c45607a | 1539 | int ignored = 0; |
1c45607a | 1540 | int max = 256; |
0c419421 | 1541 | u8 ch; |
1c45607a JS |
1542 | |
1543 | do { | |
1544 | if (max-- < 0) | |
1545 | break; | |
1da177e4 | 1546 | |
1c45607a | 1547 | ch = inb(port->ioaddr + UART_RX); |
0c419421 | 1548 | if (hwid && (status & UART_LSR_OE)) |
d249e662 | 1549 | outb(port->FCR | UART_FCR_CLEAR_RCVR, |
aaa28e9f | 1550 | port->ioaddr + UART_FCR); |
15517806 JS |
1551 | status &= port->read_status_mask; |
1552 | if (status & port->ignore_status_mask) { | |
1c45607a JS |
1553 | if (++ignored > 100) |
1554 | break; | |
1555 | } else { | |
1556 | char flag = 0; | |
70640052 | 1557 | if (status & UART_LSR_BRK_ERROR_BITS) { |
15517806 | 1558 | if (status & UART_LSR_BI) { |
1c45607a JS |
1559 | flag = TTY_BREAK; |
1560 | port->icount.brk++; | |
1da177e4 | 1561 | |
0ad9e7d1 | 1562 | if (port->port.flags & ASYNC_SAK) |
1c45607a | 1563 | do_SAK(tty); |
15517806 | 1564 | } else if (status & UART_LSR_PE) { |
1c45607a JS |
1565 | flag = TTY_PARITY; |
1566 | port->icount.parity++; | |
15517806 | 1567 | } else if (status & UART_LSR_FE) { |
1c45607a JS |
1568 | flag = TTY_FRAME; |
1569 | port->icount.frame++; | |
15517806 | 1570 | } else if (status & UART_LSR_OE) { |
1c45607a JS |
1571 | flag = TTY_OVERRUN; |
1572 | port->icount.overrun++; | |
6de6e5c4 | 1573 | } |
1c45607a | 1574 | } |
eb68ac04 JS |
1575 | if (!tty_insert_flip_char(&port->port, ch, flag)) { |
1576 | port->icount.buf_overrun++; | |
1c45607a | 1577 | break; |
eb68ac04 | 1578 | } |
1c45607a | 1579 | } |
1da177e4 | 1580 | |
0c419421 | 1581 | if (hwid) |
1c45607a | 1582 | break; |
1da177e4 | 1583 | |
15517806 JS |
1584 | status = inb(port->ioaddr + UART_LSR); |
1585 | } while (status & UART_LSR_DR); | |
1da177e4 | 1586 | |
0c419421 JS |
1587 | return status; |
1588 | } | |
1589 | ||
1590 | static u8 mxser_receive_chars(struct tty_struct *tty, | |
1591 | struct mxser_port *port, u8 status) | |
1592 | { | |
9dd6f306 | 1593 | if (!mxser_receive_chars_new(port, status)) |
95b3ea4c | 1594 | status = mxser_receive_chars_old(tty, port, status); |
0c419421 | 1595 | |
2e124b4a | 1596 | tty_flip_buffer_push(&port->port); |
15517806 JS |
1597 | |
1598 | return status; | |
1da177e4 LT |
1599 | } |
1600 | ||
216ba023 | 1601 | static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port) |
1da177e4 | 1602 | { |
3b88dbff | 1603 | int count; |
1da177e4 | 1604 | |
1c45607a JS |
1605 | if (port->x_char) { |
1606 | outb(port->x_char, port->ioaddr + UART_TX); | |
1607 | port->x_char = 0; | |
1c45607a JS |
1608 | port->icount.tx++; |
1609 | return; | |
1610 | } | |
1da177e4 | 1611 | |
265ceff7 | 1612 | if (!port->xmit_cnt || tty->flow.stopped || |
5d1ea1ad | 1613 | (tty->hw_stopped && !mxser_16550A_or_MUST(port))) { |
740165f7 | 1614 | __mxser_stop_tx(port); |
1c45607a | 1615 | return; |
1da177e4 LT |
1616 | } |
1617 | ||
1c45607a JS |
1618 | count = port->xmit_fifo_size; |
1619 | do { | |
0ad9e7d1 | 1620 | outb(port->port.xmit_buf[port->xmit_tail++], |
1c45607a | 1621 | port->ioaddr + UART_TX); |
3b88dbff JS |
1622 | port->xmit_tail &= SERIAL_XMIT_SIZE - 1; |
1623 | port->icount.tx++; | |
265ceff7 | 1624 | if (!--port->xmit_cnt) |
1c45607a JS |
1625 | break; |
1626 | } while (--count > 0); | |
1da177e4 | 1627 | |
464eb8f5 | 1628 | if (port->xmit_cnt < WAKEUP_CHARS) |
216ba023 | 1629 | tty_wakeup(tty); |
1c45607a | 1630 | |
265ceff7 | 1631 | if (!port->xmit_cnt) |
740165f7 | 1632 | __mxser_stop_tx(port); |
1da177e4 LT |
1633 | } |
1634 | ||
9e40ea1f JS |
1635 | static bool mxser_port_isr(struct mxser_port *port) |
1636 | { | |
1637 | struct tty_struct *tty; | |
30f6027f | 1638 | u8 iir, status; |
9e40ea1f JS |
1639 | bool error = false; |
1640 | ||
1641 | iir = inb(port->ioaddr + UART_IIR); | |
1642 | if (iir & UART_IIR_NO_INT) | |
1643 | return true; | |
1644 | ||
1645 | iir &= MOXA_MUST_IIR_MASK; | |
1646 | tty = tty_port_tty_get(&port->port); | |
274ab58d | 1647 | if (!tty) { |
9e40ea1f | 1648 | status = inb(port->ioaddr + UART_LSR); |
d249e662 | 1649 | outb(port->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, |
aaa28e9f | 1650 | port->ioaddr + UART_FCR); |
9e40ea1f JS |
1651 | inb(port->ioaddr + UART_MSR); |
1652 | ||
1653 | error = true; | |
1654 | goto put_tty; | |
1655 | } | |
1656 | ||
1657 | status = inb(port->ioaddr + UART_LSR); | |
1658 | ||
9e40ea1f JS |
1659 | if (port->board->must_hwid) { |
1660 | if (iir == MOXA_MUST_IIR_GDA || | |
1661 | iir == MOXA_MUST_IIR_RDA || | |
1662 | iir == MOXA_MUST_IIR_RTO || | |
1663 | iir == MOXA_MUST_IIR_LSR) | |
1664 | status = mxser_receive_chars(tty, port, status); | |
1665 | } else { | |
1666 | status &= port->read_status_mask; | |
1667 | if (status & UART_LSR_DR) | |
1668 | status = mxser_receive_chars(tty, port, status); | |
1669 | } | |
1670 | ||
30f6027f | 1671 | mxser_check_modem_status(tty, port); |
9e40ea1f JS |
1672 | |
1673 | if (port->board->must_hwid) { | |
1674 | if (iir == 0x02 && (status & UART_LSR_THRE)) | |
1675 | mxser_transmit_chars(tty, port); | |
1676 | } else { | |
1677 | if (status & UART_LSR_THRE) | |
1678 | mxser_transmit_chars(tty, port); | |
1679 | } | |
1680 | ||
1681 | put_tty: | |
1682 | tty_kref_put(tty); | |
1683 | ||
1684 | return error; | |
1685 | } | |
1686 | ||
1da177e4 | 1687 | /* |
1c45607a | 1688 | * This is the serial driver's generic interrupt routine |
1da177e4 | 1689 | */ |
1c45607a | 1690 | static irqreturn_t mxser_interrupt(int irq, void *dev_id) |
1da177e4 | 1691 | { |
cef222cb | 1692 | struct mxser_board *brd = dev_id; |
1c45607a | 1693 | struct mxser_port *port; |
1c45607a | 1694 | unsigned int int_cnt, pass_counter = 0; |
c24c31ff | 1695 | unsigned int i, max = brd->nports; |
1c45607a | 1696 | int handled = IRQ_NONE; |
9cb5c9c3 | 1697 | u8 irqbits, bits, mask = BIT(max) - 1; |
1da177e4 | 1698 | |
1c45607a | 1699 | while (pass_counter++ < MXSER_ISR_PASS_LIMIT) { |
9cb5c9c3 JS |
1700 | irqbits = inb(brd->vector) & mask; |
1701 | if (irqbits == mask) | |
1c45607a | 1702 | break; |
1da177e4 | 1703 | |
1c45607a JS |
1704 | handled = IRQ_HANDLED; |
1705 | for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) { | |
9cb5c9c3 | 1706 | if (irqbits == mask) |
1c45607a JS |
1707 | break; |
1708 | if (bits & irqbits) | |
1709 | continue; | |
1710 | port = &brd->ports[i]; | |
1711 | ||
1712 | int_cnt = 0; | |
1713 | spin_lock(&port->slock); | |
1714 | do { | |
9e40ea1f | 1715 | if (mxser_port_isr(port)) |
1c45607a | 1716 | break; |
1c45607a JS |
1717 | } while (int_cnt++ < MXSER_ISR_PASS_LIMIT); |
1718 | spin_unlock(&port->slock); | |
1719 | } | |
1720 | } | |
1da177e4 | 1721 | |
1c45607a JS |
1722 | return handled; |
1723 | } | |
1da177e4 | 1724 | |
1c45607a JS |
1725 | static const struct tty_operations mxser_ops = { |
1726 | .open = mxser_open, | |
1727 | .close = mxser_close, | |
1728 | .write = mxser_write, | |
1729 | .put_char = mxser_put_char, | |
1730 | .flush_chars = mxser_flush_chars, | |
1731 | .write_room = mxser_write_room, | |
1732 | .chars_in_buffer = mxser_chars_in_buffer, | |
1733 | .flush_buffer = mxser_flush_buffer, | |
1734 | .ioctl = mxser_ioctl, | |
1735 | .throttle = mxser_throttle, | |
1736 | .unthrottle = mxser_unthrottle, | |
1737 | .set_termios = mxser_set_termios, | |
1738 | .stop = mxser_stop, | |
1739 | .start = mxser_start, | |
1740 | .hangup = mxser_hangup, | |
1741 | .break_ctl = mxser_rs_break, | |
1742 | .wait_until_sent = mxser_wait_until_sent, | |
1743 | .tiocmget = mxser_tiocmget, | |
1744 | .tiocmset = mxser_tiocmset, | |
6da5b587 AV |
1745 | .set_serial = mxser_set_serial_info, |
1746 | .get_serial = mxser_get_serial_info, | |
0587102c | 1747 | .get_icount = mxser_get_icount, |
1c45607a | 1748 | }; |
1da177e4 | 1749 | |
04b757df | 1750 | static const struct tty_port_operations mxser_port_ops = { |
31f35939 | 1751 | .carrier_raised = mxser_carrier_raised, |
fcc8ac18 | 1752 | .dtr_rts = mxser_dtr_rts, |
6769140d AC |
1753 | .activate = mxser_activate, |
1754 | .shutdown = mxser_shutdown_port, | |
31f35939 AC |
1755 | }; |
1756 | ||
1c45607a JS |
1757 | /* |
1758 | * The MOXA Smartio/Industio serial driver boot-time initialization code! | |
1759 | */ | |
1da177e4 | 1760 | |
c24c31ff | 1761 | static void mxser_initbrd(struct mxser_board *brd, bool high_baud) |
1da177e4 | 1762 | { |
1c45607a JS |
1763 | struct mxser_port *info; |
1764 | unsigned int i; | |
57faa7d6 JS |
1765 | bool is_mu860; |
1766 | ||
1767 | brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr); | |
1768 | is_mu860 = brd->must_hwid == MOXA_MUST_MU860_HWID; | |
1769 | ||
1770 | for (i = 0; i < UART_INFO_NUM; i++) { | |
1771 | if (Gpci_uart_info[i].type == brd->must_hwid) { | |
1772 | brd->max_baud = Gpci_uart_info[i].max_baud; | |
1773 | ||
1774 | /* exception....CP-102 */ | |
c24c31ff | 1775 | if (high_baud) |
57faa7d6 JS |
1776 | brd->max_baud = 921600; |
1777 | break; | |
1778 | } | |
1779 | } | |
1780 | ||
1781 | if (is_mu860) { | |
1782 | /* set to RS232 mode by default */ | |
1783 | outb(0, brd->vector + 4); | |
1784 | outb(0, brd->vector + 0x0c); | |
1785 | } | |
1da177e4 | 1786 | |
c24c31ff | 1787 | for (i = 0; i < brd->nports; i++) { |
1c45607a | 1788 | info = &brd->ports[i]; |
57faa7d6 JS |
1789 | if (is_mu860) { |
1790 | if (i < 4) | |
1791 | info->opmode_ioaddr = brd->vector + 4; | |
1792 | else | |
1793 | info->opmode_ioaddr = brd->vector + 0x0c; | |
1794 | } | |
44b7d1b3 | 1795 | tty_port_init(&info->port); |
31f35939 | 1796 | info->port.ops = &mxser_port_ops; |
1c45607a | 1797 | info->board = brd; |
1da177e4 | 1798 | |
1c45607a | 1799 | /* Enhance mode enabled here */ |
292955a7 | 1800 | if (brd->must_hwid != MOXA_OTHER_UART) |
edb7d27c | 1801 | mxser_must_set_enhance_mode(info->ioaddr, true); |
1da177e4 | 1802 | |
58a2ddb3 | 1803 | info->type = PORT_16550A; |
1da177e4 | 1804 | |
c3db20c3 | 1805 | mxser_process_txrx_fifo(info); |
1da177e4 | 1806 | |
44b7d1b3 AC |
1807 | info->port.close_delay = 5 * HZ / 10; |
1808 | info->port.closing_wait = 30 * HZ; | |
1c45607a | 1809 | spin_lock_init(&info->slock); |
1da177e4 | 1810 | |
1c45607a JS |
1811 | /* before set INT ISR, disable all int */ |
1812 | outb(inb(info->ioaddr + UART_IER) & 0xf0, | |
1813 | info->ioaddr + UART_IER); | |
1814 | } | |
1c45607a | 1815 | } |
1da177e4 | 1816 | |
9671f099 | 1817 | static int mxser_probe(struct pci_dev *pdev, |
1c45607a | 1818 | const struct pci_device_id *ent) |
1da177e4 | 1819 | { |
1c45607a | 1820 | struct mxser_board *brd; |
13d4aba8 | 1821 | unsigned int i, base; |
1c45607a | 1822 | unsigned long ioaddress; |
c24c31ff | 1823 | unsigned short nports = MXSER_NPORTS(ent->driver_data); |
9e17df37 | 1824 | struct device *tty_dev; |
1c45607a | 1825 | int retval = -EINVAL; |
1da177e4 | 1826 | |
f8b6b327 | 1827 | i = find_first_zero_bit(mxser_boards, MXSER_BOARDS); |
1c45607a | 1828 | if (i >= MXSER_BOARDS) { |
83766bc6 JS |
1829 | dev_err(&pdev->dev, "too many boards found (maximum %d), board " |
1830 | "not configured\n", MXSER_BOARDS); | |
1c45607a JS |
1831 | goto err; |
1832 | } | |
1833 | ||
ad1c92ff JS |
1834 | brd = devm_kzalloc(&pdev->dev, struct_size(brd, ports, nports), |
1835 | GFP_KERNEL); | |
f8b6b327 JS |
1836 | if (!brd) |
1837 | goto err; | |
1838 | ||
13d4aba8 | 1839 | brd->idx = i; |
f8b6b327 | 1840 | __set_bit(brd->idx, mxser_boards); |
13d4aba8 | 1841 | base = i * MXSER_PORTS_PER_BOARD; |
1c45607a | 1842 | |
dcb04e21 | 1843 | retval = pcim_enable_device(pdev); |
1c45607a | 1844 | if (retval) { |
83766bc6 | 1845 | dev_err(&pdev->dev, "PCI enable failed\n"); |
f8b6b327 | 1846 | goto err_zero; |
1c45607a JS |
1847 | } |
1848 | ||
1849 | /* io address */ | |
1850 | ioaddress = pci_resource_start(pdev, 2); | |
1851 | retval = pci_request_region(pdev, 2, "mxser(IO)"); | |
1852 | if (retval) | |
f8b6b327 | 1853 | goto err_zero; |
1c45607a | 1854 | |
c24c31ff JS |
1855 | brd->nports = nports; |
1856 | for (i = 0; i < nports; i++) | |
1c45607a JS |
1857 | brd->ports[i].ioaddr = ioaddress + 8 * i; |
1858 | ||
1859 | /* vector */ | |
1860 | ioaddress = pci_resource_start(pdev, 3); | |
1861 | retval = pci_request_region(pdev, 3, "mxser(vector)"); | |
1862 | if (retval) | |
df480518 | 1863 | goto err_zero; |
1c45607a JS |
1864 | brd->vector = ioaddress; |
1865 | ||
1866 | /* irq */ | |
1867 | brd->irq = pdev->irq; | |
1868 | ||
c24c31ff | 1869 | mxser_initbrd(brd, ent->driver_data & MXSER_HIGHBAUD); |
7f0e79dc JS |
1870 | |
1871 | retval = devm_request_irq(&pdev->dev, brd->irq, mxser_interrupt, | |
1872 | IRQF_SHARED, "mxser", brd); | |
1873 | if (retval) { | |
1874 | dev_err(&pdev->dev, "request irq failed"); | |
1875 | goto err_relbrd; | |
1876 | } | |
1c45607a | 1877 | |
c24c31ff | 1878 | for (i = 0; i < nports; i++) { |
9e17df37 | 1879 | tty_dev = tty_port_register_device(&brd->ports[i].port, |
13d4aba8 | 1880 | mxvar_sdriver, base + i, &pdev->dev); |
9e17df37 AK |
1881 | if (IS_ERR(tty_dev)) { |
1882 | retval = PTR_ERR(tty_dev); | |
1b581f17 | 1883 | for (; i > 0; i--) |
9e17df37 | 1884 | tty_unregister_device(mxvar_sdriver, |
13d4aba8 | 1885 | base + i - 1); |
9e17df37 AK |
1886 | goto err_relbrd; |
1887 | } | |
1888 | } | |
1c45607a JS |
1889 | |
1890 | pci_set_drvdata(pdev, brd); | |
1891 | ||
1892 | return 0; | |
9e17df37 | 1893 | err_relbrd: |
c24c31ff | 1894 | for (i = 0; i < nports; i++) |
9e17df37 | 1895 | tty_port_destroy(&brd->ports[i].port); |
df480518 | 1896 | err_zero: |
f8b6b327 | 1897 | __clear_bit(brd->idx, mxser_boards); |
1c45607a JS |
1898 | err: |
1899 | return retval; | |
1da177e4 LT |
1900 | } |
1901 | ||
ae8d8a14 | 1902 | static void mxser_remove(struct pci_dev *pdev) |
1da177e4 | 1903 | { |
1c45607a | 1904 | struct mxser_board *brd = pci_get_drvdata(pdev); |
13d4aba8 | 1905 | unsigned int i, base = brd->idx * MXSER_PORTS_PER_BOARD; |
d450f085 | 1906 | |
c24c31ff | 1907 | for (i = 0; i < brd->nports; i++) { |
13d4aba8 | 1908 | tty_unregister_device(mxvar_sdriver, base + i); |
d450f085 JS |
1909 | tty_port_destroy(&brd->ports[i].port); |
1910 | } | |
1da177e4 | 1911 | |
f8b6b327 | 1912 | __clear_bit(brd->idx, mxser_boards); |
1da177e4 LT |
1913 | } |
1914 | ||
1c45607a JS |
1915 | static struct pci_driver mxser_driver = { |
1916 | .name = "mxser", | |
1917 | .id_table = mxser_pcibrds, | |
1918 | .probe = mxser_probe, | |
91116cba | 1919 | .remove = mxser_remove |
1c45607a JS |
1920 | }; |
1921 | ||
1922 | static int __init mxser_module_init(void) | |
1da177e4 | 1923 | { |
1df00924 | 1924 | int retval; |
1da177e4 | 1925 | |
39b7b42b JS |
1926 | mxvar_sdriver = tty_alloc_driver(MXSER_PORTS, TTY_DRIVER_REAL_RAW | |
1927 | TTY_DRIVER_DYNAMIC_DEV); | |
1928 | if (IS_ERR(mxvar_sdriver)) | |
1929 | return PTR_ERR(mxvar_sdriver); | |
1c45607a | 1930 | |
1c45607a | 1931 | /* Initialize the tty_driver structure */ |
1c45607a JS |
1932 | mxvar_sdriver->name = "ttyMI"; |
1933 | mxvar_sdriver->major = ttymajor; | |
1934 | mxvar_sdriver->minor_start = 0; | |
1c45607a JS |
1935 | mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL; |
1936 | mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL; | |
1937 | mxvar_sdriver->init_termios = tty_std_termios; | |
1938 | mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL; | |
1c45607a JS |
1939 | tty_set_operations(mxvar_sdriver, &mxser_ops); |
1940 | ||
1941 | retval = tty_register_driver(mxvar_sdriver); | |
1942 | if (retval) { | |
1943 | printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family " | |
1944 | "tty driver !\n"); | |
1945 | goto err_put; | |
1da177e4 | 1946 | } |
1c45607a | 1947 | |
1c45607a JS |
1948 | retval = pci_register_driver(&mxser_driver); |
1949 | if (retval) { | |
83766bc6 | 1950 | printk(KERN_ERR "mxser: can't register pci driver\n"); |
29134367 | 1951 | goto err_unr; |
1c45607a JS |
1952 | } |
1953 | ||
1c45607a JS |
1954 | return 0; |
1955 | err_unr: | |
1956 | tty_unregister_driver(mxvar_sdriver); | |
1957 | err_put: | |
9f90a4dd | 1958 | tty_driver_kref_put(mxvar_sdriver); |
1c45607a JS |
1959 | return retval; |
1960 | } | |
1961 | ||
1962 | static void __exit mxser_module_exit(void) | |
1963 | { | |
1c45607a | 1964 | pci_unregister_driver(&mxser_driver); |
1c45607a | 1965 | tty_unregister_driver(mxvar_sdriver); |
9f90a4dd | 1966 | tty_driver_kref_put(mxvar_sdriver); |
1da177e4 LT |
1967 | } |
1968 | ||
1969 | module_init(mxser_module_init); | |
1970 | module_exit(mxser_module_exit); |