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b0407983 MW |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * USB4 specific functionality | |
4 | * | |
5 | * Copyright (C) 2019, Intel Corporation | |
6 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> | |
7 | * Rajmohan Mani <rajmohan.mani@intel.com> | |
8 | */ | |
9 | ||
10 | #include <linux/delay.h> | |
11 | #include <linux/ktime.h> | |
12 | ||
02d12855 | 13 | #include "sb_regs.h" |
b0407983 MW |
14 | #include "tb.h" |
15 | ||
16 | #define USB4_DATA_DWORDS 16 | |
17 | #define USB4_DATA_RETRIES 3 | |
18 | ||
19 | enum usb4_switch_op { | |
20 | USB4_SWITCH_OP_QUERY_DP_RESOURCE = 0x10, | |
21 | USB4_SWITCH_OP_ALLOC_DP_RESOURCE = 0x11, | |
22 | USB4_SWITCH_OP_DEALLOC_DP_RESOURCE = 0x12, | |
23 | USB4_SWITCH_OP_NVM_WRITE = 0x20, | |
24 | USB4_SWITCH_OP_NVM_AUTH = 0x21, | |
25 | USB4_SWITCH_OP_NVM_READ = 0x22, | |
26 | USB4_SWITCH_OP_NVM_SET_OFFSET = 0x23, | |
27 | USB4_SWITCH_OP_DROM_READ = 0x24, | |
28 | USB4_SWITCH_OP_NVM_SECTOR_SIZE = 0x25, | |
29 | }; | |
30 | ||
02d12855 RM |
31 | enum usb4_sb_target { |
32 | USB4_SB_TARGET_ROUTER, | |
33 | USB4_SB_TARGET_PARTNER, | |
34 | USB4_SB_TARGET_RETIMER, | |
35 | }; | |
36 | ||
b0407983 MW |
37 | #define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2) |
38 | #define USB4_NVM_READ_OFFSET_SHIFT 2 | |
39 | #define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24) | |
40 | #define USB4_NVM_READ_LENGTH_SHIFT 24 | |
41 | ||
42 | #define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK | |
43 | #define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT | |
44 | ||
45 | #define USB4_DROM_ADDRESS_MASK GENMASK(14, 2) | |
46 | #define USB4_DROM_ADDRESS_SHIFT 2 | |
47 | #define USB4_DROM_SIZE_MASK GENMASK(19, 15) | |
48 | #define USB4_DROM_SIZE_SHIFT 15 | |
49 | ||
50 | #define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0) | |
51 | ||
7e72846b MW |
52 | typedef int (*read_block_fn)(void *, unsigned int, void *, size_t); |
53 | typedef int (*write_block_fn)(void *, const void *, size_t); | |
b0407983 MW |
54 | |
55 | static int usb4_switch_wait_for_bit(struct tb_switch *sw, u32 offset, u32 bit, | |
56 | u32 value, int timeout_msec) | |
57 | { | |
58 | ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec); | |
59 | ||
60 | do { | |
61 | u32 val; | |
62 | int ret; | |
63 | ||
64 | ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1); | |
65 | if (ret) | |
66 | return ret; | |
67 | ||
68 | if ((val & bit) == value) | |
69 | return 0; | |
70 | ||
71 | usleep_range(50, 100); | |
72 | } while (ktime_before(ktime_get(), timeout)); | |
73 | ||
74 | return -ETIMEDOUT; | |
75 | } | |
76 | ||
77 | static int usb4_switch_op_read_data(struct tb_switch *sw, void *data, | |
78 | size_t dwords) | |
79 | { | |
80 | if (dwords > USB4_DATA_DWORDS) | |
81 | return -EINVAL; | |
82 | ||
83 | return tb_sw_read(sw, data, TB_CFG_SWITCH, ROUTER_CS_9, dwords); | |
84 | } | |
85 | ||
86 | static int usb4_switch_op_write_data(struct tb_switch *sw, const void *data, | |
87 | size_t dwords) | |
88 | { | |
89 | if (dwords > USB4_DATA_DWORDS) | |
90 | return -EINVAL; | |
91 | ||
92 | return tb_sw_write(sw, data, TB_CFG_SWITCH, ROUTER_CS_9, dwords); | |
93 | } | |
94 | ||
7e72846b MW |
95 | static int usb4_do_read_data(u16 address, void *buf, size_t size, |
96 | read_block_fn read_block, void *read_block_data) | |
b0407983 MW |
97 | { |
98 | unsigned int retries = USB4_DATA_RETRIES; | |
99 | unsigned int offset; | |
100 | ||
101 | offset = address & 3; | |
102 | address = address & ~3; | |
103 | ||
104 | do { | |
105 | size_t nbytes = min_t(size_t, size, USB4_DATA_DWORDS * 4); | |
106 | unsigned int dwaddress, dwords; | |
107 | u8 data[USB4_DATA_DWORDS * 4]; | |
108 | int ret; | |
109 | ||
110 | dwaddress = address / 4; | |
111 | dwords = ALIGN(nbytes, 4) / 4; | |
112 | ||
7e72846b | 113 | ret = read_block(read_block_data, dwaddress, data, dwords); |
b0407983 | 114 | if (ret) { |
6bfe3347 MW |
115 | if (ret != -ENODEV && retries--) |
116 | continue; | |
b0407983 MW |
117 | return ret; |
118 | } | |
119 | ||
120 | memcpy(buf, data + offset, nbytes); | |
121 | ||
122 | size -= nbytes; | |
123 | address += nbytes; | |
124 | buf += nbytes; | |
125 | } while (size > 0); | |
126 | ||
127 | return 0; | |
128 | } | |
129 | ||
7e72846b MW |
130 | static int usb4_do_write_data(unsigned int address, const void *buf, size_t size, |
131 | write_block_fn write_next_block, void *write_block_data) | |
b0407983 MW |
132 | { |
133 | unsigned int retries = USB4_DATA_RETRIES; | |
134 | unsigned int offset; | |
135 | ||
136 | offset = address & 3; | |
137 | address = address & ~3; | |
138 | ||
139 | do { | |
140 | u32 nbytes = min_t(u32, size, USB4_DATA_DWORDS * 4); | |
141 | u8 data[USB4_DATA_DWORDS * 4]; | |
142 | int ret; | |
143 | ||
144 | memcpy(data + offset, buf, nbytes); | |
145 | ||
7e72846b | 146 | ret = write_next_block(write_block_data, data, nbytes / 4); |
b0407983 MW |
147 | if (ret) { |
148 | if (ret == -ETIMEDOUT) { | |
149 | if (retries--) | |
150 | continue; | |
151 | ret = -EIO; | |
152 | } | |
153 | return ret; | |
154 | } | |
155 | ||
156 | size -= nbytes; | |
157 | address += nbytes; | |
158 | buf += nbytes; | |
159 | } while (size > 0); | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
fe265a06 MW |
164 | static int usb4_switch_op(struct tb_switch *sw, u16 opcode, u32 *metadata, |
165 | u8 *status) | |
b0407983 MW |
166 | { |
167 | u32 val; | |
168 | int ret; | |
169 | ||
fe265a06 MW |
170 | if (metadata) { |
171 | ret = tb_sw_write(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1); | |
172 | if (ret) | |
173 | return ret; | |
174 | } | |
175 | ||
b0407983 MW |
176 | val = opcode | ROUTER_CS_26_OV; |
177 | ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); | |
178 | if (ret) | |
179 | return ret; | |
180 | ||
181 | ret = usb4_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500); | |
182 | if (ret) | |
183 | return ret; | |
184 | ||
185 | ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); | |
c3bf9930 MW |
186 | if (ret) |
187 | return ret; | |
188 | ||
b0407983 MW |
189 | if (val & ROUTER_CS_26_ONS) |
190 | return -EOPNOTSUPP; | |
191 | ||
661b1947 MW |
192 | if (status) |
193 | *status = (val & ROUTER_CS_26_STATUS_MASK) >> | |
194 | ROUTER_CS_26_STATUS_SHIFT; | |
fe265a06 MW |
195 | |
196 | return metadata ? | |
197 | tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1) : 0; | |
b0407983 MW |
198 | } |
199 | ||
b2911a59 MW |
200 | static void usb4_switch_check_wakes(struct tb_switch *sw) |
201 | { | |
202 | struct tb_port *port; | |
203 | bool wakeup = false; | |
204 | u32 val; | |
205 | ||
206 | if (!device_may_wakeup(&sw->dev)) | |
207 | return; | |
208 | ||
209 | if (tb_route(sw)) { | |
210 | if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1)) | |
211 | return; | |
212 | ||
213 | tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n", | |
214 | (val & ROUTER_CS_6_WOPS) ? "yes" : "no", | |
215 | (val & ROUTER_CS_6_WOUS) ? "yes" : "no"); | |
216 | ||
217 | wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS); | |
218 | } | |
219 | ||
220 | /* Check for any connected downstream ports for USB4 wake */ | |
221 | tb_switch_for_each_port(sw, port) { | |
222 | if (!tb_port_has_remote(port)) | |
223 | continue; | |
224 | ||
225 | if (tb_port_read(port, &val, TB_CFG_PORT, | |
226 | port->cap_usb4 + PORT_CS_18, 1)) | |
227 | break; | |
228 | ||
229 | tb_port_dbg(port, "USB4 wake: %s\n", | |
230 | (val & PORT_CS_18_WOU4S) ? "yes" : "no"); | |
231 | ||
232 | if (val & PORT_CS_18_WOU4S) | |
233 | wakeup = true; | |
234 | } | |
235 | ||
236 | if (wakeup) | |
237 | pm_wakeup_event(&sw->dev, 0); | |
238 | } | |
239 | ||
bbcf40b3 MW |
240 | static bool link_is_usb4(struct tb_port *port) |
241 | { | |
242 | u32 val; | |
243 | ||
244 | if (!port->cap_usb4) | |
245 | return false; | |
246 | ||
247 | if (tb_port_read(port, &val, TB_CFG_PORT, | |
248 | port->cap_usb4 + PORT_CS_18, 1)) | |
249 | return false; | |
250 | ||
251 | return !(val & PORT_CS_18_TCM); | |
252 | } | |
253 | ||
b0407983 MW |
254 | /** |
255 | * usb4_switch_setup() - Additional setup for USB4 device | |
256 | * @sw: USB4 router to setup | |
257 | * | |
258 | * USB4 routers need additional settings in order to enable all the | |
259 | * tunneling. This function enables USB and PCIe tunneling if it can be | |
260 | * enabled (e.g the parent switch also supports them). If USB tunneling | |
261 | * is not available for some reason (like that there is Thunderbolt 3 | |
262 | * switch upstream) then the internal xHCI controller is enabled | |
263 | * instead. | |
264 | */ | |
265 | int usb4_switch_setup(struct tb_switch *sw) | |
266 | { | |
bbcf40b3 | 267 | struct tb_port *downstream_port; |
b0407983 MW |
268 | struct tb_switch *parent; |
269 | bool tbt3, xhci; | |
270 | u32 val = 0; | |
271 | int ret; | |
272 | ||
b2911a59 MW |
273 | usb4_switch_check_wakes(sw); |
274 | ||
b0407983 MW |
275 | if (!tb_route(sw)) |
276 | return 0; | |
277 | ||
278 | ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1); | |
279 | if (ret) | |
280 | return ret; | |
281 | ||
bbcf40b3 MW |
282 | parent = tb_switch_parent(sw); |
283 | downstream_port = tb_port_at(tb_route(sw), parent); | |
284 | sw->link_usb4 = link_is_usb4(downstream_port); | |
285 | tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT3"); | |
286 | ||
b0407983 MW |
287 | xhci = val & ROUTER_CS_6_HCI; |
288 | tbt3 = !(val & ROUTER_CS_6_TNS); | |
289 | ||
290 | tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n", | |
291 | tbt3 ? "yes" : "no", xhci ? "yes" : "no"); | |
292 | ||
293 | ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); | |
294 | if (ret) | |
295 | return ret; | |
296 | ||
bbcf40b3 | 297 | if (sw->link_usb4 && tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) { |
e6f81858 RM |
298 | val |= ROUTER_CS_5_UTO; |
299 | xhci = false; | |
300 | } | |
301 | ||
b0407983 MW |
302 | /* Only enable PCIe tunneling if the parent router supports it */ |
303 | if (tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) { | |
304 | val |= ROUTER_CS_5_PTO; | |
e6f81858 RM |
305 | /* |
306 | * xHCI can be enabled if PCIe tunneling is supported | |
307 | * and the parent does not have any USB3 dowstream | |
308 | * adapters (so we cannot do USB 3.x tunneling). | |
309 | */ | |
c7a7ac84 | 310 | if (xhci) |
b0407983 MW |
311 | val |= ROUTER_CS_5_HCO; |
312 | } | |
313 | ||
314 | /* TBT3 supported by the CM */ | |
315 | val |= ROUTER_CS_5_C3S; | |
316 | /* Tunneling configuration is ready now */ | |
317 | val |= ROUTER_CS_5_CV; | |
318 | ||
319 | ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); | |
320 | if (ret) | |
321 | return ret; | |
322 | ||
323 | return usb4_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR, | |
324 | ROUTER_CS_6_CR, 50); | |
325 | } | |
326 | ||
327 | /** | |
328 | * usb4_switch_read_uid() - Read UID from USB4 router | |
329 | * @sw: USB4 router | |
21d78d86 | 330 | * @uid: UID is stored here |
b0407983 MW |
331 | * |
332 | * Reads 64-bit UID from USB4 router config space. | |
333 | */ | |
334 | int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid) | |
335 | { | |
336 | return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2); | |
337 | } | |
338 | ||
7e72846b | 339 | static int usb4_switch_drom_read_block(void *data, |
b0407983 MW |
340 | unsigned int dwaddress, void *buf, |
341 | size_t dwords) | |
342 | { | |
7e72846b | 343 | struct tb_switch *sw = data; |
b0407983 MW |
344 | u8 status = 0; |
345 | u32 metadata; | |
346 | int ret; | |
347 | ||
348 | metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK; | |
349 | metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) & | |
350 | USB4_DROM_ADDRESS_MASK; | |
351 | ||
fe265a06 | 352 | ret = usb4_switch_op(sw, USB4_SWITCH_OP_DROM_READ, &metadata, &status); |
b0407983 MW |
353 | if (ret) |
354 | return ret; | |
355 | ||
356 | if (status) | |
357 | return -EIO; | |
358 | ||
359 | return usb4_switch_op_read_data(sw, buf, dwords); | |
360 | } | |
361 | ||
362 | /** | |
363 | * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM | |
364 | * @sw: USB4 router | |
21d78d86 MW |
365 | * @address: Byte address inside DROM to start reading |
366 | * @buf: Buffer where the DROM content is stored | |
367 | * @size: Number of bytes to read from DROM | |
b0407983 MW |
368 | * |
369 | * Uses USB4 router operations to read router DROM. For devices this | |
370 | * should always work but for hosts it may return %-EOPNOTSUPP in which | |
371 | * case the host router does not have DROM. | |
372 | */ | |
373 | int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf, | |
374 | size_t size) | |
375 | { | |
7e72846b MW |
376 | return usb4_do_read_data(address, buf, size, |
377 | usb4_switch_drom_read_block, sw); | |
b0407983 MW |
378 | } |
379 | ||
b0407983 MW |
380 | /** |
381 | * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding | |
382 | * @sw: USB4 router | |
383 | * | |
384 | * Checks whether conditions are met so that lane bonding can be | |
385 | * established with the upstream router. Call only for device routers. | |
386 | */ | |
387 | bool usb4_switch_lane_bonding_possible(struct tb_switch *sw) | |
388 | { | |
389 | struct tb_port *up; | |
390 | int ret; | |
391 | u32 val; | |
392 | ||
393 | up = tb_upstream_port(sw); | |
394 | ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1); | |
395 | if (ret) | |
396 | return false; | |
397 | ||
398 | return !!(val & PORT_CS_18_BE); | |
399 | } | |
400 | ||
b2911a59 MW |
401 | /** |
402 | * usb4_switch_set_wake() - Enabled/disable wake | |
403 | * @sw: USB4 router | |
404 | * @flags: Wakeup flags (%0 to disable) | |
405 | * | |
406 | * Enables/disables router to wake up from sleep. | |
407 | */ | |
408 | int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags) | |
409 | { | |
410 | struct tb_port *port; | |
411 | u64 route = tb_route(sw); | |
412 | u32 val; | |
413 | int ret; | |
414 | ||
415 | /* | |
416 | * Enable wakes coming from all USB4 downstream ports (from | |
417 | * child routers). For device routers do this also for the | |
418 | * upstream USB4 port. | |
419 | */ | |
420 | tb_switch_for_each_port(sw, port) { | |
421 | if (!route && tb_is_upstream_port(port)) | |
422 | continue; | |
423 | ||
424 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
425 | port->cap_usb4 + PORT_CS_19, 1); | |
426 | if (ret) | |
427 | return ret; | |
428 | ||
429 | val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4); | |
430 | ||
431 | if (flags & TB_WAKE_ON_CONNECT) | |
432 | val |= PORT_CS_19_WOC; | |
433 | if (flags & TB_WAKE_ON_DISCONNECT) | |
434 | val |= PORT_CS_19_WOD; | |
435 | if (flags & TB_WAKE_ON_USB4) | |
436 | val |= PORT_CS_19_WOU4; | |
437 | ||
438 | ret = tb_port_write(port, &val, TB_CFG_PORT, | |
439 | port->cap_usb4 + PORT_CS_19, 1); | |
440 | if (ret) | |
441 | return ret; | |
442 | } | |
443 | ||
444 | /* | |
445 | * Enable wakes from PCIe and USB 3.x on this router. Only | |
446 | * needed for device routers. | |
447 | */ | |
448 | if (route) { | |
449 | ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); | |
450 | if (ret) | |
451 | return ret; | |
452 | ||
453 | val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU); | |
454 | if (flags & TB_WAKE_ON_USB3) | |
455 | val |= ROUTER_CS_5_WOU; | |
456 | if (flags & TB_WAKE_ON_PCIE) | |
457 | val |= ROUTER_CS_5_WOP; | |
458 | ||
459 | ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); | |
460 | if (ret) | |
461 | return ret; | |
462 | } | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
b0407983 MW |
467 | /** |
468 | * usb4_switch_set_sleep() - Prepare the router to enter sleep | |
469 | * @sw: USB4 router | |
470 | * | |
b2911a59 MW |
471 | * Sets sleep bit for the router. Returns when the router sleep ready |
472 | * bit has been asserted. | |
b0407983 MW |
473 | */ |
474 | int usb4_switch_set_sleep(struct tb_switch *sw) | |
475 | { | |
476 | int ret; | |
477 | u32 val; | |
478 | ||
479 | /* Set sleep bit and wait for sleep ready to be asserted */ | |
480 | ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); | |
481 | if (ret) | |
482 | return ret; | |
483 | ||
484 | val |= ROUTER_CS_5_SLP; | |
485 | ||
486 | ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); | |
487 | if (ret) | |
488 | return ret; | |
489 | ||
490 | return usb4_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR, | |
491 | ROUTER_CS_6_SLPR, 500); | |
492 | } | |
493 | ||
494 | /** | |
495 | * usb4_switch_nvm_sector_size() - Return router NVM sector size | |
496 | * @sw: USB4 router | |
497 | * | |
498 | * If the router supports NVM operations this function returns the NVM | |
499 | * sector size in bytes. If NVM operations are not supported returns | |
500 | * %-EOPNOTSUPP. | |
501 | */ | |
502 | int usb4_switch_nvm_sector_size(struct tb_switch *sw) | |
503 | { | |
504 | u32 metadata; | |
505 | u8 status; | |
506 | int ret; | |
507 | ||
fe265a06 MW |
508 | ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &metadata, |
509 | &status); | |
b0407983 MW |
510 | if (ret) |
511 | return ret; | |
512 | ||
513 | if (status) | |
514 | return status == 0x2 ? -EOPNOTSUPP : -EIO; | |
515 | ||
b0407983 MW |
516 | return metadata & USB4_NVM_SECTOR_SIZE_MASK; |
517 | } | |
518 | ||
7e72846b | 519 | static int usb4_switch_nvm_read_block(void *data, |
b0407983 MW |
520 | unsigned int dwaddress, void *buf, size_t dwords) |
521 | { | |
7e72846b | 522 | struct tb_switch *sw = data; |
b0407983 MW |
523 | u8 status = 0; |
524 | u32 metadata; | |
525 | int ret; | |
526 | ||
527 | metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) & | |
528 | USB4_NVM_READ_LENGTH_MASK; | |
529 | metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) & | |
530 | USB4_NVM_READ_OFFSET_MASK; | |
531 | ||
fe265a06 | 532 | ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_READ, &metadata, &status); |
b0407983 MW |
533 | if (ret) |
534 | return ret; | |
535 | ||
536 | if (status) | |
537 | return -EIO; | |
538 | ||
539 | return usb4_switch_op_read_data(sw, buf, dwords); | |
540 | } | |
541 | ||
542 | /** | |
543 | * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM | |
544 | * @sw: USB4 router | |
545 | * @address: Starting address in bytes | |
546 | * @buf: Read data is placed here | |
547 | * @size: How many bytes to read | |
548 | * | |
549 | * Reads NVM contents of the router. If NVM is not supported returns | |
550 | * %-EOPNOTSUPP. | |
551 | */ | |
552 | int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf, | |
553 | size_t size) | |
554 | { | |
7e72846b MW |
555 | return usb4_do_read_data(address, buf, size, |
556 | usb4_switch_nvm_read_block, sw); | |
b0407983 MW |
557 | } |
558 | ||
559 | static int usb4_switch_nvm_set_offset(struct tb_switch *sw, | |
560 | unsigned int address) | |
561 | { | |
562 | u32 metadata, dwaddress; | |
563 | u8 status = 0; | |
564 | int ret; | |
565 | ||
566 | dwaddress = address / 4; | |
567 | metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) & | |
568 | USB4_NVM_SET_OFFSET_MASK; | |
569 | ||
fe265a06 MW |
570 | ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &metadata, |
571 | &status); | |
b0407983 MW |
572 | if (ret) |
573 | return ret; | |
574 | ||
575 | return status ? -EIO : 0; | |
576 | } | |
577 | ||
7e72846b MW |
578 | static int usb4_switch_nvm_write_next_block(void *data, const void *buf, |
579 | size_t dwords) | |
b0407983 | 580 | { |
7e72846b | 581 | struct tb_switch *sw = data; |
b0407983 MW |
582 | u8 status; |
583 | int ret; | |
584 | ||
585 | ret = usb4_switch_op_write_data(sw, buf, dwords); | |
586 | if (ret) | |
587 | return ret; | |
588 | ||
fe265a06 | 589 | ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_WRITE, NULL, &status); |
b0407983 MW |
590 | if (ret) |
591 | return ret; | |
592 | ||
593 | return status ? -EIO : 0; | |
594 | } | |
595 | ||
596 | /** | |
597 | * usb4_switch_nvm_write() - Write to the router NVM | |
598 | * @sw: USB4 router | |
599 | * @address: Start address where to write in bytes | |
600 | * @buf: Pointer to the data to write | |
601 | * @size: Size of @buf in bytes | |
602 | * | |
603 | * Writes @buf to the router NVM using USB4 router operations. If NVM | |
604 | * write is not supported returns %-EOPNOTSUPP. | |
605 | */ | |
606 | int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address, | |
607 | const void *buf, size_t size) | |
608 | { | |
609 | int ret; | |
610 | ||
611 | ret = usb4_switch_nvm_set_offset(sw, address); | |
612 | if (ret) | |
613 | return ret; | |
614 | ||
7e72846b MW |
615 | return usb4_do_write_data(address, buf, size, |
616 | usb4_switch_nvm_write_next_block, sw); | |
b0407983 MW |
617 | } |
618 | ||
619 | /** | |
620 | * usb4_switch_nvm_authenticate() - Authenticate new NVM | |
621 | * @sw: USB4 router | |
622 | * | |
623 | * After the new NVM has been written via usb4_switch_nvm_write(), this | |
661b1947 MW |
624 | * function triggers NVM authentication process. The router gets power |
625 | * cycled and if the authentication is successful the new NVM starts | |
b0407983 | 626 | * running. In case of failure returns negative errno. |
661b1947 MW |
627 | * |
628 | * The caller should call usb4_switch_nvm_authenticate_status() to read | |
629 | * the status of the authentication after power cycle. It should be the | |
630 | * first router operation to avoid the status being lost. | |
b0407983 MW |
631 | */ |
632 | int usb4_switch_nvm_authenticate(struct tb_switch *sw) | |
633 | { | |
b0407983 MW |
634 | int ret; |
635 | ||
fe265a06 | 636 | ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, NULL, NULL); |
661b1947 MW |
637 | switch (ret) { |
638 | /* | |
639 | * The router is power cycled once NVM_AUTH is started so it is | |
640 | * expected to get any of the following errors back. | |
641 | */ | |
642 | case -EACCES: | |
643 | case -ENOTCONN: | |
644 | case -ETIMEDOUT: | |
645 | return 0; | |
646 | ||
647 | default: | |
648 | return ret; | |
649 | } | |
650 | } | |
651 | ||
652 | /** | |
653 | * usb4_switch_nvm_authenticate_status() - Read status of last NVM authenticate | |
654 | * @sw: USB4 router | |
655 | * @status: Status code of the operation | |
656 | * | |
657 | * The function checks if there is status available from the last NVM | |
658 | * authenticate router operation. If there is status then %0 is returned | |
659 | * and the status code is placed in @status. Returns negative errno in case | |
660 | * of failure. | |
661 | * | |
662 | * Must be called before any other router operation. | |
663 | */ | |
664 | int usb4_switch_nvm_authenticate_status(struct tb_switch *sw, u32 *status) | |
665 | { | |
666 | u16 opcode; | |
667 | u32 val; | |
668 | int ret; | |
669 | ||
670 | ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); | |
b0407983 MW |
671 | if (ret) |
672 | return ret; | |
673 | ||
661b1947 MW |
674 | /* Check that the opcode is correct */ |
675 | opcode = val & ROUTER_CS_26_OPCODE_MASK; | |
676 | if (opcode == USB4_SWITCH_OP_NVM_AUTH) { | |
677 | if (val & ROUTER_CS_26_OV) | |
678 | return -EBUSY; | |
679 | if (val & ROUTER_CS_26_ONS) | |
680 | return -EOPNOTSUPP; | |
681 | ||
682 | *status = (val & ROUTER_CS_26_STATUS_MASK) >> | |
683 | ROUTER_CS_26_STATUS_SHIFT; | |
684 | } else { | |
685 | *status = 0; | |
b0407983 | 686 | } |
661b1947 MW |
687 | |
688 | return 0; | |
b0407983 MW |
689 | } |
690 | ||
691 | /** | |
692 | * usb4_switch_query_dp_resource() - Query availability of DP IN resource | |
693 | * @sw: USB4 router | |
694 | * @in: DP IN adapter | |
695 | * | |
696 | * For DP tunneling this function can be used to query availability of | |
697 | * DP IN resource. Returns true if the resource is available for DP | |
698 | * tunneling, false otherwise. | |
699 | */ | |
700 | bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in) | |
701 | { | |
fe265a06 | 702 | u32 metadata = in->port; |
b0407983 MW |
703 | u8 status; |
704 | int ret; | |
705 | ||
fe265a06 MW |
706 | ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &metadata, |
707 | &status); | |
b0407983 MW |
708 | /* |
709 | * If DP resource allocation is not supported assume it is | |
710 | * always available. | |
711 | */ | |
712 | if (ret == -EOPNOTSUPP) | |
713 | return true; | |
714 | else if (ret) | |
715 | return false; | |
716 | ||
717 | return !status; | |
718 | } | |
719 | ||
720 | /** | |
721 | * usb4_switch_alloc_dp_resource() - Allocate DP IN resource | |
722 | * @sw: USB4 router | |
723 | * @in: DP IN adapter | |
724 | * | |
725 | * Allocates DP IN resource for DP tunneling using USB4 router | |
726 | * operations. If the resource was allocated returns %0. Otherwise | |
727 | * returns negative errno, in particular %-EBUSY if the resource is | |
728 | * already allocated. | |
729 | */ | |
730 | int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in) | |
731 | { | |
fe265a06 | 732 | u32 metadata = in->port; |
b0407983 MW |
733 | u8 status; |
734 | int ret; | |
735 | ||
fe265a06 MW |
736 | ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &metadata, |
737 | &status); | |
b0407983 MW |
738 | if (ret == -EOPNOTSUPP) |
739 | return 0; | |
740 | else if (ret) | |
741 | return ret; | |
742 | ||
743 | return status ? -EBUSY : 0; | |
744 | } | |
745 | ||
746 | /** | |
747 | * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource | |
748 | * @sw: USB4 router | |
749 | * @in: DP IN adapter | |
750 | * | |
751 | * Releases the previously allocated DP IN resource. | |
752 | */ | |
753 | int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in) | |
754 | { | |
fe265a06 | 755 | u32 metadata = in->port; |
b0407983 MW |
756 | u8 status; |
757 | int ret; | |
758 | ||
fe265a06 MW |
759 | ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &metadata, |
760 | &status); | |
b0407983 MW |
761 | if (ret == -EOPNOTSUPP) |
762 | return 0; | |
763 | else if (ret) | |
764 | return ret; | |
765 | ||
766 | return status ? -EIO : 0; | |
767 | } | |
768 | ||
769 | static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port) | |
770 | { | |
771 | struct tb_port *p; | |
772 | int usb4_idx = 0; | |
773 | ||
774 | /* Assume port is primary */ | |
775 | tb_switch_for_each_port(sw, p) { | |
776 | if (!tb_port_is_null(p)) | |
777 | continue; | |
778 | if (tb_is_upstream_port(p)) | |
779 | continue; | |
780 | if (!p->link_nr) { | |
781 | if (p == port) | |
782 | break; | |
783 | usb4_idx++; | |
784 | } | |
785 | } | |
786 | ||
787 | return usb4_idx; | |
788 | } | |
789 | ||
790 | /** | |
791 | * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter | |
792 | * @sw: USB4 router | |
793 | * @port: USB4 port | |
794 | * | |
795 | * USB4 routers have direct mapping between USB4 ports and PCIe | |
796 | * downstream adapters where the PCIe topology is extended. This | |
797 | * function returns the corresponding downstream PCIe adapter or %NULL | |
798 | * if no such mapping was possible. | |
799 | */ | |
800 | struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw, | |
801 | const struct tb_port *port) | |
802 | { | |
803 | int usb4_idx = usb4_port_idx(sw, port); | |
804 | struct tb_port *p; | |
805 | int pcie_idx = 0; | |
806 | ||
807 | /* Find PCIe down port matching usb4_port */ | |
808 | tb_switch_for_each_port(sw, p) { | |
809 | if (!tb_port_is_pcie_down(p)) | |
810 | continue; | |
811 | ||
9cac51a0 | 812 | if (pcie_idx == usb4_idx) |
b0407983 MW |
813 | return p; |
814 | ||
815 | pcie_idx++; | |
816 | } | |
817 | ||
818 | return NULL; | |
819 | } | |
820 | ||
e6f81858 RM |
821 | /** |
822 | * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter | |
823 | * @sw: USB4 router | |
824 | * @port: USB4 port | |
825 | * | |
826 | * USB4 routers have direct mapping between USB4 ports and USB 3.x | |
827 | * downstream adapters where the USB 3.x topology is extended. This | |
828 | * function returns the corresponding downstream USB 3.x adapter or | |
829 | * %NULL if no such mapping was possible. | |
830 | */ | |
831 | struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw, | |
832 | const struct tb_port *port) | |
833 | { | |
834 | int usb4_idx = usb4_port_idx(sw, port); | |
835 | struct tb_port *p; | |
836 | int usb_idx = 0; | |
837 | ||
838 | /* Find USB3 down port matching usb4_port */ | |
839 | tb_switch_for_each_port(sw, p) { | |
840 | if (!tb_port_is_usb3_down(p)) | |
841 | continue; | |
842 | ||
77cfa40f | 843 | if (usb_idx == usb4_idx) |
e6f81858 RM |
844 | return p; |
845 | ||
846 | usb_idx++; | |
847 | } | |
848 | ||
849 | return NULL; | |
850 | } | |
851 | ||
b0407983 MW |
852 | /** |
853 | * usb4_port_unlock() - Unlock USB4 downstream port | |
854 | * @port: USB4 port to unlock | |
855 | * | |
856 | * Unlocks USB4 downstream port so that the connection manager can | |
857 | * access the router below this port. | |
858 | */ | |
859 | int usb4_port_unlock(struct tb_port *port) | |
860 | { | |
861 | int ret; | |
862 | u32 val; | |
863 | ||
864 | ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1); | |
865 | if (ret) | |
866 | return ret; | |
867 | ||
868 | val &= ~ADP_CS_4_LCK; | |
869 | return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1); | |
870 | } | |
3b1d8d57 | 871 | |
e28178bf MW |
872 | static int usb4_port_set_configured(struct tb_port *port, bool configured) |
873 | { | |
874 | int ret; | |
875 | u32 val; | |
876 | ||
877 | if (!port->cap_usb4) | |
878 | return -EINVAL; | |
879 | ||
880 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
881 | port->cap_usb4 + PORT_CS_19, 1); | |
882 | if (ret) | |
883 | return ret; | |
884 | ||
885 | if (configured) | |
886 | val |= PORT_CS_19_PC; | |
887 | else | |
888 | val &= ~PORT_CS_19_PC; | |
889 | ||
890 | return tb_port_write(port, &val, TB_CFG_PORT, | |
891 | port->cap_usb4 + PORT_CS_19, 1); | |
892 | } | |
893 | ||
894 | /** | |
895 | * usb4_port_configure() - Set USB4 port configured | |
896 | * @port: USB4 router | |
897 | * | |
898 | * Sets the USB4 link to be configured for power management purposes. | |
899 | */ | |
900 | int usb4_port_configure(struct tb_port *port) | |
901 | { | |
902 | return usb4_port_set_configured(port, true); | |
903 | } | |
904 | ||
905 | /** | |
906 | * usb4_port_unconfigure() - Set USB4 port unconfigured | |
907 | * @port: USB4 router | |
908 | * | |
909 | * Sets the USB4 link to be unconfigured for power management purposes. | |
910 | */ | |
911 | void usb4_port_unconfigure(struct tb_port *port) | |
912 | { | |
913 | usb4_port_set_configured(port, false); | |
914 | } | |
915 | ||
284652a4 MW |
916 | static int usb4_set_xdomain_configured(struct tb_port *port, bool configured) |
917 | { | |
918 | int ret; | |
919 | u32 val; | |
920 | ||
921 | if (!port->cap_usb4) | |
922 | return -EINVAL; | |
923 | ||
924 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
925 | port->cap_usb4 + PORT_CS_19, 1); | |
926 | if (ret) | |
927 | return ret; | |
928 | ||
929 | if (configured) | |
930 | val |= PORT_CS_19_PID; | |
931 | else | |
932 | val &= ~PORT_CS_19_PID; | |
933 | ||
934 | return tb_port_write(port, &val, TB_CFG_PORT, | |
935 | port->cap_usb4 + PORT_CS_19, 1); | |
936 | } | |
937 | ||
938 | /** | |
939 | * usb4_port_configure_xdomain() - Configure port for XDomain | |
940 | * @port: USB4 port connected to another host | |
941 | * | |
942 | * Marks the USB4 port as being connected to another host. Returns %0 in | |
943 | * success and negative errno in failure. | |
944 | */ | |
945 | int usb4_port_configure_xdomain(struct tb_port *port) | |
946 | { | |
947 | return usb4_set_xdomain_configured(port, true); | |
948 | } | |
949 | ||
950 | /** | |
951 | * usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain | |
952 | * @port: USB4 port that was connected to another host | |
953 | * | |
954 | * Clears USB4 port from being marked as XDomain. | |
955 | */ | |
956 | void usb4_port_unconfigure_xdomain(struct tb_port *port) | |
957 | { | |
958 | usb4_set_xdomain_configured(port, false); | |
959 | } | |
960 | ||
3b1d8d57 MW |
961 | static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit, |
962 | u32 value, int timeout_msec) | |
963 | { | |
964 | ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec); | |
965 | ||
966 | do { | |
967 | u32 val; | |
968 | int ret; | |
969 | ||
970 | ret = tb_port_read(port, &val, TB_CFG_PORT, offset, 1); | |
971 | if (ret) | |
972 | return ret; | |
973 | ||
974 | if ((val & bit) == value) | |
975 | return 0; | |
976 | ||
977 | usleep_range(50, 100); | |
978 | } while (ktime_before(ktime_get(), timeout)); | |
979 | ||
980 | return -ETIMEDOUT; | |
981 | } | |
982 | ||
02d12855 RM |
983 | static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords) |
984 | { | |
985 | if (dwords > USB4_DATA_DWORDS) | |
986 | return -EINVAL; | |
987 | ||
988 | return tb_port_read(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2, | |
989 | dwords); | |
990 | } | |
991 | ||
992 | static int usb4_port_write_data(struct tb_port *port, const void *data, | |
993 | size_t dwords) | |
994 | { | |
995 | if (dwords > USB4_DATA_DWORDS) | |
996 | return -EINVAL; | |
997 | ||
998 | return tb_port_write(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2, | |
999 | dwords); | |
1000 | } | |
1001 | ||
1002 | static int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target, | |
1003 | u8 index, u8 reg, void *buf, u8 size) | |
1004 | { | |
1005 | size_t dwords = DIV_ROUND_UP(size, 4); | |
1006 | int ret; | |
1007 | u32 val; | |
1008 | ||
1009 | if (!port->cap_usb4) | |
1010 | return -EINVAL; | |
1011 | ||
1012 | val = reg; | |
1013 | val |= size << PORT_CS_1_LENGTH_SHIFT; | |
1014 | val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK; | |
1015 | if (target == USB4_SB_TARGET_RETIMER) | |
1016 | val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT); | |
1017 | val |= PORT_CS_1_PND; | |
1018 | ||
1019 | ret = tb_port_write(port, &val, TB_CFG_PORT, | |
1020 | port->cap_usb4 + PORT_CS_1, 1); | |
1021 | if (ret) | |
1022 | return ret; | |
1023 | ||
1024 | ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1, | |
1025 | PORT_CS_1_PND, 0, 500); | |
1026 | if (ret) | |
1027 | return ret; | |
1028 | ||
1029 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1030 | port->cap_usb4 + PORT_CS_1, 1); | |
1031 | if (ret) | |
1032 | return ret; | |
1033 | ||
1034 | if (val & PORT_CS_1_NR) | |
1035 | return -ENODEV; | |
1036 | if (val & PORT_CS_1_RC) | |
1037 | return -EIO; | |
1038 | ||
1039 | return buf ? usb4_port_read_data(port, buf, dwords) : 0; | |
1040 | } | |
1041 | ||
1042 | static int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target, | |
1043 | u8 index, u8 reg, const void *buf, u8 size) | |
1044 | { | |
1045 | size_t dwords = DIV_ROUND_UP(size, 4); | |
1046 | int ret; | |
1047 | u32 val; | |
1048 | ||
1049 | if (!port->cap_usb4) | |
1050 | return -EINVAL; | |
1051 | ||
1052 | if (buf) { | |
1053 | ret = usb4_port_write_data(port, buf, dwords); | |
1054 | if (ret) | |
1055 | return ret; | |
1056 | } | |
1057 | ||
1058 | val = reg; | |
1059 | val |= size << PORT_CS_1_LENGTH_SHIFT; | |
1060 | val |= PORT_CS_1_WNR_WRITE; | |
1061 | val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK; | |
1062 | if (target == USB4_SB_TARGET_RETIMER) | |
1063 | val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT); | |
1064 | val |= PORT_CS_1_PND; | |
1065 | ||
1066 | ret = tb_port_write(port, &val, TB_CFG_PORT, | |
1067 | port->cap_usb4 + PORT_CS_1, 1); | |
1068 | if (ret) | |
1069 | return ret; | |
1070 | ||
1071 | ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1, | |
1072 | PORT_CS_1_PND, 0, 500); | |
1073 | if (ret) | |
1074 | return ret; | |
1075 | ||
1076 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1077 | port->cap_usb4 + PORT_CS_1, 1); | |
1078 | if (ret) | |
1079 | return ret; | |
1080 | ||
1081 | if (val & PORT_CS_1_NR) | |
1082 | return -ENODEV; | |
1083 | if (val & PORT_CS_1_RC) | |
1084 | return -EIO; | |
1085 | ||
1086 | return 0; | |
1087 | } | |
1088 | ||
1089 | static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target, | |
1090 | u8 index, enum usb4_sb_opcode opcode, int timeout_msec) | |
1091 | { | |
1092 | ktime_t timeout; | |
1093 | u32 val; | |
1094 | int ret; | |
1095 | ||
1096 | val = opcode; | |
1097 | ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, &val, | |
1098 | sizeof(val)); | |
1099 | if (ret) | |
1100 | return ret; | |
1101 | ||
1102 | timeout = ktime_add_ms(ktime_get(), timeout_msec); | |
1103 | ||
1104 | do { | |
1105 | /* Check results */ | |
1106 | ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE, | |
1107 | &val, sizeof(val)); | |
1108 | if (ret) | |
1109 | return ret; | |
1110 | ||
1111 | switch (val) { | |
1112 | case 0: | |
1113 | return 0; | |
1114 | ||
1115 | case USB4_SB_OPCODE_ERR: | |
1116 | return -EAGAIN; | |
1117 | ||
1118 | case USB4_SB_OPCODE_ONS: | |
1119 | return -EOPNOTSUPP; | |
1120 | ||
1121 | default: | |
1122 | if (val != opcode) | |
1123 | return -EIO; | |
1124 | break; | |
1125 | } | |
1126 | } while (ktime_before(ktime_get(), timeout)); | |
1127 | ||
1128 | return -ETIMEDOUT; | |
1129 | } | |
1130 | ||
1131 | /** | |
1132 | * usb4_port_enumerate_retimers() - Send RT broadcast transaction | |
1133 | * @port: USB4 port | |
1134 | * | |
1135 | * This forces the USB4 port to send broadcast RT transaction which | |
1136 | * makes the retimers on the link to assign index to themselves. Returns | |
1137 | * %0 in case of success and negative errno if there was an error. | |
1138 | */ | |
1139 | int usb4_port_enumerate_retimers(struct tb_port *port) | |
1140 | { | |
1141 | u32 val; | |
1142 | ||
1143 | val = USB4_SB_OPCODE_ENUMERATE_RETIMERS; | |
1144 | return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0, | |
1145 | USB4_SB_OPCODE, &val, sizeof(val)); | |
1146 | } | |
1147 | ||
1148 | static inline int usb4_port_retimer_op(struct tb_port *port, u8 index, | |
1149 | enum usb4_sb_opcode opcode, | |
1150 | int timeout_msec) | |
1151 | { | |
1152 | return usb4_port_sb_op(port, USB4_SB_TARGET_RETIMER, index, opcode, | |
1153 | timeout_msec); | |
1154 | } | |
1155 | ||
1156 | /** | |
1157 | * usb4_port_retimer_read() - Read from retimer sideband registers | |
1158 | * @port: USB4 port | |
1159 | * @index: Retimer index | |
1160 | * @reg: Sideband register to read | |
1161 | * @buf: Data from @reg is stored here | |
1162 | * @size: Number of bytes to read | |
1163 | * | |
1164 | * Function reads retimer sideband registers starting from @reg. The | |
1165 | * retimer is connected to @port at @index. Returns %0 in case of | |
1166 | * success, and read data is copied to @buf. If there is no retimer | |
1167 | * present at given @index returns %-ENODEV. In any other failure | |
1168 | * returns negative errno. | |
1169 | */ | |
1170 | int usb4_port_retimer_read(struct tb_port *port, u8 index, u8 reg, void *buf, | |
1171 | u8 size) | |
1172 | { | |
1173 | return usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index, reg, buf, | |
1174 | size); | |
1175 | } | |
1176 | ||
1177 | /** | |
1178 | * usb4_port_retimer_write() - Write to retimer sideband registers | |
1179 | * @port: USB4 port | |
1180 | * @index: Retimer index | |
1181 | * @reg: Sideband register to write | |
1182 | * @buf: Data that is written starting from @reg | |
1183 | * @size: Number of bytes to write | |
1184 | * | |
1185 | * Writes retimer sideband registers starting from @reg. The retimer is | |
1186 | * connected to @port at @index. Returns %0 in case of success. If there | |
1187 | * is no retimer present at given @index returns %-ENODEV. In any other | |
1188 | * failure returns negative errno. | |
1189 | */ | |
1190 | int usb4_port_retimer_write(struct tb_port *port, u8 index, u8 reg, | |
1191 | const void *buf, u8 size) | |
1192 | { | |
1193 | return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, reg, buf, | |
1194 | size); | |
1195 | } | |
1196 | ||
1197 | /** | |
1198 | * usb4_port_retimer_is_last() - Is the retimer last on-board retimer | |
1199 | * @port: USB4 port | |
1200 | * @index: Retimer index | |
1201 | * | |
1202 | * If the retimer at @index is last one (connected directly to the | |
1203 | * Type-C port) this function returns %1. If it is not returns %0. If | |
1204 | * the retimer is not present returns %-ENODEV. Otherwise returns | |
1205 | * negative errno. | |
1206 | */ | |
1207 | int usb4_port_retimer_is_last(struct tb_port *port, u8 index) | |
1208 | { | |
1209 | u32 metadata; | |
1210 | int ret; | |
1211 | ||
1212 | ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_LAST_RETIMER, | |
1213 | 500); | |
1214 | if (ret) | |
1215 | return ret; | |
1216 | ||
1217 | ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata, | |
1218 | sizeof(metadata)); | |
1219 | return ret ? ret : metadata & 1; | |
1220 | } | |
1221 | ||
1222 | /** | |
1223 | * usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size | |
1224 | * @port: USB4 port | |
1225 | * @index: Retimer index | |
1226 | * | |
1227 | * Reads NVM sector size (in bytes) of a retimer at @index. This | |
1228 | * operation can be used to determine whether the retimer supports NVM | |
1229 | * upgrade for example. Returns sector size in bytes or negative errno | |
1230 | * in case of error. Specifically returns %-ENODEV if there is no | |
1231 | * retimer at @index. | |
1232 | */ | |
1233 | int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index) | |
1234 | { | |
1235 | u32 metadata; | |
1236 | int ret; | |
1237 | ||
1238 | ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE, | |
1239 | 500); | |
1240 | if (ret) | |
1241 | return ret; | |
1242 | ||
1243 | ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata, | |
1244 | sizeof(metadata)); | |
1245 | return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK; | |
1246 | } | |
1247 | ||
1248 | static int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index, | |
1249 | unsigned int address) | |
1250 | { | |
1251 | u32 metadata, dwaddress; | |
1252 | int ret; | |
1253 | ||
1254 | dwaddress = address / 4; | |
1255 | metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) & | |
1256 | USB4_NVM_SET_OFFSET_MASK; | |
1257 | ||
1258 | ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata, | |
1259 | sizeof(metadata)); | |
1260 | if (ret) | |
1261 | return ret; | |
1262 | ||
1263 | return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_SET_OFFSET, | |
1264 | 500); | |
1265 | } | |
1266 | ||
1267 | struct retimer_info { | |
1268 | struct tb_port *port; | |
1269 | u8 index; | |
1270 | }; | |
1271 | ||
1272 | static int usb4_port_retimer_nvm_write_next_block(void *data, const void *buf, | |
1273 | size_t dwords) | |
1274 | ||
1275 | { | |
1276 | const struct retimer_info *info = data; | |
1277 | struct tb_port *port = info->port; | |
1278 | u8 index = info->index; | |
1279 | int ret; | |
1280 | ||
1281 | ret = usb4_port_retimer_write(port, index, USB4_SB_DATA, | |
1282 | buf, dwords * 4); | |
1283 | if (ret) | |
1284 | return ret; | |
1285 | ||
1286 | return usb4_port_retimer_op(port, index, | |
1287 | USB4_SB_OPCODE_NVM_BLOCK_WRITE, 1000); | |
1288 | } | |
1289 | ||
1290 | /** | |
1291 | * usb4_port_retimer_nvm_write() - Write to retimer NVM | |
1292 | * @port: USB4 port | |
1293 | * @index: Retimer index | |
1294 | * @address: Byte address where to start the write | |
1295 | * @buf: Data to write | |
1296 | * @size: Size in bytes how much to write | |
1297 | * | |
1298 | * Writes @size bytes from @buf to the retimer NVM. Used for NVM | |
1299 | * upgrade. Returns %0 if the data was written successfully and negative | |
1300 | * errno in case of failure. Specifically returns %-ENODEV if there is | |
1301 | * no retimer at @index. | |
1302 | */ | |
1303 | int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address, | |
1304 | const void *buf, size_t size) | |
1305 | { | |
1306 | struct retimer_info info = { .port = port, .index = index }; | |
1307 | int ret; | |
1308 | ||
1309 | ret = usb4_port_retimer_nvm_set_offset(port, index, address); | |
1310 | if (ret) | |
1311 | return ret; | |
1312 | ||
1313 | return usb4_do_write_data(address, buf, size, | |
1314 | usb4_port_retimer_nvm_write_next_block, &info); | |
1315 | } | |
1316 | ||
1317 | /** | |
1318 | * usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade | |
1319 | * @port: USB4 port | |
1320 | * @index: Retimer index | |
1321 | * | |
1322 | * After the new NVM image has been written via usb4_port_retimer_nvm_write() | |
1323 | * this function can be used to trigger the NVM upgrade process. If | |
1324 | * successful the retimer restarts with the new NVM and may not have the | |
1325 | * index set so one needs to call usb4_port_enumerate_retimers() to | |
1326 | * force index to be assigned. | |
1327 | */ | |
1328 | int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index) | |
1329 | { | |
1330 | u32 val; | |
1331 | ||
1332 | /* | |
1333 | * We need to use the raw operation here because once the | |
1334 | * authentication completes the retimer index is not set anymore | |
1335 | * so we do not get back the status now. | |
1336 | */ | |
1337 | val = USB4_SB_OPCODE_NVM_AUTH_WRITE; | |
1338 | return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, | |
1339 | USB4_SB_OPCODE, &val, sizeof(val)); | |
1340 | } | |
1341 | ||
1342 | /** | |
1343 | * usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade | |
1344 | * @port: USB4 port | |
1345 | * @index: Retimer index | |
1346 | * @status: Raw status code read from metadata | |
1347 | * | |
1348 | * This can be called after usb4_port_retimer_nvm_authenticate() and | |
1349 | * usb4_port_enumerate_retimers() to fetch status of the NVM upgrade. | |
1350 | * | |
1351 | * Returns %0 if the authentication status was successfully read. The | |
1352 | * completion metadata (the result) is then stored into @status. If | |
1353 | * reading the status fails, returns negative errno. | |
1354 | */ | |
1355 | int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index, | |
1356 | u32 *status) | |
1357 | { | |
1358 | u32 metadata, val; | |
1359 | int ret; | |
1360 | ||
1361 | ret = usb4_port_retimer_read(port, index, USB4_SB_OPCODE, &val, | |
1362 | sizeof(val)); | |
1363 | if (ret) | |
1364 | return ret; | |
1365 | ||
1366 | switch (val) { | |
1367 | case 0: | |
1368 | *status = 0; | |
1369 | return 0; | |
1370 | ||
1371 | case USB4_SB_OPCODE_ERR: | |
1372 | ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, | |
1373 | &metadata, sizeof(metadata)); | |
1374 | if (ret) | |
1375 | return ret; | |
1376 | ||
1377 | *status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK; | |
1378 | return 0; | |
1379 | ||
1380 | case USB4_SB_OPCODE_ONS: | |
1381 | return -EOPNOTSUPP; | |
1382 | ||
1383 | default: | |
1384 | return -EIO; | |
1385 | } | |
1386 | } | |
1387 | ||
1388 | static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress, | |
1389 | void *buf, size_t dwords) | |
1390 | { | |
1391 | const struct retimer_info *info = data; | |
1392 | struct tb_port *port = info->port; | |
1393 | u8 index = info->index; | |
1394 | u32 metadata; | |
1395 | int ret; | |
1396 | ||
1397 | metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT; | |
1398 | if (dwords < USB4_DATA_DWORDS) | |
1399 | metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT; | |
1400 | ||
1401 | ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata, | |
1402 | sizeof(metadata)); | |
1403 | if (ret) | |
1404 | return ret; | |
1405 | ||
1406 | ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_READ, 500); | |
1407 | if (ret) | |
1408 | return ret; | |
1409 | ||
1410 | return usb4_port_retimer_read(port, index, USB4_SB_DATA, buf, | |
1411 | dwords * 4); | |
1412 | } | |
1413 | ||
1414 | /** | |
1415 | * usb4_port_retimer_nvm_read() - Read contents of retimer NVM | |
1416 | * @port: USB4 port | |
1417 | * @index: Retimer index | |
1418 | * @address: NVM address (in bytes) to start reading | |
1419 | * @buf: Data read from NVM is stored here | |
1420 | * @size: Number of bytes to read | |
1421 | * | |
1422 | * Reads retimer NVM and copies the contents to @buf. Returns %0 if the | |
1423 | * read was successful and negative errno in case of failure. | |
1424 | * Specifically returns %-ENODEV if there is no retimer at @index. | |
1425 | */ | |
1426 | int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index, | |
1427 | unsigned int address, void *buf, size_t size) | |
1428 | { | |
1429 | struct retimer_info info = { .port = port, .index = index }; | |
1430 | ||
1431 | return usb4_do_read_data(address, buf, size, | |
1432 | usb4_port_retimer_nvm_read_block, &info); | |
1433 | } | |
1434 | ||
3b1d8d57 MW |
1435 | /** |
1436 | * usb4_usb3_port_max_link_rate() - Maximum support USB3 link rate | |
1437 | * @port: USB3 adapter port | |
1438 | * | |
1439 | * Return maximum supported link rate of a USB3 adapter in Mb/s. | |
1440 | * Negative errno in case of error. | |
1441 | */ | |
1442 | int usb4_usb3_port_max_link_rate(struct tb_port *port) | |
1443 | { | |
1444 | int ret, lr; | |
1445 | u32 val; | |
1446 | ||
1447 | if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port)) | |
1448 | return -EINVAL; | |
1449 | ||
1450 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1451 | port->cap_adap + ADP_USB3_CS_4, 1); | |
1452 | if (ret) | |
1453 | return ret; | |
1454 | ||
1455 | lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT; | |
1456 | return lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000; | |
1457 | } | |
1458 | ||
1459 | /** | |
1460 | * usb4_usb3_port_actual_link_rate() - Established USB3 link rate | |
1461 | * @port: USB3 adapter port | |
1462 | * | |
1463 | * Return actual established link rate of a USB3 adapter in Mb/s. If the | |
1464 | * link is not up returns %0 and negative errno in case of failure. | |
1465 | */ | |
1466 | int usb4_usb3_port_actual_link_rate(struct tb_port *port) | |
1467 | { | |
1468 | int ret, lr; | |
1469 | u32 val; | |
1470 | ||
1471 | if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port)) | |
1472 | return -EINVAL; | |
1473 | ||
1474 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1475 | port->cap_adap + ADP_USB3_CS_4, 1); | |
1476 | if (ret) | |
1477 | return ret; | |
1478 | ||
1479 | if (!(val & ADP_USB3_CS_4_ULV)) | |
1480 | return 0; | |
1481 | ||
1482 | lr = val & ADP_USB3_CS_4_ALR_MASK; | |
1483 | return lr == ADP_USB3_CS_4_ALR_20G ? 20000 : 10000; | |
1484 | } | |
1485 | ||
1486 | static int usb4_usb3_port_cm_request(struct tb_port *port, bool request) | |
1487 | { | |
1488 | int ret; | |
1489 | u32 val; | |
1490 | ||
1491 | if (!tb_port_is_usb3_down(port)) | |
1492 | return -EINVAL; | |
1493 | if (tb_route(port->sw)) | |
1494 | return -EINVAL; | |
1495 | ||
1496 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1497 | port->cap_adap + ADP_USB3_CS_2, 1); | |
1498 | if (ret) | |
1499 | return ret; | |
1500 | ||
1501 | if (request) | |
1502 | val |= ADP_USB3_CS_2_CMR; | |
1503 | else | |
1504 | val &= ~ADP_USB3_CS_2_CMR; | |
1505 | ||
1506 | ret = tb_port_write(port, &val, TB_CFG_PORT, | |
1507 | port->cap_adap + ADP_USB3_CS_2, 1); | |
1508 | if (ret) | |
1509 | return ret; | |
1510 | ||
1511 | /* | |
1512 | * We can use val here directly as the CMR bit is in the same place | |
1513 | * as HCA. Just mask out others. | |
1514 | */ | |
1515 | val &= ADP_USB3_CS_2_CMR; | |
1516 | return usb4_port_wait_for_bit(port, port->cap_adap + ADP_USB3_CS_1, | |
1517 | ADP_USB3_CS_1_HCA, val, 1500); | |
1518 | } | |
1519 | ||
1520 | static inline int usb4_usb3_port_set_cm_request(struct tb_port *port) | |
1521 | { | |
1522 | return usb4_usb3_port_cm_request(port, true); | |
1523 | } | |
1524 | ||
1525 | static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port) | |
1526 | { | |
1527 | return usb4_usb3_port_cm_request(port, false); | |
1528 | } | |
1529 | ||
1530 | static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale) | |
1531 | { | |
1532 | unsigned long uframes; | |
1533 | ||
4c767ce4 | 1534 | uframes = bw * 512UL << scale; |
3b1d8d57 MW |
1535 | return DIV_ROUND_CLOSEST(uframes * 8000, 1000 * 1000); |
1536 | } | |
1537 | ||
1538 | static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale) | |
1539 | { | |
1540 | unsigned long uframes; | |
1541 | ||
1542 | /* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */ | |
1543 | uframes = ((unsigned long)mbps * 1000 * 1000) / 8000; | |
4c767ce4 | 1544 | return DIV_ROUND_UP(uframes, 512UL << scale); |
3b1d8d57 MW |
1545 | } |
1546 | ||
1547 | static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port, | |
1548 | int *upstream_bw, | |
1549 | int *downstream_bw) | |
1550 | { | |
1551 | u32 val, bw, scale; | |
1552 | int ret; | |
1553 | ||
1554 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1555 | port->cap_adap + ADP_USB3_CS_2, 1); | |
1556 | if (ret) | |
1557 | return ret; | |
1558 | ||
1559 | ret = tb_port_read(port, &scale, TB_CFG_PORT, | |
1560 | port->cap_adap + ADP_USB3_CS_3, 1); | |
1561 | if (ret) | |
1562 | return ret; | |
1563 | ||
1564 | scale &= ADP_USB3_CS_3_SCALE_MASK; | |
1565 | ||
1566 | bw = val & ADP_USB3_CS_2_AUBW_MASK; | |
1567 | *upstream_bw = usb3_bw_to_mbps(bw, scale); | |
1568 | ||
1569 | bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT; | |
1570 | *downstream_bw = usb3_bw_to_mbps(bw, scale); | |
1571 | ||
1572 | return 0; | |
1573 | } | |
1574 | ||
1575 | /** | |
1576 | * usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3 | |
1577 | * @port: USB3 adapter port | |
1578 | * @upstream_bw: Allocated upstream bandwidth is stored here | |
1579 | * @downstream_bw: Allocated downstream bandwidth is stored here | |
1580 | * | |
1581 | * Stores currently allocated USB3 bandwidth into @upstream_bw and | |
1582 | * @downstream_bw in Mb/s. Returns %0 in case of success and negative | |
1583 | * errno in failure. | |
1584 | */ | |
1585 | int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw, | |
1586 | int *downstream_bw) | |
1587 | { | |
1588 | int ret; | |
1589 | ||
1590 | ret = usb4_usb3_port_set_cm_request(port); | |
1591 | if (ret) | |
1592 | return ret; | |
1593 | ||
1594 | ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw, | |
1595 | downstream_bw); | |
1596 | usb4_usb3_port_clear_cm_request(port); | |
1597 | ||
1598 | return ret; | |
1599 | } | |
1600 | ||
1601 | static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port, | |
1602 | int *upstream_bw, | |
1603 | int *downstream_bw) | |
1604 | { | |
1605 | u32 val, bw, scale; | |
1606 | int ret; | |
1607 | ||
1608 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1609 | port->cap_adap + ADP_USB3_CS_1, 1); | |
1610 | if (ret) | |
1611 | return ret; | |
1612 | ||
1613 | ret = tb_port_read(port, &scale, TB_CFG_PORT, | |
1614 | port->cap_adap + ADP_USB3_CS_3, 1); | |
1615 | if (ret) | |
1616 | return ret; | |
1617 | ||
1618 | scale &= ADP_USB3_CS_3_SCALE_MASK; | |
1619 | ||
1620 | bw = val & ADP_USB3_CS_1_CUBW_MASK; | |
1621 | *upstream_bw = usb3_bw_to_mbps(bw, scale); | |
1622 | ||
1623 | bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT; | |
1624 | *downstream_bw = usb3_bw_to_mbps(bw, scale); | |
1625 | ||
1626 | return 0; | |
1627 | } | |
1628 | ||
1629 | static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port, | |
1630 | int upstream_bw, | |
1631 | int downstream_bw) | |
1632 | { | |
1633 | u32 val, ubw, dbw, scale; | |
1634 | int ret; | |
1635 | ||
1636 | /* Read the used scale, hardware default is 0 */ | |
1637 | ret = tb_port_read(port, &scale, TB_CFG_PORT, | |
1638 | port->cap_adap + ADP_USB3_CS_3, 1); | |
1639 | if (ret) | |
1640 | return ret; | |
1641 | ||
1642 | scale &= ADP_USB3_CS_3_SCALE_MASK; | |
1643 | ubw = mbps_to_usb3_bw(upstream_bw, scale); | |
1644 | dbw = mbps_to_usb3_bw(downstream_bw, scale); | |
1645 | ||
1646 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1647 | port->cap_adap + ADP_USB3_CS_2, 1); | |
1648 | if (ret) | |
1649 | return ret; | |
1650 | ||
1651 | val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK); | |
1652 | val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT; | |
1653 | val |= ubw; | |
1654 | ||
1655 | return tb_port_write(port, &val, TB_CFG_PORT, | |
1656 | port->cap_adap + ADP_USB3_CS_2, 1); | |
1657 | } | |
1658 | ||
1659 | /** | |
1660 | * usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3 | |
1661 | * @port: USB3 adapter port | |
1662 | * @upstream_bw: New upstream bandwidth | |
1663 | * @downstream_bw: New downstream bandwidth | |
1664 | * | |
1665 | * This can be used to set how much bandwidth is allocated for the USB3 | |
1666 | * tunneled isochronous traffic. @upstream_bw and @downstream_bw are the | |
1667 | * new values programmed to the USB3 adapter allocation registers. If | |
1668 | * the values are lower than what is currently consumed the allocation | |
1669 | * is set to what is currently consumed instead (consumed bandwidth | |
1670 | * cannot be taken away by CM). The actual new values are returned in | |
1671 | * @upstream_bw and @downstream_bw. | |
1672 | * | |
1673 | * Returns %0 in case of success and negative errno if there was a | |
1674 | * failure. | |
1675 | */ | |
1676 | int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw, | |
1677 | int *downstream_bw) | |
1678 | { | |
1679 | int ret, consumed_up, consumed_down, allocate_up, allocate_down; | |
1680 | ||
1681 | ret = usb4_usb3_port_set_cm_request(port); | |
1682 | if (ret) | |
1683 | return ret; | |
1684 | ||
1685 | ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up, | |
1686 | &consumed_down); | |
1687 | if (ret) | |
1688 | goto err_request; | |
1689 | ||
1690 | /* Don't allow it go lower than what is consumed */ | |
1691 | allocate_up = max(*upstream_bw, consumed_up); | |
1692 | allocate_down = max(*downstream_bw, consumed_down); | |
1693 | ||
1694 | ret = usb4_usb3_port_write_allocated_bandwidth(port, allocate_up, | |
1695 | allocate_down); | |
1696 | if (ret) | |
1697 | goto err_request; | |
1698 | ||
1699 | *upstream_bw = allocate_up; | |
1700 | *downstream_bw = allocate_down; | |
1701 | ||
1702 | err_request: | |
1703 | usb4_usb3_port_clear_cm_request(port); | |
1704 | return ret; | |
1705 | } | |
1706 | ||
1707 | /** | |
1708 | * usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth | |
1709 | * @port: USB3 adapter port | |
1710 | * @upstream_bw: New allocated upstream bandwidth | |
1711 | * @downstream_bw: New allocated downstream bandwidth | |
1712 | * | |
1713 | * Releases USB3 allocated bandwidth down to what is actually consumed. | |
1714 | * The new bandwidth is returned in @upstream_bw and @downstream_bw. | |
1715 | * | |
1716 | * Returns 0% in success and negative errno in case of failure. | |
1717 | */ | |
1718 | int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw, | |
1719 | int *downstream_bw) | |
1720 | { | |
1721 | int ret, consumed_up, consumed_down; | |
1722 | ||
1723 | ret = usb4_usb3_port_set_cm_request(port); | |
1724 | if (ret) | |
1725 | return ret; | |
1726 | ||
1727 | ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up, | |
1728 | &consumed_down); | |
1729 | if (ret) | |
1730 | goto err_request; | |
1731 | ||
1732 | /* | |
1733 | * Always keep 1000 Mb/s to make sure xHCI has at least some | |
1734 | * bandwidth available for isochronous traffic. | |
1735 | */ | |
1736 | if (consumed_up < 1000) | |
1737 | consumed_up = 1000; | |
1738 | if (consumed_down < 1000) | |
1739 | consumed_down = 1000; | |
1740 | ||
1741 | ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up, | |
1742 | consumed_down); | |
1743 | if (ret) | |
1744 | goto err_request; | |
1745 | ||
1746 | *upstream_bw = consumed_up; | |
1747 | *downstream_bw = consumed_down; | |
1748 | ||
1749 | err_request: | |
1750 | usb4_usb3_port_clear_cm_request(port); | |
1751 | return ret; | |
1752 | } |