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b0407983 MW |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * USB4 specific functionality | |
4 | * | |
5 | * Copyright (C) 2019, Intel Corporation | |
6 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> | |
7 | * Rajmohan Mani <rajmohan.mani@intel.com> | |
8 | */ | |
9 | ||
10 | #include <linux/delay.h> | |
11 | #include <linux/ktime.h> | |
12 | ||
02d12855 | 13 | #include "sb_regs.h" |
b0407983 MW |
14 | #include "tb.h" |
15 | ||
b0407983 MW |
16 | #define USB4_DATA_RETRIES 3 |
17 | ||
02d12855 RM |
18 | enum usb4_sb_target { |
19 | USB4_SB_TARGET_ROUTER, | |
20 | USB4_SB_TARGET_PARTNER, | |
21 | USB4_SB_TARGET_RETIMER, | |
22 | }; | |
23 | ||
b0407983 MW |
24 | #define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2) |
25 | #define USB4_NVM_READ_OFFSET_SHIFT 2 | |
26 | #define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24) | |
27 | #define USB4_NVM_READ_LENGTH_SHIFT 24 | |
28 | ||
29 | #define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK | |
30 | #define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT | |
31 | ||
32 | #define USB4_DROM_ADDRESS_MASK GENMASK(14, 2) | |
33 | #define USB4_DROM_ADDRESS_SHIFT 2 | |
34 | #define USB4_DROM_SIZE_MASK GENMASK(19, 15) | |
35 | #define USB4_DROM_SIZE_SHIFT 15 | |
36 | ||
37 | #define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0) | |
38 | ||
56ad3aef MW |
39 | #define USB4_BA_LENGTH_MASK GENMASK(7, 0) |
40 | #define USB4_BA_INDEX_MASK GENMASK(15, 0) | |
41 | ||
42 | enum usb4_ba_index { | |
43 | USB4_BA_MAX_USB3 = 0x1, | |
44 | USB4_BA_MIN_DP_AUX = 0x2, | |
45 | USB4_BA_MIN_DP_MAIN = 0x3, | |
46 | USB4_BA_MAX_PCIE = 0x4, | |
47 | USB4_BA_MAX_HI = 0x5, | |
48 | }; | |
49 | ||
50 | #define USB4_BA_VALUE_MASK GENMASK(31, 16) | |
51 | #define USB4_BA_VALUE_SHIFT 16 | |
52 | ||
9490f711 MW |
53 | static int usb4_native_switch_op(struct tb_switch *sw, u16 opcode, |
54 | u32 *metadata, u8 *status, | |
55 | const void *tx_data, size_t tx_dwords, | |
56 | void *rx_data, size_t rx_dwords) | |
b0407983 MW |
57 | { |
58 | u32 val; | |
59 | int ret; | |
60 | ||
fe265a06 MW |
61 | if (metadata) { |
62 | ret = tb_sw_write(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1); | |
63 | if (ret) | |
64 | return ret; | |
65 | } | |
83bab44a MW |
66 | if (tx_dwords) { |
67 | ret = tb_sw_write(sw, tx_data, TB_CFG_SWITCH, ROUTER_CS_9, | |
68 | tx_dwords); | |
69 | if (ret) | |
70 | return ret; | |
71 | } | |
fe265a06 | 72 | |
b0407983 MW |
73 | val = opcode | ROUTER_CS_26_OV; |
74 | ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); | |
75 | if (ret) | |
76 | return ret; | |
77 | ||
1639664f | 78 | ret = tb_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500); |
b0407983 MW |
79 | if (ret) |
80 | return ret; | |
81 | ||
82 | ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); | |
c3bf9930 MW |
83 | if (ret) |
84 | return ret; | |
85 | ||
b0407983 MW |
86 | if (val & ROUTER_CS_26_ONS) |
87 | return -EOPNOTSUPP; | |
88 | ||
661b1947 MW |
89 | if (status) |
90 | *status = (val & ROUTER_CS_26_STATUS_MASK) >> | |
91 | ROUTER_CS_26_STATUS_SHIFT; | |
fe265a06 | 92 | |
83bab44a MW |
93 | if (metadata) { |
94 | ret = tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1); | |
95 | if (ret) | |
96 | return ret; | |
97 | } | |
98 | if (rx_dwords) { | |
99 | ret = tb_sw_read(sw, rx_data, TB_CFG_SWITCH, ROUTER_CS_9, | |
100 | rx_dwords); | |
101 | if (ret) | |
102 | return ret; | |
103 | } | |
104 | ||
b0407983 MW |
105 | return 0; |
106 | } | |
107 | ||
9490f711 MW |
108 | static int __usb4_switch_op(struct tb_switch *sw, u16 opcode, u32 *metadata, |
109 | u8 *status, const void *tx_data, size_t tx_dwords, | |
110 | void *rx_data, size_t rx_dwords) | |
111 | { | |
112 | const struct tb_cm_ops *cm_ops = sw->tb->cm_ops; | |
113 | ||
9b383037 | 114 | if (tx_dwords > NVM_DATA_DWORDS || rx_dwords > NVM_DATA_DWORDS) |
9490f711 MW |
115 | return -EINVAL; |
116 | ||
117 | /* | |
118 | * If the connection manager implementation provides USB4 router | |
119 | * operation proxy callback, call it here instead of running the | |
120 | * operation natively. | |
121 | */ | |
122 | if (cm_ops->usb4_switch_op) { | |
123 | int ret; | |
124 | ||
125 | ret = cm_ops->usb4_switch_op(sw, opcode, metadata, status, | |
126 | tx_data, tx_dwords, rx_data, | |
127 | rx_dwords); | |
128 | if (ret != -EOPNOTSUPP) | |
129 | return ret; | |
130 | ||
131 | /* | |
132 | * If the proxy was not supported then run the native | |
133 | * router operation instead. | |
134 | */ | |
135 | } | |
136 | ||
137 | return usb4_native_switch_op(sw, opcode, metadata, status, tx_data, | |
138 | tx_dwords, rx_data, rx_dwords); | |
139 | } | |
140 | ||
83bab44a MW |
141 | static inline int usb4_switch_op(struct tb_switch *sw, u16 opcode, |
142 | u32 *metadata, u8 *status) | |
143 | { | |
144 | return __usb4_switch_op(sw, opcode, metadata, status, NULL, 0, NULL, 0); | |
145 | } | |
146 | ||
147 | static inline int usb4_switch_op_data(struct tb_switch *sw, u16 opcode, | |
148 | u32 *metadata, u8 *status, | |
149 | const void *tx_data, size_t tx_dwords, | |
150 | void *rx_data, size_t rx_dwords) | |
151 | { | |
152 | return __usb4_switch_op(sw, opcode, metadata, status, tx_data, | |
153 | tx_dwords, rx_data, rx_dwords); | |
b0407983 MW |
154 | } |
155 | ||
b2911a59 MW |
156 | static void usb4_switch_check_wakes(struct tb_switch *sw) |
157 | { | |
a5cfc9d6 RK |
158 | bool wakeup_usb4 = false; |
159 | struct usb4_port *usb4; | |
b2911a59 MW |
160 | struct tb_port *port; |
161 | bool wakeup = false; | |
162 | u32 val; | |
163 | ||
164 | if (!device_may_wakeup(&sw->dev)) | |
165 | return; | |
166 | ||
167 | if (tb_route(sw)) { | |
168 | if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1)) | |
169 | return; | |
170 | ||
171 | tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n", | |
172 | (val & ROUTER_CS_6_WOPS) ? "yes" : "no", | |
173 | (val & ROUTER_CS_6_WOUS) ? "yes" : "no"); | |
174 | ||
175 | wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS); | |
176 | } | |
177 | ||
a5cfc9d6 RK |
178 | /* |
179 | * Check for any downstream ports for USB4 wake, | |
180 | * connection wake and disconnection wake. | |
181 | */ | |
b2911a59 | 182 | tb_switch_for_each_port(sw, port) { |
a5cfc9d6 | 183 | if (!port->cap_usb4) |
b2911a59 MW |
184 | continue; |
185 | ||
186 | if (tb_port_read(port, &val, TB_CFG_PORT, | |
187 | port->cap_usb4 + PORT_CS_18, 1)) | |
188 | break; | |
189 | ||
a5cfc9d6 RK |
190 | tb_port_dbg(port, "USB4 wake: %s, connection wake: %s, disconnection wake: %s\n", |
191 | (val & PORT_CS_18_WOU4S) ? "yes" : "no", | |
192 | (val & PORT_CS_18_WOCS) ? "yes" : "no", | |
193 | (val & PORT_CS_18_WODS) ? "yes" : "no"); | |
194 | ||
195 | wakeup_usb4 = val & (PORT_CS_18_WOU4S | PORT_CS_18_WOCS | | |
196 | PORT_CS_18_WODS); | |
197 | ||
198 | usb4 = port->usb4; | |
199 | if (device_may_wakeup(&usb4->dev) && wakeup_usb4) | |
200 | pm_wakeup_event(&usb4->dev, 0); | |
b2911a59 | 201 | |
a5cfc9d6 | 202 | wakeup |= wakeup_usb4; |
b2911a59 MW |
203 | } |
204 | ||
205 | if (wakeup) | |
206 | pm_wakeup_event(&sw->dev, 0); | |
207 | } | |
208 | ||
bbcf40b3 MW |
209 | static bool link_is_usb4(struct tb_port *port) |
210 | { | |
211 | u32 val; | |
212 | ||
213 | if (!port->cap_usb4) | |
214 | return false; | |
215 | ||
216 | if (tb_port_read(port, &val, TB_CFG_PORT, | |
217 | port->cap_usb4 + PORT_CS_18, 1)) | |
218 | return false; | |
219 | ||
220 | return !(val & PORT_CS_18_TCM); | |
221 | } | |
222 | ||
b0407983 MW |
223 | /** |
224 | * usb4_switch_setup() - Additional setup for USB4 device | |
225 | * @sw: USB4 router to setup | |
226 | * | |
227 | * USB4 routers need additional settings in order to enable all the | |
228 | * tunneling. This function enables USB and PCIe tunneling if it can be | |
229 | * enabled (e.g the parent switch also supports them). If USB tunneling | |
230 | * is not available for some reason (like that there is Thunderbolt 3 | |
231 | * switch upstream) then the internal xHCI controller is enabled | |
232 | * instead. | |
233 | */ | |
234 | int usb4_switch_setup(struct tb_switch *sw) | |
235 | { | |
bbcf40b3 | 236 | struct tb_port *downstream_port; |
b0407983 MW |
237 | struct tb_switch *parent; |
238 | bool tbt3, xhci; | |
239 | u32 val = 0; | |
240 | int ret; | |
241 | ||
b2911a59 MW |
242 | usb4_switch_check_wakes(sw); |
243 | ||
b0407983 MW |
244 | if (!tb_route(sw)) |
245 | return 0; | |
246 | ||
247 | ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1); | |
248 | if (ret) | |
249 | return ret; | |
250 | ||
bbcf40b3 MW |
251 | parent = tb_switch_parent(sw); |
252 | downstream_port = tb_port_at(tb_route(sw), parent); | |
253 | sw->link_usb4 = link_is_usb4(downstream_port); | |
0f28879c | 254 | tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT"); |
bbcf40b3 | 255 | |
b0407983 MW |
256 | xhci = val & ROUTER_CS_6_HCI; |
257 | tbt3 = !(val & ROUTER_CS_6_TNS); | |
258 | ||
259 | tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n", | |
260 | tbt3 ? "yes" : "no", xhci ? "yes" : "no"); | |
261 | ||
262 | ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); | |
263 | if (ret) | |
264 | return ret; | |
265 | ||
c6da62a2 MW |
266 | if (tb_acpi_may_tunnel_usb3() && sw->link_usb4 && |
267 | tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) { | |
e6f81858 RM |
268 | val |= ROUTER_CS_5_UTO; |
269 | xhci = false; | |
270 | } | |
271 | ||
c6da62a2 MW |
272 | /* |
273 | * Only enable PCIe tunneling if the parent router supports it | |
274 | * and it is not disabled. | |
275 | */ | |
276 | if (tb_acpi_may_tunnel_pcie() && | |
277 | tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) { | |
b0407983 | 278 | val |= ROUTER_CS_5_PTO; |
e6f81858 RM |
279 | /* |
280 | * xHCI can be enabled if PCIe tunneling is supported | |
281 | * and the parent does not have any USB3 dowstream | |
282 | * adapters (so we cannot do USB 3.x tunneling). | |
283 | */ | |
c7a7ac84 | 284 | if (xhci) |
b0407983 MW |
285 | val |= ROUTER_CS_5_HCO; |
286 | } | |
287 | ||
288 | /* TBT3 supported by the CM */ | |
289 | val |= ROUTER_CS_5_C3S; | |
290 | /* Tunneling configuration is ready now */ | |
291 | val |= ROUTER_CS_5_CV; | |
292 | ||
293 | ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); | |
294 | if (ret) | |
295 | return ret; | |
296 | ||
1639664f GF |
297 | return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR, |
298 | ROUTER_CS_6_CR, 50); | |
b0407983 MW |
299 | } |
300 | ||
301 | /** | |
302 | * usb4_switch_read_uid() - Read UID from USB4 router | |
303 | * @sw: USB4 router | |
21d78d86 | 304 | * @uid: UID is stored here |
b0407983 MW |
305 | * |
306 | * Reads 64-bit UID from USB4 router config space. | |
307 | */ | |
308 | int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid) | |
309 | { | |
310 | return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2); | |
311 | } | |
312 | ||
7e72846b | 313 | static int usb4_switch_drom_read_block(void *data, |
b0407983 MW |
314 | unsigned int dwaddress, void *buf, |
315 | size_t dwords) | |
316 | { | |
7e72846b | 317 | struct tb_switch *sw = data; |
b0407983 MW |
318 | u8 status = 0; |
319 | u32 metadata; | |
320 | int ret; | |
321 | ||
322 | metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK; | |
323 | metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) & | |
324 | USB4_DROM_ADDRESS_MASK; | |
325 | ||
83bab44a MW |
326 | ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_DROM_READ, &metadata, |
327 | &status, NULL, 0, buf, dwords); | |
b0407983 MW |
328 | if (ret) |
329 | return ret; | |
330 | ||
83bab44a | 331 | return status ? -EIO : 0; |
b0407983 MW |
332 | } |
333 | ||
334 | /** | |
335 | * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM | |
336 | * @sw: USB4 router | |
21d78d86 MW |
337 | * @address: Byte address inside DROM to start reading |
338 | * @buf: Buffer where the DROM content is stored | |
339 | * @size: Number of bytes to read from DROM | |
b0407983 MW |
340 | * |
341 | * Uses USB4 router operations to read router DROM. For devices this | |
342 | * should always work but for hosts it may return %-EOPNOTSUPP in which | |
343 | * case the host router does not have DROM. | |
344 | */ | |
345 | int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf, | |
346 | size_t size) | |
347 | { | |
9b383037 MW |
348 | return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES, |
349 | usb4_switch_drom_read_block, sw); | |
b0407983 MW |
350 | } |
351 | ||
b0407983 MW |
352 | /** |
353 | * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding | |
354 | * @sw: USB4 router | |
355 | * | |
356 | * Checks whether conditions are met so that lane bonding can be | |
357 | * established with the upstream router. Call only for device routers. | |
358 | */ | |
359 | bool usb4_switch_lane_bonding_possible(struct tb_switch *sw) | |
360 | { | |
361 | struct tb_port *up; | |
362 | int ret; | |
363 | u32 val; | |
364 | ||
365 | up = tb_upstream_port(sw); | |
366 | ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1); | |
367 | if (ret) | |
368 | return false; | |
369 | ||
370 | return !!(val & PORT_CS_18_BE); | |
371 | } | |
372 | ||
b2911a59 MW |
373 | /** |
374 | * usb4_switch_set_wake() - Enabled/disable wake | |
375 | * @sw: USB4 router | |
376 | * @flags: Wakeup flags (%0 to disable) | |
377 | * | |
378 | * Enables/disables router to wake up from sleep. | |
379 | */ | |
380 | int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags) | |
381 | { | |
a5cfc9d6 | 382 | struct usb4_port *usb4; |
b2911a59 MW |
383 | struct tb_port *port; |
384 | u64 route = tb_route(sw); | |
385 | u32 val; | |
386 | int ret; | |
387 | ||
388 | /* | |
389 | * Enable wakes coming from all USB4 downstream ports (from | |
390 | * child routers). For device routers do this also for the | |
391 | * upstream USB4 port. | |
392 | */ | |
393 | tb_switch_for_each_port(sw, port) { | |
f8fa2c2e MW |
394 | if (!tb_port_is_null(port)) |
395 | continue; | |
b2911a59 MW |
396 | if (!route && tb_is_upstream_port(port)) |
397 | continue; | |
f8fa2c2e MW |
398 | if (!port->cap_usb4) |
399 | continue; | |
b2911a59 MW |
400 | |
401 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
402 | port->cap_usb4 + PORT_CS_19, 1); | |
403 | if (ret) | |
404 | return ret; | |
405 | ||
406 | val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4); | |
407 | ||
3caf8887 | 408 | if (tb_is_upstream_port(port)) { |
b2911a59 | 409 | val |= PORT_CS_19_WOU4; |
3caf8887 MW |
410 | } else { |
411 | bool configured = val & PORT_CS_19_PC; | |
a5cfc9d6 | 412 | usb4 = port->usb4; |
3caf8887 | 413 | |
a5cfc9d6 RK |
414 | if (((flags & TB_WAKE_ON_CONNECT) | |
415 | device_may_wakeup(&usb4->dev)) && !configured) | |
3caf8887 | 416 | val |= PORT_CS_19_WOC; |
a5cfc9d6 RK |
417 | if (((flags & TB_WAKE_ON_DISCONNECT) | |
418 | device_may_wakeup(&usb4->dev)) && configured) | |
3caf8887 MW |
419 | val |= PORT_CS_19_WOD; |
420 | if ((flags & TB_WAKE_ON_USB4) && configured) | |
421 | val |= PORT_CS_19_WOU4; | |
422 | } | |
b2911a59 MW |
423 | |
424 | ret = tb_port_write(port, &val, TB_CFG_PORT, | |
425 | port->cap_usb4 + PORT_CS_19, 1); | |
426 | if (ret) | |
427 | return ret; | |
428 | } | |
429 | ||
430 | /* | |
6026b703 | 431 | * Enable wakes from PCIe, USB 3.x and DP on this router. Only |
b2911a59 MW |
432 | * needed for device routers. |
433 | */ | |
434 | if (route) { | |
435 | ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); | |
436 | if (ret) | |
437 | return ret; | |
438 | ||
6026b703 | 439 | val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU | ROUTER_CS_5_WOD); |
b2911a59 MW |
440 | if (flags & TB_WAKE_ON_USB3) |
441 | val |= ROUTER_CS_5_WOU; | |
442 | if (flags & TB_WAKE_ON_PCIE) | |
443 | val |= ROUTER_CS_5_WOP; | |
6026b703 MW |
444 | if (flags & TB_WAKE_ON_DP) |
445 | val |= ROUTER_CS_5_WOD; | |
b2911a59 MW |
446 | |
447 | ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); | |
448 | if (ret) | |
449 | return ret; | |
450 | } | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
b0407983 MW |
455 | /** |
456 | * usb4_switch_set_sleep() - Prepare the router to enter sleep | |
457 | * @sw: USB4 router | |
458 | * | |
b2911a59 MW |
459 | * Sets sleep bit for the router. Returns when the router sleep ready |
460 | * bit has been asserted. | |
b0407983 MW |
461 | */ |
462 | int usb4_switch_set_sleep(struct tb_switch *sw) | |
463 | { | |
464 | int ret; | |
465 | u32 val; | |
466 | ||
467 | /* Set sleep bit and wait for sleep ready to be asserted */ | |
468 | ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); | |
469 | if (ret) | |
470 | return ret; | |
471 | ||
472 | val |= ROUTER_CS_5_SLP; | |
473 | ||
474 | ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); | |
475 | if (ret) | |
476 | return ret; | |
477 | ||
1639664f GF |
478 | return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR, |
479 | ROUTER_CS_6_SLPR, 500); | |
b0407983 MW |
480 | } |
481 | ||
482 | /** | |
483 | * usb4_switch_nvm_sector_size() - Return router NVM sector size | |
484 | * @sw: USB4 router | |
485 | * | |
486 | * If the router supports NVM operations this function returns the NVM | |
487 | * sector size in bytes. If NVM operations are not supported returns | |
488 | * %-EOPNOTSUPP. | |
489 | */ | |
490 | int usb4_switch_nvm_sector_size(struct tb_switch *sw) | |
491 | { | |
492 | u32 metadata; | |
493 | u8 status; | |
494 | int ret; | |
495 | ||
fe265a06 MW |
496 | ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &metadata, |
497 | &status); | |
b0407983 MW |
498 | if (ret) |
499 | return ret; | |
500 | ||
501 | if (status) | |
502 | return status == 0x2 ? -EOPNOTSUPP : -EIO; | |
503 | ||
b0407983 MW |
504 | return metadata & USB4_NVM_SECTOR_SIZE_MASK; |
505 | } | |
506 | ||
7e72846b | 507 | static int usb4_switch_nvm_read_block(void *data, |
b0407983 MW |
508 | unsigned int dwaddress, void *buf, size_t dwords) |
509 | { | |
7e72846b | 510 | struct tb_switch *sw = data; |
b0407983 MW |
511 | u8 status = 0; |
512 | u32 metadata; | |
513 | int ret; | |
514 | ||
515 | metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) & | |
516 | USB4_NVM_READ_LENGTH_MASK; | |
517 | metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) & | |
518 | USB4_NVM_READ_OFFSET_MASK; | |
519 | ||
83bab44a MW |
520 | ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_READ, &metadata, |
521 | &status, NULL, 0, buf, dwords); | |
b0407983 MW |
522 | if (ret) |
523 | return ret; | |
524 | ||
83bab44a | 525 | return status ? -EIO : 0; |
b0407983 MW |
526 | } |
527 | ||
528 | /** | |
529 | * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM | |
530 | * @sw: USB4 router | |
531 | * @address: Starting address in bytes | |
532 | * @buf: Read data is placed here | |
533 | * @size: How many bytes to read | |
534 | * | |
535 | * Reads NVM contents of the router. If NVM is not supported returns | |
536 | * %-EOPNOTSUPP. | |
537 | */ | |
538 | int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf, | |
539 | size_t size) | |
540 | { | |
9b383037 MW |
541 | return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES, |
542 | usb4_switch_nvm_read_block, sw); | |
b0407983 MW |
543 | } |
544 | ||
1cbf680f MW |
545 | /** |
546 | * usb4_switch_nvm_set_offset() - Set NVM write offset | |
547 | * @sw: USB4 router | |
548 | * @address: Start offset | |
549 | * | |
550 | * Explicitly sets NVM write offset. Normally when writing to NVM this | |
551 | * is done automatically by usb4_switch_nvm_write(). | |
552 | * | |
553 | * Returns %0 in success and negative errno if there was a failure. | |
554 | */ | |
555 | int usb4_switch_nvm_set_offset(struct tb_switch *sw, unsigned int address) | |
b0407983 MW |
556 | { |
557 | u32 metadata, dwaddress; | |
558 | u8 status = 0; | |
559 | int ret; | |
560 | ||
561 | dwaddress = address / 4; | |
562 | metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) & | |
563 | USB4_NVM_SET_OFFSET_MASK; | |
564 | ||
fe265a06 MW |
565 | ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &metadata, |
566 | &status); | |
b0407983 MW |
567 | if (ret) |
568 | return ret; | |
569 | ||
570 | return status ? -EIO : 0; | |
571 | } | |
572 | ||
9b383037 MW |
573 | static int usb4_switch_nvm_write_next_block(void *data, unsigned int dwaddress, |
574 | const void *buf, size_t dwords) | |
b0407983 | 575 | { |
7e72846b | 576 | struct tb_switch *sw = data; |
b0407983 MW |
577 | u8 status; |
578 | int ret; | |
579 | ||
83bab44a MW |
580 | ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_WRITE, NULL, &status, |
581 | buf, dwords, NULL, 0); | |
b0407983 MW |
582 | if (ret) |
583 | return ret; | |
584 | ||
585 | return status ? -EIO : 0; | |
586 | } | |
587 | ||
588 | /** | |
589 | * usb4_switch_nvm_write() - Write to the router NVM | |
590 | * @sw: USB4 router | |
591 | * @address: Start address where to write in bytes | |
592 | * @buf: Pointer to the data to write | |
593 | * @size: Size of @buf in bytes | |
594 | * | |
595 | * Writes @buf to the router NVM using USB4 router operations. If NVM | |
596 | * write is not supported returns %-EOPNOTSUPP. | |
597 | */ | |
598 | int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address, | |
599 | const void *buf, size_t size) | |
600 | { | |
601 | int ret; | |
602 | ||
603 | ret = usb4_switch_nvm_set_offset(sw, address); | |
604 | if (ret) | |
605 | return ret; | |
606 | ||
9b383037 MW |
607 | return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES, |
608 | usb4_switch_nvm_write_next_block, sw); | |
b0407983 MW |
609 | } |
610 | ||
611 | /** | |
612 | * usb4_switch_nvm_authenticate() - Authenticate new NVM | |
613 | * @sw: USB4 router | |
614 | * | |
615 | * After the new NVM has been written via usb4_switch_nvm_write(), this | |
661b1947 MW |
616 | * function triggers NVM authentication process. The router gets power |
617 | * cycled and if the authentication is successful the new NVM starts | |
b0407983 | 618 | * running. In case of failure returns negative errno. |
661b1947 MW |
619 | * |
620 | * The caller should call usb4_switch_nvm_authenticate_status() to read | |
621 | * the status of the authentication after power cycle. It should be the | |
622 | * first router operation to avoid the status being lost. | |
b0407983 MW |
623 | */ |
624 | int usb4_switch_nvm_authenticate(struct tb_switch *sw) | |
625 | { | |
b0407983 MW |
626 | int ret; |
627 | ||
fe265a06 | 628 | ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, NULL, NULL); |
661b1947 MW |
629 | switch (ret) { |
630 | /* | |
631 | * The router is power cycled once NVM_AUTH is started so it is | |
632 | * expected to get any of the following errors back. | |
633 | */ | |
634 | case -EACCES: | |
635 | case -ENOTCONN: | |
636 | case -ETIMEDOUT: | |
637 | return 0; | |
638 | ||
639 | default: | |
640 | return ret; | |
641 | } | |
642 | } | |
643 | ||
644 | /** | |
645 | * usb4_switch_nvm_authenticate_status() - Read status of last NVM authenticate | |
646 | * @sw: USB4 router | |
647 | * @status: Status code of the operation | |
648 | * | |
649 | * The function checks if there is status available from the last NVM | |
650 | * authenticate router operation. If there is status then %0 is returned | |
651 | * and the status code is placed in @status. Returns negative errno in case | |
652 | * of failure. | |
653 | * | |
654 | * Must be called before any other router operation. | |
655 | */ | |
656 | int usb4_switch_nvm_authenticate_status(struct tb_switch *sw, u32 *status) | |
657 | { | |
9490f711 | 658 | const struct tb_cm_ops *cm_ops = sw->tb->cm_ops; |
661b1947 MW |
659 | u16 opcode; |
660 | u32 val; | |
661 | int ret; | |
662 | ||
9490f711 MW |
663 | if (cm_ops->usb4_switch_nvm_authenticate_status) { |
664 | ret = cm_ops->usb4_switch_nvm_authenticate_status(sw, status); | |
665 | if (ret != -EOPNOTSUPP) | |
666 | return ret; | |
667 | } | |
668 | ||
661b1947 | 669 | ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); |
b0407983 MW |
670 | if (ret) |
671 | return ret; | |
672 | ||
661b1947 MW |
673 | /* Check that the opcode is correct */ |
674 | opcode = val & ROUTER_CS_26_OPCODE_MASK; | |
675 | if (opcode == USB4_SWITCH_OP_NVM_AUTH) { | |
676 | if (val & ROUTER_CS_26_OV) | |
677 | return -EBUSY; | |
678 | if (val & ROUTER_CS_26_ONS) | |
679 | return -EOPNOTSUPP; | |
680 | ||
681 | *status = (val & ROUTER_CS_26_STATUS_MASK) >> | |
682 | ROUTER_CS_26_STATUS_SHIFT; | |
683 | } else { | |
684 | *status = 0; | |
b0407983 | 685 | } |
661b1947 MW |
686 | |
687 | return 0; | |
b0407983 MW |
688 | } |
689 | ||
56ad3aef MW |
690 | /** |
691 | * usb4_switch_credits_init() - Read buffer allocation parameters | |
692 | * @sw: USB4 router | |
693 | * | |
694 | * Reads @sw buffer allocation parameters and initializes @sw buffer | |
695 | * allocation fields accordingly. Specifically @sw->credits_allocation | |
696 | * is set to %true if these parameters can be used in tunneling. | |
697 | * | |
698 | * Returns %0 on success and negative errno otherwise. | |
699 | */ | |
700 | int usb4_switch_credits_init(struct tb_switch *sw) | |
701 | { | |
702 | int max_usb3, min_dp_aux, min_dp_main, max_pcie, max_dma; | |
703 | int ret, length, i, nports; | |
704 | const struct tb_port *port; | |
705 | u32 data[NVM_DATA_DWORDS]; | |
706 | u32 metadata = 0; | |
707 | u8 status = 0; | |
708 | ||
709 | memset(data, 0, sizeof(data)); | |
710 | ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_BUFFER_ALLOC, &metadata, | |
711 | &status, NULL, 0, data, ARRAY_SIZE(data)); | |
712 | if (ret) | |
713 | return ret; | |
714 | if (status) | |
715 | return -EIO; | |
716 | ||
717 | length = metadata & USB4_BA_LENGTH_MASK; | |
718 | if (WARN_ON(length > ARRAY_SIZE(data))) | |
719 | return -EMSGSIZE; | |
720 | ||
721 | max_usb3 = -1; | |
722 | min_dp_aux = -1; | |
723 | min_dp_main = -1; | |
724 | max_pcie = -1; | |
725 | max_dma = -1; | |
726 | ||
727 | tb_sw_dbg(sw, "credit allocation parameters:\n"); | |
728 | ||
729 | for (i = 0; i < length; i++) { | |
730 | u16 index, value; | |
731 | ||
732 | index = data[i] & USB4_BA_INDEX_MASK; | |
733 | value = (data[i] & USB4_BA_VALUE_MASK) >> USB4_BA_VALUE_SHIFT; | |
734 | ||
735 | switch (index) { | |
736 | case USB4_BA_MAX_USB3: | |
737 | tb_sw_dbg(sw, " USB3: %u\n", value); | |
738 | max_usb3 = value; | |
739 | break; | |
740 | case USB4_BA_MIN_DP_AUX: | |
741 | tb_sw_dbg(sw, " DP AUX: %u\n", value); | |
742 | min_dp_aux = value; | |
743 | break; | |
744 | case USB4_BA_MIN_DP_MAIN: | |
745 | tb_sw_dbg(sw, " DP main: %u\n", value); | |
746 | min_dp_main = value; | |
747 | break; | |
748 | case USB4_BA_MAX_PCIE: | |
749 | tb_sw_dbg(sw, " PCIe: %u\n", value); | |
750 | max_pcie = value; | |
751 | break; | |
752 | case USB4_BA_MAX_HI: | |
753 | tb_sw_dbg(sw, " DMA: %u\n", value); | |
754 | max_dma = value; | |
755 | break; | |
756 | default: | |
757 | tb_sw_dbg(sw, " unknown credit allocation index %#x, skipping\n", | |
758 | index); | |
759 | break; | |
760 | } | |
761 | } | |
762 | ||
763 | /* | |
764 | * Validate the buffer allocation preferences. If we find | |
765 | * issues, log a warning and fall back using the hard-coded | |
766 | * values. | |
767 | */ | |
768 | ||
769 | /* Host router must report baMaxHI */ | |
770 | if (!tb_route(sw) && max_dma < 0) { | |
771 | tb_sw_warn(sw, "host router is missing baMaxHI\n"); | |
772 | goto err_invalid; | |
773 | } | |
774 | ||
775 | nports = 0; | |
776 | tb_switch_for_each_port(sw, port) { | |
777 | if (tb_port_is_null(port)) | |
778 | nports++; | |
779 | } | |
780 | ||
781 | /* Must have DP buffer allocation (multiple USB4 ports) */ | |
782 | if (nports > 2 && (min_dp_aux < 0 || min_dp_main < 0)) { | |
783 | tb_sw_warn(sw, "multiple USB4 ports require baMinDPaux/baMinDPmain\n"); | |
784 | goto err_invalid; | |
785 | } | |
786 | ||
787 | tb_switch_for_each_port(sw, port) { | |
788 | if (tb_port_is_dpout(port) && min_dp_main < 0) { | |
789 | tb_sw_warn(sw, "missing baMinDPmain"); | |
790 | goto err_invalid; | |
791 | } | |
792 | if ((tb_port_is_dpin(port) || tb_port_is_dpout(port)) && | |
793 | min_dp_aux < 0) { | |
794 | tb_sw_warn(sw, "missing baMinDPaux"); | |
795 | goto err_invalid; | |
796 | } | |
797 | if ((tb_port_is_usb3_down(port) || tb_port_is_usb3_up(port)) && | |
798 | max_usb3 < 0) { | |
799 | tb_sw_warn(sw, "missing baMaxUSB3"); | |
800 | goto err_invalid; | |
801 | } | |
802 | if ((tb_port_is_pcie_down(port) || tb_port_is_pcie_up(port)) && | |
803 | max_pcie < 0) { | |
804 | tb_sw_warn(sw, "missing baMaxPCIe"); | |
805 | goto err_invalid; | |
806 | } | |
807 | } | |
808 | ||
809 | /* | |
810 | * Buffer allocation passed the validation so we can use it in | |
811 | * path creation. | |
812 | */ | |
813 | sw->credit_allocation = true; | |
814 | if (max_usb3 > 0) | |
815 | sw->max_usb3_credits = max_usb3; | |
816 | if (min_dp_aux > 0) | |
817 | sw->min_dp_aux_credits = min_dp_aux; | |
818 | if (min_dp_main > 0) | |
819 | sw->min_dp_main_credits = min_dp_main; | |
820 | if (max_pcie > 0) | |
821 | sw->max_pcie_credits = max_pcie; | |
822 | if (max_dma > 0) | |
823 | sw->max_dma_credits = max_dma; | |
824 | ||
825 | return 0; | |
826 | ||
827 | err_invalid: | |
828 | return -EINVAL; | |
829 | } | |
830 | ||
b0407983 MW |
831 | /** |
832 | * usb4_switch_query_dp_resource() - Query availability of DP IN resource | |
833 | * @sw: USB4 router | |
834 | * @in: DP IN adapter | |
835 | * | |
836 | * For DP tunneling this function can be used to query availability of | |
837 | * DP IN resource. Returns true if the resource is available for DP | |
838 | * tunneling, false otherwise. | |
839 | */ | |
840 | bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in) | |
841 | { | |
fe265a06 | 842 | u32 metadata = in->port; |
b0407983 MW |
843 | u8 status; |
844 | int ret; | |
845 | ||
fe265a06 MW |
846 | ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &metadata, |
847 | &status); | |
b0407983 MW |
848 | /* |
849 | * If DP resource allocation is not supported assume it is | |
850 | * always available. | |
851 | */ | |
852 | if (ret == -EOPNOTSUPP) | |
853 | return true; | |
854 | else if (ret) | |
855 | return false; | |
856 | ||
857 | return !status; | |
858 | } | |
859 | ||
860 | /** | |
861 | * usb4_switch_alloc_dp_resource() - Allocate DP IN resource | |
862 | * @sw: USB4 router | |
863 | * @in: DP IN adapter | |
864 | * | |
865 | * Allocates DP IN resource for DP tunneling using USB4 router | |
866 | * operations. If the resource was allocated returns %0. Otherwise | |
867 | * returns negative errno, in particular %-EBUSY if the resource is | |
868 | * already allocated. | |
869 | */ | |
870 | int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in) | |
871 | { | |
fe265a06 | 872 | u32 metadata = in->port; |
b0407983 MW |
873 | u8 status; |
874 | int ret; | |
875 | ||
fe265a06 MW |
876 | ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &metadata, |
877 | &status); | |
b0407983 MW |
878 | if (ret == -EOPNOTSUPP) |
879 | return 0; | |
880 | else if (ret) | |
881 | return ret; | |
882 | ||
883 | return status ? -EBUSY : 0; | |
884 | } | |
885 | ||
886 | /** | |
887 | * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource | |
888 | * @sw: USB4 router | |
889 | * @in: DP IN adapter | |
890 | * | |
891 | * Releases the previously allocated DP IN resource. | |
892 | */ | |
893 | int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in) | |
894 | { | |
fe265a06 | 895 | u32 metadata = in->port; |
b0407983 MW |
896 | u8 status; |
897 | int ret; | |
898 | ||
fe265a06 MW |
899 | ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &metadata, |
900 | &status); | |
b0407983 MW |
901 | if (ret == -EOPNOTSUPP) |
902 | return 0; | |
903 | else if (ret) | |
904 | return ret; | |
905 | ||
906 | return status ? -EIO : 0; | |
907 | } | |
908 | ||
909 | static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port) | |
910 | { | |
911 | struct tb_port *p; | |
912 | int usb4_idx = 0; | |
913 | ||
914 | /* Assume port is primary */ | |
915 | tb_switch_for_each_port(sw, p) { | |
916 | if (!tb_port_is_null(p)) | |
917 | continue; | |
918 | if (tb_is_upstream_port(p)) | |
919 | continue; | |
920 | if (!p->link_nr) { | |
921 | if (p == port) | |
922 | break; | |
923 | usb4_idx++; | |
924 | } | |
925 | } | |
926 | ||
927 | return usb4_idx; | |
928 | } | |
929 | ||
930 | /** | |
931 | * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter | |
932 | * @sw: USB4 router | |
933 | * @port: USB4 port | |
934 | * | |
935 | * USB4 routers have direct mapping between USB4 ports and PCIe | |
936 | * downstream adapters where the PCIe topology is extended. This | |
937 | * function returns the corresponding downstream PCIe adapter or %NULL | |
938 | * if no such mapping was possible. | |
939 | */ | |
940 | struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw, | |
941 | const struct tb_port *port) | |
942 | { | |
943 | int usb4_idx = usb4_port_idx(sw, port); | |
944 | struct tb_port *p; | |
945 | int pcie_idx = 0; | |
946 | ||
947 | /* Find PCIe down port matching usb4_port */ | |
948 | tb_switch_for_each_port(sw, p) { | |
949 | if (!tb_port_is_pcie_down(p)) | |
950 | continue; | |
951 | ||
9cac51a0 | 952 | if (pcie_idx == usb4_idx) |
b0407983 MW |
953 | return p; |
954 | ||
955 | pcie_idx++; | |
956 | } | |
957 | ||
958 | return NULL; | |
959 | } | |
960 | ||
e6f81858 RM |
961 | /** |
962 | * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter | |
963 | * @sw: USB4 router | |
964 | * @port: USB4 port | |
965 | * | |
966 | * USB4 routers have direct mapping between USB4 ports and USB 3.x | |
967 | * downstream adapters where the USB 3.x topology is extended. This | |
968 | * function returns the corresponding downstream USB 3.x adapter or | |
969 | * %NULL if no such mapping was possible. | |
970 | */ | |
971 | struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw, | |
972 | const struct tb_port *port) | |
973 | { | |
974 | int usb4_idx = usb4_port_idx(sw, port); | |
975 | struct tb_port *p; | |
976 | int usb_idx = 0; | |
977 | ||
978 | /* Find USB3 down port matching usb4_port */ | |
979 | tb_switch_for_each_port(sw, p) { | |
980 | if (!tb_port_is_usb3_down(p)) | |
981 | continue; | |
982 | ||
77cfa40f | 983 | if (usb_idx == usb4_idx) |
e6f81858 RM |
984 | return p; |
985 | ||
986 | usb_idx++; | |
987 | } | |
988 | ||
989 | return NULL; | |
990 | } | |
991 | ||
cae5f515 MW |
992 | /** |
993 | * usb4_switch_add_ports() - Add USB4 ports for this router | |
994 | * @sw: USB4 router | |
995 | * | |
996 | * For USB4 router finds all USB4 ports and registers devices for each. | |
997 | * Can be called to any router. | |
998 | * | |
999 | * Return %0 in case of success and negative errno in case of failure. | |
1000 | */ | |
1001 | int usb4_switch_add_ports(struct tb_switch *sw) | |
1002 | { | |
1003 | struct tb_port *port; | |
1004 | ||
1005 | if (tb_switch_is_icm(sw) || !tb_switch_is_usb4(sw)) | |
1006 | return 0; | |
1007 | ||
1008 | tb_switch_for_each_port(sw, port) { | |
1009 | struct usb4_port *usb4; | |
1010 | ||
1011 | if (!tb_port_is_null(port)) | |
1012 | continue; | |
1013 | if (!port->cap_usb4) | |
1014 | continue; | |
1015 | ||
1016 | usb4 = usb4_port_device_add(port); | |
1017 | if (IS_ERR(usb4)) { | |
1018 | usb4_switch_remove_ports(sw); | |
1019 | return PTR_ERR(usb4); | |
1020 | } | |
1021 | ||
1022 | port->usb4 = usb4; | |
1023 | } | |
1024 | ||
1025 | return 0; | |
1026 | } | |
1027 | ||
1028 | /** | |
1029 | * usb4_switch_remove_ports() - Removes USB4 ports from this router | |
1030 | * @sw: USB4 router | |
1031 | * | |
1032 | * Unregisters previously registered USB4 ports. | |
1033 | */ | |
1034 | void usb4_switch_remove_ports(struct tb_switch *sw) | |
1035 | { | |
1036 | struct tb_port *port; | |
1037 | ||
1038 | tb_switch_for_each_port(sw, port) { | |
1039 | if (port->usb4) { | |
1040 | usb4_port_device_remove(port->usb4); | |
1041 | port->usb4 = NULL; | |
1042 | } | |
1043 | } | |
1044 | } | |
1045 | ||
b0407983 MW |
1046 | /** |
1047 | * usb4_port_unlock() - Unlock USB4 downstream port | |
1048 | * @port: USB4 port to unlock | |
1049 | * | |
1050 | * Unlocks USB4 downstream port so that the connection manager can | |
1051 | * access the router below this port. | |
1052 | */ | |
1053 | int usb4_port_unlock(struct tb_port *port) | |
1054 | { | |
1055 | int ret; | |
1056 | u32 val; | |
1057 | ||
1058 | ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1); | |
1059 | if (ret) | |
1060 | return ret; | |
1061 | ||
1062 | val &= ~ADP_CS_4_LCK; | |
1063 | return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1); | |
1064 | } | |
3b1d8d57 | 1065 | |
5d2569cb ML |
1066 | /** |
1067 | * usb4_port_hotplug_enable() - Enables hotplug for a port | |
1068 | * @port: USB4 port to operate on | |
1069 | * | |
1070 | * Enables hot plug events on a given port. This is only intended | |
1071 | * to be used on lane, DP-IN, and DP-OUT adapters. | |
1072 | */ | |
1073 | int usb4_port_hotplug_enable(struct tb_port *port) | |
1074 | { | |
1075 | int ret; | |
1076 | u32 val; | |
1077 | ||
1078 | ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_5, 1); | |
1079 | if (ret) | |
1080 | return ret; | |
1081 | ||
1082 | val &= ~ADP_CS_5_DHP; | |
1083 | return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_5, 1); | |
1084 | } | |
1085 | ||
e28178bf MW |
1086 | static int usb4_port_set_configured(struct tb_port *port, bool configured) |
1087 | { | |
1088 | int ret; | |
1089 | u32 val; | |
1090 | ||
1091 | if (!port->cap_usb4) | |
1092 | return -EINVAL; | |
1093 | ||
1094 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1095 | port->cap_usb4 + PORT_CS_19, 1); | |
1096 | if (ret) | |
1097 | return ret; | |
1098 | ||
1099 | if (configured) | |
1100 | val |= PORT_CS_19_PC; | |
1101 | else | |
1102 | val &= ~PORT_CS_19_PC; | |
1103 | ||
1104 | return tb_port_write(port, &val, TB_CFG_PORT, | |
1105 | port->cap_usb4 + PORT_CS_19, 1); | |
1106 | } | |
1107 | ||
1108 | /** | |
1109 | * usb4_port_configure() - Set USB4 port configured | |
1110 | * @port: USB4 router | |
1111 | * | |
1112 | * Sets the USB4 link to be configured for power management purposes. | |
1113 | */ | |
1114 | int usb4_port_configure(struct tb_port *port) | |
1115 | { | |
1116 | return usb4_port_set_configured(port, true); | |
1117 | } | |
1118 | ||
1119 | /** | |
1120 | * usb4_port_unconfigure() - Set USB4 port unconfigured | |
1121 | * @port: USB4 router | |
1122 | * | |
1123 | * Sets the USB4 link to be unconfigured for power management purposes. | |
1124 | */ | |
1125 | void usb4_port_unconfigure(struct tb_port *port) | |
1126 | { | |
1127 | usb4_port_set_configured(port, false); | |
1128 | } | |
1129 | ||
284652a4 MW |
1130 | static int usb4_set_xdomain_configured(struct tb_port *port, bool configured) |
1131 | { | |
1132 | int ret; | |
1133 | u32 val; | |
1134 | ||
1135 | if (!port->cap_usb4) | |
1136 | return -EINVAL; | |
1137 | ||
1138 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1139 | port->cap_usb4 + PORT_CS_19, 1); | |
1140 | if (ret) | |
1141 | return ret; | |
1142 | ||
1143 | if (configured) | |
1144 | val |= PORT_CS_19_PID; | |
1145 | else | |
1146 | val &= ~PORT_CS_19_PID; | |
1147 | ||
1148 | return tb_port_write(port, &val, TB_CFG_PORT, | |
1149 | port->cap_usb4 + PORT_CS_19, 1); | |
1150 | } | |
1151 | ||
1152 | /** | |
1153 | * usb4_port_configure_xdomain() - Configure port for XDomain | |
1154 | * @port: USB4 port connected to another host | |
f9cad07b | 1155 | * @xd: XDomain that is connected to the port |
284652a4 | 1156 | * |
f9cad07b MW |
1157 | * Marks the USB4 port as being connected to another host and updates |
1158 | * the link type. Returns %0 in success and negative errno in failure. | |
284652a4 | 1159 | */ |
f9cad07b | 1160 | int usb4_port_configure_xdomain(struct tb_port *port, struct tb_xdomain *xd) |
284652a4 | 1161 | { |
f9cad07b | 1162 | xd->link_usb4 = link_is_usb4(port); |
284652a4 MW |
1163 | return usb4_set_xdomain_configured(port, true); |
1164 | } | |
1165 | ||
1166 | /** | |
1167 | * usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain | |
1168 | * @port: USB4 port that was connected to another host | |
1169 | * | |
1170 | * Clears USB4 port from being marked as XDomain. | |
1171 | */ | |
1172 | void usb4_port_unconfigure_xdomain(struct tb_port *port) | |
1173 | { | |
1174 | usb4_set_xdomain_configured(port, false); | |
1175 | } | |
1176 | ||
3b1d8d57 MW |
1177 | static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit, |
1178 | u32 value, int timeout_msec) | |
1179 | { | |
1180 | ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec); | |
1181 | ||
1182 | do { | |
1183 | u32 val; | |
1184 | int ret; | |
1185 | ||
1186 | ret = tb_port_read(port, &val, TB_CFG_PORT, offset, 1); | |
1187 | if (ret) | |
1188 | return ret; | |
1189 | ||
1190 | if ((val & bit) == value) | |
1191 | return 0; | |
1192 | ||
1193 | usleep_range(50, 100); | |
1194 | } while (ktime_before(ktime_get(), timeout)); | |
1195 | ||
1196 | return -ETIMEDOUT; | |
1197 | } | |
1198 | ||
02d12855 RM |
1199 | static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords) |
1200 | { | |
9b383037 | 1201 | if (dwords > NVM_DATA_DWORDS) |
02d12855 RM |
1202 | return -EINVAL; |
1203 | ||
1204 | return tb_port_read(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2, | |
1205 | dwords); | |
1206 | } | |
1207 | ||
1208 | static int usb4_port_write_data(struct tb_port *port, const void *data, | |
1209 | size_t dwords) | |
1210 | { | |
9b383037 | 1211 | if (dwords > NVM_DATA_DWORDS) |
02d12855 RM |
1212 | return -EINVAL; |
1213 | ||
1214 | return tb_port_write(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2, | |
1215 | dwords); | |
1216 | } | |
1217 | ||
1218 | static int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target, | |
1219 | u8 index, u8 reg, void *buf, u8 size) | |
1220 | { | |
1221 | size_t dwords = DIV_ROUND_UP(size, 4); | |
1222 | int ret; | |
1223 | u32 val; | |
1224 | ||
1225 | if (!port->cap_usb4) | |
1226 | return -EINVAL; | |
1227 | ||
1228 | val = reg; | |
1229 | val |= size << PORT_CS_1_LENGTH_SHIFT; | |
1230 | val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK; | |
1231 | if (target == USB4_SB_TARGET_RETIMER) | |
1232 | val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT); | |
1233 | val |= PORT_CS_1_PND; | |
1234 | ||
1235 | ret = tb_port_write(port, &val, TB_CFG_PORT, | |
1236 | port->cap_usb4 + PORT_CS_1, 1); | |
1237 | if (ret) | |
1238 | return ret; | |
1239 | ||
1240 | ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1, | |
1241 | PORT_CS_1_PND, 0, 500); | |
1242 | if (ret) | |
1243 | return ret; | |
1244 | ||
1245 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1246 | port->cap_usb4 + PORT_CS_1, 1); | |
1247 | if (ret) | |
1248 | return ret; | |
1249 | ||
1250 | if (val & PORT_CS_1_NR) | |
1251 | return -ENODEV; | |
1252 | if (val & PORT_CS_1_RC) | |
1253 | return -EIO; | |
1254 | ||
1255 | return buf ? usb4_port_read_data(port, buf, dwords) : 0; | |
1256 | } | |
1257 | ||
1258 | static int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target, | |
1259 | u8 index, u8 reg, const void *buf, u8 size) | |
1260 | { | |
1261 | size_t dwords = DIV_ROUND_UP(size, 4); | |
1262 | int ret; | |
1263 | u32 val; | |
1264 | ||
1265 | if (!port->cap_usb4) | |
1266 | return -EINVAL; | |
1267 | ||
1268 | if (buf) { | |
1269 | ret = usb4_port_write_data(port, buf, dwords); | |
1270 | if (ret) | |
1271 | return ret; | |
1272 | } | |
1273 | ||
1274 | val = reg; | |
1275 | val |= size << PORT_CS_1_LENGTH_SHIFT; | |
1276 | val |= PORT_CS_1_WNR_WRITE; | |
1277 | val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK; | |
1278 | if (target == USB4_SB_TARGET_RETIMER) | |
1279 | val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT); | |
1280 | val |= PORT_CS_1_PND; | |
1281 | ||
1282 | ret = tb_port_write(port, &val, TB_CFG_PORT, | |
1283 | port->cap_usb4 + PORT_CS_1, 1); | |
1284 | if (ret) | |
1285 | return ret; | |
1286 | ||
1287 | ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1, | |
1288 | PORT_CS_1_PND, 0, 500); | |
1289 | if (ret) | |
1290 | return ret; | |
1291 | ||
1292 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1293 | port->cap_usb4 + PORT_CS_1, 1); | |
1294 | if (ret) | |
1295 | return ret; | |
1296 | ||
1297 | if (val & PORT_CS_1_NR) | |
1298 | return -ENODEV; | |
1299 | if (val & PORT_CS_1_RC) | |
1300 | return -EIO; | |
1301 | ||
1302 | return 0; | |
1303 | } | |
1304 | ||
1305 | static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target, | |
1306 | u8 index, enum usb4_sb_opcode opcode, int timeout_msec) | |
1307 | { | |
1308 | ktime_t timeout; | |
1309 | u32 val; | |
1310 | int ret; | |
1311 | ||
1312 | val = opcode; | |
1313 | ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, &val, | |
1314 | sizeof(val)); | |
1315 | if (ret) | |
1316 | return ret; | |
1317 | ||
1318 | timeout = ktime_add_ms(ktime_get(), timeout_msec); | |
1319 | ||
1320 | do { | |
1321 | /* Check results */ | |
1322 | ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE, | |
1323 | &val, sizeof(val)); | |
1324 | if (ret) | |
1325 | return ret; | |
1326 | ||
1327 | switch (val) { | |
1328 | case 0: | |
1329 | return 0; | |
1330 | ||
1331 | case USB4_SB_OPCODE_ERR: | |
1332 | return -EAGAIN; | |
1333 | ||
1334 | case USB4_SB_OPCODE_ONS: | |
1335 | return -EOPNOTSUPP; | |
1336 | ||
1337 | default: | |
1338 | if (val != opcode) | |
1339 | return -EIO; | |
1340 | break; | |
1341 | } | |
1342 | } while (ktime_before(ktime_get(), timeout)); | |
1343 | ||
1344 | return -ETIMEDOUT; | |
1345 | } | |
1346 | ||
3406de7c RM |
1347 | static int usb4_port_set_router_offline(struct tb_port *port, bool offline) |
1348 | { | |
1349 | u32 val = !offline; | |
1350 | int ret; | |
1351 | ||
1352 | ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0, | |
1353 | USB4_SB_METADATA, &val, sizeof(val)); | |
1354 | if (ret) | |
1355 | return ret; | |
1356 | ||
1357 | val = USB4_SB_OPCODE_ROUTER_OFFLINE; | |
1358 | return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0, | |
1359 | USB4_SB_OPCODE, &val, sizeof(val)); | |
1360 | } | |
1361 | ||
1362 | /** | |
1363 | * usb4_port_router_offline() - Put the USB4 port to offline mode | |
1364 | * @port: USB4 port | |
1365 | * | |
1366 | * This function puts the USB4 port into offline mode. In this mode the | |
1367 | * port does not react on hotplug events anymore. This needs to be | |
1368 | * called before retimer access is done when the USB4 links is not up. | |
1369 | * | |
1370 | * Returns %0 in case of success and negative errno if there was an | |
1371 | * error. | |
1372 | */ | |
1373 | int usb4_port_router_offline(struct tb_port *port) | |
1374 | { | |
1375 | return usb4_port_set_router_offline(port, true); | |
1376 | } | |
1377 | ||
1378 | /** | |
1379 | * usb4_port_router_online() - Put the USB4 port back to online | |
1380 | * @port: USB4 port | |
1381 | * | |
1382 | * Makes the USB4 port functional again. | |
1383 | */ | |
1384 | int usb4_port_router_online(struct tb_port *port) | |
1385 | { | |
1386 | return usb4_port_set_router_offline(port, false); | |
1387 | } | |
1388 | ||
02d12855 RM |
1389 | /** |
1390 | * usb4_port_enumerate_retimers() - Send RT broadcast transaction | |
1391 | * @port: USB4 port | |
1392 | * | |
1393 | * This forces the USB4 port to send broadcast RT transaction which | |
1394 | * makes the retimers on the link to assign index to themselves. Returns | |
1395 | * %0 in case of success and negative errno if there was an error. | |
1396 | */ | |
1397 | int usb4_port_enumerate_retimers(struct tb_port *port) | |
1398 | { | |
1399 | u32 val; | |
1400 | ||
1401 | val = USB4_SB_OPCODE_ENUMERATE_RETIMERS; | |
1402 | return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0, | |
1403 | USB4_SB_OPCODE, &val, sizeof(val)); | |
1404 | } | |
1405 | ||
8a90e4fa GF |
1406 | /** |
1407 | * usb4_port_clx_supported() - Check if CLx is supported by the link | |
1408 | * @port: Port to check for CLx support for | |
1409 | * | |
1410 | * PORT_CS_18_CPS bit reflects if the link supports CLx including | |
1411 | * active cables (if connected on the link). | |
1412 | */ | |
1413 | bool usb4_port_clx_supported(struct tb_port *port) | |
1414 | { | |
1415 | int ret; | |
1416 | u32 val; | |
1417 | ||
1418 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1419 | port->cap_usb4 + PORT_CS_18, 1); | |
1420 | if (ret) | |
1421 | return false; | |
1422 | ||
1423 | return !!(val & PORT_CS_18_CPS); | |
1424 | } | |
1425 | ||
d0f1e0c2 MW |
1426 | /** |
1427 | * usb4_port_margining_caps() - Read USB4 port marginig capabilities | |
1428 | * @port: USB4 port | |
1429 | * @caps: Array with at least two elements to hold the results | |
1430 | * | |
1431 | * Reads the USB4 port lane margining capabilities into @caps. | |
1432 | */ | |
1433 | int usb4_port_margining_caps(struct tb_port *port, u32 *caps) | |
1434 | { | |
1435 | int ret; | |
1436 | ||
1437 | ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0, | |
1438 | USB4_SB_OPCODE_READ_LANE_MARGINING_CAP, 500); | |
1439 | if (ret) | |
1440 | return ret; | |
1441 | ||
1442 | return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0, | |
1443 | USB4_SB_DATA, caps, sizeof(*caps) * 2); | |
1444 | } | |
1445 | ||
1446 | /** | |
1447 | * usb4_port_hw_margin() - Run hardware lane margining on port | |
1448 | * @port: USB4 port | |
1449 | * @lanes: Which lanes to run (must match the port capabilities). Can be | |
1450 | * %0, %1 or %7. | |
1451 | * @ber_level: BER level contour value | |
1452 | * @timing: Perform timing margining instead of voltage | |
1453 | * @right_high: Use Right/high margin instead of left/low | |
1454 | * @results: Array with at least two elements to hold the results | |
1455 | * | |
1456 | * Runs hardware lane margining on USB4 port and returns the result in | |
1457 | * @results. | |
1458 | */ | |
1459 | int usb4_port_hw_margin(struct tb_port *port, unsigned int lanes, | |
1460 | unsigned int ber_level, bool timing, bool right_high, | |
1461 | u32 *results) | |
1462 | { | |
1463 | u32 val; | |
1464 | int ret; | |
1465 | ||
1466 | val = lanes; | |
1467 | if (timing) | |
1468 | val |= USB4_MARGIN_HW_TIME; | |
1469 | if (right_high) | |
1470 | val |= USB4_MARGIN_HW_RH; | |
1471 | if (ber_level) | |
1472 | val |= (ber_level << USB4_MARGIN_HW_BER_SHIFT) & | |
1473 | USB4_MARGIN_HW_BER_MASK; | |
1474 | ||
1475 | ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0, | |
1476 | USB4_SB_METADATA, &val, sizeof(val)); | |
1477 | if (ret) | |
1478 | return ret; | |
1479 | ||
1480 | ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0, | |
1481 | USB4_SB_OPCODE_RUN_HW_LANE_MARGINING, 2500); | |
1482 | if (ret) | |
1483 | return ret; | |
1484 | ||
1485 | return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0, | |
1486 | USB4_SB_DATA, results, sizeof(*results) * 2); | |
1487 | } | |
1488 | ||
1489 | /** | |
1490 | * usb4_port_sw_margin() - Run software lane margining on port | |
1491 | * @port: USB4 port | |
1492 | * @lanes: Which lanes to run (must match the port capabilities). Can be | |
1493 | * %0, %1 or %7. | |
1494 | * @timing: Perform timing margining instead of voltage | |
1495 | * @right_high: Use Right/high margin instead of left/low | |
1496 | * @counter: What to do with the error counter | |
1497 | * | |
1498 | * Runs software lane margining on USB4 port. Read back the error | |
1499 | * counters by calling usb4_port_sw_margin_errors(). Returns %0 in | |
1500 | * success and negative errno otherwise. | |
1501 | */ | |
1502 | int usb4_port_sw_margin(struct tb_port *port, unsigned int lanes, bool timing, | |
1503 | bool right_high, u32 counter) | |
1504 | { | |
1505 | u32 val; | |
1506 | int ret; | |
1507 | ||
1508 | val = lanes; | |
1509 | if (timing) | |
1510 | val |= USB4_MARGIN_SW_TIME; | |
1511 | if (right_high) | |
1512 | val |= USB4_MARGIN_SW_RH; | |
1513 | val |= (counter << USB4_MARGIN_SW_COUNTER_SHIFT) & | |
1514 | USB4_MARGIN_SW_COUNTER_MASK; | |
1515 | ||
1516 | ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0, | |
1517 | USB4_SB_METADATA, &val, sizeof(val)); | |
1518 | if (ret) | |
1519 | return ret; | |
1520 | ||
1521 | return usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0, | |
1522 | USB4_SB_OPCODE_RUN_SW_LANE_MARGINING, 2500); | |
1523 | } | |
1524 | ||
1525 | /** | |
1526 | * usb4_port_sw_margin_errors() - Read the software margining error counters | |
1527 | * @port: USB4 port | |
1528 | * @errors: Error metadata is copied here. | |
1529 | * | |
1530 | * This reads back the software margining error counters from the port. | |
1531 | * Returns %0 in success and negative errno otherwise. | |
1532 | */ | |
1533 | int usb4_port_sw_margin_errors(struct tb_port *port, u32 *errors) | |
1534 | { | |
1535 | int ret; | |
1536 | ||
1537 | ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0, | |
1538 | USB4_SB_OPCODE_READ_SW_MARGIN_ERR, 150); | |
1539 | if (ret) | |
1540 | return ret; | |
1541 | ||
1542 | return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0, | |
1543 | USB4_SB_METADATA, errors, sizeof(*errors)); | |
1544 | } | |
1545 | ||
02d12855 RM |
1546 | static inline int usb4_port_retimer_op(struct tb_port *port, u8 index, |
1547 | enum usb4_sb_opcode opcode, | |
1548 | int timeout_msec) | |
1549 | { | |
1550 | return usb4_port_sb_op(port, USB4_SB_TARGET_RETIMER, index, opcode, | |
1551 | timeout_msec); | |
1552 | } | |
1553 | ||
3406de7c RM |
1554 | /** |
1555 | * usb4_port_retimer_set_inbound_sbtx() - Enable sideband channel transactions | |
1556 | * @port: USB4 port | |
1557 | * @index: Retimer index | |
1558 | * | |
1559 | * Enables sideband channel transations on SBTX. Can be used when USB4 | |
1560 | * link does not go up, for example if there is no device connected. | |
1561 | */ | |
1562 | int usb4_port_retimer_set_inbound_sbtx(struct tb_port *port, u8 index) | |
1563 | { | |
1564 | int ret; | |
1565 | ||
1566 | ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX, | |
1567 | 500); | |
1568 | ||
1569 | if (ret != -ENODEV) | |
1570 | return ret; | |
1571 | ||
1572 | /* | |
1573 | * Per the USB4 retimer spec, the retimer is not required to | |
1574 | * send an RT (Retimer Transaction) response for the first | |
1575 | * SET_INBOUND_SBTX command | |
1576 | */ | |
1577 | return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX, | |
1578 | 500); | |
1579 | } | |
1580 | ||
cd0c1e58 GF |
1581 | /** |
1582 | * usb4_port_retimer_unset_inbound_sbtx() - Disable sideband channel transactions | |
1583 | * @port: USB4 port | |
1584 | * @index: Retimer index | |
1585 | * | |
1586 | * Disables sideband channel transations on SBTX. The reverse of | |
1587 | * usb4_port_retimer_set_inbound_sbtx(). | |
1588 | */ | |
1589 | int usb4_port_retimer_unset_inbound_sbtx(struct tb_port *port, u8 index) | |
1590 | { | |
1591 | return usb4_port_retimer_op(port, index, | |
1592 | USB4_SB_OPCODE_UNSET_INBOUND_SBTX, 500); | |
1593 | } | |
1594 | ||
02d12855 RM |
1595 | /** |
1596 | * usb4_port_retimer_read() - Read from retimer sideband registers | |
1597 | * @port: USB4 port | |
1598 | * @index: Retimer index | |
1599 | * @reg: Sideband register to read | |
1600 | * @buf: Data from @reg is stored here | |
1601 | * @size: Number of bytes to read | |
1602 | * | |
1603 | * Function reads retimer sideband registers starting from @reg. The | |
1604 | * retimer is connected to @port at @index. Returns %0 in case of | |
1605 | * success, and read data is copied to @buf. If there is no retimer | |
1606 | * present at given @index returns %-ENODEV. In any other failure | |
1607 | * returns negative errno. | |
1608 | */ | |
1609 | int usb4_port_retimer_read(struct tb_port *port, u8 index, u8 reg, void *buf, | |
1610 | u8 size) | |
1611 | { | |
1612 | return usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index, reg, buf, | |
1613 | size); | |
1614 | } | |
1615 | ||
1616 | /** | |
1617 | * usb4_port_retimer_write() - Write to retimer sideband registers | |
1618 | * @port: USB4 port | |
1619 | * @index: Retimer index | |
1620 | * @reg: Sideband register to write | |
1621 | * @buf: Data that is written starting from @reg | |
1622 | * @size: Number of bytes to write | |
1623 | * | |
1624 | * Writes retimer sideband registers starting from @reg. The retimer is | |
1625 | * connected to @port at @index. Returns %0 in case of success. If there | |
1626 | * is no retimer present at given @index returns %-ENODEV. In any other | |
1627 | * failure returns negative errno. | |
1628 | */ | |
1629 | int usb4_port_retimer_write(struct tb_port *port, u8 index, u8 reg, | |
1630 | const void *buf, u8 size) | |
1631 | { | |
1632 | return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, reg, buf, | |
1633 | size); | |
1634 | } | |
1635 | ||
1636 | /** | |
1637 | * usb4_port_retimer_is_last() - Is the retimer last on-board retimer | |
1638 | * @port: USB4 port | |
1639 | * @index: Retimer index | |
1640 | * | |
1641 | * If the retimer at @index is last one (connected directly to the | |
1642 | * Type-C port) this function returns %1. If it is not returns %0. If | |
1643 | * the retimer is not present returns %-ENODEV. Otherwise returns | |
1644 | * negative errno. | |
1645 | */ | |
1646 | int usb4_port_retimer_is_last(struct tb_port *port, u8 index) | |
1647 | { | |
1648 | u32 metadata; | |
1649 | int ret; | |
1650 | ||
1651 | ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_LAST_RETIMER, | |
1652 | 500); | |
1653 | if (ret) | |
1654 | return ret; | |
1655 | ||
1656 | ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata, | |
1657 | sizeof(metadata)); | |
1658 | return ret ? ret : metadata & 1; | |
1659 | } | |
1660 | ||
1661 | /** | |
1662 | * usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size | |
1663 | * @port: USB4 port | |
1664 | * @index: Retimer index | |
1665 | * | |
1666 | * Reads NVM sector size (in bytes) of a retimer at @index. This | |
1667 | * operation can be used to determine whether the retimer supports NVM | |
1668 | * upgrade for example. Returns sector size in bytes or negative errno | |
1669 | * in case of error. Specifically returns %-ENODEV if there is no | |
1670 | * retimer at @index. | |
1671 | */ | |
1672 | int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index) | |
1673 | { | |
1674 | u32 metadata; | |
1675 | int ret; | |
1676 | ||
1677 | ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE, | |
1678 | 500); | |
1679 | if (ret) | |
1680 | return ret; | |
1681 | ||
1682 | ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata, | |
1683 | sizeof(metadata)); | |
1684 | return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK; | |
1685 | } | |
1686 | ||
faa1c615 RM |
1687 | /** |
1688 | * usb4_port_retimer_nvm_set_offset() - Set NVM write offset | |
1689 | * @port: USB4 port | |
1690 | * @index: Retimer index | |
1691 | * @address: Start offset | |
1692 | * | |
1693 | * Exlicitly sets NVM write offset. Normally when writing to NVM this is | |
1694 | * done automatically by usb4_port_retimer_nvm_write(). | |
1695 | * | |
1696 | * Returns %0 in success and negative errno if there was a failure. | |
1697 | */ | |
1698 | int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index, | |
1699 | unsigned int address) | |
02d12855 RM |
1700 | { |
1701 | u32 metadata, dwaddress; | |
1702 | int ret; | |
1703 | ||
1704 | dwaddress = address / 4; | |
1705 | metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) & | |
1706 | USB4_NVM_SET_OFFSET_MASK; | |
1707 | ||
1708 | ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata, | |
1709 | sizeof(metadata)); | |
1710 | if (ret) | |
1711 | return ret; | |
1712 | ||
1713 | return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_SET_OFFSET, | |
1714 | 500); | |
1715 | } | |
1716 | ||
1717 | struct retimer_info { | |
1718 | struct tb_port *port; | |
1719 | u8 index; | |
1720 | }; | |
1721 | ||
9b383037 MW |
1722 | static int usb4_port_retimer_nvm_write_next_block(void *data, |
1723 | unsigned int dwaddress, const void *buf, size_t dwords) | |
02d12855 RM |
1724 | |
1725 | { | |
1726 | const struct retimer_info *info = data; | |
1727 | struct tb_port *port = info->port; | |
1728 | u8 index = info->index; | |
1729 | int ret; | |
1730 | ||
1731 | ret = usb4_port_retimer_write(port, index, USB4_SB_DATA, | |
1732 | buf, dwords * 4); | |
1733 | if (ret) | |
1734 | return ret; | |
1735 | ||
1736 | return usb4_port_retimer_op(port, index, | |
1737 | USB4_SB_OPCODE_NVM_BLOCK_WRITE, 1000); | |
1738 | } | |
1739 | ||
1740 | /** | |
1741 | * usb4_port_retimer_nvm_write() - Write to retimer NVM | |
1742 | * @port: USB4 port | |
1743 | * @index: Retimer index | |
1744 | * @address: Byte address where to start the write | |
1745 | * @buf: Data to write | |
1746 | * @size: Size in bytes how much to write | |
1747 | * | |
1748 | * Writes @size bytes from @buf to the retimer NVM. Used for NVM | |
1749 | * upgrade. Returns %0 if the data was written successfully and negative | |
1750 | * errno in case of failure. Specifically returns %-ENODEV if there is | |
1751 | * no retimer at @index. | |
1752 | */ | |
1753 | int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address, | |
1754 | const void *buf, size_t size) | |
1755 | { | |
1756 | struct retimer_info info = { .port = port, .index = index }; | |
1757 | int ret; | |
1758 | ||
1759 | ret = usb4_port_retimer_nvm_set_offset(port, index, address); | |
1760 | if (ret) | |
1761 | return ret; | |
1762 | ||
9b383037 MW |
1763 | return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES, |
1764 | usb4_port_retimer_nvm_write_next_block, &info); | |
02d12855 RM |
1765 | } |
1766 | ||
1767 | /** | |
1768 | * usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade | |
1769 | * @port: USB4 port | |
1770 | * @index: Retimer index | |
1771 | * | |
1772 | * After the new NVM image has been written via usb4_port_retimer_nvm_write() | |
1773 | * this function can be used to trigger the NVM upgrade process. If | |
1774 | * successful the retimer restarts with the new NVM and may not have the | |
1775 | * index set so one needs to call usb4_port_enumerate_retimers() to | |
1776 | * force index to be assigned. | |
1777 | */ | |
1778 | int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index) | |
1779 | { | |
1780 | u32 val; | |
1781 | ||
1782 | /* | |
1783 | * We need to use the raw operation here because once the | |
1784 | * authentication completes the retimer index is not set anymore | |
1785 | * so we do not get back the status now. | |
1786 | */ | |
1787 | val = USB4_SB_OPCODE_NVM_AUTH_WRITE; | |
1788 | return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, | |
1789 | USB4_SB_OPCODE, &val, sizeof(val)); | |
1790 | } | |
1791 | ||
1792 | /** | |
1793 | * usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade | |
1794 | * @port: USB4 port | |
1795 | * @index: Retimer index | |
1796 | * @status: Raw status code read from metadata | |
1797 | * | |
1798 | * This can be called after usb4_port_retimer_nvm_authenticate() and | |
1799 | * usb4_port_enumerate_retimers() to fetch status of the NVM upgrade. | |
1800 | * | |
1801 | * Returns %0 if the authentication status was successfully read. The | |
1802 | * completion metadata (the result) is then stored into @status. If | |
1803 | * reading the status fails, returns negative errno. | |
1804 | */ | |
1805 | int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index, | |
1806 | u32 *status) | |
1807 | { | |
1808 | u32 metadata, val; | |
1809 | int ret; | |
1810 | ||
1811 | ret = usb4_port_retimer_read(port, index, USB4_SB_OPCODE, &val, | |
1812 | sizeof(val)); | |
1813 | if (ret) | |
1814 | return ret; | |
1815 | ||
1816 | switch (val) { | |
1817 | case 0: | |
1818 | *status = 0; | |
1819 | return 0; | |
1820 | ||
1821 | case USB4_SB_OPCODE_ERR: | |
1822 | ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, | |
1823 | &metadata, sizeof(metadata)); | |
1824 | if (ret) | |
1825 | return ret; | |
1826 | ||
1827 | *status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK; | |
1828 | return 0; | |
1829 | ||
1830 | case USB4_SB_OPCODE_ONS: | |
1831 | return -EOPNOTSUPP; | |
1832 | ||
1833 | default: | |
1834 | return -EIO; | |
1835 | } | |
1836 | } | |
1837 | ||
1838 | static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress, | |
1839 | void *buf, size_t dwords) | |
1840 | { | |
1841 | const struct retimer_info *info = data; | |
1842 | struct tb_port *port = info->port; | |
1843 | u8 index = info->index; | |
1844 | u32 metadata; | |
1845 | int ret; | |
1846 | ||
1847 | metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT; | |
9b383037 | 1848 | if (dwords < NVM_DATA_DWORDS) |
02d12855 RM |
1849 | metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT; |
1850 | ||
1851 | ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata, | |
1852 | sizeof(metadata)); | |
1853 | if (ret) | |
1854 | return ret; | |
1855 | ||
1856 | ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_READ, 500); | |
1857 | if (ret) | |
1858 | return ret; | |
1859 | ||
1860 | return usb4_port_retimer_read(port, index, USB4_SB_DATA, buf, | |
1861 | dwords * 4); | |
1862 | } | |
1863 | ||
1864 | /** | |
1865 | * usb4_port_retimer_nvm_read() - Read contents of retimer NVM | |
1866 | * @port: USB4 port | |
1867 | * @index: Retimer index | |
1868 | * @address: NVM address (in bytes) to start reading | |
1869 | * @buf: Data read from NVM is stored here | |
1870 | * @size: Number of bytes to read | |
1871 | * | |
1872 | * Reads retimer NVM and copies the contents to @buf. Returns %0 if the | |
1873 | * read was successful and negative errno in case of failure. | |
1874 | * Specifically returns %-ENODEV if there is no retimer at @index. | |
1875 | */ | |
1876 | int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index, | |
1877 | unsigned int address, void *buf, size_t size) | |
1878 | { | |
1879 | struct retimer_info info = { .port = port, .index = index }; | |
1880 | ||
9b383037 MW |
1881 | return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES, |
1882 | usb4_port_retimer_nvm_read_block, &info); | |
02d12855 RM |
1883 | } |
1884 | ||
f0a57dd3 GF |
1885 | static inline unsigned int |
1886 | usb4_usb3_port_max_bandwidth(const struct tb_port *port, unsigned int bw) | |
1887 | { | |
1888 | /* Take the possible bandwidth limitation into account */ | |
1889 | if (port->max_bw) | |
1890 | return min(bw, port->max_bw); | |
1891 | return bw; | |
1892 | } | |
1893 | ||
3b1d8d57 MW |
1894 | /** |
1895 | * usb4_usb3_port_max_link_rate() - Maximum support USB3 link rate | |
1896 | * @port: USB3 adapter port | |
1897 | * | |
1898 | * Return maximum supported link rate of a USB3 adapter in Mb/s. | |
1899 | * Negative errno in case of error. | |
1900 | */ | |
1901 | int usb4_usb3_port_max_link_rate(struct tb_port *port) | |
1902 | { | |
1903 | int ret, lr; | |
1904 | u32 val; | |
1905 | ||
1906 | if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port)) | |
1907 | return -EINVAL; | |
1908 | ||
1909 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1910 | port->cap_adap + ADP_USB3_CS_4, 1); | |
1911 | if (ret) | |
1912 | return ret; | |
1913 | ||
1914 | lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT; | |
f0a57dd3 GF |
1915 | ret = lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000; |
1916 | ||
1917 | return usb4_usb3_port_max_bandwidth(port, ret); | |
3b1d8d57 MW |
1918 | } |
1919 | ||
1920 | /** | |
1921 | * usb4_usb3_port_actual_link_rate() - Established USB3 link rate | |
1922 | * @port: USB3 adapter port | |
1923 | * | |
1924 | * Return actual established link rate of a USB3 adapter in Mb/s. If the | |
1925 | * link is not up returns %0 and negative errno in case of failure. | |
1926 | */ | |
1927 | int usb4_usb3_port_actual_link_rate(struct tb_port *port) | |
1928 | { | |
1929 | int ret, lr; | |
1930 | u32 val; | |
1931 | ||
1932 | if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port)) | |
1933 | return -EINVAL; | |
1934 | ||
1935 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1936 | port->cap_adap + ADP_USB3_CS_4, 1); | |
1937 | if (ret) | |
1938 | return ret; | |
1939 | ||
1940 | if (!(val & ADP_USB3_CS_4_ULV)) | |
1941 | return 0; | |
1942 | ||
1943 | lr = val & ADP_USB3_CS_4_ALR_MASK; | |
f0a57dd3 GF |
1944 | ret = lr == ADP_USB3_CS_4_ALR_20G ? 20000 : 10000; |
1945 | ||
1946 | return usb4_usb3_port_max_bandwidth(port, ret); | |
3b1d8d57 MW |
1947 | } |
1948 | ||
1949 | static int usb4_usb3_port_cm_request(struct tb_port *port, bool request) | |
1950 | { | |
1951 | int ret; | |
1952 | u32 val; | |
1953 | ||
1954 | if (!tb_port_is_usb3_down(port)) | |
1955 | return -EINVAL; | |
1956 | if (tb_route(port->sw)) | |
1957 | return -EINVAL; | |
1958 | ||
1959 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
1960 | port->cap_adap + ADP_USB3_CS_2, 1); | |
1961 | if (ret) | |
1962 | return ret; | |
1963 | ||
1964 | if (request) | |
1965 | val |= ADP_USB3_CS_2_CMR; | |
1966 | else | |
1967 | val &= ~ADP_USB3_CS_2_CMR; | |
1968 | ||
1969 | ret = tb_port_write(port, &val, TB_CFG_PORT, | |
1970 | port->cap_adap + ADP_USB3_CS_2, 1); | |
1971 | if (ret) | |
1972 | return ret; | |
1973 | ||
1974 | /* | |
1975 | * We can use val here directly as the CMR bit is in the same place | |
1976 | * as HCA. Just mask out others. | |
1977 | */ | |
1978 | val &= ADP_USB3_CS_2_CMR; | |
1979 | return usb4_port_wait_for_bit(port, port->cap_adap + ADP_USB3_CS_1, | |
1980 | ADP_USB3_CS_1_HCA, val, 1500); | |
1981 | } | |
1982 | ||
1983 | static inline int usb4_usb3_port_set_cm_request(struct tb_port *port) | |
1984 | { | |
1985 | return usb4_usb3_port_cm_request(port, true); | |
1986 | } | |
1987 | ||
1988 | static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port) | |
1989 | { | |
1990 | return usb4_usb3_port_cm_request(port, false); | |
1991 | } | |
1992 | ||
1993 | static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale) | |
1994 | { | |
1995 | unsigned long uframes; | |
1996 | ||
4c767ce4 | 1997 | uframes = bw * 512UL << scale; |
3b1d8d57 MW |
1998 | return DIV_ROUND_CLOSEST(uframes * 8000, 1000 * 1000); |
1999 | } | |
2000 | ||
2001 | static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale) | |
2002 | { | |
2003 | unsigned long uframes; | |
2004 | ||
2005 | /* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */ | |
2006 | uframes = ((unsigned long)mbps * 1000 * 1000) / 8000; | |
4c767ce4 | 2007 | return DIV_ROUND_UP(uframes, 512UL << scale); |
3b1d8d57 MW |
2008 | } |
2009 | ||
2010 | static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port, | |
2011 | int *upstream_bw, | |
2012 | int *downstream_bw) | |
2013 | { | |
2014 | u32 val, bw, scale; | |
2015 | int ret; | |
2016 | ||
2017 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2018 | port->cap_adap + ADP_USB3_CS_2, 1); | |
2019 | if (ret) | |
2020 | return ret; | |
2021 | ||
2022 | ret = tb_port_read(port, &scale, TB_CFG_PORT, | |
2023 | port->cap_adap + ADP_USB3_CS_3, 1); | |
2024 | if (ret) | |
2025 | return ret; | |
2026 | ||
2027 | scale &= ADP_USB3_CS_3_SCALE_MASK; | |
2028 | ||
2029 | bw = val & ADP_USB3_CS_2_AUBW_MASK; | |
2030 | *upstream_bw = usb3_bw_to_mbps(bw, scale); | |
2031 | ||
2032 | bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT; | |
2033 | *downstream_bw = usb3_bw_to_mbps(bw, scale); | |
2034 | ||
2035 | return 0; | |
2036 | } | |
2037 | ||
2038 | /** | |
2039 | * usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3 | |
2040 | * @port: USB3 adapter port | |
2041 | * @upstream_bw: Allocated upstream bandwidth is stored here | |
2042 | * @downstream_bw: Allocated downstream bandwidth is stored here | |
2043 | * | |
2044 | * Stores currently allocated USB3 bandwidth into @upstream_bw and | |
2045 | * @downstream_bw in Mb/s. Returns %0 in case of success and negative | |
2046 | * errno in failure. | |
2047 | */ | |
2048 | int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw, | |
2049 | int *downstream_bw) | |
2050 | { | |
2051 | int ret; | |
2052 | ||
2053 | ret = usb4_usb3_port_set_cm_request(port); | |
2054 | if (ret) | |
2055 | return ret; | |
2056 | ||
2057 | ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw, | |
2058 | downstream_bw); | |
2059 | usb4_usb3_port_clear_cm_request(port); | |
2060 | ||
2061 | return ret; | |
2062 | } | |
2063 | ||
2064 | static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port, | |
2065 | int *upstream_bw, | |
2066 | int *downstream_bw) | |
2067 | { | |
2068 | u32 val, bw, scale; | |
2069 | int ret; | |
2070 | ||
2071 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2072 | port->cap_adap + ADP_USB3_CS_1, 1); | |
2073 | if (ret) | |
2074 | return ret; | |
2075 | ||
2076 | ret = tb_port_read(port, &scale, TB_CFG_PORT, | |
2077 | port->cap_adap + ADP_USB3_CS_3, 1); | |
2078 | if (ret) | |
2079 | return ret; | |
2080 | ||
2081 | scale &= ADP_USB3_CS_3_SCALE_MASK; | |
2082 | ||
2083 | bw = val & ADP_USB3_CS_1_CUBW_MASK; | |
2084 | *upstream_bw = usb3_bw_to_mbps(bw, scale); | |
2085 | ||
2086 | bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT; | |
2087 | *downstream_bw = usb3_bw_to_mbps(bw, scale); | |
2088 | ||
2089 | return 0; | |
2090 | } | |
2091 | ||
2092 | static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port, | |
2093 | int upstream_bw, | |
2094 | int downstream_bw) | |
2095 | { | |
2096 | u32 val, ubw, dbw, scale; | |
c82510b1 | 2097 | int ret, max_bw; |
3b1d8d57 | 2098 | |
c82510b1 MW |
2099 | /* Figure out suitable scale */ |
2100 | scale = 0; | |
2101 | max_bw = max(upstream_bw, downstream_bw); | |
2102 | while (scale < 64) { | |
2103 | if (mbps_to_usb3_bw(max_bw, scale) < 4096) | |
2104 | break; | |
2105 | scale++; | |
2106 | } | |
2107 | ||
2108 | if (WARN_ON(scale >= 64)) | |
2109 | return -EINVAL; | |
2110 | ||
2111 | ret = tb_port_write(port, &scale, TB_CFG_PORT, | |
2112 | port->cap_adap + ADP_USB3_CS_3, 1); | |
3b1d8d57 MW |
2113 | if (ret) |
2114 | return ret; | |
2115 | ||
3b1d8d57 MW |
2116 | ubw = mbps_to_usb3_bw(upstream_bw, scale); |
2117 | dbw = mbps_to_usb3_bw(downstream_bw, scale); | |
2118 | ||
c82510b1 MW |
2119 | tb_port_dbg(port, "scaled bandwidth %u/%u, scale %u\n", ubw, dbw, scale); |
2120 | ||
3b1d8d57 MW |
2121 | ret = tb_port_read(port, &val, TB_CFG_PORT, |
2122 | port->cap_adap + ADP_USB3_CS_2, 1); | |
2123 | if (ret) | |
2124 | return ret; | |
2125 | ||
2126 | val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK); | |
2127 | val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT; | |
2128 | val |= ubw; | |
2129 | ||
2130 | return tb_port_write(port, &val, TB_CFG_PORT, | |
2131 | port->cap_adap + ADP_USB3_CS_2, 1); | |
2132 | } | |
2133 | ||
2134 | /** | |
2135 | * usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3 | |
2136 | * @port: USB3 adapter port | |
2137 | * @upstream_bw: New upstream bandwidth | |
2138 | * @downstream_bw: New downstream bandwidth | |
2139 | * | |
2140 | * This can be used to set how much bandwidth is allocated for the USB3 | |
2141 | * tunneled isochronous traffic. @upstream_bw and @downstream_bw are the | |
2142 | * new values programmed to the USB3 adapter allocation registers. If | |
2143 | * the values are lower than what is currently consumed the allocation | |
2144 | * is set to what is currently consumed instead (consumed bandwidth | |
2145 | * cannot be taken away by CM). The actual new values are returned in | |
2146 | * @upstream_bw and @downstream_bw. | |
2147 | * | |
2148 | * Returns %0 in case of success and negative errno if there was a | |
2149 | * failure. | |
2150 | */ | |
2151 | int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw, | |
2152 | int *downstream_bw) | |
2153 | { | |
2154 | int ret, consumed_up, consumed_down, allocate_up, allocate_down; | |
2155 | ||
2156 | ret = usb4_usb3_port_set_cm_request(port); | |
2157 | if (ret) | |
2158 | return ret; | |
2159 | ||
2160 | ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up, | |
2161 | &consumed_down); | |
2162 | if (ret) | |
2163 | goto err_request; | |
2164 | ||
2165 | /* Don't allow it go lower than what is consumed */ | |
2166 | allocate_up = max(*upstream_bw, consumed_up); | |
2167 | allocate_down = max(*downstream_bw, consumed_down); | |
2168 | ||
2169 | ret = usb4_usb3_port_write_allocated_bandwidth(port, allocate_up, | |
2170 | allocate_down); | |
2171 | if (ret) | |
2172 | goto err_request; | |
2173 | ||
2174 | *upstream_bw = allocate_up; | |
2175 | *downstream_bw = allocate_down; | |
2176 | ||
2177 | err_request: | |
2178 | usb4_usb3_port_clear_cm_request(port); | |
2179 | return ret; | |
2180 | } | |
2181 | ||
2182 | /** | |
2183 | * usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth | |
2184 | * @port: USB3 adapter port | |
2185 | * @upstream_bw: New allocated upstream bandwidth | |
2186 | * @downstream_bw: New allocated downstream bandwidth | |
2187 | * | |
2188 | * Releases USB3 allocated bandwidth down to what is actually consumed. | |
2189 | * The new bandwidth is returned in @upstream_bw and @downstream_bw. | |
2190 | * | |
2191 | * Returns 0% in success and negative errno in case of failure. | |
2192 | */ | |
2193 | int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw, | |
2194 | int *downstream_bw) | |
2195 | { | |
2196 | int ret, consumed_up, consumed_down; | |
2197 | ||
2198 | ret = usb4_usb3_port_set_cm_request(port); | |
2199 | if (ret) | |
2200 | return ret; | |
2201 | ||
2202 | ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up, | |
2203 | &consumed_down); | |
2204 | if (ret) | |
2205 | goto err_request; | |
2206 | ||
2207 | /* | |
2208 | * Always keep 1000 Mb/s to make sure xHCI has at least some | |
2209 | * bandwidth available for isochronous traffic. | |
2210 | */ | |
2211 | if (consumed_up < 1000) | |
2212 | consumed_up = 1000; | |
2213 | if (consumed_down < 1000) | |
2214 | consumed_down = 1000; | |
2215 | ||
2216 | ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up, | |
2217 | consumed_down); | |
2218 | if (ret) | |
2219 | goto err_request; | |
2220 | ||
2221 | *upstream_bw = consumed_up; | |
2222 | *downstream_bw = consumed_down; | |
2223 | ||
2224 | err_request: | |
2225 | usb4_usb3_port_clear_cm_request(port); | |
2226 | return ret; | |
2227 | } | |
e3273801 MW |
2228 | |
2229 | static bool is_usb4_dpin(const struct tb_port *port) | |
2230 | { | |
2231 | if (!tb_port_is_dpin(port)) | |
2232 | return false; | |
2233 | if (!tb_switch_is_usb4(port->sw)) | |
2234 | return false; | |
2235 | return true; | |
2236 | } | |
2237 | ||
2238 | /** | |
2239 | * usb4_dp_port_set_cm_id() - Assign CM ID to the DP IN adapter | |
2240 | * @port: DP IN adapter | |
2241 | * @cm_id: CM ID to assign | |
2242 | * | |
2243 | * Sets CM ID for the @port. Returns %0 on success and negative errno | |
2244 | * otherwise. Speficially returns %-EOPNOTSUPP if the @port does not | |
2245 | * support this. | |
2246 | */ | |
2247 | int usb4_dp_port_set_cm_id(struct tb_port *port, int cm_id) | |
2248 | { | |
2249 | u32 val; | |
2250 | int ret; | |
2251 | ||
2252 | if (!is_usb4_dpin(port)) | |
2253 | return -EOPNOTSUPP; | |
2254 | ||
2255 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2256 | port->cap_adap + ADP_DP_CS_2, 1); | |
2257 | if (ret) | |
2258 | return ret; | |
2259 | ||
2260 | val &= ~ADP_DP_CS_2_CM_ID_MASK; | |
2261 | val |= cm_id << ADP_DP_CS_2_CM_ID_SHIFT; | |
2262 | ||
2263 | return tb_port_write(port, &val, TB_CFG_PORT, | |
2264 | port->cap_adap + ADP_DP_CS_2, 1); | |
2265 | } | |
2266 | ||
2267 | /** | |
2268 | * usb4_dp_port_bw_mode_supported() - Is the bandwidth allocation mode supported | |
2269 | * @port: DP IN adapter to check | |
2270 | * | |
2271 | * Can be called to any DP IN adapter. Returns true if the adapter | |
2272 | * supports USB4 bandwidth allocation mode, false otherwise. | |
2273 | */ | |
2274 | bool usb4_dp_port_bw_mode_supported(struct tb_port *port) | |
2275 | { | |
2276 | int ret; | |
2277 | u32 val; | |
2278 | ||
2279 | if (!is_usb4_dpin(port)) | |
2280 | return false; | |
2281 | ||
2282 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2283 | port->cap_adap + DP_LOCAL_CAP, 1); | |
2284 | if (ret) | |
2285 | return false; | |
2286 | ||
2287 | return !!(val & DP_COMMON_CAP_BW_MODE); | |
2288 | } | |
2289 | ||
2290 | /** | |
2291 | * usb4_dp_port_bw_mode_enabled() - Is the bandwidth allocation mode enabled | |
2292 | * @port: DP IN adapter to check | |
2293 | * | |
2294 | * Can be called to any DP IN adapter. Returns true if the bandwidth | |
2295 | * allocation mode has been enabled, false otherwise. | |
2296 | */ | |
2297 | bool usb4_dp_port_bw_mode_enabled(struct tb_port *port) | |
2298 | { | |
2299 | int ret; | |
2300 | u32 val; | |
2301 | ||
2302 | if (!is_usb4_dpin(port)) | |
2303 | return false; | |
2304 | ||
2305 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2306 | port->cap_adap + ADP_DP_CS_8, 1); | |
2307 | if (ret) | |
2308 | return false; | |
2309 | ||
2310 | return !!(val & ADP_DP_CS_8_DPME); | |
2311 | } | |
2312 | ||
2313 | /** | |
2314 | * usb4_dp_port_set_cm_bw_mode_supported() - Set/clear CM support for bandwidth allocation mode | |
2315 | * @port: DP IN adapter | |
2316 | * @supported: Does the CM support bandwidth allocation mode | |
2317 | * | |
2318 | * Can be called to any DP IN adapter. Sets or clears the CM support bit | |
2319 | * of the DP IN adapter. Returns %0 in success and negative errno | |
2320 | * otherwise. Specifically returns %-OPNOTSUPP if the passed in adapter | |
2321 | * does not support this. | |
2322 | */ | |
2323 | int usb4_dp_port_set_cm_bw_mode_supported(struct tb_port *port, bool supported) | |
2324 | { | |
2325 | u32 val; | |
2326 | int ret; | |
2327 | ||
2328 | if (!is_usb4_dpin(port)) | |
2329 | return -EOPNOTSUPP; | |
2330 | ||
2331 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2332 | port->cap_adap + ADP_DP_CS_2, 1); | |
2333 | if (ret) | |
2334 | return ret; | |
2335 | ||
2336 | if (supported) | |
2337 | val |= ADP_DP_CS_2_CMMS; | |
2338 | else | |
2339 | val &= ~ADP_DP_CS_2_CMMS; | |
2340 | ||
2341 | return tb_port_write(port, &val, TB_CFG_PORT, | |
2342 | port->cap_adap + ADP_DP_CS_2, 1); | |
2343 | } | |
2344 | ||
2345 | /** | |
2346 | * usb4_dp_port_group_id() - Return Group ID assigned for the adapter | |
2347 | * @port: DP IN adapter | |
2348 | * | |
2349 | * Reads bandwidth allocation Group ID from the DP IN adapter and | |
2350 | * returns it. If the adapter does not support setting Group_ID | |
2351 | * %-EOPNOTSUPP is returned. | |
2352 | */ | |
2353 | int usb4_dp_port_group_id(struct tb_port *port) | |
2354 | { | |
2355 | u32 val; | |
2356 | int ret; | |
2357 | ||
2358 | if (!is_usb4_dpin(port)) | |
2359 | return -EOPNOTSUPP; | |
2360 | ||
2361 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2362 | port->cap_adap + ADP_DP_CS_2, 1); | |
2363 | if (ret) | |
2364 | return ret; | |
2365 | ||
2366 | return (val & ADP_DP_CS_2_GROUP_ID_MASK) >> ADP_DP_CS_2_GROUP_ID_SHIFT; | |
2367 | } | |
2368 | ||
2369 | /** | |
2370 | * usb4_dp_port_set_group_id() - Set adapter Group ID | |
2371 | * @port: DP IN adapter | |
2372 | * @group_id: Group ID for the adapter | |
2373 | * | |
2374 | * Sets bandwidth allocation mode Group ID for the DP IN adapter. | |
2375 | * Returns %0 in case of success and negative errno otherwise. | |
2376 | * Specifically returns %-EOPNOTSUPP if the adapter does not support | |
2377 | * this. | |
2378 | */ | |
2379 | int usb4_dp_port_set_group_id(struct tb_port *port, int group_id) | |
2380 | { | |
2381 | u32 val; | |
2382 | int ret; | |
2383 | ||
2384 | if (!is_usb4_dpin(port)) | |
2385 | return -EOPNOTSUPP; | |
2386 | ||
2387 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2388 | port->cap_adap + ADP_DP_CS_2, 1); | |
2389 | if (ret) | |
2390 | return ret; | |
2391 | ||
2392 | val &= ~ADP_DP_CS_2_GROUP_ID_MASK; | |
2393 | val |= group_id << ADP_DP_CS_2_GROUP_ID_SHIFT; | |
2394 | ||
2395 | return tb_port_write(port, &val, TB_CFG_PORT, | |
2396 | port->cap_adap + ADP_DP_CS_2, 1); | |
2397 | } | |
2398 | ||
2399 | /** | |
2400 | * usb4_dp_port_nrd() - Read non-reduced rate and lanes | |
2401 | * @port: DP IN adapter | |
2402 | * @rate: Non-reduced rate in Mb/s is placed here | |
2403 | * @lanes: Non-reduced lanes are placed here | |
2404 | * | |
2405 | * Reads the non-reduced rate and lanes from the DP IN adapter. Returns | |
2406 | * %0 in success and negative errno otherwise. Specifically returns | |
2407 | * %-EOPNOTSUPP if the adapter does not support this. | |
2408 | */ | |
2409 | int usb4_dp_port_nrd(struct tb_port *port, int *rate, int *lanes) | |
2410 | { | |
2411 | u32 val, tmp; | |
2412 | int ret; | |
2413 | ||
2414 | if (!is_usb4_dpin(port)) | |
2415 | return -EOPNOTSUPP; | |
2416 | ||
2417 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2418 | port->cap_adap + ADP_DP_CS_2, 1); | |
2419 | if (ret) | |
2420 | return ret; | |
2421 | ||
2422 | tmp = (val & ADP_DP_CS_2_NRD_MLR_MASK) >> ADP_DP_CS_2_NRD_MLR_SHIFT; | |
2423 | switch (tmp) { | |
2424 | case DP_COMMON_CAP_RATE_RBR: | |
2425 | *rate = 1620; | |
2426 | break; | |
2427 | case DP_COMMON_CAP_RATE_HBR: | |
2428 | *rate = 2700; | |
2429 | break; | |
2430 | case DP_COMMON_CAP_RATE_HBR2: | |
2431 | *rate = 5400; | |
2432 | break; | |
2433 | case DP_COMMON_CAP_RATE_HBR3: | |
2434 | *rate = 8100; | |
2435 | break; | |
2436 | } | |
2437 | ||
2438 | tmp = val & ADP_DP_CS_2_NRD_MLC_MASK; | |
2439 | switch (tmp) { | |
2440 | case DP_COMMON_CAP_1_LANE: | |
2441 | *lanes = 1; | |
2442 | break; | |
2443 | case DP_COMMON_CAP_2_LANES: | |
2444 | *lanes = 2; | |
2445 | break; | |
2446 | case DP_COMMON_CAP_4_LANES: | |
2447 | *lanes = 4; | |
2448 | break; | |
2449 | } | |
2450 | ||
2451 | return 0; | |
2452 | } | |
2453 | ||
2454 | /** | |
2455 | * usb4_dp_port_set_nrd() - Set non-reduced rate and lanes | |
2456 | * @port: DP IN adapter | |
2457 | * @rate: Non-reduced rate in Mb/s | |
2458 | * @lanes: Non-reduced lanes | |
2459 | * | |
2460 | * Before the capabilities reduction this function can be used to set | |
2461 | * the non-reduced values for the DP IN adapter. Returns %0 in success | |
2462 | * and negative errno otherwise. If the adapter does not support this | |
2463 | * %-EOPNOTSUPP is returned. | |
2464 | */ | |
2465 | int usb4_dp_port_set_nrd(struct tb_port *port, int rate, int lanes) | |
2466 | { | |
2467 | u32 val; | |
2468 | int ret; | |
2469 | ||
2470 | if (!is_usb4_dpin(port)) | |
2471 | return -EOPNOTSUPP; | |
2472 | ||
2473 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2474 | port->cap_adap + ADP_DP_CS_2, 1); | |
2475 | if (ret) | |
2476 | return ret; | |
2477 | ||
2478 | val &= ~ADP_DP_CS_2_NRD_MLR_MASK; | |
2479 | ||
2480 | switch (rate) { | |
2481 | case 1620: | |
2482 | break; | |
2483 | case 2700: | |
2484 | val |= (DP_COMMON_CAP_RATE_HBR << ADP_DP_CS_2_NRD_MLR_SHIFT) | |
2485 | & ADP_DP_CS_2_NRD_MLR_MASK; | |
2486 | break; | |
2487 | case 5400: | |
2488 | val |= (DP_COMMON_CAP_RATE_HBR2 << ADP_DP_CS_2_NRD_MLR_SHIFT) | |
2489 | & ADP_DP_CS_2_NRD_MLR_MASK; | |
2490 | break; | |
2491 | case 8100: | |
2492 | val |= (DP_COMMON_CAP_RATE_HBR3 << ADP_DP_CS_2_NRD_MLR_SHIFT) | |
2493 | & ADP_DP_CS_2_NRD_MLR_MASK; | |
2494 | break; | |
2495 | default: | |
2496 | return -EINVAL; | |
2497 | } | |
2498 | ||
2499 | val &= ~ADP_DP_CS_2_NRD_MLC_MASK; | |
2500 | ||
2501 | switch (lanes) { | |
2502 | case 1: | |
2503 | break; | |
2504 | case 2: | |
2505 | val |= DP_COMMON_CAP_2_LANES; | |
2506 | break; | |
2507 | case 4: | |
2508 | val |= DP_COMMON_CAP_4_LANES; | |
2509 | break; | |
2510 | default: | |
2511 | return -EINVAL; | |
2512 | } | |
2513 | ||
2514 | return tb_port_write(port, &val, TB_CFG_PORT, | |
2515 | port->cap_adap + ADP_DP_CS_2, 1); | |
2516 | } | |
2517 | ||
2518 | /** | |
2519 | * usb4_dp_port_granularity() - Return granularity for the bandwidth values | |
2520 | * @port: DP IN adapter | |
2521 | * | |
2522 | * Reads the programmed granularity from @port. If the DP IN adapter does | |
2523 | * not support bandwidth allocation mode returns %-EOPNOTSUPP and negative | |
2524 | * errno in other error cases. | |
2525 | */ | |
2526 | int usb4_dp_port_granularity(struct tb_port *port) | |
2527 | { | |
2528 | u32 val; | |
2529 | int ret; | |
2530 | ||
2531 | if (!is_usb4_dpin(port)) | |
2532 | return -EOPNOTSUPP; | |
2533 | ||
2534 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2535 | port->cap_adap + ADP_DP_CS_2, 1); | |
2536 | if (ret) | |
2537 | return ret; | |
2538 | ||
2539 | val &= ADP_DP_CS_2_GR_MASK; | |
2540 | val >>= ADP_DP_CS_2_GR_SHIFT; | |
2541 | ||
2542 | switch (val) { | |
2543 | case ADP_DP_CS_2_GR_0_25G: | |
2544 | return 250; | |
2545 | case ADP_DP_CS_2_GR_0_5G: | |
2546 | return 500; | |
2547 | case ADP_DP_CS_2_GR_1G: | |
2548 | return 1000; | |
2549 | } | |
2550 | ||
2551 | return -EINVAL; | |
2552 | } | |
2553 | ||
2554 | /** | |
2555 | * usb4_dp_port_set_granularity() - Set granularity for the bandwidth values | |
2556 | * @port: DP IN adapter | |
2557 | * @granularity: Granularity in Mb/s. Supported values: 1000, 500 and 250. | |
2558 | * | |
2559 | * Sets the granularity used with the estimated, allocated and requested | |
2560 | * bandwidth. Returns %0 in success and negative errno otherwise. If the | |
2561 | * adapter does not support this %-EOPNOTSUPP is returned. | |
2562 | */ | |
2563 | int usb4_dp_port_set_granularity(struct tb_port *port, int granularity) | |
2564 | { | |
2565 | u32 val; | |
2566 | int ret; | |
2567 | ||
2568 | if (!is_usb4_dpin(port)) | |
2569 | return -EOPNOTSUPP; | |
2570 | ||
2571 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2572 | port->cap_adap + ADP_DP_CS_2, 1); | |
2573 | if (ret) | |
2574 | return ret; | |
2575 | ||
2576 | val &= ~ADP_DP_CS_2_GR_MASK; | |
2577 | ||
2578 | switch (granularity) { | |
2579 | case 250: | |
2580 | val |= ADP_DP_CS_2_GR_0_25G << ADP_DP_CS_2_GR_SHIFT; | |
2581 | break; | |
2582 | case 500: | |
2583 | val |= ADP_DP_CS_2_GR_0_5G << ADP_DP_CS_2_GR_SHIFT; | |
2584 | break; | |
2585 | case 1000: | |
2586 | val |= ADP_DP_CS_2_GR_1G << ADP_DP_CS_2_GR_SHIFT; | |
2587 | break; | |
2588 | default: | |
2589 | return -EINVAL; | |
2590 | } | |
2591 | ||
2592 | return tb_port_write(port, &val, TB_CFG_PORT, | |
2593 | port->cap_adap + ADP_DP_CS_2, 1); | |
2594 | } | |
2595 | ||
2596 | /** | |
2597 | * usb4_dp_port_set_estimated_bw() - Set estimated bandwidth | |
2598 | * @port: DP IN adapter | |
2599 | * @bw: Estimated bandwidth in Mb/s. | |
2600 | * | |
2601 | * Sets the estimated bandwidth to @bw. Set the granularity by calling | |
2602 | * usb4_dp_port_set_granularity() before calling this. The @bw is round | |
2603 | * down to the closest granularity multiplier. Returns %0 in success | |
2604 | * and negative errno otherwise. Specifically returns %-EOPNOTSUPP if | |
2605 | * the adapter does not support this. | |
2606 | */ | |
2607 | int usb4_dp_port_set_estimated_bw(struct tb_port *port, int bw) | |
2608 | { | |
2609 | u32 val, granularity; | |
2610 | int ret; | |
2611 | ||
2612 | if (!is_usb4_dpin(port)) | |
2613 | return -EOPNOTSUPP; | |
2614 | ||
2615 | ret = usb4_dp_port_granularity(port); | |
2616 | if (ret < 0) | |
2617 | return ret; | |
2618 | granularity = ret; | |
2619 | ||
2620 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2621 | port->cap_adap + ADP_DP_CS_2, 1); | |
2622 | if (ret) | |
2623 | return ret; | |
2624 | ||
2625 | val &= ~ADP_DP_CS_2_ESTIMATED_BW_MASK; | |
2626 | val |= (bw / granularity) << ADP_DP_CS_2_ESTIMATED_BW_SHIFT; | |
2627 | ||
2628 | return tb_port_write(port, &val, TB_CFG_PORT, | |
2629 | port->cap_adap + ADP_DP_CS_2, 1); | |
2630 | } | |
2631 | ||
2632 | /** | |
2633 | * usb4_dp_port_allocated_bw() - Return allocated bandwidth | |
2634 | * @port: DP IN adapter | |
2635 | * | |
2636 | * Reads and returns allocated bandwidth for @port in Mb/s (taking into | |
2637 | * account the programmed granularity). Returns negative errno in case | |
2638 | * of error. | |
2639 | */ | |
2640 | int usb4_dp_port_allocated_bw(struct tb_port *port) | |
2641 | { | |
2642 | u32 val, granularity; | |
2643 | int ret; | |
2644 | ||
2645 | if (!is_usb4_dpin(port)) | |
2646 | return -EOPNOTSUPP; | |
2647 | ||
2648 | ret = usb4_dp_port_granularity(port); | |
2649 | if (ret < 0) | |
2650 | return ret; | |
2651 | granularity = ret; | |
2652 | ||
2653 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2654 | port->cap_adap + DP_STATUS, 1); | |
2655 | if (ret) | |
2656 | return ret; | |
2657 | ||
2658 | val &= DP_STATUS_ALLOCATED_BW_MASK; | |
2659 | val >>= DP_STATUS_ALLOCATED_BW_SHIFT; | |
2660 | ||
2661 | return val * granularity; | |
2662 | } | |
2663 | ||
2664 | static int __usb4_dp_port_set_cm_ack(struct tb_port *port, bool ack) | |
2665 | { | |
2666 | u32 val; | |
2667 | int ret; | |
2668 | ||
2669 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2670 | port->cap_adap + ADP_DP_CS_2, 1); | |
2671 | if (ret) | |
2672 | return ret; | |
2673 | ||
2674 | if (ack) | |
2675 | val |= ADP_DP_CS_2_CA; | |
2676 | else | |
2677 | val &= ~ADP_DP_CS_2_CA; | |
2678 | ||
2679 | return tb_port_write(port, &val, TB_CFG_PORT, | |
2680 | port->cap_adap + ADP_DP_CS_2, 1); | |
2681 | } | |
2682 | ||
2683 | static inline int usb4_dp_port_set_cm_ack(struct tb_port *port) | |
2684 | { | |
2685 | return __usb4_dp_port_set_cm_ack(port, true); | |
2686 | } | |
2687 | ||
2688 | static int usb4_dp_port_wait_and_clear_cm_ack(struct tb_port *port, | |
2689 | int timeout_msec) | |
2690 | { | |
2691 | ktime_t end; | |
2692 | u32 val; | |
2693 | int ret; | |
2694 | ||
2695 | ret = __usb4_dp_port_set_cm_ack(port, false); | |
2696 | if (ret) | |
2697 | return ret; | |
2698 | ||
2699 | end = ktime_add_ms(ktime_get(), timeout_msec); | |
2700 | do { | |
2701 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2702 | port->cap_adap + ADP_DP_CS_8, 1); | |
2703 | if (ret) | |
2704 | return ret; | |
2705 | ||
2706 | if (!(val & ADP_DP_CS_8_DR)) | |
2707 | break; | |
2708 | ||
2709 | usleep_range(50, 100); | |
2710 | } while (ktime_before(ktime_get(), end)); | |
2711 | ||
2712 | if (val & ADP_DP_CS_8_DR) | |
2713 | return -ETIMEDOUT; | |
2714 | ||
2715 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2716 | port->cap_adap + ADP_DP_CS_2, 1); | |
2717 | if (ret) | |
2718 | return ret; | |
2719 | ||
2720 | val &= ~ADP_DP_CS_2_CA; | |
2721 | return tb_port_write(port, &val, TB_CFG_PORT, | |
2722 | port->cap_adap + ADP_DP_CS_2, 1); | |
2723 | } | |
2724 | ||
2725 | /** | |
2726 | * usb4_dp_port_allocate_bw() - Set allocated bandwidth | |
2727 | * @port: DP IN adapter | |
2728 | * @bw: New allocated bandwidth in Mb/s | |
2729 | * | |
2730 | * Communicates the new allocated bandwidth with the DPCD (graphics | |
2731 | * driver). Takes into account the programmed granularity. Returns %0 in | |
2732 | * success and negative errno in case of error. | |
2733 | */ | |
2734 | int usb4_dp_port_allocate_bw(struct tb_port *port, int bw) | |
2735 | { | |
2736 | u32 val, granularity; | |
2737 | int ret; | |
2738 | ||
2739 | if (!is_usb4_dpin(port)) | |
2740 | return -EOPNOTSUPP; | |
2741 | ||
2742 | ret = usb4_dp_port_granularity(port); | |
2743 | if (ret < 0) | |
2744 | return ret; | |
2745 | granularity = ret; | |
2746 | ||
2747 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2748 | port->cap_adap + DP_STATUS, 1); | |
2749 | if (ret) | |
2750 | return ret; | |
2751 | ||
2752 | val &= ~DP_STATUS_ALLOCATED_BW_MASK; | |
2753 | val |= (bw / granularity) << DP_STATUS_ALLOCATED_BW_SHIFT; | |
2754 | ||
2755 | ret = tb_port_write(port, &val, TB_CFG_PORT, | |
2756 | port->cap_adap + DP_STATUS, 1); | |
2757 | if (ret) | |
2758 | return ret; | |
2759 | ||
2760 | ret = usb4_dp_port_set_cm_ack(port); | |
2761 | if (ret) | |
2762 | return ret; | |
2763 | ||
2764 | return usb4_dp_port_wait_and_clear_cm_ack(port, 500); | |
2765 | } | |
2766 | ||
2767 | /** | |
2768 | * usb4_dp_port_requested_bw() - Read requested bandwidth | |
2769 | * @port: DP IN adapter | |
2770 | * | |
2771 | * Reads the DPCD (graphics driver) requested bandwidth and returns it | |
2772 | * in Mb/s. Takes the programmed granularity into account. In case of | |
2773 | * error returns negative errno. Specifically returns %-EOPNOTSUPP if | |
ace75e18 MW |
2774 | * the adapter does not support bandwidth allocation mode, and %ENODATA |
2775 | * if there is no active bandwidth request from the graphics driver. | |
e3273801 MW |
2776 | */ |
2777 | int usb4_dp_port_requested_bw(struct tb_port *port) | |
2778 | { | |
2779 | u32 val, granularity; | |
2780 | int ret; | |
2781 | ||
2782 | if (!is_usb4_dpin(port)) | |
2783 | return -EOPNOTSUPP; | |
2784 | ||
2785 | ret = usb4_dp_port_granularity(port); | |
2786 | if (ret < 0) | |
2787 | return ret; | |
2788 | granularity = ret; | |
2789 | ||
2790 | ret = tb_port_read(port, &val, TB_CFG_PORT, | |
2791 | port->cap_adap + ADP_DP_CS_8, 1); | |
2792 | if (ret) | |
ace75e18 | 2793 | return ret; |
e3273801 MW |
2794 | |
2795 | if (!(val & ADP_DP_CS_8_DR)) | |
ace75e18 | 2796 | return -ENODATA; |
e3273801 MW |
2797 | |
2798 | return (val & ADP_DP_CS_8_REQUESTED_BW_MASK) * granularity; | |
2799 | } |