[linux-2.6-block.git] / drivers / thunderbolt / tb_regs.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Thunderbolt driver - Port/Switch config area registers
 *
 * Every thunderbolt device consists (logically) of a switch with multiple
 * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH,
 * COUNTERS) which are used to configure the device.
 *
 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
 * Copyright (C) 2018, Intel Corporation
 */

#ifndef _TB_REGS
#define _TB_REGS

#include <linux/types.h>


#define TB_ROUTE_SHIFT 8  /* number of bits in a port entry of a route */


/*
 * TODO: should be 63? But we do not know how to receive frames larger than 256
 * bytes at the frame level. (header + checksum = 16, 60*4 = 240)
 */
#define TB_MAX_CONFIG_RW_LENGTH 60

enum tb_switch_cap {
	TB_SWITCH_CAP_TMU		= 0x03,
	TB_SWITCH_CAP_VSE		= 0x05,
};

enum tb_switch_vse_cap {
	TB_VSE_CAP_PLUG_EVENTS		= 0x01, /* also EEPROM */
	TB_VSE_CAP_TIME2		= 0x03,
	TB_VSE_CAP_CP_LP		= 0x04,
	TB_VSE_CAP_LINK_CONTROLLER	= 0x06, /* also IECS */
};

enum tb_port_cap {
	TB_PORT_CAP_PHY			= 0x01,
	TB_PORT_CAP_POWER		= 0x02,
	TB_PORT_CAP_TIME1		= 0x03,
	TB_PORT_CAP_ADAP		= 0x04,
	TB_PORT_CAP_VSE			= 0x05,
	TB_PORT_CAP_USB4		= 0x06,
};

enum tb_port_state {
	TB_PORT_DISABLED	= 0, /* tb_cap_phy.disable == 1 */
	TB_PORT_CONNECTING	= 1, /* retry */
	TB_PORT_UP		= 2,
	TB_PORT_UNPLUGGED	= 7,
};

/* capability headers */

struct tb_cap_basic {
	u8 next;
	/* enum tb_cap cap:8; prevent "narrower than values of its type" */
	u8 cap; /* if cap == 0x05 then we have a extended capability */
} __packed;

/**
 * struct tb_cap_extended_short - Switch extended short capability
 * @next: Pointer to the next capability. If @next and @length are zero
 *	  then we have a long cap.
 * @cap: Base capability ID (see &enum tb_switch_cap)
 * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
 * @length: Length of this capability
 */
struct tb_cap_extended_short {
	u8 next;
	u8 cap;
	u8 vsec_id;
	u8 length;
} __packed;

/**
 * struct tb_cap_extended_long - Switch extended long capability
 * @zero1: This field should be zero
 * @cap: Base capability ID (see &enum tb_switch_cap)
 * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
 * @zero2: This field should be zero
 * @next: Pointer to the next capability
 * @length: Length of this capability
 */
struct tb_cap_extended_long {
	u8 zero1;
	u8 cap;
	u8 vsec_id;
	u8 zero2;
	u16 next;
	u16 length;
} __packed;

/**
 * struct tb_cap_any - Structure capable of hold every capability
 * @basic: Basic capability
 * @extended_short: Vendor specific capability
 * @extended_long: Vendor specific extended capability
 */
struct tb_cap_any {
	union {
		struct tb_cap_basic basic;
		struct tb_cap_extended_short extended_short;
		struct tb_cap_extended_long extended_long;
	};
} __packed;

/* capabilities */

struct tb_cap_link_controller {
	struct tb_cap_extended_long cap_header;
	u32 count:4; /* number of link controllers */
	u32 unknown1:4;
	u32 base_offset:8; /*
			    * offset (into this capability) of the configuration
			    * area of the first link controller
			    */
	u32 length:12; /* link controller configuration area length */
	u32 unknown2:4; /* TODO check that length is correct */
} __packed;

struct tb_cap_phy {
	struct tb_cap_basic cap_header;
	u32 unknown1:16;
	u32 unknown2:14;
	bool disable:1;
	u32 unknown3:11;
	enum tb_port_state state:4;
	u32 unknown4:2;
} __packed;

struct tb_eeprom_ctl {
	bool fl_sk:1; /* send pulse to transfer one bit */
	bool fl_cs:1; /* set to 0 before access */
	bool fl_di:1; /* to eeprom */
	bool fl_do:1; /* from eeprom */
	bool bit_banging_enable:1; /* set to 1 before access */
	bool not_present:1; /* should be 0 */
	bool unknown1:1;
	bool present:1; /* should be 1 */
	u32 unknown2:24;
} __packed;

struct tb_cap_plug_events {
	struct tb_cap_extended_short cap_header;
	u32 __unknown1:2; /* VSC_CS_1 */
	u32 plug_events:5; /* VSC_CS_1 */
	u32 __unknown2:25; /* VSC_CS_1 */
	u32 vsc_cs_2;
	u32 vsc_cs_3;
	struct tb_eeprom_ctl eeprom_ctl;
	u32 __unknown5[7]; /* VSC_CS_5 -> VSC_CS_11 */
	u32 drom_offset; /* VSC_CS_12: 32 bit register, but eeprom addresses are 16 bit */
} __packed;

/* device headers */

/* Present on port 0 in TB_CFG_SWITCH at address zero. */
struct tb_regs_switch_header {
	/* DWORD 0 */
	u16 vendor_id;
	u16 device_id;
	/* DWORD 1 */
	u32 first_cap_offset:8;
	u32 upstream_port_number:6;
	u32 max_port_number:6;
	u32 depth:3;
	u32 __unknown1:1;
	u32 revision:8;
	/* DWORD 2 */
	u32 route_lo;
	/* DWORD 3 */
	u32 route_hi:31;
	bool enabled:1;
	/* DWORD 4 */
	u32 plug_events_delay:8; /*
				  * RW, pause between plug events in
				  * milliseconds. Writing 0x00 is interpreted
				  * as 255ms.
				  */
	u32 cmuv:8;
	u32 __unknown4:8;
	u32 thunderbolt_version:8;
} __packed;

/* USB4 version 1.0 */
#define USB4_VERSION_1_0			0x20

#define ROUTER_CS_1				0x01
#define ROUTER_CS_4				0x04
#define ROUTER_CS_5				0x05
#define ROUTER_CS_5_SLP				BIT(0)
#define ROUTER_CS_5_WOP				BIT(1)
#define ROUTER_CS_5_WOU				BIT(2)
#define ROUTER_CS_5_WOD				BIT(3)
#define ROUTER_CS_5_C3S				BIT(23)
#define ROUTER_CS_5_PTO				BIT(24)
#define ROUTER_CS_5_UTO				BIT(25)
#define ROUTER_CS_5_HCO				BIT(26)
#define ROUTER_CS_5_CV				BIT(31)
#define ROUTER_CS_6				0x06
#define ROUTER_CS_6_SLPR			BIT(0)
#define ROUTER_CS_6_TNS				BIT(1)
#define ROUTER_CS_6_WOPS			BIT(2)
#define ROUTER_CS_6_WOUS			BIT(3)
#define ROUTER_CS_6_HCI				BIT(18)
#define ROUTER_CS_6_CR				BIT(25)
#define ROUTER_CS_7				0x07
#define ROUTER_CS_9				0x09
#define ROUTER_CS_25				0x19
#define ROUTER_CS_26				0x1a
#define ROUTER_CS_26_OPCODE_MASK		GENMASK(15, 0)
#define ROUTER_CS_26_STATUS_MASK		GENMASK(29, 24)
#define ROUTER_CS_26_STATUS_SHIFT		24
#define ROUTER_CS_26_ONS			BIT(30)
#define ROUTER_CS_26_OV				BIT(31)

/* USB4 router operations opcodes */
enum usb4_switch_op {
	USB4_SWITCH_OP_QUERY_DP_RESOURCE = 0x10,
	USB4_SWITCH_OP_ALLOC_DP_RESOURCE = 0x11,
	USB4_SWITCH_OP_DEALLOC_DP_RESOURCE = 0x12,
	USB4_SWITCH_OP_NVM_WRITE = 0x20,
	USB4_SWITCH_OP_NVM_AUTH = 0x21,
	USB4_SWITCH_OP_NVM_READ = 0x22,
	USB4_SWITCH_OP_NVM_SET_OFFSET = 0x23,
	USB4_SWITCH_OP_DROM_READ = 0x24,
	USB4_SWITCH_OP_NVM_SECTOR_SIZE = 0x25,
	USB4_SWITCH_OP_BUFFER_ALLOC = 0x33,
};

/* Router TMU configuration */
#define TMU_RTR_CS_0				0x00
#define TMU_RTR_CS_0_FREQ_WIND_MASK		GENMASK(26, 16)
#define TMU_RTR_CS_0_TD				BIT(27)
#define TMU_RTR_CS_0_UCAP			BIT(30)
#define TMU_RTR_CS_1				0x01
#define TMU_RTR_CS_1_LOCAL_TIME_NS_MASK		GENMASK(31, 16)
#define TMU_RTR_CS_1_LOCAL_TIME_NS_SHIFT	16
#define TMU_RTR_CS_2				0x02
#define TMU_RTR_CS_3				0x03
#define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK		GENMASK(15, 0)
#define TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK	GENMASK(31, 16)
#define TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT	16
#define TMU_RTR_CS_15				0xf
#define TMU_RTR_CS_15_FREQ_AVG_MASK		GENMASK(5, 0)
#define TMU_RTR_CS_15_DELAY_AVG_MASK		GENMASK(11, 6)
#define TMU_RTR_CS_15_OFFSET_AVG_MASK		GENMASK(17, 12)
#define TMU_RTR_CS_15_ERROR_AVG_MASK		GENMASK(23, 18)
#define TMU_RTR_CS_22				0x16
#define TMU_RTR_CS_24				0x18
#define TMU_RTR_CS_25				0x19

enum tb_port_type {
	TB_TYPE_INACTIVE	= 0x000000,
	TB_TYPE_PORT		= 0x000001,
	TB_TYPE_NHI		= 0x000002,
	/* TB_TYPE_ETHERNET	= 0x020000, lower order bits are not known */
	/* TB_TYPE_SATA		= 0x080000, lower order bits are not known */
	TB_TYPE_DP_HDMI_IN	= 0x0e0101,
	TB_TYPE_DP_HDMI_OUT	= 0x0e0102,
	TB_TYPE_PCIE_DOWN	= 0x100101,
	TB_TYPE_PCIE_UP		= 0x100102,
	TB_TYPE_USB3_DOWN	= 0x200101,
	TB_TYPE_USB3_UP		= 0x200102,
};

/* Present on every port in TB_CF_PORT at address zero. */
struct tb_regs_port_header {
	/* DWORD 0 */
	u16 vendor_id;
	u16 device_id;
	/* DWORD 1 */
	u32 first_cap_offset:8;
	u32 max_counters:11;
	u32 counters_support:1;
	u32 __unknown1:4;
	u32 revision:8;
	/* DWORD 2 */
	enum tb_port_type type:24;
	u32 thunderbolt_version:8;
	/* DWORD 3 */
	u32 __unknown2:20;
	u32 port_number:6;
	u32 __unknown3:6;
	/* DWORD 4 */
	u32 nfc_credits;
	/* DWORD 5 */
	u32 max_in_hop_id:11;
	u32 max_out_hop_id:11;
	u32 __unknown4:10;
	/* DWORD 6 */
	u32 __unknown5;
	/* DWORD 7 */
	u32 __unknown6;

} __packed;

/* Basic adapter configuration registers */
#define ADP_CS_4				0x04
#define ADP_CS_4_NFC_BUFFERS_MASK		GENMASK(9, 0)
#define ADP_CS_4_TOTAL_BUFFERS_MASK		GENMASK(29, 20)
#define ADP_CS_4_TOTAL_BUFFERS_SHIFT		20
#define ADP_CS_4_LCK				BIT(31)
#define ADP_CS_5				0x05
#define ADP_CS_5_LCA_MASK			GENMASK(28, 22)
#define ADP_CS_5_LCA_SHIFT			22

/* TMU adapter registers */
#define TMU_ADP_CS_3				0x03
#define TMU_ADP_CS_3_UDM			BIT(29)
#define TMU_ADP_CS_6				0x06
#define TMU_ADP_CS_6_DTS			BIT(1)

/* Lane adapter registers */
#define LANE_ADP_CS_0				0x00
#define LANE_ADP_CS_0_SUPPORTED_SPEED_MASK	GENMASK(19, 16)
#define LANE_ADP_CS_0_SUPPORTED_SPEED_SHIFT	16
#define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK	GENMASK(25, 20)
#define LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT	20
#define LANE_ADP_CS_0_SUPPORTED_WIDTH_DUAL	0x2
#define LANE_ADP_CS_0_CL0S_SUPPORT		BIT(26)
#define LANE_ADP_CS_0_CL1_SUPPORT		BIT(27)
#define LANE_ADP_CS_1				0x01
#define LANE_ADP_CS_1_TARGET_SPEED_MASK		GENMASK(3, 0)
#define LANE_ADP_CS_1_TARGET_SPEED_GEN3		0xc
#define LANE_ADP_CS_1_TARGET_WIDTH_MASK		GENMASK(9, 4)
#define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT	4
#define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE	0x1
#define LANE_ADP_CS_1_TARGET_WIDTH_DUAL		0x3
#define LANE_ADP_CS_1_CL0S_ENABLE		BIT(10)
#define LANE_ADP_CS_1_CL1_ENABLE		BIT(11)
#define LANE_ADP_CS_1_LD			BIT(14)
#define LANE_ADP_CS_1_LB			BIT(15)
#define LANE_ADP_CS_1_CURRENT_SPEED_MASK	GENMASK(19, 16)
#define LANE_ADP_CS_1_CURRENT_SPEED_SHIFT	16
#define LANE_ADP_CS_1_CURRENT_SPEED_GEN2	0x8
#define LANE_ADP_CS_1_CURRENT_SPEED_GEN3	0x4
#define LANE_ADP_CS_1_CURRENT_WIDTH_MASK	GENMASK(25, 20)
#define LANE_ADP_CS_1_CURRENT_WIDTH_SHIFT	20
#define LANE_ADP_CS_1_PMS			BIT(30)

/* USB4 port registers */
#define PORT_CS_1				0x01
#define PORT_CS_1_LENGTH_SHIFT			8
#define PORT_CS_1_TARGET_MASK			GENMASK(18, 16)
#define PORT_CS_1_TARGET_SHIFT			16
#define PORT_CS_1_RETIMER_INDEX_SHIFT		20
#define PORT_CS_1_WNR_WRITE			BIT(24)
#define PORT_CS_1_NR				BIT(25)
#define PORT_CS_1_RC				BIT(26)
#define PORT_CS_1_PND				BIT(31)
#define PORT_CS_2				0x02
#define PORT_CS_18				0x12
#define PORT_CS_18_BE				BIT(8)
#define PORT_CS_18_TCM				BIT(9)
#define PORT_CS_18_CPS				BIT(10)
#define PORT_CS_18_WOU4S			BIT(18)
#define PORT_CS_19				0x13
#define PORT_CS_19_PC				BIT(3)
#define PORT_CS_19_PID				BIT(4)
#define PORT_CS_19_WOC				BIT(16)
#define PORT_CS_19_WOD				BIT(17)
#define PORT_CS_19_WOU4				BIT(18)

/* Display Port adapter registers */
#define ADP_DP_CS_0				0x00
#define ADP_DP_CS_0_VIDEO_HOPID_MASK		GENMASK(26, 16)
#define ADP_DP_CS_0_VIDEO_HOPID_SHIFT		16
#define ADP_DP_CS_0_AE				BIT(30)
#define ADP_DP_CS_0_VE				BIT(31)
#define ADP_DP_CS_1_AUX_TX_HOPID_MASK		GENMASK(10, 0)
#define ADP_DP_CS_1_AUX_RX_HOPID_MASK		GENMASK(21, 11)
#define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT		11
#define ADP_DP_CS_2				0x02
#define ADP_DP_CS_2_HDP				BIT(6)
#define ADP_DP_CS_3				0x03
#define ADP_DP_CS_3_HDPC			BIT(9)
#define DP_LOCAL_CAP				0x04
#define DP_REMOTE_CAP				0x05
#define DP_STATUS_CTRL				0x06
#define DP_STATUS_CTRL_CMHS			BIT(25)
#define DP_STATUS_CTRL_UF			BIT(26)
#define DP_COMMON_CAP				0x07
/*
 * DP_COMMON_CAP offsets work also for DP_LOCAL_CAP and DP_REMOTE_CAP
 * with exception of DPRX done.
 */
#define DP_COMMON_CAP_RATE_MASK			GENMASK(11, 8)
#define DP_COMMON_CAP_RATE_SHIFT		8
#define DP_COMMON_CAP_RATE_RBR			0x0
#define DP_COMMON_CAP_RATE_HBR			0x1
#define DP_COMMON_CAP_RATE_HBR2			0x2
#define DP_COMMON_CAP_RATE_HBR3			0x3
#define DP_COMMON_CAP_LANES_MASK		GENMASK(14, 12)
#define DP_COMMON_CAP_LANES_SHIFT		12
#define DP_COMMON_CAP_1_LANE			0x0
#define DP_COMMON_CAP_2_LANES			0x1
#define DP_COMMON_CAP_4_LANES			0x2
#define DP_COMMON_CAP_LTTPR_NS			BIT(27)
#define DP_COMMON_CAP_DPRX_DONE			BIT(31)

/* PCIe adapter registers */
#define ADP_PCIE_CS_0				0x00
#define ADP_PCIE_CS_0_PE			BIT(31)

/* USB adapter registers */
#define ADP_USB3_CS_0				0x00
#define ADP_USB3_CS_0_V				BIT(30)
#define ADP_USB3_CS_0_PE			BIT(31)
#define ADP_USB3_CS_1				0x01
#define ADP_USB3_CS_1_CUBW_MASK			GENMASK(11, 0)
#define ADP_USB3_CS_1_CDBW_MASK			GENMASK(23, 12)
#define ADP_USB3_CS_1_CDBW_SHIFT		12
#define ADP_USB3_CS_1_HCA			BIT(31)
#define ADP_USB3_CS_2				0x02
#define ADP_USB3_CS_2_AUBW_MASK			GENMASK(11, 0)
#define ADP_USB3_CS_2_ADBW_MASK			GENMASK(23, 12)
#define ADP_USB3_CS_2_ADBW_SHIFT		12
#define ADP_USB3_CS_2_CMR			BIT(31)
#define ADP_USB3_CS_3				0x03
#define ADP_USB3_CS_3_SCALE_MASK		GENMASK(5, 0)
#define ADP_USB3_CS_4				0x04
#define ADP_USB3_CS_4_ALR_MASK			GENMASK(6, 0)
#define ADP_USB3_CS_4_ALR_20G			0x1
#define ADP_USB3_CS_4_ULV			BIT(7)
#define ADP_USB3_CS_4_MSLR_MASK			GENMASK(18, 12)
#define ADP_USB3_CS_4_MSLR_SHIFT		12
#define ADP_USB3_CS_4_MSLR_20G			0x1

/* Hop register from TB_CFG_HOPS. 8 byte per entry. */
struct tb_regs_hop {
	/* DWORD 0 */
	u32 next_hop:11; /*
			  * hop to take after sending the packet through
			  * out_port (on the incoming port of the next switch)
			  */
	u32 out_port:6; /* next port of the path (on the same switch) */
	u32 initial_credits:8;
	u32 unknown1:6; /* set to zero */
	bool enable:1;

	/* DWORD 1 */
	u32 weight:4;
	u32 unknown2:4; /* set to zero */
	u32 priority:3;
	bool drop_packages:1;
	u32 counter:11; /* index into TB_CFG_COUNTERS on this port */
	bool counter_enable:1;
	bool ingress_fc:1;
	bool egress_fc:1;
	bool ingress_shared_buffer:1;
	bool egress_shared_buffer:1;
	bool pending:1;
	u32 unknown3:3; /* set to zero */
} __packed;

/* TMU Thunderbolt 3 registers */
#define TB_TIME_VSEC_3_CS_9			0x9
#define TB_TIME_VSEC_3_CS_9_TMU_OBJ_MASK	GENMASK(17, 16)
#define TB_TIME_VSEC_3_CS_26			0x1a
#define TB_TIME_VSEC_3_CS_26_TD			BIT(22)

/*
 * Used for Titan Ridge only. Bits are part of the same register: TMU_ADP_CS_6
 * (see above) as in USB4 spec, but these specific bits used for Titan Ridge
 * only and reserved in USB4 spec.
 */
#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_MASK	GENMASK(3, 2)
#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL1	BIT(2)
#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL2	BIT(3)

/* Plug Events registers */
#define TB_PLUG_EVENTS_USB_DISABLE		BIT(2)
#define TB_PLUG_EVENTS_CS_1_LANE_DISABLE	BIT(3)
#define TB_PLUG_EVENTS_CS_1_DPOUT_DISABLE	BIT(4)
#define TB_PLUG_EVENTS_CS_1_LOW_DPIN_DISABLE	BIT(5)
#define TB_PLUG_EVENTS_CS_1_HIGH_DPIN_DISABLE	BIT(6)

#define TB_PLUG_EVENTS_PCIE_WR_DATA		0x1b
#define TB_PLUG_EVENTS_PCIE_CMD			0x1c
#define TB_PLUG_EVENTS_PCIE_CMD_DW_OFFSET_MASK	GENMASK(9, 0)
#define TB_PLUG_EVENTS_PCIE_CMD_BR_SHIFT	10
#define TB_PLUG_EVENTS_PCIE_CMD_BR_MASK		GENMASK(17, 10)
#define TB_PLUG_EVENTS_PCIE_CMD_RD_WR_MASK	BIT(21)
#define TB_PLUG_EVENTS_PCIE_CMD_WR		0x1
#define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_SHIFT	22
#define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_MASK	GENMASK(24, 22)
#define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_VAL	0x2
#define TB_PLUG_EVENTS_PCIE_CMD_REQ_ACK_MASK	BIT(30)
#define TB_PLUG_EVENTS_PCIE_CMD_TIMEOUT_MASK	BIT(31)
#define TB_PLUG_EVENTS_PCIE_CMD_RD_DATA		0x1d

/* CP Low Power registers */
#define TB_LOW_PWR_C1_CL1			0x1
#define TB_LOW_PWR_C1_CL1_OBJ_MASK		GENMASK(4, 1)
#define TB_LOW_PWR_C1_CL2_OBJ_MASK		GENMASK(4, 1)
#define TB_LOW_PWR_C1_PORT_A_MASK		GENMASK(2, 1)
#define TB_LOW_PWR_C0_PORT_B_MASK		GENMASK(4, 3)
#define TB_LOW_PWR_C3_CL1			0x3

/* Common link controller registers */
#define TB_LC_DESC				0x02
#define TB_LC_DESC_NLC_MASK			GENMASK(3, 0)
#define TB_LC_DESC_SIZE_SHIFT			8
#define TB_LC_DESC_SIZE_MASK			GENMASK(15, 8)
#define TB_LC_DESC_PORT_SIZE_SHIFT		16
#define TB_LC_DESC_PORT_SIZE_MASK		GENMASK(27, 16)
#define TB_LC_FUSE				0x03
#define TB_LC_SNK_ALLOCATION			0x10
#define TB_LC_SNK_ALLOCATION_SNK0_MASK		GENMASK(3, 0)
#define TB_LC_SNK_ALLOCATION_SNK0_CM		0x1
#define TB_LC_SNK_ALLOCATION_SNK1_SHIFT		4
#define TB_LC_SNK_ALLOCATION_SNK1_MASK		GENMASK(7, 4)
#define TB_LC_SNK_ALLOCATION_SNK1_CM		0x1
#define TB_LC_POWER				0x740

/* Link controller registers */
#define TB_LC_CS_42				0x2a
#define TB_LC_CS_42_USB_PLUGGED			BIT(31)

#define TB_LC_PORT_ATTR				0x8d
#define TB_LC_PORT_ATTR_BE			BIT(12)

#define TB_LC_SX_CTRL				0x96
#define TB_LC_SX_CTRL_WOC			BIT(1)
#define TB_LC_SX_CTRL_WOD			BIT(2)
#define TB_LC_SX_CTRL_WODPC			BIT(3)
#define TB_LC_SX_CTRL_WODPD			BIT(4)
#define TB_LC_SX_CTRL_WOU4			BIT(5)
#define TB_LC_SX_CTRL_WOP			BIT(6)
#define TB_LC_SX_CTRL_L1C			BIT(16)
#define TB_LC_SX_CTRL_L1D			BIT(17)
#define TB_LC_SX_CTRL_L2C			BIT(20)
#define TB_LC_SX_CTRL_L2D			BIT(21)
#define TB_LC_SX_CTRL_SLI			BIT(29)
#define TB_LC_SX_CTRL_UPSTREAM			BIT(30)
#define TB_LC_SX_CTRL_SLP			BIT(31)
#define TB_LC_LINK_ATTR				0x97
#define TB_LC_LINK_ATTR_CPS			BIT(18)

#define TB_LC_LINK_REQ				0xad
#define TB_LC_LINK_REQ_XHCI_CONNECT		BIT(31)

#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
7adf6097	2	/*
15c6784c	3	* Thunderbolt driver - Port/Switch config area registers
7adf6097 AN	4	*
	5	* Every thunderbolt device consists (logically) of a switch with multiple
	6	* ports. Every port contains up to four config regions (HOPS, PORT, SWITCH,
	7	* COUNTERS) which are used to configure the device.
	8	*
	9	* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
15c6784c	10	* Copyright (C) 2018, Intel Corporation
7adf6097 AN	11	*/
	12
	13	#ifndef _TB_REGS
	14	#define _TB_REGS
	15
	16	#include <linux/types.h>
	17
	18
	19	#define TB_ROUTE_SHIFT 8 /* number of bits in a port entry of a route */
	20
	21
	22	/*
	23	* TODO: should be 63? But we do not know how to receive frames larger than 256
	24	* bytes at the frame level. (header + checksum = 16, 60*4 = 240)
	25	*/
	26	#define TB_MAX_CONFIG_RW_LENGTH 60
	27
da2da04b	28	enum tb_switch_cap {
cf29b9af	29	TB_SWITCH_CAP_TMU = 0x03,
da2da04b MW	30	TB_SWITCH_CAP_VSE = 0x05,
	31	};
	32
	33	enum tb_switch_vse_cap {
	34	TB_VSE_CAP_PLUG_EVENTS = 0x01, /* also EEPROM */
	35	TB_VSE_CAP_TIME2 = 0x03,
483c9d82	36	TB_VSE_CAP_CP_LP = 0x04,
da2da04b MW	37	TB_VSE_CAP_LINK_CONTROLLER = 0x06, /* also IECS */
	38	};
	39
	40	enum tb_port_cap {
	41	TB_PORT_CAP_PHY = 0x01,
54e41810	42	TB_PORT_CAP_POWER = 0x02,
da2da04b MW	43	TB_PORT_CAP_TIME1 = 0x03,
	44	TB_PORT_CAP_ADAP = 0x04,
	45	TB_PORT_CAP_VSE = 0x05,
b0407983	46	TB_PORT_CAP_USB4 = 0x06,
7adf6097 AN	47	};
	48
	49	enum tb_port_state {
	50	TB_PORT_DISABLED = 0, /* tb_cap_phy.disable == 1 */
	51	TB_PORT_CONNECTING = 1, /* retry */
	52	TB_PORT_UP = 2,
	53	TB_PORT_UNPLUGGED = 7,
	54	};
	55
	56	/* capability headers */
	57
	58	struct tb_cap_basic {
	59	u8 next;
	60	/* enum tb_cap cap:8; prevent "narrower than values of its type" */
	61	u8 cap; /* if cap == 0x05 then we have a extended capability */
	62	} __packed;
	63
da2da04b MW	64	/**
	65	* struct tb_cap_extended_short - Switch extended short capability
	66	* @next: Pointer to the next capability. If @next and @length are zero
	67	* then we have a long cap.
	68	* @cap: Base capability ID (see &enum tb_switch_cap)
	69	* @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
	70	* @length: Length of this capability
	71	*/
7adf6097	72	struct tb_cap_extended_short {
da2da04b MW	73	u8 next;
	74	u8 cap;
	75	u8 vsec_id;
7adf6097 AN	76	u8 length;
	77	} __packed;
	78
da2da04b MW	79	/**
	80	* struct tb_cap_extended_long - Switch extended long capability
	81	* @zero1: This field should be zero
	82	* @cap: Base capability ID (see &enum tb_switch_cap)
	83	* @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
	84	* @zero2: This field should be zero
	85	* @next: Pointer to the next capability
	86	* @length: Length of this capability
	87	*/
7adf6097 AN	88	struct tb_cap_extended_long {
7adf6097 AN	89	u8 zero1;
da2da04b MW	90	u8 cap;
da2da04b MW	91	u8 vsec_id;
7adf6097 AN	92	u8 zero2;
	93	u16 next;
	94	u16 length;
	95	} __packed;
	96
8f831011 MW	97	/**
	98	* struct tb_cap_any - Structure capable of hold every capability
	99	* @basic: Basic capability
	100	* @extended_short: Vendor specific capability
	101	* @extended_long: Vendor specific extended capability
	102	*/
	103	struct tb_cap_any {
	104	union {
	105	struct tb_cap_basic basic;
	106	struct tb_cap_extended_short extended_short;
	107	struct tb_cap_extended_long extended_long;
	108	};
	109	} __packed;
	110
7adf6097 AN	111	/* capabilities */
	112
	113	struct tb_cap_link_controller {
	114	struct tb_cap_extended_long cap_header;
	115	u32 count:4; /* number of link controllers */
	116	u32 unknown1:4;
	117	u32 base_offset:8; /*
	118	* offset (into this capability) of the configuration
	119	* area of the first link controller
	120	*/
	121	u32 length:12; /* link controller configuration area length */
	122	u32 unknown2:4; /* TODO check that length is correct */
	123	} __packed;
	124
	125	struct tb_cap_phy {
	126	struct tb_cap_basic cap_header;
	127	u32 unknown1:16;
	128	u32 unknown2:14;
	129	bool disable:1;
	130	u32 unknown3:11;
	131	enum tb_port_state state:4;
	132	u32 unknown4:2;
	133	} __packed;
	134
	135	struct tb_eeprom_ctl {
144c4a77 ML	136	bool fl_sk:1; /* send pulse to transfer one bit */
	137	bool fl_cs:1; /* set to 0 before access */
	138	bool fl_di:1; /* to eeprom */
	139	bool fl_do:1; /* from eeprom */
	140	bool bit_banging_enable:1; /* set to 1 before access */
7adf6097 AN	141	bool not_present:1; /* should be 0 */
	142	bool unknown1:1;
	143	bool present:1; /* should be 1 */
	144	u32 unknown2:24;
	145	} __packed;
	146
	147	struct tb_cap_plug_events {
	148	struct tb_cap_extended_short cap_header;
51d4d64c ML	149	u32 __unknown1:2; /* VSC_CS_1 */
	150	u32 plug_events:5; /* VSC_CS_1 */
	151	u32 __unknown2:25; /* VSC_CS_1 */
	152	u32 vsc_cs_2;
	153	u32 vsc_cs_3;
7adf6097	154	struct tb_eeprom_ctl eeprom_ctl;
51d4d64c ML	155	u32 __unknown5[7]; /* VSC_CS_5 -> VSC_CS_11 */
51d4d64c ML	156	u32 drom_offset; /* VSC_CS_12: 32 bit register, but eeprom addresses are 16 bit */
7adf6097 AN	157	} __packed;
	158
	159	/* device headers */
	160
	161	/* Present on port 0 in TB_CFG_SWITCH at address zero. */
	162	struct tb_regs_switch_header {
	163	/* DWORD 0 */
	164	u16 vendor_id;
	165	u16 device_id;
	166	/* DWORD 1 */
	167	u32 first_cap_offset:8;
	168	u32 upstream_port_number:6;
	169	u32 max_port_number:6;
	170	u32 depth:3;
	171	u32 __unknown1:1;
	172	u32 revision:8;
	173	/* DWORD 2 */
	174	u32 route_lo;
	175	/* DWORD 3 */
	176	u32 route_hi:31;
	177	bool enabled:1;
	178	/* DWORD 4 */
	179	u32 plug_events_delay:8; /*
	180	* RW, pause between plug events in
	181	* milliseconds. Writing 0x00 is interpreted
	182	* as 255ms.
	183	*/
b0407983 MW	184	u32 cmuv:8;
b0407983 MW	185	u32 __unknown4:8;
7adf6097 AN	186	u32 thunderbolt_version:8;
	187	} __packed;
	188
b0407983 MW	189	/* USB4 version 1.0 */
	190	#define USB4_VERSION_1_0 0x20
	191
	192	#define ROUTER_CS_1 0x01
	193	#define ROUTER_CS_4 0x04
	194	#define ROUTER_CS_5 0x05
	195	#define ROUTER_CS_5_SLP BIT(0)
b2911a59 MW	196	#define ROUTER_CS_5_WOP BIT(1)
b2911a59 MW	197	#define ROUTER_CS_5_WOU BIT(2)
6026b703	198	#define ROUTER_CS_5_WOD BIT(3)
b0407983 MW	199	#define ROUTER_CS_5_C3S BIT(23)
b0407983 MW	200	#define ROUTER_CS_5_PTO BIT(24)
e6f81858	201	#define ROUTER_CS_5_UTO BIT(25)
b0407983 MW	202	#define ROUTER_CS_5_HCO BIT(26)
	203	#define ROUTER_CS_5_CV BIT(31)
	204	#define ROUTER_CS_6 0x06
	205	#define ROUTER_CS_6_SLPR BIT(0)
	206	#define ROUTER_CS_6_TNS BIT(1)
b2911a59 MW	207	#define ROUTER_CS_6_WOPS BIT(2)
b2911a59 MW	208	#define ROUTER_CS_6_WOUS BIT(3)
b0407983 MW	209	#define ROUTER_CS_6_HCI BIT(18)
	210	#define ROUTER_CS_6_CR BIT(25)
	211	#define ROUTER_CS_7 0x07
	212	#define ROUTER_CS_9 0x09
	213	#define ROUTER_CS_25 0x19
	214	#define ROUTER_CS_26 0x1a
661b1947	215	#define ROUTER_CS_26_OPCODE_MASK GENMASK(15, 0)
b0407983 MW	216	#define ROUTER_CS_26_STATUS_MASK GENMASK(29, 24)
	217	#define ROUTER_CS_26_STATUS_SHIFT 24
	218	#define ROUTER_CS_26_ONS BIT(30)
	219	#define ROUTER_CS_26_OV BIT(31)
	220
579f1421 MW	221	/* USB4 router operations opcodes */
	222	enum usb4_switch_op {
	223	USB4_SWITCH_OP_QUERY_DP_RESOURCE = 0x10,
	224	USB4_SWITCH_OP_ALLOC_DP_RESOURCE = 0x11,
	225	USB4_SWITCH_OP_DEALLOC_DP_RESOURCE = 0x12,
	226	USB4_SWITCH_OP_NVM_WRITE = 0x20,
	227	USB4_SWITCH_OP_NVM_AUTH = 0x21,
	228	USB4_SWITCH_OP_NVM_READ = 0x22,
	229	USB4_SWITCH_OP_NVM_SET_OFFSET = 0x23,
	230	USB4_SWITCH_OP_DROM_READ = 0x24,
	231	USB4_SWITCH_OP_NVM_SECTOR_SIZE = 0x25,
56ad3aef	232	USB4_SWITCH_OP_BUFFER_ALLOC = 0x33,
579f1421 MW	233	};
579f1421 MW	234
cf29b9af RM	235	/* Router TMU configuration */
cf29b9af RM	236	#define TMU_RTR_CS_0 0x00
b017a46d	237	#define TMU_RTR_CS_0_FREQ_WIND_MASK GENMASK(26, 16)
cf29b9af RM	238	#define TMU_RTR_CS_0_TD BIT(27)
	239	#define TMU_RTR_CS_0_UCAP BIT(30)
	240	#define TMU_RTR_CS_1 0x01
	241	#define TMU_RTR_CS_1_LOCAL_TIME_NS_MASK GENMASK(31, 16)
	242	#define TMU_RTR_CS_1_LOCAL_TIME_NS_SHIFT 16
	243	#define TMU_RTR_CS_2 0x02
	244	#define TMU_RTR_CS_3 0x03
	245	#define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK GENMASK(15, 0)
	246	#define TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK GENMASK(31, 16)
	247	#define TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT 16
b017a46d GF	248	#define TMU_RTR_CS_15 0xf
	249	#define TMU_RTR_CS_15_FREQ_AVG_MASK GENMASK(5, 0)
	250	#define TMU_RTR_CS_15_DELAY_AVG_MASK GENMASK(11, 6)
	251	#define TMU_RTR_CS_15_OFFSET_AVG_MASK GENMASK(17, 12)
	252	#define TMU_RTR_CS_15_ERROR_AVG_MASK GENMASK(23, 18)
cf29b9af RM	253	#define TMU_RTR_CS_22 0x16
cf29b9af RM	254	#define TMU_RTR_CS_24 0x18
a28ec0e1	255	#define TMU_RTR_CS_25 0x19
cf29b9af	256
7adf6097 AN	257	enum tb_port_type {
	258	TB_TYPE_INACTIVE = 0x000000,
	259	TB_TYPE_PORT = 0x000001,
	260	TB_TYPE_NHI = 0x000002,
	261	/* TB_TYPE_ETHERNET = 0x020000, lower order bits are not known */
	262	/* TB_TYPE_SATA = 0x080000, lower order bits are not known */
	263	TB_TYPE_DP_HDMI_IN = 0x0e0101,
	264	TB_TYPE_DP_HDMI_OUT = 0x0e0102,
	265	TB_TYPE_PCIE_DOWN = 0x100101,
	266	TB_TYPE_PCIE_UP = 0x100102,
e6f81858 RM	267	TB_TYPE_USB3_DOWN = 0x200101,
e6f81858 RM	268	TB_TYPE_USB3_UP = 0x200102,
7adf6097 AN	269	};
	270
	271	/* Present on every port in TB_CF_PORT at address zero. */
	272	struct tb_regs_port_header {
	273	/* DWORD 0 */
	274	u16 vendor_id;
	275	u16 device_id;
	276	/* DWORD 1 */
	277	u32 first_cap_offset:8;
	278	u32 max_counters:11;
54e41810 GF	279	u32 counters_support:1;
54e41810 GF	280	u32 __unknown1:4;
7adf6097 AN	281	u32 revision:8;
	282	/* DWORD 2 */
	283	enum tb_port_type type:24;
	284	u32 thunderbolt_version:8;
	285	/* DWORD 3 */
	286	u32 __unknown2:20;
	287	u32 port_number:6;
	288	u32 __unknown3:6;
	289	/* DWORD 4 */
	290	u32 nfc_credits;
	291	/* DWORD 5 */
	292	u32 max_in_hop_id:11;
	293	u32 max_out_hop_id:11;
c356915e	294	u32 __unknown4:10;
7adf6097 AN	295	/* DWORD 6 */
	296	u32 __unknown5;
	297	/* DWORD 7 */
	298	u32 __unknown6;
	299
	300	} __packed;
	301
8f57d478 MW	302	/* Basic adapter configuration registers */
	303	#define ADP_CS_4 0x04
	304	#define ADP_CS_4_NFC_BUFFERS_MASK GENMASK(9, 0)
	305	#define ADP_CS_4_TOTAL_BUFFERS_MASK GENMASK(29, 20)
	306	#define ADP_CS_4_TOTAL_BUFFERS_SHIFT 20
b0407983	307	#define ADP_CS_4_LCK BIT(31)
8f57d478 MW	308	#define ADP_CS_5 0x05
	309	#define ADP_CS_5_LCA_MASK GENMASK(28, 22)
	310	#define ADP_CS_5_LCA_SHIFT 22
4f807e47	311
cf29b9af RM	312	/* TMU adapter registers */
	313	#define TMU_ADP_CS_3 0x03
	314	#define TMU_ADP_CS_3_UDM BIT(29)
a28ec0e1 GF	315	#define TMU_ADP_CS_6 0x06
a28ec0e1 GF	316	#define TMU_ADP_CS_6_DTS BIT(1)
cf29b9af	317
91c0c120 MW	318	/* Lane adapter registers */
91c0c120 MW	319	#define LANE_ADP_CS_0 0x00
8e1de704 MW	320	#define LANE_ADP_CS_0_SUPPORTED_SPEED_MASK GENMASK(19, 16)
8e1de704 MW	321	#define LANE_ADP_CS_0_SUPPORTED_SPEED_SHIFT 16
91c0c120 MW	322	#define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK GENMASK(25, 20)
91c0c120 MW	323	#define LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT 20
8e1de704	324	#define LANE_ADP_CS_0_SUPPORTED_WIDTH_DUAL 0x2
8a90e4fa GF	325	#define LANE_ADP_CS_0_CL0S_SUPPORT BIT(26)
8a90e4fa GF	326	#define LANE_ADP_CS_0_CL1_SUPPORT BIT(27)
91c0c120	327	#define LANE_ADP_CS_1 0x01
8e1de704 MW	328	#define LANE_ADP_CS_1_TARGET_SPEED_MASK GENMASK(3, 0)
8e1de704 MW	329	#define LANE_ADP_CS_1_TARGET_SPEED_GEN3 0xc
91c0c120 MW	330	#define LANE_ADP_CS_1_TARGET_WIDTH_MASK GENMASK(9, 4)
	331	#define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT 4
	332	#define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE 0x1
	333	#define LANE_ADP_CS_1_TARGET_WIDTH_DUAL 0x3
8a90e4fa GF	334	#define LANE_ADP_CS_1_CL0S_ENABLE BIT(10)
8a90e4fa GF	335	#define LANE_ADP_CS_1_CL1_ENABLE BIT(11)
341d4518	336	#define LANE_ADP_CS_1_LD BIT(14)
91c0c120 MW	337	#define LANE_ADP_CS_1_LB BIT(15)
	338	#define LANE_ADP_CS_1_CURRENT_SPEED_MASK GENMASK(19, 16)
	339	#define LANE_ADP_CS_1_CURRENT_SPEED_SHIFT 16
	340	#define LANE_ADP_CS_1_CURRENT_SPEED_GEN2 0x8
	341	#define LANE_ADP_CS_1_CURRENT_SPEED_GEN3 0x4
	342	#define LANE_ADP_CS_1_CURRENT_WIDTH_MASK GENMASK(25, 20)
	343	#define LANE_ADP_CS_1_CURRENT_WIDTH_SHIFT 20
8a90e4fa	344	#define LANE_ADP_CS_1_PMS BIT(30)
91c0c120	345
b0407983	346	/* USB4 port registers */
02d12855 RM	347	#define PORT_CS_1 0x01
	348	#define PORT_CS_1_LENGTH_SHIFT 8
	349	#define PORT_CS_1_TARGET_MASK GENMASK(18, 16)
	350	#define PORT_CS_1_TARGET_SHIFT 16
	351	#define PORT_CS_1_RETIMER_INDEX_SHIFT 20
	352	#define PORT_CS_1_WNR_WRITE BIT(24)
	353	#define PORT_CS_1_NR BIT(25)
	354	#define PORT_CS_1_RC BIT(26)
	355	#define PORT_CS_1_PND BIT(31)
	356	#define PORT_CS_2 0x02
b0407983 MW	357	#define PORT_CS_18 0x12
b0407983 MW	358	#define PORT_CS_18_BE BIT(8)
bbcf40b3	359	#define PORT_CS_18_TCM BIT(9)
8a90e4fa	360	#define PORT_CS_18_CPS BIT(10)
b2911a59	361	#define PORT_CS_18_WOU4S BIT(18)
b0407983 MW	362	#define PORT_CS_19 0x13
b0407983 MW	363	#define PORT_CS_19_PC BIT(3)
284652a4	364	#define PORT_CS_19_PID BIT(4)
b2911a59 MW	365	#define PORT_CS_19_WOC BIT(16)
	366	#define PORT_CS_19_WOD BIT(17)
	367	#define PORT_CS_19_WOU4 BIT(18)
b0407983	368
4f807e47	369	/* Display Port adapter registers */
98176380 MW	370	#define ADP_DP_CS_0 0x00
	371	#define ADP_DP_CS_0_VIDEO_HOPID_MASK GENMASK(26, 16)
	372	#define ADP_DP_CS_0_VIDEO_HOPID_SHIFT 16
	373	#define ADP_DP_CS_0_AE BIT(30)
	374	#define ADP_DP_CS_0_VE BIT(31)
	375	#define ADP_DP_CS_1_AUX_TX_HOPID_MASK GENMASK(10, 0)
	376	#define ADP_DP_CS_1_AUX_RX_HOPID_MASK GENMASK(21, 11)
	377	#define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT 11
	378	#define ADP_DP_CS_2 0x02
	379	#define ADP_DP_CS_2_HDP BIT(6)
	380	#define ADP_DP_CS_3 0x03
	381	#define ADP_DP_CS_3_HDPC BIT(9)
	382	#define DP_LOCAL_CAP 0x04
	383	#define DP_REMOTE_CAP 0x05
de718ac7 MW	384	#define DP_STATUS_CTRL 0x06
	385	#define DP_STATUS_CTRL_CMHS BIT(25)
	386	#define DP_STATUS_CTRL_UF BIT(26)
a11b88ad MW	387	#define DP_COMMON_CAP 0x07
	388	/*
	389	* DP_COMMON_CAP offsets work also for DP_LOCAL_CAP and DP_REMOTE_CAP
	390	* with exception of DPRX done.
	391	*/
	392	#define DP_COMMON_CAP_RATE_MASK GENMASK(11, 8)
	393	#define DP_COMMON_CAP_RATE_SHIFT 8
	394	#define DP_COMMON_CAP_RATE_RBR 0x0
	395	#define DP_COMMON_CAP_RATE_HBR 0x1
	396	#define DP_COMMON_CAP_RATE_HBR2 0x2
	397	#define DP_COMMON_CAP_RATE_HBR3 0x3
	398	#define DP_COMMON_CAP_LANES_MASK GENMASK(14, 12)
	399	#define DP_COMMON_CAP_LANES_SHIFT 12
	400	#define DP_COMMON_CAP_1_LANE 0x0
	401	#define DP_COMMON_CAP_2_LANES 0x1
	402	#define DP_COMMON_CAP_4_LANES 0x2
3eddfc12	403	#define DP_COMMON_CAP_LTTPR_NS BIT(27)
a11b88ad	404	#define DP_COMMON_CAP_DPRX_DONE BIT(31)
c5ee6feb	405
93f36ade	406	/* PCIe adapter registers */
778bfca3 MW	407	#define ADP_PCIE_CS_0 0x00
778bfca3 MW	408	#define ADP_PCIE_CS_0_PE BIT(31)
93f36ade	409
e6f81858 RM	410	/* USB adapter registers */
	411	#define ADP_USB3_CS_0 0x00
	412	#define ADP_USB3_CS_0_V BIT(30)
	413	#define ADP_USB3_CS_0_PE BIT(31)
3b1d8d57 MW	414	#define ADP_USB3_CS_1 0x01
	415	#define ADP_USB3_CS_1_CUBW_MASK GENMASK(11, 0)
	416	#define ADP_USB3_CS_1_CDBW_MASK GENMASK(23, 12)
	417	#define ADP_USB3_CS_1_CDBW_SHIFT 12
	418	#define ADP_USB3_CS_1_HCA BIT(31)
	419	#define ADP_USB3_CS_2 0x02
	420	#define ADP_USB3_CS_2_AUBW_MASK GENMASK(11, 0)
	421	#define ADP_USB3_CS_2_ADBW_MASK GENMASK(23, 12)
	422	#define ADP_USB3_CS_2_ADBW_SHIFT 12
	423	#define ADP_USB3_CS_2_CMR BIT(31)
	424	#define ADP_USB3_CS_3 0x03
	425	#define ADP_USB3_CS_3_SCALE_MASK GENMASK(5, 0)
	426	#define ADP_USB3_CS_4 0x04
	427	#define ADP_USB3_CS_4_ALR_MASK GENMASK(6, 0)
	428	#define ADP_USB3_CS_4_ALR_20G 0x1
	429	#define ADP_USB3_CS_4_ULV BIT(7)
	430	#define ADP_USB3_CS_4_MSLR_MASK GENMASK(18, 12)
	431	#define ADP_USB3_CS_4_MSLR_SHIFT 12
	432	#define ADP_USB3_CS_4_MSLR_20G 0x1
e6f81858	433
7adf6097 AN	434	/* Hop register from TB_CFG_HOPS. 8 byte per entry. */
	435	struct tb_regs_hop {
	436	/* DWORD 0 */
	437	u32 next_hop:11; /*
	438	* hop to take after sending the packet through
	439	* out_port (on the incoming port of the next switch)
	440	*/
	441	u32 out_port:6; /* next port of the path (on the same switch) */
	442	u32 initial_credits:8;
	443	u32 unknown1:6; /* set to zero */
	444	bool enable:1;
	445
	446	/* DWORD 1 */
	447	u32 weight:4;
	448	u32 unknown2:4; /* set to zero */
	449	u32 priority:3;
	450	bool drop_packages:1;
	451	u32 counter:11; /* index into TB_CFG_COUNTERS on this port */
	452	bool counter_enable:1;
	453	bool ingress_fc:1;
	454	bool egress_fc:1;
	455	bool ingress_shared_buffer:1;
	456	bool egress_shared_buffer:1;
49442693 MW	457	bool pending:1;
49442693 MW	458	u32 unknown3:3; /* set to zero */
7adf6097 AN	459	} __packed;
7adf6097 AN	460
23ccd21c	461	/* TMU Thunderbolt 3 registers */
43f977bc GF	462	#define TB_TIME_VSEC_3_CS_9 0x9
	463	#define TB_TIME_VSEC_3_CS_9_TMU_OBJ_MASK GENMASK(17, 16)
	464	#define TB_TIME_VSEC_3_CS_26 0x1a
	465	#define TB_TIME_VSEC_3_CS_26_TD BIT(22)
	466
	467	/*
	468	* Used for Titan Ridge only. Bits are part of the same register: TMU_ADP_CS_6
	469	* (see above) as in USB4 spec, but these specific bits used for Titan Ridge
	470	* only and reserved in USB4 spec.
	471	*/
	472	#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_MASK GENMASK(3, 2)
	473	#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL1 BIT(2)
	474	#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL2 BIT(3)
	475
	476	/* Plug Events registers */
30a4eca6	477	#define TB_PLUG_EVENTS_USB_DISABLE BIT(2)
51d4d64c ML	478	#define TB_PLUG_EVENTS_CS_1_LANE_DISABLE BIT(3)
	479	#define TB_PLUG_EVENTS_CS_1_DPOUT_DISABLE BIT(4)
	480	#define TB_PLUG_EVENTS_CS_1_LOW_DPIN_DISABLE BIT(5)
	481	#define TB_PLUG_EVENTS_CS_1_HIGH_DPIN_DISABLE BIT(6)
30a4eca6	482
43f977bc GF	483	#define TB_PLUG_EVENTS_PCIE_WR_DATA 0x1b
	484	#define TB_PLUG_EVENTS_PCIE_CMD 0x1c
	485	#define TB_PLUG_EVENTS_PCIE_CMD_DW_OFFSET_MASK GENMASK(9, 0)
	486	#define TB_PLUG_EVENTS_PCIE_CMD_BR_SHIFT 10
	487	#define TB_PLUG_EVENTS_PCIE_CMD_BR_MASK GENMASK(17, 10)
	488	#define TB_PLUG_EVENTS_PCIE_CMD_RD_WR_MASK BIT(21)
	489	#define TB_PLUG_EVENTS_PCIE_CMD_WR 0x1
	490	#define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_SHIFT 22
	491	#define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_MASK GENMASK(24, 22)
	492	#define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_VAL 0x2
	493	#define TB_PLUG_EVENTS_PCIE_CMD_REQ_ACK_MASK BIT(30)
	494	#define TB_PLUG_EVENTS_PCIE_CMD_TIMEOUT_MASK BIT(31)
	495	#define TB_PLUG_EVENTS_PCIE_CMD_RD_DATA 0x1d
	496
	497	/* CP Low Power registers */
	498	#define TB_LOW_PWR_C1_CL1 0x1
	499	#define TB_LOW_PWR_C1_CL1_OBJ_MASK GENMASK(4, 1)
	500	#define TB_LOW_PWR_C1_CL2_OBJ_MASK GENMASK(4, 1)
	501	#define TB_LOW_PWR_C1_PORT_A_MASK GENMASK(2, 1)
	502	#define TB_LOW_PWR_C0_PORT_B_MASK GENMASK(4, 3)
	503	#define TB_LOW_PWR_C3_CL1 0x3
23ccd21c	504
a9be5582	505	/* Common link controller registers */
43f977bc GF	506	#define TB_LC_DESC 0x02
	507	#define TB_LC_DESC_NLC_MASK GENMASK(3, 0)
	508	#define TB_LC_DESC_SIZE_SHIFT 8
	509	#define TB_LC_DESC_SIZE_MASK GENMASK(15, 8)
	510	#define TB_LC_DESC_PORT_SIZE_SHIFT 16
	511	#define TB_LC_DESC_PORT_SIZE_MASK GENMASK(27, 16)
	512	#define TB_LC_FUSE 0x03
	513	#define TB_LC_SNK_ALLOCATION 0x10
	514	#define TB_LC_SNK_ALLOCATION_SNK0_MASK GENMASK(3, 0)
	515	#define TB_LC_SNK_ALLOCATION_SNK0_CM 0x1
	516	#define TB_LC_SNK_ALLOCATION_SNK1_SHIFT 4
	517	#define TB_LC_SNK_ALLOCATION_SNK1_MASK GENMASK(7, 4)
	518	#define TB_LC_SNK_ALLOCATION_SNK1_CM 0x1
	519	#define TB_LC_POWER 0x740
7adf6097	520
e879a709	521	/* Link controller registers */
30a4eca6 MW	522	#define TB_LC_CS_42 0x2a
	523	#define TB_LC_CS_42_USB_PLUGGED BIT(31)
	524
43f977bc GF	525	#define TB_LC_PORT_ATTR 0x8d
	526	#define TB_LC_PORT_ATTR_BE BIT(12)
	527
	528	#define TB_LC_SX_CTRL 0x96
	529	#define TB_LC_SX_CTRL_WOC BIT(1)
	530	#define TB_LC_SX_CTRL_WOD BIT(2)
	531	#define TB_LC_SX_CTRL_WODPC BIT(3)
	532	#define TB_LC_SX_CTRL_WODPD BIT(4)
	533	#define TB_LC_SX_CTRL_WOU4 BIT(5)
	534	#define TB_LC_SX_CTRL_WOP BIT(6)
	535	#define TB_LC_SX_CTRL_L1C BIT(16)
	536	#define TB_LC_SX_CTRL_L1D BIT(17)
	537	#define TB_LC_SX_CTRL_L2C BIT(20)
	538	#define TB_LC_SX_CTRL_L2D BIT(21)
	539	#define TB_LC_SX_CTRL_SLI BIT(29)
	540	#define TB_LC_SX_CTRL_UPSTREAM BIT(30)
	541	#define TB_LC_SX_CTRL_SLP BIT(31)
	542	#define TB_LC_LINK_ATTR 0x97
	543	#define TB_LC_LINK_ATTR_CPS BIT(18)
e879a709	544
30a4eca6 MW	545	#define TB_LC_LINK_REQ 0xad
	546	#define TB_LC_LINK_REQ_XHCI_CONNECT BIT(31)
	547
7adf6097	548	#endif