[linux-2.6-block.git] / drivers / thunderbolt / sb_regs.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * USB4 port sideband registers found on routers and retimers
 *
 * Copyright (C) 2020, Intel Corporation
 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
 *	    Rajmohan Mani <rajmohan.mani@intel.com>
 */

#ifndef _SB_REGS
#define _SB_REGS

#define USB4_SB_VENDOR_ID			0x00
#define USB4_SB_PRODUCT_ID			0x01
#define USB4_SB_FW_VERSION			0x02
#define USB4_SB_DEBUG_CONF			0x05
#define USB4_SB_DEBUG				0x06
#define USB4_SB_LRD_TUNING			0x07
#define USB4_SB_OPCODE				0x08

enum usb4_sb_opcode {
	USB4_SB_OPCODE_ERR = 0x20525245,			/* "ERR " */
	USB4_SB_OPCODE_ONS = 0x444d4321,			/* "!CMD" */
	USB4_SB_OPCODE_ROUTER_OFFLINE = 0x4e45534c,		/* "LSEN" */
	USB4_SB_OPCODE_ENUMERATE_RETIMERS = 0x4d554e45,		/* "ENUM" */
	USB4_SB_OPCODE_SET_INBOUND_SBTX = 0x5055534c,		/* "LSUP" */
	USB4_SB_OPCODE_UNSET_INBOUND_SBTX = 0x50555355,		/* "USUP" */
	USB4_SB_OPCODE_QUERY_LAST_RETIMER = 0x5453414c,		/* "LAST" */
	USB4_SB_OPCODE_QUERY_CABLE_RETIMER = 0x524c4243,	/* "CBLR" */
	USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE = 0x53534e47,	/* "GNSS" */
	USB4_SB_OPCODE_NVM_SET_OFFSET = 0x53504f42,		/* "BOPS" */
	USB4_SB_OPCODE_NVM_BLOCK_WRITE = 0x574b4c42,		/* "BLKW" */
	USB4_SB_OPCODE_NVM_AUTH_WRITE = 0x48545541,		/* "AUTH" */
	USB4_SB_OPCODE_NVM_READ = 0x52524641,			/* "AFRR" */
	USB4_SB_OPCODE_READ_LANE_MARGINING_CAP = 0x50434452,	/* "RDCP" */
	USB4_SB_OPCODE_RUN_HW_LANE_MARGINING = 0x474d4852,	/* "RHMG" */
	USB4_SB_OPCODE_RUN_SW_LANE_MARGINING = 0x474d5352,	/* "RSMG" */
	USB4_SB_OPCODE_READ_SW_MARGIN_ERR = 0x57534452,		/* "RDSW" */
};

#define USB4_SB_METADATA			0x09
#define USB4_SB_METADATA_NVM_AUTH_WRITE_MASK	GENMASK(5, 0)
#define USB4_SB_LINK_CONF			0x0c
#define USB4_SB_GEN23_TXFFE			0x0d
#define USB4_SB_GEN4_TXFFE			0x0e
#define USB4_SB_VERSION				0x0f
#define USB4_SB_DATA				0x12

/* USB4_SB_OPCODE_READ_LANE_MARGINING_CAP */
#define USB4_MARGIN_CAP_0_MODES_HW		BIT(0)
#define USB4_MARGIN_CAP_0_MODES_SW		BIT(1)
#define USB4_MARGIN_CAP_0_2_LANES		BIT(2)
#define USB4_MARGIN_CAP_0_VOLTAGE_INDP_MASK	GENMASK(4, 3)
#define USB4_MARGIN_CAP_0_VOLTAGE_MIN		0x0
#define USB4_MARGIN_CAP_0_VOLTAGE_HL		0x1
#define USB4_MARGIN_CAP_0_VOLTAGE_BOTH		0x2
#define USB4_MARGIN_CAP_0_TIME			BIT(5)
#define USB4_MARGIN_CAP_0_VOLTAGE_STEPS_MASK	GENMASK(12, 6)
#define USB4_MARGIN_CAP_0_MAX_VOLTAGE_OFFSET_MASK GENMASK(18, 13)
#define USB4_MARGIN_CAP_0_OPT_VOLTAGE_SUPPORT	BIT(19)
#define USB4_MARGIN_CAP_0_VOLT_STEPS_OPT_MASK	GENMASK(26, 20)
#define USB4_MARGIN_CAP_1_MAX_VOLT_OFS_OPT_MASK GENMASK(7, 0)
#define USB4_MARGIN_CAP_1_TIME_DESTR		BIT(8)
#define USB4_MARGIN_CAP_1_TIME_INDP_MASK	GENMASK(10, 9)
#define USB4_MARGIN_CAP_1_TIME_MIN		0x0
#define USB4_MARGIN_CAP_1_TIME_LR		0x1
#define USB4_MARGIN_CAP_1_TIME_BOTH		0x2
#define USB4_MARGIN_CAP_1_TIME_STEPS_MASK	GENMASK(15, 11)
#define USB4_MARGIN_CAP_1_TIME_OFFSET_MASK	GENMASK(20, 16)
#define USB4_MARGIN_CAP_1_MIN_BER_MASK		GENMASK(25, 21)
#define USB4_MARGIN_CAP_1_MAX_BER_MASK		GENMASK(30, 26)

/* USB4_SB_OPCODE_RUN_HW_LANE_MARGINING */
#define USB4_MARGIN_HW_TIME			BIT(3)
#define USB4_MARGIN_HW_RH			BIT(4)
#define USB4_MARGIN_HW_BER_MASK			GENMASK(9, 5)
#define USB4_MARGIN_HW_BER_SHIFT		5
#define USB4_MARGIN_HW_OPT_VOLTAGE		BIT(10)

/* Applicable to all margin values */
#define USB4_MARGIN_HW_RES_1_MARGIN_MASK	GENMASK(6, 0)
#define USB4_MARGIN_HW_RES_1_EXCEEDS		BIT(7)
/* Different lane margin shifts */
#define USB4_MARGIN_HW_RES_1_L0_LL_MARGIN_SHIFT	8
#define USB4_MARGIN_HW_RES_1_L1_RH_MARGIN_SHIFT	16
#define USB4_MARGIN_HW_RES_1_L1_LL_MARGIN_SHIFT	24

/* USB4_SB_OPCODE_RUN_SW_LANE_MARGINING */
#define USB4_MARGIN_SW_LANES_MASK		GENMASK(2, 0)
#define USB4_MARGIN_SW_LANE_0			0x0
#define USB4_MARGIN_SW_LANE_1			0x1
#define USB4_MARGIN_SW_ALL_LANES		0x7
#define USB4_MARGIN_SW_TIME			BIT(3)
#define USB4_MARGIN_SW_RH			BIT(4)
#define USB4_MARGIN_SW_OPT_VOLTAGE		BIT(5)
#define USB4_MARGIN_SW_VT_MASK			GENMASK(12, 6)
#define USB4_MARGIN_SW_COUNTER_MASK		GENMASK(14, 13)

#define USB4_MARGIN_SW_ERR_COUNTER_LANE_0_MASK	GENMASK(3, 0)
#define USB4_MARGIN_SW_ERR_COUNTER_LANE_1_MASK	GENMASK(7, 4)

#endif
Commit	Line	Data
02d12855 RM	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* USB4 port sideband registers found on routers and retimers
	4	*
	5	* Copyright (C) 2020, Intel Corporation
	6	* Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
	7	* Rajmohan Mani <rajmohan.mani@intel.com>
	8	*/
	9
	10	#ifndef _SB_REGS
	11	#define _SB_REGS
	12
dacb1287 KK	13	#define USB4_SB_VENDOR_ID 0x00
dacb1287 KK	14	#define USB4_SB_PRODUCT_ID 0x01
6d241fa0 MW	15	#define USB4_SB_FW_VERSION 0x02
	16	#define USB4_SB_DEBUG_CONF 0x05
	17	#define USB4_SB_DEBUG 0x06
	18	#define USB4_SB_LRD_TUNING 0x07
02d12855 RM	19	#define USB4_SB_OPCODE 0x08
	20
	21	enum usb4_sb_opcode {
	22	USB4_SB_OPCODE_ERR = 0x20525245, /* "ERR " */
	23	USB4_SB_OPCODE_ONS = 0x444d4321, /* "!CMD" */
3406de7c	24	USB4_SB_OPCODE_ROUTER_OFFLINE = 0x4e45534c, /* "LSEN" */
02d12855	25	USB4_SB_OPCODE_ENUMERATE_RETIMERS = 0x4d554e45, /* "ENUM" */
3406de7c	26	USB4_SB_OPCODE_SET_INBOUND_SBTX = 0x5055534c, /* "LSUP" */
cd0c1e58	27	USB4_SB_OPCODE_UNSET_INBOUND_SBTX = 0x50555355, /* "USUP" */
02d12855	28	USB4_SB_OPCODE_QUERY_LAST_RETIMER = 0x5453414c, /* "LAST" */
ff6ab055	29	USB4_SB_OPCODE_QUERY_CABLE_RETIMER = 0x524c4243, /* "CBLR" */
02d12855 RM	30	USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE = 0x53534e47, /* "GNSS" */
	31	USB4_SB_OPCODE_NVM_SET_OFFSET = 0x53504f42, /* "BOPS" */
	32	USB4_SB_OPCODE_NVM_BLOCK_WRITE = 0x574b4c42, /* "BLKW" */
	33	USB4_SB_OPCODE_NVM_AUTH_WRITE = 0x48545541, /* "AUTH" */
	34	USB4_SB_OPCODE_NVM_READ = 0x52524641, /* "AFRR" */
d0f1e0c2 MW	35	USB4_SB_OPCODE_READ_LANE_MARGINING_CAP = 0x50434452, /* "RDCP" */
	36	USB4_SB_OPCODE_RUN_HW_LANE_MARGINING = 0x474d4852, /* "RHMG" */
	37	USB4_SB_OPCODE_RUN_SW_LANE_MARGINING = 0x474d5352, /* "RSMG" */
	38	USB4_SB_OPCODE_READ_SW_MARGIN_ERR = 0x57534452, /* "RDSW" */
02d12855 RM	39	};
	40
	41	#define USB4_SB_METADATA 0x09
	42	#define USB4_SB_METADATA_NVM_AUTH_WRITE_MASK GENMASK(5, 0)
6d241fa0 MW	43	#define USB4_SB_LINK_CONF 0x0c
	44	#define USB4_SB_GEN23_TXFFE 0x0d
	45	#define USB4_SB_GEN4_TXFFE 0x0e
	46	#define USB4_SB_VERSION 0x0f
02d12855 RM	47	#define USB4_SB_DATA 0x12
02d12855 RM	48
d0f1e0c2 MW	49	/* USB4_SB_OPCODE_READ_LANE_MARGINING_CAP */
	50	#define USB4_MARGIN_CAP_0_MODES_HW BIT(0)
	51	#define USB4_MARGIN_CAP_0_MODES_SW BIT(1)
	52	#define USB4_MARGIN_CAP_0_2_LANES BIT(2)
	53	#define USB4_MARGIN_CAP_0_VOLTAGE_INDP_MASK GENMASK(4, 3)
d0f1e0c2 MW	54	#define USB4_MARGIN_CAP_0_VOLTAGE_MIN 0x0
	55	#define USB4_MARGIN_CAP_0_VOLTAGE_HL 0x1
	56	#define USB4_MARGIN_CAP_0_VOLTAGE_BOTH 0x2
	57	#define USB4_MARGIN_CAP_0_TIME BIT(5)
	58	#define USB4_MARGIN_CAP_0_VOLTAGE_STEPS_MASK GENMASK(12, 6)
d0f1e0c2	59	#define USB4_MARGIN_CAP_0_MAX_VOLTAGE_OFFSET_MASK GENMASK(18, 13)
9fafd46b RS	60	#define USB4_MARGIN_CAP_0_OPT_VOLTAGE_SUPPORT BIT(19)
	61	#define USB4_MARGIN_CAP_0_VOLT_STEPS_OPT_MASK GENMASK(26, 20)
	62	#define USB4_MARGIN_CAP_1_MAX_VOLT_OFS_OPT_MASK GENMASK(7, 0)
d0f1e0c2 MW	63	#define USB4_MARGIN_CAP_1_TIME_DESTR BIT(8)
d0f1e0c2 MW	64	#define USB4_MARGIN_CAP_1_TIME_INDP_MASK GENMASK(10, 9)
d0f1e0c2 MW	65	#define USB4_MARGIN_CAP_1_TIME_MIN 0x0
	66	#define USB4_MARGIN_CAP_1_TIME_LR 0x1
	67	#define USB4_MARGIN_CAP_1_TIME_BOTH 0x2
	68	#define USB4_MARGIN_CAP_1_TIME_STEPS_MASK GENMASK(15, 11)
d0f1e0c2	69	#define USB4_MARGIN_CAP_1_TIME_OFFSET_MASK GENMASK(20, 16)
d0f1e0c2	70	#define USB4_MARGIN_CAP_1_MIN_BER_MASK GENMASK(25, 21)
d0f1e0c2	71	#define USB4_MARGIN_CAP_1_MAX_BER_MASK GENMASK(30, 26)
d0f1e0c2 MW	72
	73	/* USB4_SB_OPCODE_RUN_HW_LANE_MARGINING */
	74	#define USB4_MARGIN_HW_TIME BIT(3)
	75	#define USB4_MARGIN_HW_RH BIT(4)
	76	#define USB4_MARGIN_HW_BER_MASK GENMASK(9, 5)
	77	#define USB4_MARGIN_HW_BER_SHIFT 5
9fafd46b	78	#define USB4_MARGIN_HW_OPT_VOLTAGE BIT(10)
d0f1e0c2 MW	79
	80	/* Applicable to all margin values */
	81	#define USB4_MARGIN_HW_RES_1_MARGIN_MASK GENMASK(6, 0)
	82	#define USB4_MARGIN_HW_RES_1_EXCEEDS BIT(7)
	83	/* Different lane margin shifts */
	84	#define USB4_MARGIN_HW_RES_1_L0_LL_MARGIN_SHIFT 8
	85	#define USB4_MARGIN_HW_RES_1_L1_RH_MARGIN_SHIFT 16
	86	#define USB4_MARGIN_HW_RES_1_L1_LL_MARGIN_SHIFT 24
	87
	88	/* USB4_SB_OPCODE_RUN_SW_LANE_MARGINING */
10904df3 K	89	#define USB4_MARGIN_SW_LANES_MASK GENMASK(2, 0)
	90	#define USB4_MARGIN_SW_LANE_0 0x0
	91	#define USB4_MARGIN_SW_LANE_1 0x1
	92	#define USB4_MARGIN_SW_ALL_LANES 0x7
d0f1e0c2 MW	93	#define USB4_MARGIN_SW_TIME BIT(3)
d0f1e0c2 MW	94	#define USB4_MARGIN_SW_RH BIT(4)
9fafd46b	95	#define USB4_MARGIN_SW_OPT_VOLTAGE BIT(5)
10904df3	96	#define USB4_MARGIN_SW_VT_MASK GENMASK(12, 6)
d0f1e0c2	97	#define USB4_MARGIN_SW_COUNTER_MASK GENMASK(14, 13)
d0f1e0c2	98
10904df3 K	99	#define USB4_MARGIN_SW_ERR_COUNTER_LANE_0_MASK GENMASK(3, 0)
	100	#define USB4_MARGIN_SW_ERR_COUNTER_LANE_1_MASK GENMASK(7, 4)
	101
02d12855	102	#endif