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02d12855 RM |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * USB4 port sideband registers found on routers and retimers | |
4 | * | |
5 | * Copyright (C) 2020, Intel Corporation | |
6 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> | |
7 | * Rajmohan Mani <rajmohan.mani@intel.com> | |
8 | */ | |
9 | ||
10 | #ifndef _SB_REGS | |
11 | #define _SB_REGS | |
12 | ||
dacb1287 KK |
13 | #define USB4_SB_VENDOR_ID 0x00 |
14 | #define USB4_SB_PRODUCT_ID 0x01 | |
02d12855 RM |
15 | #define USB4_SB_OPCODE 0x08 |
16 | ||
17 | enum usb4_sb_opcode { | |
18 | USB4_SB_OPCODE_ERR = 0x20525245, /* "ERR " */ | |
19 | USB4_SB_OPCODE_ONS = 0x444d4321, /* "!CMD" */ | |
3406de7c | 20 | USB4_SB_OPCODE_ROUTER_OFFLINE = 0x4e45534c, /* "LSEN" */ |
02d12855 | 21 | USB4_SB_OPCODE_ENUMERATE_RETIMERS = 0x4d554e45, /* "ENUM" */ |
3406de7c | 22 | USB4_SB_OPCODE_SET_INBOUND_SBTX = 0x5055534c, /* "LSUP" */ |
cd0c1e58 | 23 | USB4_SB_OPCODE_UNSET_INBOUND_SBTX = 0x50555355, /* "USUP" */ |
02d12855 RM |
24 | USB4_SB_OPCODE_QUERY_LAST_RETIMER = 0x5453414c, /* "LAST" */ |
25 | USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE = 0x53534e47, /* "GNSS" */ | |
26 | USB4_SB_OPCODE_NVM_SET_OFFSET = 0x53504f42, /* "BOPS" */ | |
27 | USB4_SB_OPCODE_NVM_BLOCK_WRITE = 0x574b4c42, /* "BLKW" */ | |
28 | USB4_SB_OPCODE_NVM_AUTH_WRITE = 0x48545541, /* "AUTH" */ | |
29 | USB4_SB_OPCODE_NVM_READ = 0x52524641, /* "AFRR" */ | |
d0f1e0c2 MW |
30 | USB4_SB_OPCODE_READ_LANE_MARGINING_CAP = 0x50434452, /* "RDCP" */ |
31 | USB4_SB_OPCODE_RUN_HW_LANE_MARGINING = 0x474d4852, /* "RHMG" */ | |
32 | USB4_SB_OPCODE_RUN_SW_LANE_MARGINING = 0x474d5352, /* "RSMG" */ | |
33 | USB4_SB_OPCODE_READ_SW_MARGIN_ERR = 0x57534452, /* "RDSW" */ | |
02d12855 RM |
34 | }; |
35 | ||
36 | #define USB4_SB_METADATA 0x09 | |
37 | #define USB4_SB_METADATA_NVM_AUTH_WRITE_MASK GENMASK(5, 0) | |
38 | #define USB4_SB_DATA 0x12 | |
39 | ||
d0f1e0c2 MW |
40 | /* USB4_SB_OPCODE_READ_LANE_MARGINING_CAP */ |
41 | #define USB4_MARGIN_CAP_0_MODES_HW BIT(0) | |
42 | #define USB4_MARGIN_CAP_0_MODES_SW BIT(1) | |
43 | #define USB4_MARGIN_CAP_0_2_LANES BIT(2) | |
44 | #define USB4_MARGIN_CAP_0_VOLTAGE_INDP_MASK GENMASK(4, 3) | |
45 | #define USB4_MARGIN_CAP_0_VOLTAGE_INDP_SHIFT 3 | |
46 | #define USB4_MARGIN_CAP_0_VOLTAGE_MIN 0x0 | |
47 | #define USB4_MARGIN_CAP_0_VOLTAGE_HL 0x1 | |
48 | #define USB4_MARGIN_CAP_0_VOLTAGE_BOTH 0x2 | |
49 | #define USB4_MARGIN_CAP_0_TIME BIT(5) | |
50 | #define USB4_MARGIN_CAP_0_VOLTAGE_STEPS_MASK GENMASK(12, 6) | |
51 | #define USB4_MARGIN_CAP_0_VOLTAGE_STEPS_SHIFT 6 | |
52 | #define USB4_MARGIN_CAP_0_MAX_VOLTAGE_OFFSET_MASK GENMASK(18, 13) | |
53 | #define USB4_MARGIN_CAP_0_MAX_VOLTAGE_OFFSET_SHIFT 13 | |
54 | #define USB4_MARGIN_CAP_1_TIME_DESTR BIT(8) | |
55 | #define USB4_MARGIN_CAP_1_TIME_INDP_MASK GENMASK(10, 9) | |
56 | #define USB4_MARGIN_CAP_1_TIME_INDP_SHIFT 9 | |
57 | #define USB4_MARGIN_CAP_1_TIME_MIN 0x0 | |
58 | #define USB4_MARGIN_CAP_1_TIME_LR 0x1 | |
59 | #define USB4_MARGIN_CAP_1_TIME_BOTH 0x2 | |
60 | #define USB4_MARGIN_CAP_1_TIME_STEPS_MASK GENMASK(15, 11) | |
61 | #define USB4_MARGIN_CAP_1_TIME_STEPS_SHIFT 11 | |
62 | #define USB4_MARGIN_CAP_1_TIME_OFFSET_MASK GENMASK(20, 16) | |
63 | #define USB4_MARGIN_CAP_1_TIME_OFFSET_SHIFT 16 | |
64 | #define USB4_MARGIN_CAP_1_MIN_BER_MASK GENMASK(25, 21) | |
65 | #define USB4_MARGIN_CAP_1_MIN_BER_SHIFT 21 | |
66 | #define USB4_MARGIN_CAP_1_MAX_BER_MASK GENMASK(30, 26) | |
67 | #define USB4_MARGIN_CAP_1_MAX_BER_SHIFT 26 | |
68 | #define USB4_MARGIN_CAP_1_MAX_BER_SHIFT 26 | |
69 | ||
70 | /* USB4_SB_OPCODE_RUN_HW_LANE_MARGINING */ | |
71 | #define USB4_MARGIN_HW_TIME BIT(3) | |
72 | #define USB4_MARGIN_HW_RH BIT(4) | |
73 | #define USB4_MARGIN_HW_BER_MASK GENMASK(9, 5) | |
74 | #define USB4_MARGIN_HW_BER_SHIFT 5 | |
75 | ||
76 | /* Applicable to all margin values */ | |
77 | #define USB4_MARGIN_HW_RES_1_MARGIN_MASK GENMASK(6, 0) | |
78 | #define USB4_MARGIN_HW_RES_1_EXCEEDS BIT(7) | |
79 | /* Different lane margin shifts */ | |
80 | #define USB4_MARGIN_HW_RES_1_L0_LL_MARGIN_SHIFT 8 | |
81 | #define USB4_MARGIN_HW_RES_1_L1_RH_MARGIN_SHIFT 16 | |
82 | #define USB4_MARGIN_HW_RES_1_L1_LL_MARGIN_SHIFT 24 | |
83 | ||
84 | /* USB4_SB_OPCODE_RUN_SW_LANE_MARGINING */ | |
85 | #define USB4_MARGIN_SW_TIME BIT(3) | |
86 | #define USB4_MARGIN_SW_RH BIT(4) | |
87 | #define USB4_MARGIN_SW_COUNTER_MASK GENMASK(14, 13) | |
88 | #define USB4_MARGIN_SW_COUNTER_SHIFT 13 | |
89 | #define USB4_MARGIN_SW_COUNTER_NOP 0x0 | |
90 | #define USB4_MARGIN_SW_COUNTER_CLEAR 0x1 | |
91 | #define USB4_MARGIN_SW_COUNTER_START 0x2 | |
92 | #define USB4_MARGIN_SW_COUNTER_STOP 0x3 | |
93 | ||
02d12855 | 94 | #endif |