[linux-2.6-block.git] / drivers / thunderbolt / nhi_regs.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Thunderbolt driver - NHI registers
 *
 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
 * Copyright (C) 2018, Intel Corporation
 */

#ifndef NHI_REGS_H_
#define NHI_REGS_H_

#include <linux/types.h>

enum ring_flags {
	RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */
	RING_FLAG_E2E_FLOW_CONTROL = 1 << 28,
	RING_FLAG_PCI_NO_SNOOP = 1 << 29,
	RING_FLAG_RAW = 1 << 30, /* ignore EOF/SOF mask, include checksum */
	RING_FLAG_ENABLE = 1 << 31,
};

/**
 * struct ring_desc - TX/RX ring entry
 *
 * For TX set length/eof/sof.
 * For RX length/eof/sof are set by the NHI.
 */
struct ring_desc {
	u64 phys;
	u32 length:12;
	u32 eof:4;
	u32 sof:4;
	enum ring_desc_flags flags:12;
	u32 time; /* write zero */
} __packed;

/* NHI registers in bar 0 */

/*
 * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
 * 00: physical pointer to an array of struct ring_desc
 * 08: ring tail (set by NHI)
 * 10: ring head (index of first non posted descriptor)
 * 12: descriptor count
 */
#define REG_TX_RING_BASE	0x00000

/*
 * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
 * 00: physical pointer to an array of struct ring_desc
 * 08: ring head (index of first not posted descriptor)
 * 10: ring tail (set by NHI)
 * 12: descriptor count
 * 14: max frame sizes (anything larger than 0x100 has no effect)
 */
#define REG_RX_RING_BASE	0x08000

/*
 * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
 * 00: enum_ring_flags
 * 04: isoch time stamp ?? (write 0)
 * ..: unknown
 */
#define REG_TX_OPTIONS_BASE	0x19800

/*
 * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
 * 00: enum ring_flags
 *     If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to
 *     the corresponding TX hop id.
 * 04: EOF/SOF mask (ignored for RING_FLAG_RAW rings)
 * ..: unknown
 */
#define REG_RX_OPTIONS_BASE	0x29800
#define REG_RX_OPTIONS_E2E_HOP_MASK	GENMASK(22, 12)
#define REG_RX_OPTIONS_E2E_HOP_SHIFT	12

/*
 * three bitfields: tx, rx, rx overflow
 * Every bitfield contains one bit for every hop (REG_HOP_COUNT). Registers are
 * cleared on read. New interrupts are fired only after ALL registers have been
 * read (even those containing only disabled rings).
 */
#define REG_RING_NOTIFY_BASE	0x37800
#define RING_NOTIFY_REG_COUNT(nhi) ((31 + 3 * nhi->hop_count) / 32)

/*
 * two bitfields: rx, tx
 * Both bitfields contains one bit for every hop (REG_HOP_COUNT). To
 * enable/disable interrupts set/clear the corresponding bits.
 */
#define REG_RING_INTERRUPT_BASE	0x38200
#define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32)

#define REG_INT_THROTTLING_RATE	0x38c00

/* Interrupt Vector Allocation */
#define REG_INT_VEC_ALLOC_BASE	0x38c40
#define REG_INT_VEC_ALLOC_BITS	4
#define REG_INT_VEC_ALLOC_MASK	GENMASK(3, 0)
#define REG_INT_VEC_ALLOC_REGS	(32 / REG_INT_VEC_ALLOC_BITS)

/* The last 11 bits contain the number of hops supported by the NHI port. */
#define REG_HOP_COUNT		0x39640

#define REG_DMA_MISC			0x39864
#define REG_DMA_MISC_INT_AUTO_CLEAR     BIT(2)

#define REG_INMAIL_DATA			0x39900

#define REG_INMAIL_CMD			0x39904
#define REG_INMAIL_CMD_MASK		GENMASK(7, 0)
#define REG_INMAIL_ERROR		BIT(30)
#define REG_INMAIL_OP_REQUEST		BIT(31)

#define REG_OUTMAIL_CMD			0x3990c
#define REG_OUTMAIL_CMD_OPMODE_SHIFT	8
#define REG_OUTMAIL_CMD_OPMODE_MASK	GENMASK(11, 8)

#define REG_FW_STS			0x39944
#define REG_FW_STS_NVM_AUTH_DONE	BIT(31)
#define REG_FW_STS_CIO_RESET_REQ	BIT(30)
#define REG_FW_STS_ICM_EN_CPU		BIT(2)
#define REG_FW_STS_ICM_EN_INVERT	BIT(1)
#define REG_FW_STS_ICM_EN		BIT(0)

#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
16603153	2	/*
fe948dcb	3	* Thunderbolt driver - NHI registers
16603153 AN	4	*
16603153 AN	5	* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
15c6784c	6	* Copyright (C) 2018, Intel Corporation
16603153 AN	7	*/
16603153 AN	8
fe948dcb AL	9	#ifndef NHI_REGS_H_
fe948dcb AL	10	#define NHI_REGS_H_
16603153 AN	11
	12	#include <linux/types.h>
	13
	14	enum ring_flags {
	15	RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */
	16	RING_FLAG_E2E_FLOW_CONTROL = 1 << 28,
	17	RING_FLAG_PCI_NO_SNOOP = 1 << 29,
	18	RING_FLAG_RAW = 1 << 30, /* ignore EOF/SOF mask, include checksum */
	19	RING_FLAG_ENABLE = 1 << 31,
	20	};
	21
16603153 AN	22	/**
	23	* struct ring_desc - TX/RX ring entry
	24	*
	25	* For TX set length/eof/sof.
	26	* For RX length/eof/sof are set by the NHI.
	27	*/
	28	struct ring_desc {
	29	u64 phys;
	30	u32 length:12;
	31	u32 eof:4;
	32	u32 sof:4;
	33	enum ring_desc_flags flags:12;
	34	u32 time; /* write zero */
	35	} __packed;
	36
	37	/* NHI registers in bar 0 */
	38
	39	/*
	40	* 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
	41	* 00: physical pointer to an array of struct ring_desc
	42	* 08: ring tail (set by NHI)
	43	* 10: ring head (index of first non posted descriptor)
	44	* 12: descriptor count
	45	*/
	46	#define REG_TX_RING_BASE 0x00000
	47
	48	/*
	49	* 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
	50	* 00: physical pointer to an array of struct ring_desc
	51	* 08: ring head (index of first not posted descriptor)
	52	* 10: ring tail (set by NHI)
	53	* 12: descriptor count
	54	* 14: max frame sizes (anything larger than 0x100 has no effect)
	55	*/
	56	#define REG_RX_RING_BASE 0x08000
	57
	58	/*
	59	* 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
	60	* 00: enum_ring_flags
	61	* 04: isoch time stamp ?? (write 0)
	62	* ..: unknown
	63	*/
	64	#define REG_TX_OPTIONS_BASE 0x19800
	65
	66	/*
	67	* 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
	68	* 00: enum ring_flags
	69	* If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to
	70	* the corresponding TX hop id.
	71	* 04: EOF/SOF mask (ignored for RING_FLAG_RAW rings)
	72	* ..: unknown
	73	*/
	74	#define REG_RX_OPTIONS_BASE 0x29800
9fb1e654 MW	75	#define REG_RX_OPTIONS_E2E_HOP_MASK GENMASK(22, 12)
9fb1e654 MW	76	#define REG_RX_OPTIONS_E2E_HOP_SHIFT 12
16603153 AN	77
	78	/*
	79	* three bitfields: tx, rx, rx overflow
	80	* Every bitfield contains one bit for every hop (REG_HOP_COUNT). Registers are
	81	* cleared on read. New interrupts are fired only after ALL registers have been
	82	* read (even those containing only disabled rings).
	83	*/
	84	#define REG_RING_NOTIFY_BASE 0x37800
	85	#define RING_NOTIFY_REG_COUNT(nhi) ((31 + 3 * nhi->hop_count) / 32)
	86
	87	/*
	88	* two bitfields: rx, tx
	89	* Both bitfields contains one bit for every hop (REG_HOP_COUNT). To
	90	* enable/disable interrupts set/clear the corresponding bits.
	91	*/
	92	#define REG_RING_INTERRUPT_BASE 0x38200
	93	#define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32)
	94
8c6bba10 MW	95	#define REG_INT_THROTTLING_RATE 0x38c00
8c6bba10 MW	96
046bee1f MW	97	/* Interrupt Vector Allocation */
	98	#define REG_INT_VEC_ALLOC_BASE 0x38c40
	99	#define REG_INT_VEC_ALLOC_BITS 4
	100	#define REG_INT_VEC_ALLOC_MASK GENMASK(3, 0)
	101	#define REG_INT_VEC_ALLOC_REGS (32 / REG_INT_VEC_ALLOC_BITS)
	102
16603153 AN	103	/* The last 11 bits contain the number of hops supported by the NHI port. */
	104	#define REG_HOP_COUNT 0x39640
	105
046bee1f MW	106	#define REG_DMA_MISC 0x39864
	107	#define REG_DMA_MISC_INT_AUTO_CLEAR BIT(2)
	108
cd446ee2 MW	109	#define REG_INMAIL_DATA 0x39900
	110
	111	#define REG_INMAIL_CMD 0x39904
	112	#define REG_INMAIL_CMD_MASK GENMASK(7, 0)
	113	#define REG_INMAIL_ERROR BIT(30)
	114	#define REG_INMAIL_OP_REQUEST BIT(31)
	115
	116	#define REG_OUTMAIL_CMD 0x3990c
	117	#define REG_OUTMAIL_CMD_OPMODE_SHIFT 8
	118	#define REG_OUTMAIL_CMD_OPMODE_MASK GENMASK(11, 8)
	119
f67cf491 MW	120	#define REG_FW_STS 0x39944
	121	#define REG_FW_STS_NVM_AUTH_DONE BIT(31)
	122	#define REG_FW_STS_CIO_RESET_REQ BIT(30)
	123	#define REG_FW_STS_ICM_EN_CPU BIT(2)
	124	#define REG_FW_STS_ICM_EN_INVERT BIT(1)
	125	#define REG_FW_STS_ICM_EN BIT(0)
	126
16603153	127	#endif