[linux-block.git] / drivers / thunderbolt / nhi_ops.c

// SPDX-License-Identifier: GPL-2.0
/*
 * NHI specific operations
 *
 * Copyright (C) 2019, Intel Corporation
 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
 */

#include <linux/delay.h>
#include <linux/suspend.h>

#include "nhi.h"
#include "nhi_regs.h"
#include "tb.h"

/* Ice Lake specific NHI operations */

#define ICL_LC_MAILBOX_TIMEOUT	500 /* ms */

static int check_for_device(struct device *dev, void *data)
{
	return tb_is_switch(dev);
}

static bool icl_nhi_is_device_connected(struct tb_nhi *nhi)
{
	struct tb *tb = pci_get_drvdata(nhi->pdev);
	int ret;

	ret = device_for_each_child(&tb->root_switch->dev, NULL,
				    check_for_device);
	return ret > 0;
}

static int icl_nhi_force_power(struct tb_nhi *nhi, bool power)
{
	u32 vs_cap;

	/*
	 * The Thunderbolt host controller is present always in Ice Lake
	 * but the firmware may not be loaded and running (depending
	 * whether there is device connected and so on). Each time the
	 * controller is used we need to "Force Power" it first and wait
	 * for the firmware to indicate it is up and running. This "Force
	 * Power" is really not about actually powering on/off the
	 * controller so it is accessible even if "Force Power" is off.
	 *
	 * The actual power management happens inside shared ACPI power
	 * resources using standard ACPI methods.
	 */
	pci_read_config_dword(nhi->pdev, VS_CAP_22, &vs_cap);
	if (power) {
		vs_cap &= ~VS_CAP_22_DMA_DELAY_MASK;
		vs_cap |= 0x22 << VS_CAP_22_DMA_DELAY_SHIFT;
		vs_cap |= VS_CAP_22_FORCE_POWER;
	} else {
		vs_cap &= ~VS_CAP_22_FORCE_POWER;
	}
	pci_write_config_dword(nhi->pdev, VS_CAP_22, vs_cap);

	if (power) {
		unsigned int retries = 10;
		u32 val;

		/* Wait until the firmware tells it is up and running */
		do {
			pci_read_config_dword(nhi->pdev, VS_CAP_9, &val);
			if (val & VS_CAP_9_FW_READY)
				return 0;
			msleep(250);
		} while (--retries);

		return -ETIMEDOUT;
	}

	return 0;
}

static void icl_nhi_lc_mailbox_cmd(struct tb_nhi *nhi, enum icl_lc_mailbox_cmd cmd)
{
	u32 data;

	pci_read_config_dword(nhi->pdev, VS_CAP_19, &data);
	data = (cmd << VS_CAP_19_CMD_SHIFT) & VS_CAP_19_CMD_MASK;
	pci_write_config_dword(nhi->pdev, VS_CAP_19, data | VS_CAP_19_VALID);
}

static int icl_nhi_lc_mailbox_cmd_complete(struct tb_nhi *nhi, int timeout)
{
	unsigned long end;
	u32 data;

	if (!timeout)
		goto clear;

	end = jiffies + msecs_to_jiffies(timeout);
	do {
		pci_read_config_dword(nhi->pdev, VS_CAP_18, &data);
		if (data & VS_CAP_18_DONE)
			goto clear;
		msleep(100);
	} while (time_before(jiffies, end));

	return -ETIMEDOUT;

clear:
	/* Clear the valid bit */
	pci_write_config_dword(nhi->pdev, VS_CAP_19, 0);
	return 0;
}

static void icl_nhi_set_ltr(struct tb_nhi *nhi)
{
	u32 max_ltr, ltr;

	pci_read_config_dword(nhi->pdev, VS_CAP_16, &max_ltr);
	max_ltr &= 0xffff;
	/* Program the same value for both snoop and no-snoop */
	ltr = max_ltr << 16 | max_ltr;
	pci_write_config_dword(nhi->pdev, VS_CAP_15, ltr);
}

static int icl_nhi_suspend(struct tb_nhi *nhi)
{
	int ret;

	if (icl_nhi_is_device_connected(nhi))
		return 0;

	/*
	 * If there is no device connected we need to perform both: a
	 * handshake through LC mailbox and force power down before
	 * entering D3.
	 */
	icl_nhi_lc_mailbox_cmd(nhi, ICL_LC_PREPARE_FOR_RESET);
	ret = icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT);
	if (ret)
		return ret;

	return icl_nhi_force_power(nhi, false);
}

static int icl_nhi_suspend_noirq(struct tb_nhi *nhi, bool wakeup)
{
	enum icl_lc_mailbox_cmd cmd;

	if (!pm_suspend_via_firmware())
		return icl_nhi_suspend(nhi);

	cmd = wakeup ? ICL_LC_GO2SX : ICL_LC_GO2SX_NO_WAKE;
	icl_nhi_lc_mailbox_cmd(nhi, cmd);
	return icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT);
}

static int icl_nhi_resume(struct tb_nhi *nhi)
{
	int ret;

	ret = icl_nhi_force_power(nhi, true);
	if (ret)
		return ret;

	icl_nhi_set_ltr(nhi);
	return 0;
}

static void icl_nhi_shutdown(struct tb_nhi *nhi)
{
	icl_nhi_force_power(nhi, false);
}

const struct tb_nhi_ops icl_nhi_ops = {
	.init = icl_nhi_resume,
	.suspend_noirq = icl_nhi_suspend_noirq,
	.resume_noirq = icl_nhi_resume,
	.runtime_suspend = icl_nhi_suspend,
	.runtime_resume = icl_nhi_resume,
	.shutdown = icl_nhi_shutdown,
};
Commit	Line	Data
3cdb9446 MW	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* NHI specific operations
	4	*
	5	* Copyright (C) 2019, Intel Corporation
	6	* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
	7	*/
	8
	9	#include <linux/delay.h>
	10	#include <linux/suspend.h>
	11
	12	#include "nhi.h"
	13	#include "nhi_regs.h"
	14	#include "tb.h"
	15
	16	/* Ice Lake specific NHI operations */
	17
	18	#define ICL_LC_MAILBOX_TIMEOUT 500 /* ms */
	19
	20	static int check_for_device(struct device dev, void data)
	21	{
	22	return tb_is_switch(dev);
	23	}
	24
	25	static bool icl_nhi_is_device_connected(struct tb_nhi *nhi)
	26	{
	27	struct tb *tb = pci_get_drvdata(nhi->pdev);
	28	int ret;
	29
	30	ret = device_for_each_child(&tb->root_switch->dev, NULL,
	31	check_for_device);
	32	return ret > 0;
	33	}
	34
	35	static int icl_nhi_force_power(struct tb_nhi *nhi, bool power)
	36	{
	37	u32 vs_cap;
	38
	39	/*
	40	* The Thunderbolt host controller is present always in Ice Lake
	41	* but the firmware may not be loaded and running (depending
	42	* whether there is device connected and so on). Each time the
	43	* controller is used we need to "Force Power" it first and wait
	44	* for the firmware to indicate it is up and running. This "Force
	45	* Power" is really not about actually powering on/off the
	46	* controller so it is accessible even if "Force Power" is off.
	47	*
	48	* The actual power management happens inside shared ACPI power
	49	* resources using standard ACPI methods.
	50	*/
	51	pci_read_config_dword(nhi->pdev, VS_CAP_22, &vs_cap);
	52	if (power) {
	53	vs_cap &= ~VS_CAP_22_DMA_DELAY_MASK;
	54	vs_cap \|= 0x22 << VS_CAP_22_DMA_DELAY_SHIFT;
	55	vs_cap \|= VS_CAP_22_FORCE_POWER;
	56	} else {
	57	vs_cap &= ~VS_CAP_22_FORCE_POWER;
	58	}
	59	pci_write_config_dword(nhi->pdev, VS_CAP_22, vs_cap);
	60
	61	if (power) {
	62	unsigned int retries = 10;
	63	u32 val;
	64
65	/* Wait until the firmware tells it is up and running */
66	do {
67	pci_read_config_dword(nhi->pdev, VS_CAP_9, &val);
68	if (val & VS_CAP_9_FW_READY)
69	return 0;
70	msleep(250);
71	} while (--retries);
72
73	return -ETIMEDOUT;
74	}
75
76	return 0;
77	}
78
79	static void icl_nhi_lc_mailbox_cmd(struct tb_nhi *nhi, enum icl_lc_mailbox_cmd cmd)
80	{
81	u32 data;
82
83	pci_read_config_dword(nhi->pdev, VS_CAP_19, &data);
84	data = (cmd << VS_CAP_19_CMD_SHIFT) & VS_CAP_19_CMD_MASK;
85	pci_write_config_dword(nhi->pdev, VS_CAP_19, data \| VS_CAP_19_VALID);
86	}
87
88	static int icl_nhi_lc_mailbox_cmd_complete(struct tb_nhi *nhi, int timeout)
89	{
90	unsigned long end;
91	u32 data;
92
93	if (!timeout)
94	goto clear;
95
96	end = jiffies + msecs_to_jiffies(timeout);
97	do {
98	pci_read_config_dword(nhi->pdev, VS_CAP_18, &data);
99	if (data & VS_CAP_18_DONE)
100	goto clear;
101	msleep(100);
102	} while (time_before(jiffies, end));
103
104	return -ETIMEDOUT;
105
106	clear:
107	/* Clear the valid bit */
108	pci_write_config_dword(nhi->pdev, VS_CAP_19, 0);
109	return 0;
110	}
111
112	static void icl_nhi_set_ltr(struct tb_nhi *nhi)
113	{
114	u32 max_ltr, ltr;
115
116	pci_read_config_dword(nhi->pdev, VS_CAP_16, &max_ltr);
117	max_ltr &= 0xffff;
118	/* Program the same value for both snoop and no-snoop */
119	ltr = max_ltr << 16 \| max_ltr;
120	pci_write_config_dword(nhi->pdev, VS_CAP_15, ltr);
121	}
122
123	static int icl_nhi_suspend(struct tb_nhi *nhi)
124	{
125	int ret;
126
127	if (icl_nhi_is_device_connected(nhi))
128	return 0;
129
130	/*
131	* If there is no device connected we need to perform both: a
132	* handshake through LC mailbox and force power down before
133	* entering D3.
134	*/
135	icl_nhi_lc_mailbox_cmd(nhi, ICL_LC_PREPARE_FOR_RESET);
136	ret = icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT);
137	if (ret)
138	return ret;
139
140	return icl_nhi_force_power(nhi, false);
141	}
142
143	static int icl_nhi_suspend_noirq(struct tb_nhi *nhi, bool wakeup)
144	{
145	enum icl_lc_mailbox_cmd cmd;
146
147	if (!pm_suspend_via_firmware())
148	return icl_nhi_suspend(nhi);
149
150	cmd = wakeup ? ICL_LC_GO2SX : ICL_LC_GO2SX_NO_WAKE;
151	icl_nhi_lc_mailbox_cmd(nhi, cmd);
152	return icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT);
153	}
154
155	static int icl_nhi_resume(struct tb_nhi *nhi)
156	{
157	int ret;
158
159	ret = icl_nhi_force_power(nhi, true);
160	if (ret)
161	return ret;
162
163	icl_nhi_set_ltr(nhi);
164	return 0;
165	}
166
167	static void icl_nhi_shutdown(struct tb_nhi *nhi)
168	{
169	icl_nhi_force_power(nhi, false);
170	}
171
172	const struct tb_nhi_ops icl_nhi_ops = {
173	.init = icl_nhi_resume,
174	.suspend_noirq = icl_nhi_suspend_noirq,
175	.resume_noirq = icl_nhi_resume,
176	.runtime_suspend = icl_nhi_suspend,
177	.runtime_resume = icl_nhi_resume,
178	.shutdown = icl_nhi_shutdown,
179	};