[linux-block.git] / drivers / thunderbolt / nhi.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Thunderbolt driver - NHI driver
 *
 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
 * Copyright (C) 2018, Intel Corporation
 */

#ifndef DSL3510_H_
#define DSL3510_H_

#include <linux/thunderbolt.h>

enum nhi_fw_mode {
	NHI_FW_SAFE_MODE,
	NHI_FW_AUTH_MODE,
	NHI_FW_EP_MODE,
	NHI_FW_CM_MODE,
};

enum nhi_mailbox_cmd {
	NHI_MAILBOX_SAVE_DEVS = 0x05,
	NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06,
	NHI_MAILBOX_DRV_UNLOADS = 0x07,
	NHI_MAILBOX_DISCONNECT_PA = 0x10,
	NHI_MAILBOX_DISCONNECT_PB = 0x11,
	NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23,
};

int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);
enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);

/**
 * struct tb_nhi_ops - NHI specific optional operations
 * @init: NHI specific initialization
 * @suspend_noirq: NHI specific suspend_noirq hook
 * @resume_noirq: NHI specific resume_noirq hook
 * @runtime_suspend: NHI specific runtime_suspend hook
 * @runtime_resume: NHI specific runtime_resume hook
 * @shutdown: NHI specific shutdown
 */
struct tb_nhi_ops {
	int (*init)(struct tb_nhi *nhi);
	int (*suspend_noirq)(struct tb_nhi *nhi, bool wakeup);
	int (*resume_noirq)(struct tb_nhi *nhi);
	int (*runtime_suspend)(struct tb_nhi *nhi);
	int (*runtime_resume)(struct tb_nhi *nhi);
	void (*shutdown)(struct tb_nhi *nhi);
};

extern const struct tb_nhi_ops icl_nhi_ops;

/*
 * PCI IDs used in this driver from Win Ridge forward. There is no
 * need for the PCI quirk anymore as we will use ICM also on Apple
 * hardware.
 */
#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_2C_NHI		0x1134
#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_4C_NHI		0x1137
#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI            0x157d
#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE         0x157e
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI		0x15bf
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE	0x15c0
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI	0x15d2
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE	0x15d3
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI	0x15d9
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE	0x15da
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI	0x15dc
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI	0x15dd
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI	0x15de
#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE	0x15e7
#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI		0x15e8
#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE	0x15ea
#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI		0x15eb
#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE	0x15ef
#define PCI_DEVICE_ID_INTEL_ADL_NHI0			0x463e
#define PCI_DEVICE_ID_INTEL_ADL_NHI1			0x466d
#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI	0x5781
#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI	0x5784
#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_80G_BRIDGE 0x5786
#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_40G_BRIDGE 0x57a4
#define PCI_DEVICE_ID_INTEL_MTL_M_NHI0			0x7eb2
#define PCI_DEVICE_ID_INTEL_MTL_P_NHI0			0x7ec2
#define PCI_DEVICE_ID_INTEL_MTL_P_NHI1			0x7ec3
#define PCI_DEVICE_ID_INTEL_ICL_NHI1			0x8a0d
#define PCI_DEVICE_ID_INTEL_ICL_NHI0			0x8a17
#define PCI_DEVICE_ID_INTEL_TGL_NHI0			0x9a1b
#define PCI_DEVICE_ID_INTEL_TGL_NHI1			0x9a1d
#define PCI_DEVICE_ID_INTEL_TGL_H_NHI0			0x9a1f
#define PCI_DEVICE_ID_INTEL_TGL_H_NHI1			0x9a21
#define PCI_DEVICE_ID_INTEL_RPL_NHI0			0xa73e
#define PCI_DEVICE_ID_INTEL_RPL_NHI1			0xa76d

#define PCI_CLASS_SERIAL_USB_USB4			0x0c0340

#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
16603153	2	/*
15c6784c	3	* Thunderbolt driver - NHI driver
16603153 AN	4	*
16603153 AN	5	* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
15c6784c	6	* Copyright (C) 2018, Intel Corporation
16603153 AN	7	*/
	8
	9	#ifndef DSL3510_H_
	10	#define DSL3510_H_
	11
3b3d9f4d	12	#include <linux/thunderbolt.h>
16603153	13
cd446ee2 MW	14	enum nhi_fw_mode {
	15	NHI_FW_SAFE_MODE,
	16	NHI_FW_AUTH_MODE,
	17	NHI_FW_EP_MODE,
	18	NHI_FW_CM_MODE,
	19	};
	20
	21	enum nhi_mailbox_cmd {
	22	NHI_MAILBOX_SAVE_DEVS = 0x05,
e6b245cc	23	NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06,
cd446ee2	24	NHI_MAILBOX_DRV_UNLOADS = 0x07,
d1ff7024 MW	25	NHI_MAILBOX_DISCONNECT_PA = 0x10,
d1ff7024 MW	26	NHI_MAILBOX_DISCONNECT_PB = 0x11,
cd446ee2 MW	27	NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23,
	28	};
	29
	30	int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);
	31	enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);
	32
3cdb9446 MW	33	/**
	34	* struct tb_nhi_ops - NHI specific optional operations
	35	* @init: NHI specific initialization
	36	* @suspend_noirq: NHI specific suspend_noirq hook
	37	* @resume_noirq: NHI specific resume_noirq hook
	38	* @runtime_suspend: NHI specific runtime_suspend hook
	39	* @runtime_resume: NHI specific runtime_resume hook
	40	* @shutdown: NHI specific shutdown
	41	*/
	42	struct tb_nhi_ops {
	43	int (init)(struct tb_nhi nhi);
	44	int (suspend_noirq)(struct tb_nhi nhi, bool wakeup);
	45	int (resume_noirq)(struct tb_nhi nhi);
	46	int (runtime_suspend)(struct tb_nhi nhi);
	47	int (runtime_resume)(struct tb_nhi nhi);
	48	void (shutdown)(struct tb_nhi nhi);
	49	};
	50
	51	extern const struct tb_nhi_ops icl_nhi_ops;
	52
5e2781bc MW	53	/*
	54	* PCI IDs used in this driver from Win Ridge forward. There is no
	55	* need for the PCI quirk anymore as we will use ICM also on Apple
	56	* hardware.
	57	*/
14c7d905	58	#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_2C_NHI 0x1134
db0746e3	59	#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_4C_NHI 0x1137
5e2781bc MW	60	#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI 0x157d
	61	#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e
	62	#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI 0x15bf
	63	#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0
	64	#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI 0x15d2
	65	#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE 0x15d3
	66	#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI 0x15d9
	67	#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE 0x15da
	68	#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc
	69	#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd
	70	#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de
4bac471d RM	71	#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE 0x15e7
	72	#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI 0x15e8
	73	#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE 0x15ea
	74	#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI 0x15eb
	75	#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE 0x15ef
13579486 AS	76	#define PCI_DEVICE_ID_INTEL_ADL_NHI0 0x463e
13579486 AS	77	#define PCI_DEVICE_ID_INTEL_ADL_NHI1 0x466d
6f14a210 MW	78	#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI 0x5781
6f14a210 MW	79	#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI 0x5784
f2bfa944 MW	80	#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_80G_BRIDGE 0x5786
f2bfa944 MW	81	#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_40G_BRIDGE 0x57a4
32249fd8 MW	82	#define PCI_DEVICE_ID_INTEL_MTL_M_NHI0 0x7eb2
	83	#define PCI_DEVICE_ID_INTEL_MTL_P_NHI0 0x7ec2
	84	#define PCI_DEVICE_ID_INTEL_MTL_P_NHI1 0x7ec3
3cdb9446 MW	85	#define PCI_DEVICE_ID_INTEL_ICL_NHI1 0x8a0d
3cdb9446 MW	86	#define PCI_DEVICE_ID_INTEL_ICL_NHI0 0x8a17
57d8df68 MW	87	#define PCI_DEVICE_ID_INTEL_TGL_NHI0 0x9a1b
57d8df68 MW	88	#define PCI_DEVICE_ID_INTEL_TGL_NHI1 0x9a1d
f6439c53 MW	89	#define PCI_DEVICE_ID_INTEL_TGL_H_NHI0 0x9a1f
f6439c53 MW	90	#define PCI_DEVICE_ID_INTEL_TGL_H_NHI1 0x9a21
7ec58378 GS	91	#define PCI_DEVICE_ID_INTEL_RPL_NHI0 0xa73e
7ec58378 GS	92	#define PCI_DEVICE_ID_INTEL_RPL_NHI1 0xa76d
5e2781bc	93
b0407983 MW	94	#define PCI_CLASS_SERIAL_USB_USB4 0x0c0340
b0407983 MW	95
16603153	96	#endif