Commit | Line | Data |
---|---|---|
09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
16603153 | 2 | /* |
15c6784c | 3 | * Thunderbolt driver - NHI driver |
16603153 AN |
4 | * |
5 | * The NHI (native host interface) is the pci device that allows us to send and | |
6 | * receive frames from the thunderbolt bus. | |
7 | * | |
8 | * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> | |
15c6784c | 9 | * Copyright (C) 2018, Intel Corporation |
16603153 AN |
10 | */ |
11 | ||
23dd5bb4 | 12 | #include <linux/pm_runtime.h> |
16603153 AN |
13 | #include <linux/slab.h> |
14 | #include <linux/errno.h> | |
15 | #include <linux/pci.h> | |
97486e98 | 16 | #include <linux/dma-mapping.h> |
16603153 | 17 | #include <linux/interrupt.h> |
86eaf4a5 | 18 | #include <linux/iommu.h> |
16603153 | 19 | #include <linux/module.h> |
cd446ee2 | 20 | #include <linux/delay.h> |
3cdb9446 | 21 | #include <linux/property.h> |
86eaf4a5 | 22 | #include <linux/string_helpers.h> |
16603153 AN |
23 | |
24 | #include "nhi.h" | |
25 | #include "nhi_regs.h" | |
d6cc51cd | 26 | #include "tb.h" |
16603153 AN |
27 | |
28 | #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring") | |
29 | ||
53f13319 | 30 | #define RING_FIRST_USABLE_HOPID 1 |
54669e2f MW |
31 | /* |
32 | * Used with QUIRK_E2E to specify an unused HopID the Rx credits are | |
33 | * transferred. | |
34 | */ | |
35 | #define RING_E2E_RESERVED_HOPID RING_FIRST_USABLE_HOPID | |
046bee1f MW |
36 | /* |
37 | * Minimal number of vectors when we use MSI-X. Two for control channel | |
38 | * Rx/Tx and the rest four are for cross domain DMA paths. | |
39 | */ | |
40 | #define MSIX_MIN_VECS 6 | |
41 | #define MSIX_MAX_VECS 16 | |
16603153 | 42 | |
cd446ee2 MW |
43 | #define NHI_MAILBOX_TIMEOUT 500 /* ms */ |
44 | ||
54669e2f | 45 | /* Host interface quirks */ |
e390909a | 46 | #define QUIRK_AUTO_CLEAR_INT BIT(0) |
54669e2f | 47 | #define QUIRK_E2E BIT(1) |
e390909a | 48 | |
1716efdb | 49 | static int ring_interrupt_index(const struct tb_ring *ring) |
16603153 AN |
50 | { |
51 | int bit = ring->hop; | |
52 | if (!ring->is_tx) | |
53 | bit += ring->nhi->hop_count; | |
54 | return bit; | |
55 | } | |
56 | ||
a7bfb27b | 57 | /* |
16603153 AN |
58 | * ring_interrupt_active() - activate/deactivate interrupts for a single ring |
59 | * | |
60 | * ring->nhi->lock must be held. | |
61 | */ | |
62 | static void ring_interrupt_active(struct tb_ring *ring, bool active) | |
63 | { | |
19bf4d4f LW |
64 | int reg = REG_RING_INTERRUPT_BASE + |
65 | ring_interrupt_index(ring) / 32 * 4; | |
58cdfe6f TR |
66 | int interrupt_bit = ring_interrupt_index(ring) & 31; |
67 | int mask = 1 << interrupt_bit; | |
16603153 | 68 | u32 old, new; |
046bee1f MW |
69 | |
70 | if (ring->irq > 0) { | |
71 | u32 step, shift, ivr, misc; | |
72 | void __iomem *ivr_base; | |
58cdfe6f | 73 | int auto_clear_bit; |
046bee1f MW |
74 | int index; |
75 | ||
76 | if (ring->is_tx) | |
77 | index = ring->hop; | |
78 | else | |
79 | index = ring->hop + ring->nhi->hop_count; | |
80 | ||
468c49f4 ML |
81 | /* |
82 | * Intel routers support a bit that isn't part of | |
83 | * the USB4 spec to ask the hardware to clear | |
84 | * interrupt status bits automatically since | |
85 | * we already know which interrupt was triggered. | |
86 | * | |
87 | * Other routers explicitly disable auto-clear | |
88 | * to prevent conditions that may occur where two | |
89 | * MSIX interrupts are simultaneously active and | |
90 | * reading the register clears both of them. | |
91 | */ | |
92 | misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); | |
93 | if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT) | |
58cdfe6f | 94 | auto_clear_bit = REG_DMA_MISC_INT_AUTO_CLEAR; |
468c49f4 | 95 | else |
58cdfe6f TR |
96 | auto_clear_bit = REG_DMA_MISC_DISABLE_AUTO_CLEAR; |
97 | if (!(misc & auto_clear_bit)) | |
98 | iowrite32(misc | auto_clear_bit, | |
99 | ring->nhi->iobase + REG_DMA_MISC); | |
046bee1f MW |
100 | |
101 | ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE; | |
102 | step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; | |
103 | shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; | |
104 | ivr = ioread32(ivr_base + step); | |
105 | ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift); | |
106 | if (active) | |
107 | ivr |= ring->vector << shift; | |
108 | iowrite32(ivr, ivr_base + step); | |
109 | } | |
110 | ||
16603153 AN |
111 | old = ioread32(ring->nhi->iobase + reg); |
112 | if (active) | |
113 | new = old | mask; | |
114 | else | |
115 | new = old & ~mask; | |
116 | ||
daa5140f MW |
117 | dev_dbg(&ring->nhi->pdev->dev, |
118 | "%s interrupt at register %#x bit %d (%#x -> %#x)\n", | |
58cdfe6f | 119 | active ? "enabling" : "disabling", reg, interrupt_bit, old, new); |
16603153 AN |
120 | |
121 | if (new == old) | |
122 | dev_WARN(&ring->nhi->pdev->dev, | |
123 | "interrupt for %s %d is already %s\n", | |
124 | RING_TYPE(ring), ring->hop, | |
125 | active ? "enabled" : "disabled"); | |
126 | iowrite32(new, ring->nhi->iobase + reg); | |
127 | } | |
128 | ||
a7bfb27b | 129 | /* |
16603153 AN |
130 | * nhi_disable_interrupts() - disable interrupts for all rings |
131 | * | |
132 | * Use only during init and shutdown. | |
133 | */ | |
134 | static void nhi_disable_interrupts(struct tb_nhi *nhi) | |
135 | { | |
136 | int i = 0; | |
137 | /* disable interrupts */ | |
138 | for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++) | |
139 | iowrite32(0, nhi->iobase + REG_RING_INTERRUPT_BASE + 4 * i); | |
140 | ||
141 | /* clear interrupt status bits */ | |
142 | for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++) | |
143 | ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + 4 * i); | |
144 | } | |
145 | ||
146 | /* ring helper methods */ | |
147 | ||
148 | static void __iomem *ring_desc_base(struct tb_ring *ring) | |
149 | { | |
150 | void __iomem *io = ring->nhi->iobase; | |
151 | io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE; | |
152 | io += ring->hop * 16; | |
153 | return io; | |
154 | } | |
155 | ||
156 | static void __iomem *ring_options_base(struct tb_ring *ring) | |
157 | { | |
158 | void __iomem *io = ring->nhi->iobase; | |
159 | io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE; | |
160 | io += ring->hop * 32; | |
161 | return io; | |
162 | } | |
163 | ||
94379521 | 164 | static void ring_iowrite_cons(struct tb_ring *ring, u16 cons) |
16603153 | 165 | { |
94379521 MW |
166 | /* |
167 | * The other 16-bits in the register is read-only and writes to it | |
168 | * are ignored by the hardware so we can save one ioread32() by | |
169 | * filling the read-only bits with zeroes. | |
170 | */ | |
171 | iowrite32(cons, ring_desc_base(ring) + 8); | |
172 | } | |
173 | ||
174 | static void ring_iowrite_prod(struct tb_ring *ring, u16 prod) | |
175 | { | |
176 | /* See ring_iowrite_cons() above for explanation */ | |
177 | iowrite32(prod << 16, ring_desc_base(ring) + 8); | |
16603153 AN |
178 | } |
179 | ||
180 | static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset) | |
181 | { | |
182 | iowrite32(value, ring_desc_base(ring) + offset); | |
183 | } | |
184 | ||
185 | static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset) | |
186 | { | |
187 | iowrite32(value, ring_desc_base(ring) + offset); | |
188 | iowrite32(value >> 32, ring_desc_base(ring) + offset + 4); | |
189 | } | |
190 | ||
191 | static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset) | |
192 | { | |
193 | iowrite32(value, ring_options_base(ring) + offset); | |
194 | } | |
195 | ||
196 | static bool ring_full(struct tb_ring *ring) | |
197 | { | |
198 | return ((ring->head + 1) % ring->size) == ring->tail; | |
199 | } | |
200 | ||
201 | static bool ring_empty(struct tb_ring *ring) | |
202 | { | |
203 | return ring->head == ring->tail; | |
204 | } | |
205 | ||
a7bfb27b | 206 | /* |
16603153 AN |
207 | * ring_write_descriptors() - post frames from ring->queue to the controller |
208 | * | |
209 | * ring->lock is held. | |
210 | */ | |
211 | static void ring_write_descriptors(struct tb_ring *ring) | |
212 | { | |
213 | struct ring_frame *frame, *n; | |
214 | struct ring_desc *descriptor; | |
215 | list_for_each_entry_safe(frame, n, &ring->queue, list) { | |
216 | if (ring_full(ring)) | |
217 | break; | |
218 | list_move_tail(&frame->list, &ring->in_flight); | |
219 | descriptor = &ring->descriptors[ring->head]; | |
220 | descriptor->phys = frame->buffer_phy; | |
221 | descriptor->time = 0; | |
222 | descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT; | |
223 | if (ring->is_tx) { | |
224 | descriptor->length = frame->size; | |
225 | descriptor->eof = frame->eof; | |
226 | descriptor->sof = frame->sof; | |
227 | } | |
228 | ring->head = (ring->head + 1) % ring->size; | |
94379521 MW |
229 | if (ring->is_tx) |
230 | ring_iowrite_prod(ring, ring->head); | |
231 | else | |
232 | ring_iowrite_cons(ring, ring->head); | |
16603153 AN |
233 | } |
234 | } | |
235 | ||
a7bfb27b | 236 | /* |
16603153 AN |
237 | * ring_work() - progress completed frames |
238 | * | |
239 | * If the ring is shutting down then all frames are marked as canceled and | |
240 | * their callbacks are invoked. | |
241 | * | |
242 | * Otherwise we collect all completed frame from the ring buffer, write new | |
243 | * frame to the ring buffer and invoke the callbacks for the completed frames. | |
244 | */ | |
245 | static void ring_work(struct work_struct *work) | |
246 | { | |
247 | struct tb_ring *ring = container_of(work, typeof(*ring), work); | |
248 | struct ring_frame *frame; | |
249 | bool canceled = false; | |
22b7de10 | 250 | unsigned long flags; |
16603153 | 251 | LIST_HEAD(done); |
22b7de10 MW |
252 | |
253 | spin_lock_irqsave(&ring->lock, flags); | |
16603153 AN |
254 | |
255 | if (!ring->running) { | |
256 | /* Move all frames to done and mark them as canceled. */ | |
257 | list_splice_tail_init(&ring->in_flight, &done); | |
258 | list_splice_tail_init(&ring->queue, &done); | |
259 | canceled = true; | |
260 | goto invoke_callback; | |
261 | } | |
262 | ||
263 | while (!ring_empty(ring)) { | |
264 | if (!(ring->descriptors[ring->tail].flags | |
265 | & RING_DESC_COMPLETED)) | |
266 | break; | |
267 | frame = list_first_entry(&ring->in_flight, typeof(*frame), | |
268 | list); | |
269 | list_move_tail(&frame->list, &done); | |
270 | if (!ring->is_tx) { | |
271 | frame->size = ring->descriptors[ring->tail].length; | |
272 | frame->eof = ring->descriptors[ring->tail].eof; | |
273 | frame->sof = ring->descriptors[ring->tail].sof; | |
274 | frame->flags = ring->descriptors[ring->tail].flags; | |
16603153 AN |
275 | } |
276 | ring->tail = (ring->tail + 1) % ring->size; | |
277 | } | |
278 | ring_write_descriptors(ring); | |
279 | ||
280 | invoke_callback: | |
22b7de10 MW |
281 | /* allow callbacks to schedule new work */ |
282 | spin_unlock_irqrestore(&ring->lock, flags); | |
16603153 AN |
283 | while (!list_empty(&done)) { |
284 | frame = list_first_entry(&done, typeof(*frame), list); | |
285 | /* | |
286 | * The callback may reenqueue or delete frame. | |
287 | * Do not hold on to it. | |
288 | */ | |
289 | list_del_init(&frame->list); | |
4ffe722e MW |
290 | if (frame->callback) |
291 | frame->callback(ring, frame, canceled); | |
16603153 AN |
292 | } |
293 | } | |
294 | ||
3b3d9f4d | 295 | int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame) |
16603153 | 296 | { |
22b7de10 | 297 | unsigned long flags; |
16603153 | 298 | int ret = 0; |
22b7de10 MW |
299 | |
300 | spin_lock_irqsave(&ring->lock, flags); | |
16603153 AN |
301 | if (ring->running) { |
302 | list_add_tail(&frame->list, &ring->queue); | |
303 | ring_write_descriptors(ring); | |
304 | } else { | |
305 | ret = -ESHUTDOWN; | |
306 | } | |
22b7de10 | 307 | spin_unlock_irqrestore(&ring->lock, flags); |
16603153 AN |
308 | return ret; |
309 | } | |
3b3d9f4d | 310 | EXPORT_SYMBOL_GPL(__tb_ring_enqueue); |
16603153 | 311 | |
4ffe722e MW |
312 | /** |
313 | * tb_ring_poll() - Poll one completed frame from the ring | |
314 | * @ring: Ring to poll | |
315 | * | |
316 | * This function can be called when @start_poll callback of the @ring | |
317 | * has been called. It will read one completed frame from the ring and | |
318 | * return it to the caller. Returns %NULL if there is no more completed | |
319 | * frames. | |
320 | */ | |
321 | struct ring_frame *tb_ring_poll(struct tb_ring *ring) | |
322 | { | |
323 | struct ring_frame *frame = NULL; | |
324 | unsigned long flags; | |
325 | ||
326 | spin_lock_irqsave(&ring->lock, flags); | |
327 | if (!ring->running) | |
328 | goto unlock; | |
329 | if (ring_empty(ring)) | |
330 | goto unlock; | |
331 | ||
332 | if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) { | |
333 | frame = list_first_entry(&ring->in_flight, typeof(*frame), | |
334 | list); | |
335 | list_del_init(&frame->list); | |
336 | ||
337 | if (!ring->is_tx) { | |
338 | frame->size = ring->descriptors[ring->tail].length; | |
339 | frame->eof = ring->descriptors[ring->tail].eof; | |
340 | frame->sof = ring->descriptors[ring->tail].sof; | |
341 | frame->flags = ring->descriptors[ring->tail].flags; | |
342 | } | |
343 | ||
344 | ring->tail = (ring->tail + 1) % ring->size; | |
345 | } | |
346 | ||
347 | unlock: | |
348 | spin_unlock_irqrestore(&ring->lock, flags); | |
349 | return frame; | |
350 | } | |
351 | EXPORT_SYMBOL_GPL(tb_ring_poll); | |
352 | ||
353 | static void __ring_interrupt_mask(struct tb_ring *ring, bool mask) | |
354 | { | |
355 | int idx = ring_interrupt_index(ring); | |
356 | int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4; | |
357 | int bit = idx % 32; | |
358 | u32 val; | |
359 | ||
360 | val = ioread32(ring->nhi->iobase + reg); | |
361 | if (mask) | |
362 | val &= ~BIT(bit); | |
363 | else | |
364 | val |= BIT(bit); | |
365 | iowrite32(val, ring->nhi->iobase + reg); | |
366 | } | |
367 | ||
368 | /* Both @nhi->lock and @ring->lock should be held */ | |
369 | static void __ring_interrupt(struct tb_ring *ring) | |
370 | { | |
371 | if (!ring->running) | |
372 | return; | |
373 | ||
374 | if (ring->start_poll) { | |
74657181 | 375 | __ring_interrupt_mask(ring, true); |
4ffe722e MW |
376 | ring->start_poll(ring->poll_data); |
377 | } else { | |
378 | schedule_work(&ring->work); | |
379 | } | |
380 | } | |
381 | ||
382 | /** | |
383 | * tb_ring_poll_complete() - Re-start interrupt for the ring | |
384 | * @ring: Ring to re-start the interrupt | |
385 | * | |
386 | * This will re-start (unmask) the ring interrupt once the user is done | |
387 | * with polling. | |
388 | */ | |
389 | void tb_ring_poll_complete(struct tb_ring *ring) | |
390 | { | |
391 | unsigned long flags; | |
392 | ||
393 | spin_lock_irqsave(&ring->nhi->lock, flags); | |
394 | spin_lock(&ring->lock); | |
395 | if (ring->start_poll) | |
396 | __ring_interrupt_mask(ring, false); | |
397 | spin_unlock(&ring->lock); | |
398 | spin_unlock_irqrestore(&ring->nhi->lock, flags); | |
399 | } | |
400 | EXPORT_SYMBOL_GPL(tb_ring_poll_complete); | |
401 | ||
7a1808f8 SM |
402 | static void ring_clear_msix(const struct tb_ring *ring) |
403 | { | |
468c49f4 ML |
404 | int bit; |
405 | ||
7a1808f8 SM |
406 | if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT) |
407 | return; | |
408 | ||
468c49f4 | 409 | bit = ring_interrupt_index(ring) & 31; |
7a1808f8 | 410 | if (ring->is_tx) |
468c49f4 | 411 | iowrite32(BIT(bit), ring->nhi->iobase + REG_RING_INT_CLEAR); |
7a1808f8 | 412 | else |
468c49f4 ML |
413 | iowrite32(BIT(bit), ring->nhi->iobase + REG_RING_INT_CLEAR + |
414 | 4 * (ring->nhi->hop_count / 32)); | |
7a1808f8 SM |
415 | } |
416 | ||
046bee1f MW |
417 | static irqreturn_t ring_msix(int irq, void *data) |
418 | { | |
419 | struct tb_ring *ring = data; | |
420 | ||
4ffe722e | 421 | spin_lock(&ring->nhi->lock); |
7a1808f8 | 422 | ring_clear_msix(ring); |
4ffe722e MW |
423 | spin_lock(&ring->lock); |
424 | __ring_interrupt(ring); | |
425 | spin_unlock(&ring->lock); | |
426 | spin_unlock(&ring->nhi->lock); | |
427 | ||
046bee1f MW |
428 | return IRQ_HANDLED; |
429 | } | |
430 | ||
431 | static int ring_request_msix(struct tb_ring *ring, bool no_suspend) | |
432 | { | |
433 | struct tb_nhi *nhi = ring->nhi; | |
434 | unsigned long irqflags; | |
435 | int ret; | |
436 | ||
437 | if (!nhi->pdev->msix_enabled) | |
438 | return 0; | |
439 | ||
440 | ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL); | |
441 | if (ret < 0) | |
442 | return ret; | |
443 | ||
444 | ring->vector = ret; | |
445 | ||
7342ca34 JX |
446 | ret = pci_irq_vector(ring->nhi->pdev, ring->vector); |
447 | if (ret < 0) | |
448 | goto err_ida_remove; | |
449 | ||
450 | ring->irq = ret; | |
046bee1f MW |
451 | |
452 | irqflags = no_suspend ? IRQF_NO_SUSPEND : 0; | |
7342ca34 JX |
453 | ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring); |
454 | if (ret) | |
455 | goto err_ida_remove; | |
456 | ||
457 | return 0; | |
458 | ||
459 | err_ida_remove: | |
460 | ida_simple_remove(&nhi->msix_ida, ring->vector); | |
461 | ||
462 | return ret; | |
046bee1f MW |
463 | } |
464 | ||
465 | static void ring_release_msix(struct tb_ring *ring) | |
466 | { | |
467 | if (ring->irq <= 0) | |
468 | return; | |
469 | ||
470 | free_irq(ring->irq, ring); | |
471 | ida_simple_remove(&ring->nhi->msix_ida, ring->vector); | |
472 | ring->vector = 0; | |
473 | ring->irq = 0; | |
474 | } | |
475 | ||
9a01c7c2 MW |
476 | static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring) |
477 | { | |
54669e2f | 478 | unsigned int start_hop = RING_FIRST_USABLE_HOPID; |
9a01c7c2 MW |
479 | int ret = 0; |
480 | ||
54669e2f MW |
481 | if (nhi->quirks & QUIRK_E2E) { |
482 | start_hop = RING_FIRST_USABLE_HOPID + 1; | |
483 | if (ring->flags & RING_FLAG_E2E && !ring->is_tx) { | |
484 | dev_dbg(&nhi->pdev->dev, "quirking E2E TX HopID %u -> %u\n", | |
485 | ring->e2e_tx_hop, RING_E2E_RESERVED_HOPID); | |
486 | ring->e2e_tx_hop = RING_E2E_RESERVED_HOPID; | |
487 | } | |
488 | } | |
489 | ||
9a01c7c2 MW |
490 | spin_lock_irq(&nhi->lock); |
491 | ||
492 | if (ring->hop < 0) { | |
493 | unsigned int i; | |
494 | ||
495 | /* | |
496 | * Automatically allocate HopID from the non-reserved | |
53f13319 | 497 | * range 1 .. hop_count - 1. |
9a01c7c2 | 498 | */ |
54669e2f | 499 | for (i = start_hop; i < nhi->hop_count; i++) { |
9a01c7c2 MW |
500 | if (ring->is_tx) { |
501 | if (!nhi->tx_rings[i]) { | |
502 | ring->hop = i; | |
503 | break; | |
504 | } | |
505 | } else { | |
506 | if (!nhi->rx_rings[i]) { | |
507 | ring->hop = i; | |
508 | break; | |
509 | } | |
510 | } | |
511 | } | |
512 | } | |
513 | ||
54669e2f MW |
514 | if (ring->hop > 0 && ring->hop < start_hop) { |
515 | dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop); | |
516 | ret = -EINVAL; | |
517 | goto err_unlock; | |
518 | } | |
9a01c7c2 MW |
519 | if (ring->hop < 0 || ring->hop >= nhi->hop_count) { |
520 | dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop); | |
521 | ret = -EINVAL; | |
522 | goto err_unlock; | |
523 | } | |
524 | if (ring->is_tx && nhi->tx_rings[ring->hop]) { | |
525 | dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n", | |
526 | ring->hop); | |
527 | ret = -EBUSY; | |
528 | goto err_unlock; | |
4e99c98e AS |
529 | } |
530 | if (!ring->is_tx && nhi->rx_rings[ring->hop]) { | |
9a01c7c2 MW |
531 | dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n", |
532 | ring->hop); | |
533 | ret = -EBUSY; | |
534 | goto err_unlock; | |
535 | } | |
536 | ||
537 | if (ring->is_tx) | |
538 | nhi->tx_rings[ring->hop] = ring; | |
539 | else | |
540 | nhi->rx_rings[ring->hop] = ring; | |
541 | ||
542 | err_unlock: | |
543 | spin_unlock_irq(&nhi->lock); | |
544 | ||
545 | return ret; | |
546 | } | |
547 | ||
3b3d9f4d MW |
548 | static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size, |
549 | bool transmit, unsigned int flags, | |
afe704a2 | 550 | int e2e_tx_hop, u16 sof_mask, u16 eof_mask, |
4ffe722e MW |
551 | void (*start_poll)(void *), |
552 | void *poll_data) | |
16603153 AN |
553 | { |
554 | struct tb_ring *ring = NULL; | |
daa5140f MW |
555 | |
556 | dev_dbg(&nhi->pdev->dev, "allocating %s ring %d of size %d\n", | |
557 | transmit ? "TX" : "RX", hop, size); | |
16603153 | 558 | |
16603153 AN |
559 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
560 | if (!ring) | |
59120e06 | 561 | return NULL; |
16603153 | 562 | |
22b7de10 | 563 | spin_lock_init(&ring->lock); |
16603153 AN |
564 | INIT_LIST_HEAD(&ring->queue); |
565 | INIT_LIST_HEAD(&ring->in_flight); | |
566 | INIT_WORK(&ring->work, ring_work); | |
567 | ||
568 | ring->nhi = nhi; | |
569 | ring->hop = hop; | |
570 | ring->is_tx = transmit; | |
571 | ring->size = size; | |
046bee1f | 572 | ring->flags = flags; |
afe704a2 | 573 | ring->e2e_tx_hop = e2e_tx_hop; |
9fb1e654 MW |
574 | ring->sof_mask = sof_mask; |
575 | ring->eof_mask = eof_mask; | |
16603153 AN |
576 | ring->head = 0; |
577 | ring->tail = 0; | |
578 | ring->running = false; | |
4ffe722e MW |
579 | ring->start_poll = start_poll; |
580 | ring->poll_data = poll_data; | |
046bee1f | 581 | |
16603153 AN |
582 | ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev, |
583 | size * sizeof(*ring->descriptors), | |
584 | &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO); | |
585 | if (!ring->descriptors) | |
59120e06 | 586 | goto err_free_ring; |
16603153 | 587 | |
59120e06 MW |
588 | if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND)) |
589 | goto err_free_descs; | |
590 | ||
9a01c7c2 | 591 | if (nhi_alloc_hop(nhi, ring)) |
59120e06 | 592 | goto err_release_msix; |
59120e06 | 593 | |
16603153 AN |
594 | return ring; |
595 | ||
59120e06 | 596 | err_release_msix: |
59120e06 MW |
597 | ring_release_msix(ring); |
598 | err_free_descs: | |
599 | dma_free_coherent(&ring->nhi->pdev->dev, | |
600 | ring->size * sizeof(*ring->descriptors), | |
601 | ring->descriptors, ring->descriptors_dma); | |
602 | err_free_ring: | |
16603153 | 603 | kfree(ring); |
59120e06 | 604 | |
16603153 AN |
605 | return NULL; |
606 | } | |
607 | ||
3b3d9f4d MW |
608 | /** |
609 | * tb_ring_alloc_tx() - Allocate DMA ring for transmit | |
610 | * @nhi: Pointer to the NHI the ring is to be allocated | |
611 | * @hop: HopID (ring) to allocate | |
612 | * @size: Number of entries in the ring | |
613 | * @flags: Flags for the ring | |
614 | */ | |
615 | struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size, | |
616 | unsigned int flags) | |
16603153 | 617 | { |
afe704a2 | 618 | return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, 0, NULL, NULL); |
16603153 | 619 | } |
3b3d9f4d | 620 | EXPORT_SYMBOL_GPL(tb_ring_alloc_tx); |
16603153 | 621 | |
3b3d9f4d MW |
622 | /** |
623 | * tb_ring_alloc_rx() - Allocate DMA ring for receive | |
624 | * @nhi: Pointer to the NHI the ring is to be allocated | |
9a01c7c2 | 625 | * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation. |
3b3d9f4d MW |
626 | * @size: Number of entries in the ring |
627 | * @flags: Flags for the ring | |
afe704a2 | 628 | * @e2e_tx_hop: Transmit HopID when E2E is enabled in @flags |
3b3d9f4d MW |
629 | * @sof_mask: Mask of PDF values that start a frame |
630 | * @eof_mask: Mask of PDF values that end a frame | |
4ffe722e MW |
631 | * @start_poll: If not %NULL the ring will call this function when an |
632 | * interrupt is triggered and masked, instead of callback | |
633 | * in each Rx frame. | |
634 | * @poll_data: Optional data passed to @start_poll | |
3b3d9f4d MW |
635 | */ |
636 | struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size, | |
afe704a2 MW |
637 | unsigned int flags, int e2e_tx_hop, |
638 | u16 sof_mask, u16 eof_mask, | |
4ffe722e | 639 | void (*start_poll)(void *), void *poll_data) |
16603153 | 640 | { |
afe704a2 | 641 | return tb_ring_alloc(nhi, hop, size, false, flags, e2e_tx_hop, sof_mask, eof_mask, |
4ffe722e | 642 | start_poll, poll_data); |
16603153 | 643 | } |
3b3d9f4d | 644 | EXPORT_SYMBOL_GPL(tb_ring_alloc_rx); |
16603153 AN |
645 | |
646 | /** | |
3b3d9f4d | 647 | * tb_ring_start() - enable a ring |
6894bd37 | 648 | * @ring: Ring to start |
16603153 | 649 | * |
3b3d9f4d | 650 | * Must not be invoked in parallel with tb_ring_stop(). |
16603153 | 651 | */ |
3b3d9f4d | 652 | void tb_ring_start(struct tb_ring *ring) |
16603153 | 653 | { |
9fb1e654 MW |
654 | u16 frame_size; |
655 | u32 flags; | |
656 | ||
59120e06 MW |
657 | spin_lock_irq(&ring->nhi->lock); |
658 | spin_lock(&ring->lock); | |
bdccf295 MW |
659 | if (ring->nhi->going_away) |
660 | goto err; | |
16603153 AN |
661 | if (ring->running) { |
662 | dev_WARN(&ring->nhi->pdev->dev, "ring already started\n"); | |
663 | goto err; | |
664 | } | |
daa5140f MW |
665 | dev_dbg(&ring->nhi->pdev->dev, "starting %s %d\n", |
666 | RING_TYPE(ring), ring->hop); | |
16603153 | 667 | |
9fb1e654 MW |
668 | if (ring->flags & RING_FLAG_FRAME) { |
669 | /* Means 4096 */ | |
670 | frame_size = 0; | |
671 | flags = RING_FLAG_ENABLE; | |
672 | } else { | |
673 | frame_size = TB_FRAME_SIZE; | |
674 | flags = RING_FLAG_ENABLE | RING_FLAG_RAW; | |
675 | } | |
676 | ||
16603153 AN |
677 | ring_iowrite64desc(ring, ring->descriptors_dma, 0); |
678 | if (ring->is_tx) { | |
679 | ring_iowrite32desc(ring, ring->size, 12); | |
680 | ring_iowrite32options(ring, 0, 4); /* time releated ? */ | |
9fb1e654 | 681 | ring_iowrite32options(ring, flags, 0); |
16603153 | 682 | } else { |
9fb1e654 MW |
683 | u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask; |
684 | ||
685 | ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12); | |
686 | ring_iowrite32options(ring, sof_eof_mask, 4); | |
687 | ring_iowrite32options(ring, flags, 0); | |
16603153 | 688 | } |
afe704a2 MW |
689 | |
690 | /* | |
691 | * Now that the ring valid bit is set we can configure E2E if | |
692 | * enabled for the ring. | |
693 | */ | |
694 | if (ring->flags & RING_FLAG_E2E) { | |
695 | if (!ring->is_tx) { | |
696 | u32 hop; | |
697 | ||
698 | hop = ring->e2e_tx_hop << REG_RX_OPTIONS_E2E_HOP_SHIFT; | |
699 | hop &= REG_RX_OPTIONS_E2E_HOP_MASK; | |
700 | flags |= hop; | |
701 | ||
702 | dev_dbg(&ring->nhi->pdev->dev, | |
703 | "enabling E2E for %s %d with TX HopID %d\n", | |
704 | RING_TYPE(ring), ring->hop, ring->e2e_tx_hop); | |
705 | } else { | |
706 | dev_dbg(&ring->nhi->pdev->dev, "enabling E2E for %s %d\n", | |
707 | RING_TYPE(ring), ring->hop); | |
708 | } | |
709 | ||
710 | flags |= RING_FLAG_E2E_FLOW_CONTROL; | |
711 | ring_iowrite32options(ring, flags, 0); | |
712 | } | |
713 | ||
16603153 AN |
714 | ring_interrupt_active(ring, true); |
715 | ring->running = true; | |
716 | err: | |
59120e06 MW |
717 | spin_unlock(&ring->lock); |
718 | spin_unlock_irq(&ring->nhi->lock); | |
16603153 | 719 | } |
3b3d9f4d | 720 | EXPORT_SYMBOL_GPL(tb_ring_start); |
16603153 AN |
721 | |
722 | /** | |
3b3d9f4d | 723 | * tb_ring_stop() - shutdown a ring |
6894bd37 | 724 | * @ring: Ring to stop |
16603153 AN |
725 | * |
726 | * Must not be invoked from a callback. | |
727 | * | |
3b3d9f4d MW |
728 | * This method will disable the ring. Further calls to |
729 | * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been | |
730 | * called. | |
16603153 AN |
731 | * |
732 | * All enqueued frames will be canceled and their callbacks will be executed | |
733 | * with frame->canceled set to true (on the callback thread). This method | |
734 | * returns only after all callback invocations have finished. | |
735 | */ | |
3b3d9f4d | 736 | void tb_ring_stop(struct tb_ring *ring) |
16603153 | 737 | { |
59120e06 MW |
738 | spin_lock_irq(&ring->nhi->lock); |
739 | spin_lock(&ring->lock); | |
daa5140f MW |
740 | dev_dbg(&ring->nhi->pdev->dev, "stopping %s %d\n", |
741 | RING_TYPE(ring), ring->hop); | |
bdccf295 MW |
742 | if (ring->nhi->going_away) |
743 | goto err; | |
16603153 AN |
744 | if (!ring->running) { |
745 | dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n", | |
746 | RING_TYPE(ring), ring->hop); | |
747 | goto err; | |
748 | } | |
749 | ring_interrupt_active(ring, false); | |
750 | ||
751 | ring_iowrite32options(ring, 0, 0); | |
752 | ring_iowrite64desc(ring, 0, 0); | |
94379521 | 753 | ring_iowrite32desc(ring, 0, 8); |
16603153 AN |
754 | ring_iowrite32desc(ring, 0, 12); |
755 | ring->head = 0; | |
756 | ring->tail = 0; | |
757 | ring->running = false; | |
758 | ||
759 | err: | |
59120e06 MW |
760 | spin_unlock(&ring->lock); |
761 | spin_unlock_irq(&ring->nhi->lock); | |
16603153 AN |
762 | |
763 | /* | |
764 | * schedule ring->work to invoke callbacks on all remaining frames. | |
765 | */ | |
766 | schedule_work(&ring->work); | |
767 | flush_work(&ring->work); | |
768 | } | |
3b3d9f4d | 769 | EXPORT_SYMBOL_GPL(tb_ring_stop); |
16603153 AN |
770 | |
771 | /* | |
3b3d9f4d | 772 | * tb_ring_free() - free ring |
16603153 AN |
773 | * |
774 | * When this method returns all invocations of ring->callback will have | |
775 | * finished. | |
776 | * | |
777 | * Ring must be stopped. | |
778 | * | |
779 | * Must NOT be called from ring_frame->callback! | |
780 | */ | |
3b3d9f4d | 781 | void tb_ring_free(struct tb_ring *ring) |
16603153 | 782 | { |
59120e06 | 783 | spin_lock_irq(&ring->nhi->lock); |
16603153 AN |
784 | /* |
785 | * Dissociate the ring from the NHI. This also ensures that | |
786 | * nhi_interrupt_work cannot reschedule ring->work. | |
787 | */ | |
788 | if (ring->is_tx) | |
789 | ring->nhi->tx_rings[ring->hop] = NULL; | |
790 | else | |
791 | ring->nhi->rx_rings[ring->hop] = NULL; | |
792 | ||
793 | if (ring->running) { | |
794 | dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n", | |
795 | RING_TYPE(ring), ring->hop); | |
796 | } | |
4ffe722e | 797 | spin_unlock_irq(&ring->nhi->lock); |
16603153 | 798 | |
046bee1f MW |
799 | ring_release_msix(ring); |
800 | ||
16603153 AN |
801 | dma_free_coherent(&ring->nhi->pdev->dev, |
802 | ring->size * sizeof(*ring->descriptors), | |
803 | ring->descriptors, ring->descriptors_dma); | |
804 | ||
f19b72c6 | 805 | ring->descriptors = NULL; |
16603153 AN |
806 | ring->descriptors_dma = 0; |
807 | ||
808 | ||
daa5140f MW |
809 | dev_dbg(&ring->nhi->pdev->dev, "freeing %s %d\n", RING_TYPE(ring), |
810 | ring->hop); | |
16603153 | 811 | |
a7bfb27b | 812 | /* |
046bee1f MW |
813 | * ring->work can no longer be scheduled (it is scheduled only |
814 | * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it | |
815 | * to finish before freeing the ring. | |
16603153 AN |
816 | */ |
817 | flush_work(&ring->work); | |
16603153 AN |
818 | kfree(ring); |
819 | } | |
3b3d9f4d | 820 | EXPORT_SYMBOL_GPL(tb_ring_free); |
16603153 | 821 | |
cd446ee2 MW |
822 | /** |
823 | * nhi_mailbox_cmd() - Send a command through NHI mailbox | |
824 | * @nhi: Pointer to the NHI structure | |
825 | * @cmd: Command to send | |
826 | * @data: Data to be send with the command | |
827 | * | |
828 | * Sends mailbox command to the firmware running on NHI. Returns %0 in | |
829 | * case of success and negative errno in case of failure. | |
830 | */ | |
831 | int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data) | |
832 | { | |
833 | ktime_t timeout; | |
834 | u32 val; | |
835 | ||
836 | iowrite32(data, nhi->iobase + REG_INMAIL_DATA); | |
837 | ||
838 | val = ioread32(nhi->iobase + REG_INMAIL_CMD); | |
839 | val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR); | |
840 | val |= REG_INMAIL_OP_REQUEST | cmd; | |
841 | iowrite32(val, nhi->iobase + REG_INMAIL_CMD); | |
842 | ||
843 | timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT); | |
844 | do { | |
845 | val = ioread32(nhi->iobase + REG_INMAIL_CMD); | |
846 | if (!(val & REG_INMAIL_OP_REQUEST)) | |
847 | break; | |
848 | usleep_range(10, 20); | |
849 | } while (ktime_before(ktime_get(), timeout)); | |
850 | ||
851 | if (val & REG_INMAIL_OP_REQUEST) | |
852 | return -ETIMEDOUT; | |
853 | if (val & REG_INMAIL_ERROR) | |
854 | return -EIO; | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
859 | /** | |
860 | * nhi_mailbox_mode() - Return current firmware operation mode | |
861 | * @nhi: Pointer to the NHI structure | |
862 | * | |
863 | * The function reads current firmware operation mode using NHI mailbox | |
864 | * registers and returns it to the caller. | |
865 | */ | |
866 | enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi) | |
867 | { | |
868 | u32 val; | |
869 | ||
870 | val = ioread32(nhi->iobase + REG_OUTMAIL_CMD); | |
871 | val &= REG_OUTMAIL_CMD_OPMODE_MASK; | |
872 | val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT; | |
873 | ||
874 | return (enum nhi_fw_mode)val; | |
875 | } | |
876 | ||
16603153 AN |
877 | static void nhi_interrupt_work(struct work_struct *work) |
878 | { | |
879 | struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work); | |
880 | int value = 0; /* Suppress uninitialized usage warning. */ | |
881 | int bit; | |
882 | int hop = -1; | |
883 | int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */ | |
884 | struct tb_ring *ring; | |
885 | ||
59120e06 | 886 | spin_lock_irq(&nhi->lock); |
16603153 AN |
887 | |
888 | /* | |
889 | * Starting at REG_RING_NOTIFY_BASE there are three status bitfields | |
890 | * (TX, RX, RX overflow). We iterate over the bits and read a new | |
891 | * dwords as required. The registers are cleared on read. | |
892 | */ | |
893 | for (bit = 0; bit < 3 * nhi->hop_count; bit++) { | |
894 | if (bit % 32 == 0) | |
895 | value = ioread32(nhi->iobase | |
896 | + REG_RING_NOTIFY_BASE | |
897 | + 4 * (bit / 32)); | |
898 | if (++hop == nhi->hop_count) { | |
899 | hop = 0; | |
900 | type++; | |
901 | } | |
902 | if ((value & (1 << (bit % 32))) == 0) | |
903 | continue; | |
904 | if (type == 2) { | |
905 | dev_warn(&nhi->pdev->dev, | |
906 | "RX overflow for ring %d\n", | |
907 | hop); | |
908 | continue; | |
909 | } | |
910 | if (type == 0) | |
911 | ring = nhi->tx_rings[hop]; | |
912 | else | |
913 | ring = nhi->rx_rings[hop]; | |
914 | if (ring == NULL) { | |
915 | dev_warn(&nhi->pdev->dev, | |
916 | "got interrupt for inactive %s ring %d\n", | |
917 | type ? "RX" : "TX", | |
918 | hop); | |
919 | continue; | |
920 | } | |
4ffe722e MW |
921 | |
922 | spin_lock(&ring->lock); | |
923 | __ring_interrupt(ring); | |
924 | spin_unlock(&ring->lock); | |
16603153 | 925 | } |
59120e06 | 926 | spin_unlock_irq(&nhi->lock); |
16603153 AN |
927 | } |
928 | ||
929 | static irqreturn_t nhi_msi(int irq, void *data) | |
930 | { | |
931 | struct tb_nhi *nhi = data; | |
932 | schedule_work(&nhi->interrupt_work); | |
933 | return IRQ_HANDLED; | |
934 | } | |
935 | ||
3cdb9446 | 936 | static int __nhi_suspend_noirq(struct device *dev, bool wakeup) |
23dd5bb4 AN |
937 | { |
938 | struct pci_dev *pdev = to_pci_dev(dev); | |
939 | struct tb *tb = pci_get_drvdata(pdev); | |
3cdb9446 MW |
940 | struct tb_nhi *nhi = tb->nhi; |
941 | int ret; | |
942 | ||
943 | ret = tb_domain_suspend_noirq(tb); | |
944 | if (ret) | |
945 | return ret; | |
946 | ||
947 | if (nhi->ops && nhi->ops->suspend_noirq) { | |
948 | ret = nhi->ops->suspend_noirq(tb->nhi, wakeup); | |
949 | if (ret) | |
950 | return ret; | |
951 | } | |
952 | ||
953 | return 0; | |
954 | } | |
955 | ||
956 | static int nhi_suspend_noirq(struct device *dev) | |
957 | { | |
958 | return __nhi_suspend_noirq(dev, device_may_wakeup(dev)); | |
959 | } | |
960 | ||
884e4d57 MW |
961 | static int nhi_freeze_noirq(struct device *dev) |
962 | { | |
963 | struct pci_dev *pdev = to_pci_dev(dev); | |
964 | struct tb *tb = pci_get_drvdata(pdev); | |
965 | ||
966 | return tb_domain_freeze_noirq(tb); | |
967 | } | |
968 | ||
969 | static int nhi_thaw_noirq(struct device *dev) | |
970 | { | |
971 | struct pci_dev *pdev = to_pci_dev(dev); | |
972 | struct tb *tb = pci_get_drvdata(pdev); | |
973 | ||
974 | return tb_domain_thaw_noirq(tb); | |
975 | } | |
976 | ||
3cdb9446 MW |
977 | static bool nhi_wake_supported(struct pci_dev *pdev) |
978 | { | |
979 | u8 val; | |
980 | ||
981 | /* | |
982 | * If power rails are sustainable for wakeup from S4 this | |
983 | * property is set by the BIOS. | |
984 | */ | |
985 | if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val)) | |
986 | return !!val; | |
987 | ||
988 | return true; | |
989 | } | |
990 | ||
991 | static int nhi_poweroff_noirq(struct device *dev) | |
992 | { | |
993 | struct pci_dev *pdev = to_pci_dev(dev); | |
994 | bool wakeup; | |
9d3cce0b | 995 | |
3cdb9446 MW |
996 | wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev); |
997 | return __nhi_suspend_noirq(dev, wakeup); | |
23dd5bb4 AN |
998 | } |
999 | ||
8c6bba10 MW |
1000 | static void nhi_enable_int_throttling(struct tb_nhi *nhi) |
1001 | { | |
1002 | /* Throttling is specified in 256ns increments */ | |
1003 | u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256); | |
1004 | unsigned int i; | |
1005 | ||
1006 | /* | |
1007 | * Configure interrupt throttling for all vectors even if we | |
1008 | * only use few. | |
1009 | */ | |
1010 | for (i = 0; i < MSIX_MAX_VECS; i++) { | |
1011 | u32 reg = REG_INT_THROTTLING_RATE + i * 4; | |
1012 | iowrite32(throttle, nhi->iobase + reg); | |
1013 | } | |
1014 | } | |
1015 | ||
23dd5bb4 AN |
1016 | static int nhi_resume_noirq(struct device *dev) |
1017 | { | |
1018 | struct pci_dev *pdev = to_pci_dev(dev); | |
1019 | struct tb *tb = pci_get_drvdata(pdev); | |
3cdb9446 MW |
1020 | struct tb_nhi *nhi = tb->nhi; |
1021 | int ret; | |
9d3cce0b | 1022 | |
bdccf295 MW |
1023 | /* |
1024 | * Check that the device is still there. It may be that the user | |
1025 | * unplugged last device which causes the host controller to go | |
1026 | * away on PCs. | |
1027 | */ | |
3cdb9446 MW |
1028 | if (!pci_device_is_present(pdev)) { |
1029 | nhi->going_away = true; | |
1030 | } else { | |
1031 | if (nhi->ops && nhi->ops->resume_noirq) { | |
1032 | ret = nhi->ops->resume_noirq(nhi); | |
1033 | if (ret) | |
1034 | return ret; | |
1035 | } | |
8c6bba10 | 1036 | nhi_enable_int_throttling(tb->nhi); |
3cdb9446 | 1037 | } |
bdccf295 | 1038 | |
9d3cce0b | 1039 | return tb_domain_resume_noirq(tb); |
23dd5bb4 AN |
1040 | } |
1041 | ||
f67cf491 MW |
1042 | static int nhi_suspend(struct device *dev) |
1043 | { | |
1044 | struct pci_dev *pdev = to_pci_dev(dev); | |
1045 | struct tb *tb = pci_get_drvdata(pdev); | |
1046 | ||
1047 | return tb_domain_suspend(tb); | |
1048 | } | |
1049 | ||
1050 | static void nhi_complete(struct device *dev) | |
1051 | { | |
1052 | struct pci_dev *pdev = to_pci_dev(dev); | |
1053 | struct tb *tb = pci_get_drvdata(pdev); | |
1054 | ||
2d8ff0b5 MW |
1055 | /* |
1056 | * If we were runtime suspended when system suspend started, | |
1057 | * schedule runtime resume now. It should bring the domain back | |
1058 | * to functional state. | |
1059 | */ | |
1060 | if (pm_runtime_suspended(&pdev->dev)) | |
1061 | pm_runtime_resume(&pdev->dev); | |
1062 | else | |
1063 | tb_domain_complete(tb); | |
1064 | } | |
1065 | ||
1066 | static int nhi_runtime_suspend(struct device *dev) | |
1067 | { | |
1068 | struct pci_dev *pdev = to_pci_dev(dev); | |
1069 | struct tb *tb = pci_get_drvdata(pdev); | |
3cdb9446 MW |
1070 | struct tb_nhi *nhi = tb->nhi; |
1071 | int ret; | |
1072 | ||
1073 | ret = tb_domain_runtime_suspend(tb); | |
1074 | if (ret) | |
1075 | return ret; | |
2d8ff0b5 | 1076 | |
3cdb9446 MW |
1077 | if (nhi->ops && nhi->ops->runtime_suspend) { |
1078 | ret = nhi->ops->runtime_suspend(tb->nhi); | |
1079 | if (ret) | |
1080 | return ret; | |
1081 | } | |
1082 | return 0; | |
2d8ff0b5 MW |
1083 | } |
1084 | ||
1085 | static int nhi_runtime_resume(struct device *dev) | |
1086 | { | |
1087 | struct pci_dev *pdev = to_pci_dev(dev); | |
1088 | struct tb *tb = pci_get_drvdata(pdev); | |
3cdb9446 MW |
1089 | struct tb_nhi *nhi = tb->nhi; |
1090 | int ret; | |
1091 | ||
1092 | if (nhi->ops && nhi->ops->runtime_resume) { | |
1093 | ret = nhi->ops->runtime_resume(nhi); | |
1094 | if (ret) | |
1095 | return ret; | |
1096 | } | |
2d8ff0b5 | 1097 | |
3cdb9446 | 1098 | nhi_enable_int_throttling(nhi); |
2d8ff0b5 | 1099 | return tb_domain_runtime_resume(tb); |
f67cf491 MW |
1100 | } |
1101 | ||
16603153 AN |
1102 | static void nhi_shutdown(struct tb_nhi *nhi) |
1103 | { | |
1104 | int i; | |
daa5140f MW |
1105 | |
1106 | dev_dbg(&nhi->pdev->dev, "shutdown\n"); | |
16603153 AN |
1107 | |
1108 | for (i = 0; i < nhi->hop_count; i++) { | |
1109 | if (nhi->tx_rings[i]) | |
1110 | dev_WARN(&nhi->pdev->dev, | |
1111 | "TX ring %d is still active\n", i); | |
1112 | if (nhi->rx_rings[i]) | |
1113 | dev_WARN(&nhi->pdev->dev, | |
1114 | "RX ring %d is still active\n", i); | |
1115 | } | |
1116 | nhi_disable_interrupts(nhi); | |
1117 | /* | |
1118 | * We have to release the irq before calling flush_work. Otherwise an | |
1119 | * already executing IRQ handler could call schedule_work again. | |
1120 | */ | |
046bee1f MW |
1121 | if (!nhi->pdev->msix_enabled) { |
1122 | devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi); | |
1123 | flush_work(&nhi->interrupt_work); | |
1124 | } | |
046bee1f | 1125 | ida_destroy(&nhi->msix_ida); |
3cdb9446 MW |
1126 | |
1127 | if (nhi->ops && nhi->ops->shutdown) | |
1128 | nhi->ops->shutdown(nhi); | |
046bee1f MW |
1129 | } |
1130 | ||
e390909a SM |
1131 | static void nhi_check_quirks(struct tb_nhi *nhi) |
1132 | { | |
54669e2f MW |
1133 | if (nhi->pdev->vendor == PCI_VENDOR_ID_INTEL) { |
1134 | /* | |
1135 | * Intel hardware supports auto clear of the interrupt | |
1136 | * status register right after interrupt is being | |
1137 | * issued. | |
1138 | */ | |
e390909a | 1139 | nhi->quirks |= QUIRK_AUTO_CLEAR_INT; |
54669e2f MW |
1140 | |
1141 | switch (nhi->pdev->device) { | |
1142 | case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI: | |
1143 | case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI: | |
1144 | /* | |
1145 | * Falcon Ridge controller needs the end-to-end | |
1146 | * flow control workaround to avoid losing Rx | |
1147 | * packets when RING_FLAG_E2E is set. | |
1148 | */ | |
1149 | nhi->quirks |= QUIRK_E2E; | |
1150 | break; | |
1151 | } | |
1152 | } | |
e390909a SM |
1153 | } |
1154 | ||
86eaf4a5 RM |
1155 | static int nhi_check_iommu_pdev(struct pci_dev *pdev, void *data) |
1156 | { | |
1157 | if (!pdev->external_facing || | |
1158 | !device_iommu_capable(&pdev->dev, IOMMU_CAP_PRE_BOOT_PROTECTION)) | |
1159 | return 0; | |
1160 | *(bool *)data = true; | |
1161 | return 1; /* Stop walking */ | |
1162 | } | |
1163 | ||
1164 | static void nhi_check_iommu(struct tb_nhi *nhi) | |
1165 | { | |
1166 | struct pci_bus *bus = nhi->pdev->bus; | |
1167 | bool port_ok = false; | |
1168 | ||
1169 | /* | |
1170 | * Ideally what we'd do here is grab every PCI device that | |
1171 | * represents a tunnelling adapter for this NHI and check their | |
1172 | * status directly, but unfortunately USB4 seems to make it | |
1173 | * obnoxiously difficult to reliably make any correlation. | |
1174 | * | |
1175 | * So for now we'll have to bodge it... Hoping that the system | |
1176 | * is at least sane enough that an adapter is in the same PCI | |
1177 | * segment as its NHI, if we can find *something* on that segment | |
1178 | * which meets the requirements for Kernel DMA Protection, we'll | |
1179 | * take that to imply that firmware is aware and has (hopefully) | |
1180 | * done the right thing in general. We need to know that the PCI | |
1181 | * layer has seen the ExternalFacingPort property which will then | |
1182 | * inform the IOMMU layer to enforce the complete "untrusted DMA" | |
1183 | * flow, but also that the IOMMU driver itself can be trusted not | |
1184 | * to have been subverted by a pre-boot DMA attack. | |
1185 | */ | |
1186 | while (bus->parent) | |
1187 | bus = bus->parent; | |
1188 | ||
1189 | pci_walk_bus(bus, nhi_check_iommu_pdev, &port_ok); | |
1190 | ||
1191 | nhi->iommu_dma_protection = port_ok; | |
1192 | dev_dbg(&nhi->pdev->dev, "IOMMU DMA protection is %s\n", | |
1193 | str_enabled_disabled(port_ok)); | |
1194 | } | |
1195 | ||
046bee1f MW |
1196 | static int nhi_init_msi(struct tb_nhi *nhi) |
1197 | { | |
1198 | struct pci_dev *pdev = nhi->pdev; | |
8d9dcfff | 1199 | struct device *dev = &pdev->dev; |
046bee1f MW |
1200 | int res, irq, nvec; |
1201 | ||
1202 | /* In case someone left them on. */ | |
1203 | nhi_disable_interrupts(nhi); | |
1204 | ||
8c6bba10 MW |
1205 | nhi_enable_int_throttling(nhi); |
1206 | ||
046bee1f MW |
1207 | ida_init(&nhi->msix_ida); |
1208 | ||
1209 | /* | |
1210 | * The NHI has 16 MSI-X vectors or a single MSI. We first try to | |
1211 | * get all MSI-X vectors and if we succeed, each ring will have | |
1212 | * one MSI-X. If for some reason that does not work out, we | |
1213 | * fallback to a single MSI. | |
1214 | */ | |
1215 | nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS, | |
1216 | PCI_IRQ_MSIX); | |
1217 | if (nvec < 0) { | |
1218 | nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); | |
1219 | if (nvec < 0) | |
1220 | return nvec; | |
1221 | ||
1222 | INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work); | |
1223 | ||
1224 | irq = pci_irq_vector(nhi->pdev, 0); | |
1225 | if (irq < 0) | |
1226 | return irq; | |
1227 | ||
1228 | res = devm_request_irq(&pdev->dev, irq, nhi_msi, | |
1229 | IRQF_NO_SUSPEND, "thunderbolt", nhi); | |
8d9dcfff AS |
1230 | if (res) |
1231 | return dev_err_probe(dev, res, "request_irq failed, aborting\n"); | |
046bee1f MW |
1232 | } |
1233 | ||
1234 | return 0; | |
16603153 AN |
1235 | } |
1236 | ||
3cdb9446 MW |
1237 | static bool nhi_imr_valid(struct pci_dev *pdev) |
1238 | { | |
1239 | u8 val; | |
1240 | ||
1241 | if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val)) | |
1242 | return !!val; | |
1243 | ||
1244 | return true; | |
1245 | } | |
1246 | ||
c6da62a2 MW |
1247 | static struct tb *nhi_select_cm(struct tb_nhi *nhi) |
1248 | { | |
1249 | struct tb *tb; | |
1250 | ||
1251 | /* | |
1252 | * USB4 case is simple. If we got control of any of the | |
1253 | * capabilities, we use software CM. | |
1254 | */ | |
1255 | if (tb_acpi_is_native()) | |
1256 | return tb_probe(nhi); | |
1257 | ||
1258 | /* | |
1259 | * Either firmware based CM is running (we did not get control | |
1260 | * from the firmware) or this is pre-USB4 PC so try first | |
1261 | * firmware CM and then fallback to software CM. | |
1262 | */ | |
1263 | tb = icm_probe(nhi); | |
1264 | if (!tb) | |
1265 | tb = tb_probe(nhi); | |
1266 | ||
1267 | return tb; | |
1268 | } | |
1269 | ||
16603153 AN |
1270 | static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
1271 | { | |
8d9dcfff | 1272 | struct device *dev = &pdev->dev; |
16603153 | 1273 | struct tb_nhi *nhi; |
d6cc51cd | 1274 | struct tb *tb; |
16603153 AN |
1275 | int res; |
1276 | ||
8d9dcfff AS |
1277 | if (!nhi_imr_valid(pdev)) |
1278 | return dev_err_probe(dev, -ENODEV, "firmware image not valid, aborting\n"); | |
3cdb9446 | 1279 | |
16603153 | 1280 | res = pcim_enable_device(pdev); |
8d9dcfff AS |
1281 | if (res) |
1282 | return dev_err_probe(dev, res, "cannot enable PCI device, aborting\n"); | |
16603153 | 1283 | |
16603153 | 1284 | res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt"); |
8d9dcfff AS |
1285 | if (res) |
1286 | return dev_err_probe(dev, res, "cannot obtain PCI resources, aborting\n"); | |
16603153 AN |
1287 | |
1288 | nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL); | |
1289 | if (!nhi) | |
1290 | return -ENOMEM; | |
1291 | ||
1292 | nhi->pdev = pdev; | |
3cdb9446 | 1293 | nhi->ops = (const struct tb_nhi_ops *)id->driver_data; |
ca319f55 | 1294 | /* cannot fail - table is allocated in pcim_iomap_regions */ |
16603153 AN |
1295 | nhi->iobase = pcim_iomap_table(pdev)[0]; |
1296 | nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff; | |
8d9dcfff | 1297 | dev_dbg(dev, "total paths: %d\n", nhi->hop_count); |
16603153 | 1298 | |
2a211f32 HS |
1299 | nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count, |
1300 | sizeof(*nhi->tx_rings), GFP_KERNEL); | |
1301 | nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count, | |
1302 | sizeof(*nhi->rx_rings), GFP_KERNEL); | |
16603153 AN |
1303 | if (!nhi->tx_rings || !nhi->rx_rings) |
1304 | return -ENOMEM; | |
1305 | ||
e390909a | 1306 | nhi_check_quirks(nhi); |
86eaf4a5 | 1307 | nhi_check_iommu(nhi); |
e390909a | 1308 | |
046bee1f | 1309 | res = nhi_init_msi(nhi); |
8d9dcfff AS |
1310 | if (res) |
1311 | return dev_err_probe(dev, res, "cannot enable MSI, aborting\n"); | |
16603153 | 1312 | |
59120e06 | 1313 | spin_lock_init(&nhi->lock); |
16603153 | 1314 | |
dba3caf6 | 1315 | res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
8d9dcfff AS |
1316 | if (res) |
1317 | return dev_err_probe(dev, res, "failed to set DMA mask\n"); | |
dba3caf6 | 1318 | |
16603153 AN |
1319 | pci_set_master(pdev); |
1320 | ||
3cdb9446 MW |
1321 | if (nhi->ops && nhi->ops->init) { |
1322 | res = nhi->ops->init(nhi); | |
1323 | if (res) | |
1324 | return res; | |
1325 | } | |
1326 | ||
c6da62a2 | 1327 | tb = nhi_select_cm(nhi); |
8d9dcfff AS |
1328 | if (!tb) |
1329 | return dev_err_probe(dev, -ENODEV, | |
f67cf491 | 1330 | "failed to determine connection manager, aborting\n"); |
f67cf491 | 1331 | |
8d9dcfff | 1332 | dev_dbg(dev, "NHI initialized, starting thunderbolt\n"); |
9d3cce0b MW |
1333 | |
1334 | res = tb_domain_add(tb); | |
1335 | if (res) { | |
d6cc51cd AN |
1336 | /* |
1337 | * At this point the RX/TX rings might already have been | |
1338 | * activated. Do a proper shutdown. | |
1339 | */ | |
9d3cce0b | 1340 | tb_domain_put(tb); |
d6cc51cd | 1341 | nhi_shutdown(nhi); |
68a7a2ac | 1342 | return res; |
d6cc51cd AN |
1343 | } |
1344 | pci_set_drvdata(pdev, tb); | |
16603153 | 1345 | |
b2911a59 MW |
1346 | device_wakeup_enable(&pdev->dev); |
1347 | ||
2d8ff0b5 MW |
1348 | pm_runtime_allow(&pdev->dev); |
1349 | pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY); | |
1350 | pm_runtime_use_autosuspend(&pdev->dev); | |
1351 | pm_runtime_put_autosuspend(&pdev->dev); | |
1352 | ||
16603153 AN |
1353 | return 0; |
1354 | } | |
1355 | ||
1356 | static void nhi_remove(struct pci_dev *pdev) | |
1357 | { | |
d6cc51cd AN |
1358 | struct tb *tb = pci_get_drvdata(pdev); |
1359 | struct tb_nhi *nhi = tb->nhi; | |
9d3cce0b | 1360 | |
2d8ff0b5 MW |
1361 | pm_runtime_get_sync(&pdev->dev); |
1362 | pm_runtime_dont_use_autosuspend(&pdev->dev); | |
1363 | pm_runtime_forbid(&pdev->dev); | |
1364 | ||
9d3cce0b | 1365 | tb_domain_remove(tb); |
16603153 AN |
1366 | nhi_shutdown(nhi); |
1367 | } | |
1368 | ||
23dd5bb4 AN |
1369 | /* |
1370 | * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable | |
1371 | * the tunnels asap. A corresponding pci quirk blocks the downstream bridges | |
1372 | * resume_noirq until we are done. | |
1373 | */ | |
1374 | static const struct dev_pm_ops nhi_pm_ops = { | |
1375 | .suspend_noirq = nhi_suspend_noirq, | |
1376 | .resume_noirq = nhi_resume_noirq, | |
884e4d57 | 1377 | .freeze_noirq = nhi_freeze_noirq, /* |
23dd5bb4 AN |
1378 | * we just disable hotplug, the |
1379 | * pci-tunnels stay alive. | |
1380 | */ | |
884e4d57 | 1381 | .thaw_noirq = nhi_thaw_noirq, |
23dd5bb4 | 1382 | .restore_noirq = nhi_resume_noirq, |
f67cf491 | 1383 | .suspend = nhi_suspend, |
3cdb9446 | 1384 | .poweroff_noirq = nhi_poweroff_noirq, |
f67cf491 MW |
1385 | .poweroff = nhi_suspend, |
1386 | .complete = nhi_complete, | |
2d8ff0b5 MW |
1387 | .runtime_suspend = nhi_runtime_suspend, |
1388 | .runtime_resume = nhi_runtime_resume, | |
23dd5bb4 AN |
1389 | }; |
1390 | ||
620863f7 | 1391 | static struct pci_device_id nhi_ids[] = { |
16603153 AN |
1392 | /* |
1393 | * We have to specify class, the TB bridges use the same device and | |
1d111406 | 1394 | * vendor (sub)id on gen 1 and gen 2 controllers. |
16603153 | 1395 | */ |
19bf4d4f LW |
1396 | { |
1397 | .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, | |
1398 | .vendor = PCI_VENDOR_ID_INTEL, | |
1399 | .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, | |
1400 | .subvendor = 0x2222, .subdevice = 0x1111, | |
1401 | }, | |
16603153 AN |
1402 | { |
1403 | .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, | |
1d111406 LW |
1404 | .vendor = PCI_VENDOR_ID_INTEL, |
1405 | .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, | |
16603153 AN |
1406 | .subvendor = 0x2222, .subdevice = 0x1111, |
1407 | }, | |
82a6a81c XG |
1408 | { |
1409 | .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, | |
1410 | .vendor = PCI_VENDOR_ID_INTEL, | |
1411 | .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI, | |
1412 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, | |
1413 | }, | |
16603153 AN |
1414 | { |
1415 | .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, | |
1d111406 LW |
1416 | .vendor = PCI_VENDOR_ID_INTEL, |
1417 | .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI, | |
a42fb351 | 1418 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, |
16603153 | 1419 | }, |
5e2781bc MW |
1420 | |
1421 | /* Thunderbolt 3 */ | |
1422 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) }, | |
1423 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) }, | |
1424 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) }, | |
1425 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) }, | |
1426 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) }, | |
1427 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) }, | |
1428 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) }, | |
1429 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) }, | |
4bac471d RM |
1430 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) }, |
1431 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) }, | |
3cdb9446 MW |
1432 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0), |
1433 | .driver_data = (kernel_ulong_t)&icl_nhi_ops }, | |
1434 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1), | |
1435 | .driver_data = (kernel_ulong_t)&icl_nhi_ops }, | |
1c1aac98 | 1436 | /* Thunderbolt 4 */ |
57d8df68 MW |
1437 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0), |
1438 | .driver_data = (kernel_ulong_t)&icl_nhi_ops }, | |
1439 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1), | |
1440 | .driver_data = (kernel_ulong_t)&icl_nhi_ops }, | |
f6439c53 MW |
1441 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI0), |
1442 | .driver_data = (kernel_ulong_t)&icl_nhi_ops }, | |
1443 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI1), | |
1444 | .driver_data = (kernel_ulong_t)&icl_nhi_ops }, | |
13579486 AS |
1445 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI0), |
1446 | .driver_data = (kernel_ulong_t)&icl_nhi_ops }, | |
1447 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI1), | |
1448 | .driver_data = (kernel_ulong_t)&icl_nhi_ops }, | |
7ec58378 GS |
1449 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI0), |
1450 | .driver_data = (kernel_ulong_t)&icl_nhi_ops }, | |
1451 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI1), | |
1452 | .driver_data = (kernel_ulong_t)&icl_nhi_ops }, | |
32249fd8 MW |
1453 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_M_NHI0), |
1454 | .driver_data = (kernel_ulong_t)&icl_nhi_ops }, | |
1455 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI0), | |
1456 | .driver_data = (kernel_ulong_t)&icl_nhi_ops }, | |
1457 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI1), | |
1458 | .driver_data = (kernel_ulong_t)&icl_nhi_ops }, | |
5e2781bc | 1459 | |
b0407983 MW |
1460 | /* Any USB4 compliant host */ |
1461 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) }, | |
1462 | ||
16603153 AN |
1463 | { 0,} |
1464 | }; | |
1465 | ||
1466 | MODULE_DEVICE_TABLE(pci, nhi_ids); | |
1467 | MODULE_LICENSE("GPL"); | |
1468 | ||
1469 | static struct pci_driver nhi_driver = { | |
1470 | .name = "thunderbolt", | |
1471 | .id_table = nhi_ids, | |
1472 | .probe = nhi_probe, | |
1473 | .remove = nhi_remove, | |
4caf2511 | 1474 | .shutdown = nhi_remove, |
23dd5bb4 | 1475 | .driver.pm = &nhi_pm_ops, |
16603153 AN |
1476 | }; |
1477 | ||
1478 | static int __init nhi_init(void) | |
1479 | { | |
9d3cce0b MW |
1480 | int ret; |
1481 | ||
9d3cce0b MW |
1482 | ret = tb_domain_init(); |
1483 | if (ret) | |
1484 | return ret; | |
1485 | ret = pci_register_driver(&nhi_driver); | |
1486 | if (ret) | |
1487 | tb_domain_exit(); | |
1488 | return ret; | |
16603153 AN |
1489 | } |
1490 | ||
1491 | static void __exit nhi_unload(void) | |
1492 | { | |
1493 | pci_unregister_driver(&nhi_driver); | |
9d3cce0b | 1494 | tb_domain_exit(); |
16603153 AN |
1495 | } |
1496 | ||
eafa717b | 1497 | rootfs_initcall(nhi_init); |
16603153 | 1498 | module_exit(nhi_unload); |