Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c90553b3 | 2 | /* |
15c6784c | 3 | * Thunderbolt driver - eeprom access |
c90553b3 AN |
4 | * |
5 | * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> | |
15c6784c | 6 | * Copyright (C) 2018, Intel Corporation |
c90553b3 AN |
7 | */ |
8 | ||
cd22e73b | 9 | #include <linux/crc32.h> |
f022ff7b | 10 | #include <linux/delay.h> |
c9cc3aaa | 11 | #include <linux/property.h> |
2b35404e | 12 | #include <linux/slab.h> |
c90553b3 AN |
13 | #include "tb.h" |
14 | ||
ff48bc44 | 15 | /* |
c90553b3 AN |
16 | * tb_eeprom_ctl_write() - write control word |
17 | */ | |
18 | static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl) | |
19 | { | |
144c4a77 | 20 | return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + ROUTER_CS_4, 1); |
c90553b3 AN |
21 | } |
22 | ||
ff48bc44 | 23 | /* |
c90553b3 AN |
24 | * tb_eeprom_ctl_write() - read control word |
25 | */ | |
26 | static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl) | |
27 | { | |
144c4a77 | 28 | return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + ROUTER_CS_4, 1); |
c90553b3 AN |
29 | } |
30 | ||
31 | enum tb_eeprom_transfer { | |
32 | TB_EEPROM_IN, | |
33 | TB_EEPROM_OUT, | |
34 | }; | |
35 | ||
ff48bc44 | 36 | /* |
c90553b3 AN |
37 | * tb_eeprom_active - enable rom access |
38 | * | |
39 | * WARNING: Always disable access after usage. Otherwise the controller will | |
40 | * fail to reprobe. | |
41 | */ | |
42 | static int tb_eeprom_active(struct tb_switch *sw, bool enable) | |
43 | { | |
44 | struct tb_eeprom_ctl ctl; | |
45 | int res = tb_eeprom_ctl_read(sw, &ctl); | |
46 | if (res) | |
47 | return res; | |
48 | if (enable) { | |
144c4a77 | 49 | ctl.bit_banging_enable = 1; |
c90553b3 AN |
50 | res = tb_eeprom_ctl_write(sw, &ctl); |
51 | if (res) | |
52 | return res; | |
144c4a77 | 53 | ctl.fl_cs = 0; |
c90553b3 AN |
54 | return tb_eeprom_ctl_write(sw, &ctl); |
55 | } else { | |
144c4a77 | 56 | ctl.fl_cs = 1; |
c90553b3 AN |
57 | res = tb_eeprom_ctl_write(sw, &ctl); |
58 | if (res) | |
59 | return res; | |
144c4a77 | 60 | ctl.bit_banging_enable = 0; |
c90553b3 AN |
61 | return tb_eeprom_ctl_write(sw, &ctl); |
62 | } | |
63 | } | |
64 | ||
ff48bc44 | 65 | /* |
c90553b3 AN |
66 | * tb_eeprom_transfer - transfer one bit |
67 | * | |
144c4a77 ML |
68 | * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->fl_do. |
69 | * If TB_EEPROM_OUT is passed, then ctl->fl_di will be written. | |
c90553b3 AN |
70 | */ |
71 | static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl, | |
72 | enum tb_eeprom_transfer direction) | |
73 | { | |
74 | int res; | |
75 | if (direction == TB_EEPROM_OUT) { | |
76 | res = tb_eeprom_ctl_write(sw, ctl); | |
77 | if (res) | |
78 | return res; | |
79 | } | |
144c4a77 | 80 | ctl->fl_sk = 1; |
c90553b3 AN |
81 | res = tb_eeprom_ctl_write(sw, ctl); |
82 | if (res) | |
83 | return res; | |
84 | if (direction == TB_EEPROM_IN) { | |
85 | res = tb_eeprom_ctl_read(sw, ctl); | |
86 | if (res) | |
87 | return res; | |
88 | } | |
144c4a77 | 89 | ctl->fl_sk = 0; |
c90553b3 AN |
90 | return tb_eeprom_ctl_write(sw, ctl); |
91 | } | |
92 | ||
ff48bc44 | 93 | /* |
c90553b3 AN |
94 | * tb_eeprom_out - write one byte to the bus |
95 | */ | |
96 | static int tb_eeprom_out(struct tb_switch *sw, u8 val) | |
97 | { | |
98 | struct tb_eeprom_ctl ctl; | |
99 | int i; | |
100 | int res = tb_eeprom_ctl_read(sw, &ctl); | |
101 | if (res) | |
102 | return res; | |
103 | for (i = 0; i < 8; i++) { | |
144c4a77 | 104 | ctl.fl_di = val & 0x80; |
c90553b3 AN |
105 | res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT); |
106 | if (res) | |
107 | return res; | |
108 | val <<= 1; | |
109 | } | |
110 | return 0; | |
111 | } | |
112 | ||
ff48bc44 | 113 | /* |
c90553b3 AN |
114 | * tb_eeprom_in - read one byte from the bus |
115 | */ | |
116 | static int tb_eeprom_in(struct tb_switch *sw, u8 *val) | |
117 | { | |
118 | struct tb_eeprom_ctl ctl; | |
119 | int i; | |
120 | int res = tb_eeprom_ctl_read(sw, &ctl); | |
121 | if (res) | |
122 | return res; | |
123 | *val = 0; | |
124 | for (i = 0; i < 8; i++) { | |
125 | *val <<= 1; | |
126 | res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN); | |
127 | if (res) | |
128 | return res; | |
144c4a77 | 129 | *val |= ctl.fl_do; |
c90553b3 AN |
130 | } |
131 | return 0; | |
132 | } | |
133 | ||
ff48bc44 | 134 | /* |
4deb200d MW |
135 | * tb_eeprom_get_drom_offset - get drom offset within eeprom |
136 | */ | |
137 | static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset) | |
138 | { | |
139 | struct tb_cap_plug_events cap; | |
140 | int res; | |
141 | ||
142 | if (!sw->cap_plug_events) { | |
143 | tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n"); | |
144 | return -ENODEV; | |
145 | } | |
146 | res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events, | |
147 | sizeof(cap) / 4); | |
148 | if (res) | |
149 | return res; | |
150 | ||
151 | if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) { | |
152 | tb_sw_warn(sw, "no NVM\n"); | |
153 | return -ENODEV; | |
154 | } | |
155 | ||
156 | if (cap.drom_offset > 0xffff) { | |
157 | tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n", | |
158 | cap.drom_offset); | |
159 | return -ENXIO; | |
160 | } | |
161 | *offset = cap.drom_offset; | |
162 | return 0; | |
163 | } | |
164 | ||
ff48bc44 | 165 | /* |
c90553b3 AN |
166 | * tb_eeprom_read_n - read count bytes from offset into val |
167 | */ | |
168 | static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val, | |
169 | size_t count) | |
170 | { | |
4deb200d | 171 | u16 drom_offset; |
c90553b3 | 172 | int i, res; |
4deb200d MW |
173 | |
174 | res = tb_eeprom_get_drom_offset(sw, &drom_offset); | |
175 | if (res) | |
176 | return res; | |
177 | ||
178 | offset += drom_offset; | |
179 | ||
c90553b3 AN |
180 | res = tb_eeprom_active(sw, true); |
181 | if (res) | |
182 | return res; | |
183 | res = tb_eeprom_out(sw, 3); | |
184 | if (res) | |
185 | return res; | |
186 | res = tb_eeprom_out(sw, offset >> 8); | |
187 | if (res) | |
188 | return res; | |
189 | res = tb_eeprom_out(sw, offset); | |
190 | if (res) | |
191 | return res; | |
192 | for (i = 0; i < count; i++) { | |
193 | res = tb_eeprom_in(sw, val + i); | |
194 | if (res) | |
195 | return res; | |
196 | } | |
197 | return tb_eeprom_active(sw, false); | |
198 | } | |
199 | ||
cd22e73b AN |
200 | static u8 tb_crc8(u8 *data, int len) |
201 | { | |
202 | int i, j; | |
203 | u8 val = 0xff; | |
204 | for (i = 0; i < len; i++) { | |
205 | val ^= data[i]; | |
206 | for (j = 0; j < 8; j++) | |
207 | val = (val << 1) ^ ((val & 0x80) ? 7 : 0); | |
208 | } | |
209 | return val; | |
210 | } | |
211 | ||
212 | static u32 tb_crc32(void *data, size_t len) | |
213 | { | |
214 | return ~__crc32c_le(~0, data, len); | |
215 | } | |
216 | ||
b18f9013 GF |
217 | #define TB_DROM_DATA_START 13 |
218 | #define TB_DROM_HEADER_SIZE 22 | |
219 | #define USB4_DROM_HEADER_SIZE 16 | |
220 | ||
cd22e73b AN |
221 | struct tb_drom_header { |
222 | /* BYTE 0 */ | |
223 | u8 uid_crc8; /* checksum for uid */ | |
224 | /* BYTES 1-8 */ | |
225 | u64 uid; | |
226 | /* BYTES 9-12 */ | |
227 | u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */ | |
228 | /* BYTE 13 */ | |
229 | u8 device_rom_revision; /* should be <= 1 */ | |
b18f9013 GF |
230 | u16 data_len:12; |
231 | u8 reserved:4; | |
232 | /* BYTES 16-21 - Only for TBT DROM, nonexistent in USB4 DROM */ | |
cd22e73b AN |
233 | u16 vendor_id; |
234 | u16 model_id; | |
235 | u8 model_rev; | |
236 | u8 eeprom_rev; | |
237 | } __packed; | |
238 | ||
239 | enum tb_drom_entry_type { | |
e7120778 AN |
240 | /* force unsigned to prevent "one-bit signed bitfield" warning */ |
241 | TB_DROM_ENTRY_GENERIC = 0U, | |
cd22e73b AN |
242 | TB_DROM_ENTRY_PORT, |
243 | }; | |
244 | ||
245 | struct tb_drom_entry_header { | |
246 | u8 len; | |
247 | u8 index:6; | |
248 | bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */ | |
249 | enum tb_drom_entry_type type:1; | |
250 | } __packed; | |
251 | ||
72ee3390 MW |
252 | struct tb_drom_entry_generic { |
253 | struct tb_drom_entry_header header; | |
c2a9fca1 | 254 | u8 data[]; |
72ee3390 MW |
255 | } __packed; |
256 | ||
cd22e73b AN |
257 | struct tb_drom_entry_port { |
258 | /* BYTES 0-1 */ | |
259 | struct tb_drom_entry_header header; | |
260 | /* BYTE 2 */ | |
261 | u8 dual_link_port_rid:4; | |
262 | u8 link_nr:1; | |
263 | u8 unknown1:2; | |
264 | bool has_dual_link_port:1; | |
265 | ||
266 | /* BYTE 3 */ | |
267 | u8 dual_link_port_nr:6; | |
268 | u8 unknown2:2; | |
269 | ||
270 | /* BYTES 4 - 5 TODO decode */ | |
271 | u8 micro2:4; | |
272 | u8 micro1:4; | |
273 | u8 micro3; | |
274 | ||
aae20bb6 | 275 | /* BYTES 6-7, TODO: verify (find hardware that has these set) */ |
cd22e73b AN |
276 | u8 peer_port_rid:4; |
277 | u8 unknown3:3; | |
278 | bool has_peer_port:1; | |
279 | u8 peer_port_nr:6; | |
280 | u8 unknown4:2; | |
281 | } __packed; | |
282 | ||
3231307e MW |
283 | /* USB4 product descriptor */ |
284 | struct tb_drom_entry_desc { | |
285 | struct tb_drom_entry_header header; | |
286 | u16 bcdUSBSpec; | |
287 | u16 idVendor; | |
288 | u16 idProduct; | |
289 | u16 bcdProductFWRevision; | |
290 | u32 TID; | |
291 | u8 productHWRevision; | |
292 | }; | |
cd22e73b | 293 | |
cd22e73b | 294 | /** |
b12e4824 MW |
295 | * tb_drom_read_uid_only() - Read UID directly from DROM |
296 | * @sw: Router whose UID to read | |
297 | * @uid: UID is placed here | |
cd22e73b AN |
298 | * |
299 | * Does not use the cached copy in sw->drom. Used during resume to check switch | |
300 | * identity. | |
301 | */ | |
302 | int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid) | |
303 | { | |
304 | u8 data[9]; | |
cd22e73b | 305 | u8 crc; |
4deb200d | 306 | int res; |
df1421b5 | 307 | |
c90553b3 | 308 | /* read uid */ |
4deb200d | 309 | res = tb_eeprom_read_n(sw, 0, data, 9); |
c90553b3 AN |
310 | if (res) |
311 | return res; | |
cd22e73b AN |
312 | |
313 | crc = tb_crc8(data + 1, 8); | |
314 | if (crc != data[0]) { | |
eb7bfcce | 315 | tb_sw_warn(sw, "uid crc8 mismatch (expected: %#x, got: %#x)\n", |
cd22e73b AN |
316 | data[0], crc); |
317 | return -EIO; | |
318 | } | |
319 | ||
c90553b3 AN |
320 | *uid = *(u64 *)(data+1); |
321 | return 0; | |
322 | } | |
323 | ||
72ee3390 MW |
324 | static int tb_drom_parse_entry_generic(struct tb_switch *sw, |
325 | struct tb_drom_entry_header *header) | |
326 | { | |
327 | const struct tb_drom_entry_generic *entry = | |
328 | (const struct tb_drom_entry_generic *)header; | |
329 | ||
330 | switch (header->index) { | |
331 | case 1: | |
332 | /* Length includes 2 bytes header so remove it before copy */ | |
333 | sw->vendor_name = kstrndup(entry->data, | |
334 | header->len - sizeof(*header), GFP_KERNEL); | |
335 | if (!sw->vendor_name) | |
336 | return -ENOMEM; | |
337 | break; | |
338 | ||
339 | case 2: | |
340 | sw->device_name = kstrndup(entry->data, | |
341 | header->len - sizeof(*header), GFP_KERNEL); | |
342 | if (!sw->device_name) | |
343 | return -ENOMEM; | |
344 | break; | |
3231307e MW |
345 | case 9: { |
346 | const struct tb_drom_entry_desc *desc = | |
347 | (const struct tb_drom_entry_desc *)entry; | |
348 | ||
349 | if (!sw->vendor && !sw->device) { | |
350 | sw->vendor = desc->idVendor; | |
351 | sw->device = desc->idProduct; | |
352 | } | |
353 | break; | |
354 | } | |
72ee3390 MW |
355 | } |
356 | ||
357 | return 0; | |
358 | } | |
359 | ||
02b17a41 LW |
360 | static int tb_drom_parse_entry_port(struct tb_switch *sw, |
361 | struct tb_drom_entry_header *header) | |
cd22e73b AN |
362 | { |
363 | struct tb_port *port; | |
364 | int res; | |
365 | enum tb_port_type type; | |
c90553b3 | 366 | |
1cd65d17 MW |
367 | /* |
368 | * Some DROMs list more ports than the controller actually has | |
369 | * so we skip those but allow the parser to continue. | |
370 | */ | |
371 | if (header->index > sw->config.max_port_number) { | |
372 | dev_info_once(&sw->dev, "ignoring unnecessary extra entries in DROM\n"); | |
373 | return 0; | |
374 | } | |
375 | ||
cd22e73b AN |
376 | port = &sw->ports[header->index]; |
377 | port->disabled = header->port_disabled; | |
378 | if (port->disabled) | |
379 | return 0; | |
380 | ||
381 | res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1); | |
382 | if (res) | |
383 | return res; | |
384 | type &= 0xffffff; | |
385 | ||
386 | if (type == TB_TYPE_PORT) { | |
387 | struct tb_drom_entry_port *entry = (void *) header; | |
388 | if (header->len != sizeof(*entry)) { | |
389 | tb_sw_warn(sw, | |
3543fb77 | 390 | "port entry has size %#x (expected %#zx)\n", |
cd22e73b AN |
391 | header->len, sizeof(struct tb_drom_entry_port)); |
392 | return -EIO; | |
393 | } | |
02b17a41 LW |
394 | port->link_nr = entry->link_nr; |
395 | if (entry->has_dual_link_port) | |
396 | port->dual_link_port = | |
397 | &port->sw->ports[entry->dual_link_port_nr]; | |
cd22e73b AN |
398 | } |
399 | return 0; | |
400 | } | |
401 | ||
ff48bc44 | 402 | /* |
cd22e73b AN |
403 | * tb_drom_parse_entries - parse the linked list of drom entries |
404 | * | |
405 | * Drom must have been copied to sw->drom. | |
406 | */ | |
b18f9013 | 407 | static int tb_drom_parse_entries(struct tb_switch *sw, size_t header_size) |
cd22e73b AN |
408 | { |
409 | struct tb_drom_header *header = (void *) sw->drom; | |
b18f9013 | 410 | u16 pos = header_size; |
cd22e73b | 411 | u16 drom_size = header->data_len + TB_DROM_DATA_START; |
02b17a41 | 412 | int res; |
cd22e73b AN |
413 | |
414 | while (pos < drom_size) { | |
415 | struct tb_drom_entry_header *entry = (void *) (sw->drom + pos); | |
416 | if (pos + 1 == drom_size || pos + entry->len > drom_size | |
417 | || !entry->len) { | |
f022ff7b | 418 | tb_sw_warn(sw, "DROM buffer overrun\n"); |
ebde5ba2 | 419 | return -EIO; |
cd22e73b AN |
420 | } |
421 | ||
02b17a41 LW |
422 | switch (entry->type) { |
423 | case TB_DROM_ENTRY_GENERIC: | |
72ee3390 | 424 | res = tb_drom_parse_entry_generic(sw, entry); |
02b17a41 LW |
425 | break; |
426 | case TB_DROM_ENTRY_PORT: | |
427 | res = tb_drom_parse_entry_port(sw, entry); | |
428 | break; | |
429 | } | |
430 | if (res) | |
431 | return res; | |
cd22e73b AN |
432 | |
433 | pos += entry->len; | |
434 | } | |
435 | return 0; | |
436 | } | |
437 | ||
ff48bc44 | 438 | /* |
c9cc3aaa LW |
439 | * tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present |
440 | */ | |
441 | static int tb_drom_copy_efi(struct tb_switch *sw, u16 *size) | |
442 | { | |
443 | struct device *dev = &sw->tb->nhi->pdev->dev; | |
444 | int len, res; | |
445 | ||
100c12f2 | 446 | len = device_property_count_u8(dev, "ThunderboltDROM"); |
c9cc3aaa LW |
447 | if (len < 0 || len < sizeof(struct tb_drom_header)) |
448 | return -EINVAL; | |
449 | ||
450 | sw->drom = kmalloc(len, GFP_KERNEL); | |
451 | if (!sw->drom) | |
452 | return -ENOMEM; | |
453 | ||
454 | res = device_property_read_u8_array(dev, "ThunderboltDROM", sw->drom, | |
455 | len); | |
456 | if (res) | |
457 | goto err; | |
458 | ||
459 | *size = ((struct tb_drom_header *)sw->drom)->data_len + | |
460 | TB_DROM_DATA_START; | |
461 | if (*size > len) | |
462 | goto err; | |
463 | ||
464 | return 0; | |
465 | ||
466 | err: | |
467 | kfree(sw->drom); | |
468 | sw->drom = NULL; | |
469 | return -EINVAL; | |
470 | } | |
471 | ||
3e136768 MW |
472 | static int tb_drom_copy_nvm(struct tb_switch *sw, u16 *size) |
473 | { | |
c8325b32 | 474 | u16 drom_offset; |
3e136768 MW |
475 | int ret; |
476 | ||
477 | if (!sw->dma_port) | |
478 | return -ENODEV; | |
479 | ||
c8325b32 | 480 | ret = tb_eeprom_get_drom_offset(sw, &drom_offset); |
3e136768 MW |
481 | if (ret) |
482 | return ret; | |
483 | ||
484 | if (!drom_offset) | |
485 | return -ENODEV; | |
486 | ||
487 | ret = dma_port_flash_read(sw->dma_port, drom_offset + 14, size, | |
488 | sizeof(*size)); | |
489 | if (ret) | |
490 | return ret; | |
491 | ||
492 | /* Size includes CRC8 + UID + CRC32 */ | |
493 | *size += 1 + 8 + 4; | |
494 | sw->drom = kzalloc(*size, GFP_KERNEL); | |
495 | if (!sw->drom) | |
496 | return -ENOMEM; | |
497 | ||
498 | ret = dma_port_flash_read(sw->dma_port, drom_offset, sw->drom, *size); | |
499 | if (ret) | |
500 | goto err_free; | |
501 | ||
502 | /* | |
503 | * Read UID from the minimal DROM because the one in NVM is just | |
504 | * a placeholder. | |
505 | */ | |
506 | tb_drom_read_uid_only(sw, &sw->uid); | |
507 | return 0; | |
508 | ||
509 | err_free: | |
510 | kfree(sw->drom); | |
511 | sw->drom = NULL; | |
512 | return ret; | |
513 | } | |
514 | ||
ebde5ba2 | 515 | static int usb4_copy_drom(struct tb_switch *sw, u16 *size) |
b0407983 MW |
516 | { |
517 | int ret; | |
518 | ||
519 | ret = usb4_switch_drom_read(sw, 14, size, sizeof(*size)); | |
520 | if (ret) | |
521 | return ret; | |
522 | ||
523 | /* Size includes CRC8 + UID + CRC32 */ | |
524 | *size += 1 + 8 + 4; | |
525 | sw->drom = kzalloc(*size, GFP_KERNEL); | |
526 | if (!sw->drom) | |
527 | return -ENOMEM; | |
528 | ||
529 | ret = usb4_switch_drom_read(sw, 0, sw->drom, *size); | |
530 | if (ret) { | |
531 | kfree(sw->drom); | |
532 | sw->drom = NULL; | |
533 | } | |
534 | ||
535 | return ret; | |
536 | } | |
537 | ||
ebde5ba2 | 538 | static int tb_drom_bit_bang(struct tb_switch *sw, u16 *size) |
b0407983 | 539 | { |
ebde5ba2 ML |
540 | int ret; |
541 | ||
542 | ret = tb_eeprom_read_n(sw, 14, (u8 *)size, 2); | |
543 | if (ret) | |
544 | return ret; | |
545 | ||
546 | *size &= 0x3ff; | |
547 | *size += TB_DROM_DATA_START; | |
548 | ||
549 | tb_sw_dbg(sw, "reading DROM (length: %#x)\n", *size); | |
550 | if (*size < sizeof(struct tb_drom_header)) { | |
551 | tb_sw_warn(sw, "DROM too small, aborting\n"); | |
552 | return -EIO; | |
553 | } | |
554 | ||
555 | sw->drom = kzalloc(*size, GFP_KERNEL); | |
556 | if (!sw->drom) | |
557 | return -ENOMEM; | |
558 | ||
559 | ret = tb_eeprom_read_n(sw, 0, sw->drom, *size); | |
560 | if (ret) | |
561 | goto err; | |
562 | ||
563 | return 0; | |
564 | ||
565 | err: | |
566 | kfree(sw->drom); | |
567 | sw->drom = NULL; | |
568 | return ret; | |
b0407983 MW |
569 | } |
570 | ||
ebde5ba2 | 571 | static int tb_drom_parse_v1(struct tb_switch *sw) |
3231307e MW |
572 | { |
573 | const struct tb_drom_header *header = | |
574 | (const struct tb_drom_header *)sw->drom; | |
575 | u32 crc; | |
576 | ||
577 | crc = tb_crc8((u8 *) &header->uid, 8); | |
578 | if (crc != header->uid_crc8) { | |
579 | tb_sw_warn(sw, | |
e87491a9 | 580 | "DROM UID CRC8 mismatch (expected: %#x, got: %#x)\n", |
3231307e | 581 | header->uid_crc8, crc); |
ebde5ba2 | 582 | return -EIO; |
3231307e MW |
583 | } |
584 | if (!sw->uid) | |
585 | sw->uid = header->uid; | |
586 | sw->vendor = header->vendor_id; | |
587 | sw->device = header->model_id; | |
588 | ||
589 | crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len); | |
590 | if (crc != header->data_crc32) { | |
591 | tb_sw_warn(sw, | |
592 | "DROM data CRC32 mismatch (expected: %#x, got: %#x), continuing\n", | |
593 | header->data_crc32, crc); | |
594 | } | |
595 | ||
b18f9013 | 596 | return tb_drom_parse_entries(sw, TB_DROM_HEADER_SIZE); |
3231307e MW |
597 | } |
598 | ||
599 | static int usb4_drom_parse(struct tb_switch *sw) | |
600 | { | |
601 | const struct tb_drom_header *header = | |
602 | (const struct tb_drom_header *)sw->drom; | |
603 | u32 crc; | |
604 | ||
605 | crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len); | |
606 | if (crc != header->data_crc32) { | |
607 | tb_sw_warn(sw, | |
608 | "DROM data CRC32 mismatch (expected: %#x, got: %#x), aborting\n", | |
609 | header->data_crc32, crc); | |
610 | return -EINVAL; | |
611 | } | |
612 | ||
b18f9013 | 613 | return tb_drom_parse_entries(sw, USB4_DROM_HEADER_SIZE); |
3231307e MW |
614 | } |
615 | ||
ebde5ba2 | 616 | static int tb_drom_parse(struct tb_switch *sw, u16 size) |
cd22e73b | 617 | { |
ebde5ba2 ML |
618 | const struct tb_drom_header *header = (const void *)sw->drom; |
619 | int ret; | |
cd22e73b AN |
620 | |
621 | if (header->data_len + TB_DROM_DATA_START != size) { | |
ebde5ba2 ML |
622 | tb_sw_warn(sw, "DROM size mismatch\n"); |
623 | ret = -EIO; | |
cd22e73b AN |
624 | goto err; |
625 | } | |
626 | ||
3231307e | 627 | tb_sw_dbg(sw, "DROM version: %d\n", header->device_rom_revision); |
cd22e73b | 628 | |
3231307e MW |
629 | switch (header->device_rom_revision) { |
630 | case 3: | |
ebde5ba2 | 631 | ret = usb4_drom_parse(sw); |
3231307e MW |
632 | break; |
633 | default: | |
634 | tb_sw_warn(sw, "DROM device_rom_revision %#x unknown\n", | |
635 | header->device_rom_revision); | |
636 | fallthrough; | |
637 | case 1: | |
ebde5ba2 | 638 | ret = tb_drom_parse_v1(sw); |
3231307e | 639 | break; |
cd22e73b AN |
640 | } |
641 | ||
ebde5ba2 | 642 | if (ret) { |
e87491a9 | 643 | tb_sw_warn(sw, "parsing DROM failed\n"); |
ebde5ba2 | 644 | goto err; |
f022ff7b MW |
645 | } |
646 | ||
ebde5ba2 | 647 | return 0; |
3231307e | 648 | |
cd22e73b AN |
649 | err: |
650 | kfree(sw->drom); | |
2ffa9a5d | 651 | sw->drom = NULL; |
ebde5ba2 ML |
652 | |
653 | return ret; | |
654 | } | |
655 | ||
656 | static int tb_drom_host_read(struct tb_switch *sw) | |
657 | { | |
658 | u16 size; | |
659 | ||
660 | if (tb_switch_is_usb4(sw)) { | |
661 | usb4_switch_read_uid(sw, &sw->uid); | |
662 | if (!usb4_copy_drom(sw, &size)) | |
663 | return tb_drom_parse(sw, size); | |
664 | } else { | |
665 | if (!tb_drom_copy_efi(sw, &size)) | |
666 | return tb_drom_parse(sw, size); | |
667 | ||
668 | if (!tb_drom_copy_nvm(sw, &size)) | |
669 | return tb_drom_parse(sw, size); | |
670 | ||
671 | tb_drom_read_uid_only(sw, &sw->uid); | |
672 | } | |
673 | ||
674 | return 0; | |
675 | } | |
676 | ||
677 | static int tb_drom_device_read(struct tb_switch *sw) | |
678 | { | |
679 | u16 size; | |
680 | int ret; | |
681 | ||
682 | if (tb_switch_is_usb4(sw)) { | |
683 | usb4_switch_read_uid(sw, &sw->uid); | |
684 | ret = usb4_copy_drom(sw, &size); | |
685 | } else { | |
686 | ret = tb_drom_bit_bang(sw, &size); | |
687 | } | |
688 | ||
689 | if (ret) | |
690 | return ret; | |
691 | ||
692 | return tb_drom_parse(sw, size); | |
693 | } | |
694 | ||
695 | /** | |
696 | * tb_drom_read() - Copy DROM to sw->drom and parse it | |
697 | * @sw: Router whose DROM to read and parse | |
698 | * | |
699 | * This function reads router DROM and if successful parses the entries and | |
700 | * populates the fields in @sw accordingly. Can be called for any router | |
701 | * generation. | |
702 | * | |
703 | * Returns %0 in case of success and negative errno otherwise. | |
704 | */ | |
705 | int tb_drom_read(struct tb_switch *sw) | |
706 | { | |
707 | if (sw->drom) | |
708 | return 0; | |
709 | ||
710 | if (!tb_route(sw)) | |
711 | return tb_drom_host_read(sw); | |
712 | return tb_drom_device_read(sw); | |
cd22e73b | 713 | } |