[linux-block.git] / drivers / thunderbolt / clx.c

// SPDX-License-Identifier: GPL-2.0
/*
 * CLx support
 *
 * Copyright (C) 2020 - 2023, Intel Corporation
 * Authors: Gil Fine <gil.fine@intel.com>
 *	    Mika Westerberg <mika.westerberg@linux.intel.com>
 */

#include <linux/module.h>

#include "tb.h"

static bool clx_enabled = true;
module_param_named(clx, clx_enabled, bool, 0444);
MODULE_PARM_DESC(clx, "allow low power states on the high-speed lanes (default: true)");

static const char *clx_name(unsigned int clx)
{
	switch (clx) {
	case TB_CL0S | TB_CL1 | TB_CL2:
		return "CL0s/CL1/CL2";
	case TB_CL1 | TB_CL2:
		return "CL1/CL2";
	case TB_CL0S | TB_CL2:
		return "CL0s/CL2";
	case TB_CL0S | TB_CL1:
		return "CL0s/CL1";
	case TB_CL0S:
		return "CL0s";
	case 0:
		return "disabled";
	default:
		return "unknown";
	}
}

static int tb_port_pm_secondary_set(struct tb_port *port, bool secondary)
{
	u32 phy;
	int ret;

	ret = tb_port_read(port, &phy, TB_CFG_PORT,
			   port->cap_phy + LANE_ADP_CS_1, 1);
	if (ret)
		return ret;

	if (secondary)
		phy |= LANE_ADP_CS_1_PMS;
	else
		phy &= ~LANE_ADP_CS_1_PMS;

	return tb_port_write(port, &phy, TB_CFG_PORT,
			     port->cap_phy + LANE_ADP_CS_1, 1);
}

static int tb_port_pm_secondary_enable(struct tb_port *port)
{
	return tb_port_pm_secondary_set(port, true);
}

static int tb_port_pm_secondary_disable(struct tb_port *port)
{
	return tb_port_pm_secondary_set(port, false);
}

/* Called for USB4 or Titan Ridge routers only */
static bool tb_port_clx_supported(struct tb_port *port, unsigned int clx)
{
	u32 val, mask = 0;
	bool ret;

	/* Don't enable CLx in case of two single-lane links */
	if (!port->bonded && port->dual_link_port)
		return false;

	/* Don't enable CLx in case of inter-domain link */
	if (port->xdomain)
		return false;

	if (tb_switch_is_usb4(port->sw)) {
		if (!usb4_port_clx_supported(port))
			return false;
	} else if (!tb_lc_is_clx_supported(port)) {
		return false;
	}

	if (clx & TB_CL0S)
		mask |= LANE_ADP_CS_0_CL0S_SUPPORT;
	if (clx & TB_CL1)
		mask |= LANE_ADP_CS_0_CL1_SUPPORT;
	if (clx & TB_CL2)
		mask |= LANE_ADP_CS_0_CL2_SUPPORT;

	ret = tb_port_read(port, &val, TB_CFG_PORT,
			   port->cap_phy + LANE_ADP_CS_0, 1);
	if (ret)
		return false;

	return !!(val & mask);
}

static int tb_port_clx_set(struct tb_port *port, unsigned int clx, bool enable)
{
	u32 phy, mask = 0;
	int ret;

	if (clx & TB_CL0S)
		mask |= LANE_ADP_CS_1_CL0S_ENABLE;
	if (clx & TB_CL1)
		mask |= LANE_ADP_CS_1_CL1_ENABLE;
	if (clx & TB_CL2)
		mask |= LANE_ADP_CS_1_CL2_ENABLE;

	if (!mask)
		return -EOPNOTSUPP;

	ret = tb_port_read(port, &phy, TB_CFG_PORT,
			   port->cap_phy + LANE_ADP_CS_1, 1);
	if (ret)
		return ret;

	if (enable)
		phy |= mask;
	else
		phy &= ~mask;

	return tb_port_write(port, &phy, TB_CFG_PORT,
			     port->cap_phy + LANE_ADP_CS_1, 1);
}

static int tb_port_clx_disable(struct tb_port *port, unsigned int clx)
{
	return tb_port_clx_set(port, clx, false);
}

static int tb_port_clx_enable(struct tb_port *port, unsigned int clx)
{
	return tb_port_clx_set(port, clx, true);
}

static int tb_port_clx(struct tb_port *port)
{
	u32 val;
	int ret;

	if (!tb_port_clx_supported(port, TB_CL0S | TB_CL1 | TB_CL2))
		return 0;

	ret = tb_port_read(port, &val, TB_CFG_PORT,
			   port->cap_phy + LANE_ADP_CS_1, 1);
	if (ret)
		return ret;

	if (val & LANE_ADP_CS_1_CL0S_ENABLE)
		ret |= TB_CL0S;
	if (val & LANE_ADP_CS_1_CL1_ENABLE)
		ret |= TB_CL1;
	if (val & LANE_ADP_CS_1_CL2_ENABLE)
		ret |= TB_CL2;

	return ret;
}

/**
 * tb_port_clx_is_enabled() - Is given CL state enabled
 * @port: USB4 port to check
 * @clx: Mask of CL states to check
 *
 * Returns true if any of the given CL states is enabled for @port.
 */
bool tb_port_clx_is_enabled(struct tb_port *port, unsigned int clx)
{
	return !!(tb_port_clx(port) & clx);
}

/**
 * tb_switch_clx_init() - Initialize router CL states
 * @sw: Router
 *
 * Can be called for any router. Initializes the current CL state by
 * reading it from the hardware.
 *
 * Returns %0 in case of success and negative errno in case of failure.
 */
int tb_switch_clx_init(struct tb_switch *sw)
{
	struct tb_port *up, *down;
	unsigned int clx, tmp;

	if (tb_switch_is_icm(sw))
		return 0;

	if (!tb_route(sw))
		return 0;

	if (!tb_switch_clx_is_supported(sw))
		return 0;

	up = tb_upstream_port(sw);
	down = tb_switch_downstream_port(sw);

	clx = tb_port_clx(up);
	tmp = tb_port_clx(down);
	if (clx != tmp)
		tb_sw_warn(sw, "CLx: inconsistent configuration %#x != %#x\n",
			   clx, tmp);

	tb_sw_dbg(sw, "CLx: current mode: %s\n", clx_name(clx));

	sw->clx = clx;
	return 0;
}

static int tb_switch_pm_secondary_resolve(struct tb_switch *sw)
{
	struct tb_port *up, *down;
	int ret;

	if (!tb_route(sw))
		return 0;

	up = tb_upstream_port(sw);
	down = tb_switch_downstream_port(sw);
	ret = tb_port_pm_secondary_enable(up);
	if (ret)
		return ret;

	return tb_port_pm_secondary_disable(down);
}

static int tb_switch_mask_clx_objections(struct tb_switch *sw)
{
	int up_port = sw->config.upstream_port_number;
	u32 offset, val[2], mask_obj, unmask_obj;
	int ret, i;

	/* Only Titan Ridge of pre-USB4 devices support CLx states */
	if (!tb_switch_is_titan_ridge(sw))
		return 0;

	if (!tb_route(sw))
		return 0;

	/*
	 * In Titan Ridge there are only 2 dual-lane Thunderbolt ports:
	 * Port A consists of lane adapters 1,2 and
	 * Port B consists of lane adapters 3,4
	 * If upstream port is A, (lanes are 1,2), we mask objections from
	 * port B (lanes 3,4) and unmask objections from Port A and vice-versa.
	 */
	if (up_port == 1) {
		mask_obj = TB_LOW_PWR_C0_PORT_B_MASK;
		unmask_obj = TB_LOW_PWR_C1_PORT_A_MASK;
		offset = TB_LOW_PWR_C1_CL1;
	} else {
		mask_obj = TB_LOW_PWR_C1_PORT_A_MASK;
		unmask_obj = TB_LOW_PWR_C0_PORT_B_MASK;
		offset = TB_LOW_PWR_C3_CL1;
	}

	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
			 sw->cap_lp + offset, ARRAY_SIZE(val));
	if (ret)
		return ret;

	for (i = 0; i < ARRAY_SIZE(val); i++) {
		val[i] |= mask_obj;
		val[i] &= ~unmask_obj;
	}

	return tb_sw_write(sw, &val, TB_CFG_SWITCH,
			   sw->cap_lp + offset, ARRAY_SIZE(val));
}

/**
 * tb_switch_clx_is_supported() - Is CLx supported on this type of router
 * @sw: The router to check CLx support for
 */
bool tb_switch_clx_is_supported(const struct tb_switch *sw)
{
	if (!clx_enabled)
		return false;

	if (sw->quirks & QUIRK_NO_CLX)
		return false;

	/*
	 * CLx is not enabled and validated on Intel USB4 platforms
	 * before Alder Lake.
	 */
	if (tb_switch_is_tiger_lake(sw))
		return false;

	return tb_switch_is_usb4(sw) || tb_switch_is_titan_ridge(sw);
}

static bool validate_mask(unsigned int clx)
{
	/* Previous states need to be enabled */
	if (clx & TB_CL1)
		return (clx & TB_CL0S) == TB_CL0S;
	return true;
}

/**
 * tb_switch_clx_enable() - Enable CLx on upstream port of specified router
 * @sw: Router to enable CLx for
 * @clx: The CLx state to enable
 *
 * CLx is enabled only if both sides of the link support CLx, and if both sides
 * of the link are not configured as two single lane links and only if the link
 * is not inter-domain link. The complete set of conditions is described in CM
 * Guide 1.0 section 8.1.
 *
 * Returns %0 on success or an error code on failure.
 */
int tb_switch_clx_enable(struct tb_switch *sw, unsigned int clx)
{
	bool up_clx_support, down_clx_support;
	struct tb_switch *parent_sw;
	struct tb_port *up, *down;
	int ret;

	if (!clx || sw->clx == clx)
		return 0;

	if (!validate_mask(clx))
		return -EINVAL;

	parent_sw = tb_switch_parent(sw);
	if (!parent_sw)
		return 0;

	if (!tb_switch_clx_is_supported(parent_sw) ||
	    !tb_switch_clx_is_supported(sw))
		return 0;

	/* Only support CL2 for v2 routers */
	if ((clx & TB_CL2) &&
	    (usb4_switch_version(parent_sw) < 2 ||
	     usb4_switch_version(sw) < 2))
		return -EOPNOTSUPP;

	ret = tb_switch_pm_secondary_resolve(sw);
	if (ret)
		return ret;

	up = tb_upstream_port(sw);
	down = tb_switch_downstream_port(sw);

	up_clx_support = tb_port_clx_supported(up, clx);
	down_clx_support = tb_port_clx_supported(down, clx);

	tb_port_dbg(up, "CLx: %s %ssupported\n", clx_name(clx),
		    up_clx_support ? "" : "not ");
	tb_port_dbg(down, "CLx: %s %ssupported\n", clx_name(clx),
		    down_clx_support ? "" : "not ");

	if (!up_clx_support || !down_clx_support)
		return -EOPNOTSUPP;

	ret = tb_port_clx_enable(up, clx);
	if (ret)
		return ret;

	ret = tb_port_clx_enable(down, clx);
	if (ret) {
		tb_port_clx_disable(up, clx);
		return ret;
	}

	ret = tb_switch_mask_clx_objections(sw);
	if (ret) {
		tb_port_clx_disable(up, clx);
		tb_port_clx_disable(down, clx);
		return ret;
	}

	sw->clx |= clx;

	tb_sw_dbg(sw, "CLx: %s enabled\n", clx_name(clx));
	return 0;
}

/**
 * tb_switch_clx_disable() - Disable CLx on upstream port of specified router
 * @sw: Router to disable CLx for
 *
 * Disables all CL states of the given router. Can be called on any
 * router and if the states were not enabled already does nothing.
 *
 * Returns the CL states that were disabled or negative errno in case of
 * failure.
 */
int tb_switch_clx_disable(struct tb_switch *sw)
{
	unsigned int clx = sw->clx;
	struct tb_port *up, *down;
	int ret;

	if (!tb_switch_clx_is_supported(sw))
		return 0;

	if (!clx)
		return 0;

	up = tb_upstream_port(sw);
	down = tb_switch_downstream_port(sw);

	ret = tb_port_clx_disable(up, clx);
	if (ret)
		return ret;

	ret = tb_port_clx_disable(down, clx);
	if (ret)
		return ret;

	sw->clx = 0;

	tb_sw_dbg(sw, "CLx: %s disabled\n", clx_name(clx));
	return clx;
}
Commit	Line	Data
12a14f2f MW	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* CLx support
	4	*
	5	* Copyright (C) 2020 - 2023, Intel Corporation
	6	* Authors: Gil Fine <gil.fine@intel.com>
	7	* Mika Westerberg <mika.westerberg@linux.intel.com>
	8	*/
	9
	10	#include <linux/module.h>
	11
	12	#include "tb.h"
	13
	14	static bool clx_enabled = true;
	15	module_param_named(clx, clx_enabled, bool, 0444);
	16	MODULE_PARM_DESC(clx, "allow low power states on the high-speed lanes (default: true)");
	17
768e6fe6 MW	18	static const char *clx_name(unsigned int clx)
768e6fe6 MW	19	{
fd4d58d1 MW	20	switch (clx) {
fd4d58d1 MW	21	case TB_CL0S \| TB_CL1 \| TB_CL2:
768e6fe6	22	return "CL0s/CL1/CL2";
fd4d58d1 MW	23	case TB_CL1 \| TB_CL2:
	24	return "CL1/CL2";
	25	case TB_CL0S \| TB_CL2:
	26	return "CL0s/CL2";
	27	case TB_CL0S \| TB_CL1:
768e6fe6	28	return "CL0s/CL1";
fd4d58d1	29	case TB_CL0S:
768e6fe6	30	return "CL0s";
fd4d58d1 MW	31	case 0:
	32	return "disabled";
	33	default:
	34	return "unknown";
	35	}
768e6fe6 MW	36	}
768e6fe6 MW	37
12a14f2f MW	38	static int tb_port_pm_secondary_set(struct tb_port *port, bool secondary)
	39	{
	40	u32 phy;
	41	int ret;
	42
	43	ret = tb_port_read(port, &phy, TB_CFG_PORT,
	44	port->cap_phy + LANE_ADP_CS_1, 1);
	45	if (ret)
	46	return ret;
	47
	48	if (secondary)
	49	phy \|= LANE_ADP_CS_1_PMS;
	50	else
	51	phy &= ~LANE_ADP_CS_1_PMS;
	52
	53	return tb_port_write(port, &phy, TB_CFG_PORT,
	54	port->cap_phy + LANE_ADP_CS_1, 1);
	55	}
	56
	57	static int tb_port_pm_secondary_enable(struct tb_port *port)
	58	{
	59	return tb_port_pm_secondary_set(port, true);
	60	}
	61
	62	static int tb_port_pm_secondary_disable(struct tb_port *port)
	63	{
	64	return tb_port_pm_secondary_set(port, false);
	65	}
	66
	67	/* Called for USB4 or Titan Ridge routers only */
35627353	68	static bool tb_port_clx_supported(struct tb_port *port, unsigned int clx)
12a14f2f MW	69	{
	70	u32 val, mask = 0;
	71	bool ret;
	72
	73	/* Don't enable CLx in case of two single-lane links */
	74	if (!port->bonded && port->dual_link_port)
	75	return false;
	76
	77	/* Don't enable CLx in case of inter-domain link */
	78	if (port->xdomain)
	79	return false;
	80
	81	if (tb_switch_is_usb4(port->sw)) {
	82	if (!usb4_port_clx_supported(port))
	83	return false;
	84	} else if (!tb_lc_is_clx_supported(port)) {
	85	return false;
	86	}
	87
35627353 MW	88	if (clx & TB_CL0S)
	89	mask \|= LANE_ADP_CS_0_CL0S_SUPPORT;
	90	if (clx & TB_CL1)
	91	mask \|= LANE_ADP_CS_0_CL1_SUPPORT;
	92	if (clx & TB_CL2)
12a14f2f MW	93	mask \|= LANE_ADP_CS_0_CL2_SUPPORT;
	94
	95	ret = tb_port_read(port, &val, TB_CFG_PORT,
	96	port->cap_phy + LANE_ADP_CS_0, 1);
	97	if (ret)
	98	return false;
	99
	100	return !!(val & mask);
	101	}
	102
35627353	103	static int tb_port_clx_set(struct tb_port *port, unsigned int clx, bool enable)
12a14f2f	104	{
35627353	105	u32 phy, mask = 0;
12a14f2f MW	106	int ret;
12a14f2f MW	107
35627353 MW	108	if (clx & TB_CL0S)
	109	mask \|= LANE_ADP_CS_1_CL0S_ENABLE;
	110	if (clx & TB_CL1)
	111	mask \|= LANE_ADP_CS_1_CL1_ENABLE;
fd4d58d1 MW	112	if (clx & TB_CL2)
fd4d58d1 MW	113	mask \|= LANE_ADP_CS_1_CL2_ENABLE;
35627353 MW	114
35627353 MW	115	if (!mask)
12a14f2f MW	116	return -EOPNOTSUPP;
	117
	118	ret = tb_port_read(port, &phy, TB_CFG_PORT,
	119	port->cap_phy + LANE_ADP_CS_1, 1);
	120	if (ret)
	121	return ret;
	122
	123	if (enable)
	124	phy \|= mask;
	125	else
	126	phy &= ~mask;
	127
	128	return tb_port_write(port, &phy, TB_CFG_PORT,
	129	port->cap_phy + LANE_ADP_CS_1, 1);
	130	}
	131
35627353	132	static int tb_port_clx_disable(struct tb_port *port, unsigned int clx)
12a14f2f MW	133	{
	134	return tb_port_clx_set(port, clx, false);
	135	}
	136
35627353	137	static int tb_port_clx_enable(struct tb_port *port, unsigned int clx)
12a14f2f MW	138	{
	139	return tb_port_clx_set(port, clx, true);
	140	}
	141
768e6fe6 MW	142	static int tb_port_clx(struct tb_port *port)
	143	{
	144	u32 val;
	145	int ret;
	146
	147	if (!tb_port_clx_supported(port, TB_CL0S \| TB_CL1 \| TB_CL2))
	148	return 0;
	149
	150	ret = tb_port_read(port, &val, TB_CFG_PORT,
	151	port->cap_phy + LANE_ADP_CS_1, 1);
	152	if (ret)
	153	return ret;
	154
	155	if (val & LANE_ADP_CS_1_CL0S_ENABLE)
	156	ret \|= TB_CL0S;
	157	if (val & LANE_ADP_CS_1_CL1_ENABLE)
	158	ret \|= TB_CL1;
	159	if (val & LANE_ADP_CS_1_CL2_ENABLE)
	160	ret \|= TB_CL2;
	161
	162	return ret;
	163	}
	164
12a14f2f MW	165	/**
	166	* tb_port_clx_is_enabled() - Is given CL state enabled
	167	* @port: USB4 port to check
35627353	168	* @clx: Mask of CL states to check
12a14f2f MW	169	*
	170	* Returns true if any of the given CL states is enabled for @port.
	171	*/
35627353	172	bool tb_port_clx_is_enabled(struct tb_port *port, unsigned int clx)
12a14f2f	173	{
768e6fe6 MW	174	return !!(tb_port_clx(port) & clx);
768e6fe6 MW	175	}
12a14f2f	176
768e6fe6 MW	177	/**
	178	* tb_switch_clx_init() - Initialize router CL states
	179	* @sw: Router
	180	*
	181	* Can be called for any router. Initializes the current CL state by
	182	* reading it from the hardware.
	183	*
	184	* Returns %0 in case of success and negative errno in case of failure.
	185	*/
	186	int tb_switch_clx_init(struct tb_switch *sw)
	187	{
	188	struct tb_port up, down;
	189	unsigned int clx, tmp;
12a14f2f	190
768e6fe6 MW	191	if (tb_switch_is_icm(sw))
768e6fe6 MW	192	return 0;
12a14f2f	193
768e6fe6 MW	194	if (!tb_route(sw))
768e6fe6 MW	195	return 0;
12a14f2f	196
768e6fe6 MW	197	if (!tb_switch_clx_is_supported(sw))
	198	return 0;
	199
	200	up = tb_upstream_port(sw);
	201	down = tb_switch_downstream_port(sw);
	202
	203	clx = tb_port_clx(up);
	204	tmp = tb_port_clx(down);
	205	if (clx != tmp)
	206	tb_sw_warn(sw, "CLx: inconsistent configuration %#x != %#x\n",
	207	clx, tmp);
	208
	209	tb_sw_dbg(sw, "CLx: current mode: %s\n", clx_name(clx));
	210
	211	sw->clx = clx;
	212	return 0;
12a14f2f MW	213	}
	214
	215	static int tb_switch_pm_secondary_resolve(struct tb_switch *sw)
	216	{
	217	struct tb_port up, down;
	218	int ret;
	219
	220	if (!tb_route(sw))
	221	return 0;
	222
	223	up = tb_upstream_port(sw);
	224	down = tb_switch_downstream_port(sw);
	225	ret = tb_port_pm_secondary_enable(up);
	226	if (ret)
	227	return ret;
	228
	229	return tb_port_pm_secondary_disable(down);
	230	}
	231
	232	static int tb_switch_mask_clx_objections(struct tb_switch *sw)
	233	{
	234	int up_port = sw->config.upstream_port_number;
	235	u32 offset, val[2], mask_obj, unmask_obj;
	236	int ret, i;
	237
	238	/* Only Titan Ridge of pre-USB4 devices support CLx states */
	239	if (!tb_switch_is_titan_ridge(sw))
	240	return 0;
	241
	242	if (!tb_route(sw))
	243	return 0;
	244
	245	/*
	246	* In Titan Ridge there are only 2 dual-lane Thunderbolt ports:
	247	* Port A consists of lane adapters 1,2 and
	248	* Port B consists of lane adapters 3,4
	249	* If upstream port is A, (lanes are 1,2), we mask objections from
	250	* port B (lanes 3,4) and unmask objections from Port A and vice-versa.
	251	*/
	252	if (up_port == 1) {
	253	mask_obj = TB_LOW_PWR_C0_PORT_B_MASK;
	254	unmask_obj = TB_LOW_PWR_C1_PORT_A_MASK;
	255	offset = TB_LOW_PWR_C1_CL1;
	256	} else {
	257	mask_obj = TB_LOW_PWR_C1_PORT_A_MASK;
	258	unmask_obj = TB_LOW_PWR_C0_PORT_B_MASK;
	259	offset = TB_LOW_PWR_C3_CL1;
	260	}
	261
	262	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
	263	sw->cap_lp + offset, ARRAY_SIZE(val));
	264	if (ret)
	265	return ret;
	266
	267	for (i = 0; i < ARRAY_SIZE(val); i++) {
	268	val[i] \|= mask_obj;
	269	val[i] &= ~unmask_obj;
	270	}
	271
	272	return tb_sw_write(sw, &val, TB_CFG_SWITCH,
	273	sw->cap_lp + offset, ARRAY_SIZE(val));
	274	}
	275
35627353 MW	276	/**
	277	* tb_switch_clx_is_supported() - Is CLx supported on this type of router
	278	* @sw: The router to check CLx support for
	279	*/
	280	bool tb_switch_clx_is_supported(const struct tb_switch *sw)
	281	{
	282	if (!clx_enabled)
	283	return false;
	284
	285	if (sw->quirks & QUIRK_NO_CLX)
	286	return false;
	287
	288	/*
	289	* CLx is not enabled and validated on Intel USB4 platforms
	290	* before Alder Lake.
	291	*/
	292	if (tb_switch_is_tiger_lake(sw))
	293	return false;
	294
	295	return tb_switch_is_usb4(sw) \|\| tb_switch_is_titan_ridge(sw);
	296	}
	297
	298	static bool validate_mask(unsigned int clx)
	299	{
	300	/* Previous states need to be enabled */
35627353 MW	301	if (clx & TB_CL1)
	302	return (clx & TB_CL0S) == TB_CL0S;
	303	return true;
	304	}
	305
4f9a4f25 MW	306	/**
	307	* tb_switch_clx_enable() - Enable CLx on upstream port of specified router
	308	* @sw: Router to enable CLx for
	309	* @clx: The CLx state to enable
	310	*
9650de73 MW	311	* CLx is enabled only if both sides of the link support CLx, and if both sides
	312	* of the link are not configured as two single lane links and only if the link
	313	* is not inter-domain link. The complete set of conditions is described in CM
	314	* Guide 1.0 section 8.1.
4f9a4f25	315	*
9650de73	316	* Returns %0 on success or an error code on failure.
4f9a4f25	317	*/
35627353	318	int tb_switch_clx_enable(struct tb_switch *sw, unsigned int clx)
12a14f2f MW	319	{
12a14f2f MW	320	bool up_clx_support, down_clx_support;
35627353	321	struct tb_switch *parent_sw;
12a14f2f MW	322	struct tb_port up, down;
	323	int ret;
	324
53ba2e16	325	if (!clx \|\| sw->clx == clx)
4a420eb1 MW	326	return 0;
4a420eb1 MW	327
35627353 MW	328	if (!validate_mask(clx))
35627353 MW	329	return -EINVAL;
4f9a4f25	330
35627353 MW	331	parent_sw = tb_switch_parent(sw);
35627353 MW	332	if (!parent_sw)
4f9a4f25 MW	333	return 0;
4f9a4f25 MW	334
35627353 MW	335	if (!tb_switch_clx_is_supported(parent_sw) \|\|
35627353 MW	336	!tb_switch_clx_is_supported(sw))
12a14f2f MW	337	return 0;
12a14f2f MW	338
fd4d58d1 MW	339	/* Only support CL2 for v2 routers */
	340	if ((clx & TB_CL2) &&
	341	(usb4_switch_version(parent_sw) < 2 \|\|
	342	usb4_switch_version(sw) < 2))
35627353 MW	343	return -EOPNOTSUPP;
35627353 MW	344
12a14f2f MW	345	ret = tb_switch_pm_secondary_resolve(sw);
	346	if (ret)
	347	return ret;
	348
	349	up = tb_upstream_port(sw);
	350	down = tb_switch_downstream_port(sw);
	351
	352	up_clx_support = tb_port_clx_supported(up, clx);
	353	down_clx_support = tb_port_clx_supported(down, clx);
	354
b5d15961	355	tb_port_dbg(up, "CLx: %s %ssupported\n", clx_name(clx),
12a14f2f	356	up_clx_support ? "" : "not ");
b5d15961	357	tb_port_dbg(down, "CLx: %s %ssupported\n", clx_name(clx),
12a14f2f MW	358	down_clx_support ? "" : "not ");
	359
	360	if (!up_clx_support \|\| !down_clx_support)
	361	return -EOPNOTSUPP;
	362
	363	ret = tb_port_clx_enable(up, clx);
	364	if (ret)
	365	return ret;
	366
	367	ret = tb_port_clx_enable(down, clx);
	368	if (ret) {
	369	tb_port_clx_disable(up, clx);
	370	return ret;
	371	}
	372
	373	ret = tb_switch_mask_clx_objections(sw);
	374	if (ret) {
	375	tb_port_clx_disable(up, clx);
	376	tb_port_clx_disable(down, clx);
	377	return ret;
	378	}
	379
35627353	380	sw->clx \|= clx;
12a14f2f	381
b5d15961	382	tb_sw_dbg(sw, "CLx: %s enabled\n", clx_name(clx));
12a14f2f MW	383	return 0;
	384	}
	385
	386	/**
4f9a4f25 MW	387	* tb_switch_clx_disable() - Disable CLx on upstream port of specified router
4f9a4f25 MW	388	* @sw: Router to disable CLx for
35627353 MW	389	*
	390	* Disables all CL states of the given router. Can be called on any
	391	* router and if the states were not enabled already does nothing.
12a14f2f	392	*
4a420eb1 MW	393	* Returns the CL states that were disabled or negative errno in case of
4a420eb1 MW	394	* failure.
12a14f2f	395	*/
35627353	396	int tb_switch_clx_disable(struct tb_switch *sw)
12a14f2f	397	{
35627353	398	unsigned int clx = sw->clx;
4f9a4f25 MW	399	struct tb_port up, down;
4f9a4f25 MW	400	int ret;
12a14f2f	401
12a14f2f MW	402	if (!tb_switch_clx_is_supported(sw))
	403	return 0;
	404
35627353 MW	405	if (!clx)
	406	return 0;
	407
12a14f2f MW	408	up = tb_upstream_port(sw);
12a14f2f MW	409	down = tb_switch_downstream_port(sw);
35627353	410
12a14f2f MW	411	ret = tb_port_clx_disable(up, clx);
	412	if (ret)
	413	return ret;
	414
	415	ret = tb_port_clx_disable(down, clx);
	416	if (ret)
	417	return ret;
	418
35627353	419	sw->clx = 0;
12a14f2f	420
b5d15961	421	tb_sw_dbg(sw, "CLx: %s disabled\n", clx_name(clx));
4a420eb1	422	return clx;
12a14f2f	423	}