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8926fa4f EV |
1 | /* |
2 | * DRA752 thermal data. | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments Inc. | |
5 | * Contact: | |
6 | * Eduardo Valentin <eduardo.valentin@ti.com> | |
7 | * Tero Kristo <t-kristo@ti.com> | |
8 | * | |
9 | * This file is partially autogenerated. | |
10 | * | |
11 | * This software is licensed under the terms of the GNU General Public | |
12 | * License version 2, as published by the Free Software Foundation, and | |
13 | * may be copied, distributed, and modified under those terms. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | */ | |
21 | ||
22 | #include "ti-thermal.h" | |
23 | #include "ti-bandgap.h" | |
24 | #include "dra752-bandgap.h" | |
25 | ||
26 | /* | |
27 | * DRA752 has five instances of thermal sensor: MPU, GPU, CORE, | |
28 | * IVA and DSPEVE need to describe the individual registers and | |
29 | * bit fields. | |
30 | */ | |
31 | ||
32 | /* | |
33 | * DRA752 CORE thermal sensor register offsets and bit-fields | |
34 | */ | |
35 | static struct temp_sensor_registers | |
36 | dra752_core_temp_sensor_registers = { | |
37 | .temp_sensor_ctrl = DRA752_TEMP_SENSOR_CORE_OFFSET, | |
38 | .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK, | |
39 | .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK, | |
40 | .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK, | |
41 | .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET, | |
42 | .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK, | |
43 | .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK, | |
44 | .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, | |
547f72ab | 45 | .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, |
8926fa4f EV |
46 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK, |
47 | .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK, | |
48 | .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK, | |
49 | .bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET, | |
50 | .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, | |
51 | .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, | |
52 | .tshut_threshold = DRA752_BANDGAP_TSHUT_CORE_OFFSET, | |
53 | .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK, | |
54 | .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK, | |
55 | .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET, | |
56 | .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK, | |
57 | .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK, | |
58 | .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK, | |
59 | .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET, | |
60 | .ctrl_dtemp_0 = DRA752_DTEMP_CORE_0_OFFSET, | |
61 | .ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET, | |
62 | .ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET, | |
63 | .ctrl_dtemp_3 = DRA752_DTEMP_CORE_3_OFFSET, | |
64 | .ctrl_dtemp_4 = DRA752_DTEMP_CORE_4_OFFSET, | |
65 | .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET, | |
66 | }; | |
67 | ||
68 | /* | |
69 | * DRA752 IVA thermal sensor register offsets and bit-fields | |
70 | */ | |
71 | static struct temp_sensor_registers | |
72 | dra752_iva_temp_sensor_registers = { | |
73 | .temp_sensor_ctrl = DRA752_TEMP_SENSOR_IVA_OFFSET, | |
74 | .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK, | |
75 | .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK, | |
76 | .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK, | |
77 | .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET, | |
78 | .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK, | |
79 | .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK, | |
80 | .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, | |
547f72ab | 81 | .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, |
8926fa4f EV |
82 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK, |
83 | .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK, | |
84 | .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK, | |
85 | .bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET, | |
86 | .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, | |
87 | .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, | |
88 | .tshut_threshold = DRA752_BANDGAP_TSHUT_IVA_OFFSET, | |
89 | .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK, | |
90 | .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK, | |
91 | .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET, | |
92 | .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK, | |
93 | .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK, | |
94 | .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK, | |
95 | .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET, | |
96 | .ctrl_dtemp_0 = DRA752_DTEMP_IVA_0_OFFSET, | |
97 | .ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET, | |
98 | .ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET, | |
99 | .ctrl_dtemp_3 = DRA752_DTEMP_IVA_3_OFFSET, | |
100 | .ctrl_dtemp_4 = DRA752_DTEMP_IVA_4_OFFSET, | |
101 | .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET, | |
102 | }; | |
103 | ||
104 | /* | |
105 | * DRA752 MPU thermal sensor register offsets and bit-fields | |
106 | */ | |
107 | static struct temp_sensor_registers | |
108 | dra752_mpu_temp_sensor_registers = { | |
109 | .temp_sensor_ctrl = DRA752_TEMP_SENSOR_MPU_OFFSET, | |
110 | .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK, | |
111 | .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK, | |
112 | .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK, | |
113 | .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET, | |
114 | .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK, | |
115 | .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK, | |
116 | .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, | |
547f72ab | 117 | .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, |
8926fa4f EV |
118 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK, |
119 | .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK, | |
120 | .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK, | |
121 | .bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET, | |
122 | .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, | |
123 | .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, | |
124 | .tshut_threshold = DRA752_BANDGAP_TSHUT_MPU_OFFSET, | |
125 | .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK, | |
126 | .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK, | |
127 | .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET, | |
128 | .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK, | |
129 | .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK, | |
130 | .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK, | |
131 | .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET, | |
132 | .ctrl_dtemp_0 = DRA752_DTEMP_MPU_0_OFFSET, | |
133 | .ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET, | |
134 | .ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET, | |
135 | .ctrl_dtemp_3 = DRA752_DTEMP_MPU_3_OFFSET, | |
136 | .ctrl_dtemp_4 = DRA752_DTEMP_MPU_4_OFFSET, | |
137 | .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET, | |
138 | }; | |
139 | ||
140 | /* | |
141 | * DRA752 DSPEVE thermal sensor register offsets and bit-fields | |
142 | */ | |
143 | static struct temp_sensor_registers | |
144 | dra752_dspeve_temp_sensor_registers = { | |
145 | .temp_sensor_ctrl = DRA752_TEMP_SENSOR_DSPEVE_OFFSET, | |
146 | .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK, | |
147 | .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK, | |
148 | .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK, | |
149 | .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET, | |
150 | .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK, | |
151 | .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK, | |
152 | .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, | |
547f72ab | 153 | .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, |
8926fa4f EV |
154 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK, |
155 | .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK, | |
156 | .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK, | |
157 | .bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET, | |
158 | .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, | |
159 | .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, | |
160 | .tshut_threshold = DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET, | |
161 | .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK, | |
162 | .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK, | |
163 | .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET, | |
164 | .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK, | |
165 | .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK, | |
166 | .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK, | |
167 | .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET, | |
168 | .ctrl_dtemp_0 = DRA752_DTEMP_DSPEVE_0_OFFSET, | |
169 | .ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET, | |
170 | .ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET, | |
171 | .ctrl_dtemp_3 = DRA752_DTEMP_DSPEVE_3_OFFSET, | |
172 | .ctrl_dtemp_4 = DRA752_DTEMP_DSPEVE_4_OFFSET, | |
173 | .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET, | |
174 | }; | |
175 | ||
176 | /* | |
177 | * DRA752 GPU thermal sensor register offsets and bit-fields | |
178 | */ | |
179 | static struct temp_sensor_registers | |
180 | dra752_gpu_temp_sensor_registers = { | |
181 | .temp_sensor_ctrl = DRA752_TEMP_SENSOR_GPU_OFFSET, | |
182 | .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK, | |
183 | .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK, | |
184 | .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK, | |
185 | .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET, | |
186 | .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK, | |
187 | .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK, | |
188 | .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, | |
547f72ab | 189 | .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, |
8926fa4f EV |
190 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK, |
191 | .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK, | |
192 | .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK, | |
193 | .bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET, | |
194 | .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, | |
195 | .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, | |
196 | .tshut_threshold = DRA752_BANDGAP_TSHUT_GPU_OFFSET, | |
197 | .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK, | |
198 | .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK, | |
199 | .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET, | |
200 | .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK, | |
201 | .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK, | |
202 | .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK, | |
203 | .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET, | |
204 | .ctrl_dtemp_0 = DRA752_DTEMP_GPU_0_OFFSET, | |
205 | .ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET, | |
206 | .ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET, | |
207 | .ctrl_dtemp_3 = DRA752_DTEMP_GPU_3_OFFSET, | |
208 | .ctrl_dtemp_4 = DRA752_DTEMP_GPU_4_OFFSET, | |
209 | .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET, | |
210 | }; | |
211 | ||
212 | /* Thresholds and limits for DRA752 MPU temperature sensor */ | |
213 | static struct temp_sensor_data dra752_mpu_temp_sensor_data = { | |
214 | .tshut_hot = DRA752_MPU_TSHUT_HOT, | |
215 | .tshut_cold = DRA752_MPU_TSHUT_COLD, | |
216 | .t_hot = DRA752_MPU_T_HOT, | |
217 | .t_cold = DRA752_MPU_T_COLD, | |
218 | .min_freq = DRA752_MPU_MIN_FREQ, | |
219 | .max_freq = DRA752_MPU_MAX_FREQ, | |
220 | .max_temp = DRA752_MPU_MAX_TEMP, | |
221 | .min_temp = DRA752_MPU_MIN_TEMP, | |
222 | .hyst_val = DRA752_MPU_HYST_VAL, | |
223 | .update_int1 = 1000, | |
224 | .update_int2 = 2000, | |
225 | }; | |
226 | ||
227 | /* Thresholds and limits for DRA752 GPU temperature sensor */ | |
228 | static struct temp_sensor_data dra752_gpu_temp_sensor_data = { | |
229 | .tshut_hot = DRA752_GPU_TSHUT_HOT, | |
230 | .tshut_cold = DRA752_GPU_TSHUT_COLD, | |
231 | .t_hot = DRA752_GPU_T_HOT, | |
232 | .t_cold = DRA752_GPU_T_COLD, | |
233 | .min_freq = DRA752_GPU_MIN_FREQ, | |
234 | .max_freq = DRA752_GPU_MAX_FREQ, | |
235 | .max_temp = DRA752_GPU_MAX_TEMP, | |
236 | .min_temp = DRA752_GPU_MIN_TEMP, | |
237 | .hyst_val = DRA752_GPU_HYST_VAL, | |
238 | .update_int1 = 1000, | |
239 | .update_int2 = 2000, | |
240 | }; | |
241 | ||
242 | /* Thresholds and limits for DRA752 CORE temperature sensor */ | |
243 | static struct temp_sensor_data dra752_core_temp_sensor_data = { | |
244 | .tshut_hot = DRA752_CORE_TSHUT_HOT, | |
245 | .tshut_cold = DRA752_CORE_TSHUT_COLD, | |
246 | .t_hot = DRA752_CORE_T_HOT, | |
247 | .t_cold = DRA752_CORE_T_COLD, | |
248 | .min_freq = DRA752_CORE_MIN_FREQ, | |
249 | .max_freq = DRA752_CORE_MAX_FREQ, | |
250 | .max_temp = DRA752_CORE_MAX_TEMP, | |
251 | .min_temp = DRA752_CORE_MIN_TEMP, | |
252 | .hyst_val = DRA752_CORE_HYST_VAL, | |
253 | .update_int1 = 1000, | |
254 | .update_int2 = 2000, | |
255 | }; | |
256 | ||
257 | /* Thresholds and limits for DRA752 DSPEVE temperature sensor */ | |
258 | static struct temp_sensor_data dra752_dspeve_temp_sensor_data = { | |
259 | .tshut_hot = DRA752_DSPEVE_TSHUT_HOT, | |
260 | .tshut_cold = DRA752_DSPEVE_TSHUT_COLD, | |
261 | .t_hot = DRA752_DSPEVE_T_HOT, | |
262 | .t_cold = DRA752_DSPEVE_T_COLD, | |
263 | .min_freq = DRA752_DSPEVE_MIN_FREQ, | |
264 | .max_freq = DRA752_DSPEVE_MAX_FREQ, | |
265 | .max_temp = DRA752_DSPEVE_MAX_TEMP, | |
266 | .min_temp = DRA752_DSPEVE_MIN_TEMP, | |
267 | .hyst_val = DRA752_DSPEVE_HYST_VAL, | |
268 | .update_int1 = 1000, | |
269 | .update_int2 = 2000, | |
270 | }; | |
271 | ||
272 | /* Thresholds and limits for DRA752 IVA temperature sensor */ | |
273 | static struct temp_sensor_data dra752_iva_temp_sensor_data = { | |
274 | .tshut_hot = DRA752_IVA_TSHUT_HOT, | |
275 | .tshut_cold = DRA752_IVA_TSHUT_COLD, | |
276 | .t_hot = DRA752_IVA_T_HOT, | |
277 | .t_cold = DRA752_IVA_T_COLD, | |
278 | .min_freq = DRA752_IVA_MIN_FREQ, | |
279 | .max_freq = DRA752_IVA_MAX_FREQ, | |
280 | .max_temp = DRA752_IVA_MAX_TEMP, | |
281 | .min_temp = DRA752_IVA_MIN_TEMP, | |
282 | .hyst_val = DRA752_IVA_HYST_VAL, | |
283 | .update_int1 = 1000, | |
284 | .update_int2 = 2000, | |
285 | }; | |
286 | ||
287 | /* | |
288 | * DRA752 : Temperature values in milli degree celsius | |
289 | * ADC code values from 540 to 945 | |
290 | */ | |
291 | static | |
292 | int dra752_adc_to_temp[DRA752_ADC_END_VALUE - DRA752_ADC_START_VALUE + 1] = { | |
293 | /* Index 540 - 549 */ | |
294 | -40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600, -38200, | |
295 | -37800, | |
296 | /* Index 550 - 559 */ | |
297 | -37400, -37000, -36600, -36200, -35800, -35300, -34700, -34200, -33800, | |
298 | -33400, | |
299 | /* Index 560 - 569 */ | |
300 | -33000, -32600, -32200, -31800, -31400, -31000, -30600, -30200, -29800, | |
301 | -29400, | |
302 | /* Index 570 - 579 */ | |
303 | -29000, -28600, -28200, -27700, -27100, -26600, -26200, -25800, -25400, | |
304 | -25000, | |
305 | /* Index 580 - 589 */ | |
306 | -24600, -24200, -23800, -23400, -23000, -22600, -22200, -21800, -21400, | |
307 | -21000, | |
308 | /* Index 590 - 599 */ | |
309 | -20500, -19900, -19400, -19000, -18600, -18200, -17800, -17400, -17000, | |
310 | -16600, | |
311 | /* Index 600 - 609 */ | |
312 | -16200, -15800, -15400, -15000, -14600, -14200, -13800, -13400, -13000, | |
313 | -12500, | |
314 | /* Index 610 - 619 */ | |
315 | -11900, -11400, -11000, -10600, -10200, -9800, -9400, -9000, -8600, | |
316 | -8200, | |
317 | /* Index 620 - 629 */ | |
318 | -7800, -7400, -7000, -6600, -6200, -5800, -5400, -5000, -4500, | |
319 | -3900, | |
320 | /* Index 630 - 639 */ | |
321 | -3400, -3000, -2600, -2200, -1800, -1400, -1000, -600, -200, | |
322 | 200, | |
323 | /* Index 640 - 649 */ | |
324 | 600, 1000, 1400, 1800, 2200, 2600, 3000, 3400, 3900, | |
325 | 4500, | |
326 | /* Index 650 - 659 */ | |
327 | 5000, 5400, 5800, 6200, 6600, 7000, 7400, 7800, 8200, | |
328 | 8600, | |
329 | /* Index 660 - 669 */ | |
330 | 9000, 9400, 9800, 10200, 10600, 11000, 11400, 11800, 12200, | |
331 | 12700, | |
332 | /* Index 670 - 679 */ | |
333 | 13300, 13800, 14200, 14600, 15000, 15400, 15800, 16200, 16600, | |
334 | 17000, | |
335 | /* Index 680 - 689 */ | |
336 | 17400, 17800, 18200, 18600, 19000, 19400, 19800, 20200, 20600, | |
337 | 21000, | |
338 | /* Index 690 - 699 */ | |
339 | 21400, 21900, 22500, 23000, 23400, 23800, 24200, 24600, 25000, | |
340 | 25400, | |
341 | /* Index 700 - 709 */ | |
342 | 25800, 26200, 26600, 27000, 27400, 27800, 28200, 28600, 29000, | |
343 | 29400, | |
344 | /* Index 710 - 719 */ | |
345 | 29800, 30200, 30600, 31000, 31400, 31900, 32500, 33000, 33400, | |
346 | 33800, | |
347 | /* Index 720 - 729 */ | |
348 | 34200, 34600, 35000, 35400, 35800, 36200, 36600, 37000, 37400, | |
349 | 37800, | |
350 | /* Index 730 - 739 */ | |
351 | 38200, 38600, 39000, 39400, 39800, 40200, 40600, 41000, 41400, | |
352 | 41800, | |
353 | /* Index 740 - 749 */ | |
354 | 42200, 42600, 43100, 43700, 44200, 44600, 45000, 45400, 45800, | |
355 | 46200, | |
356 | /* Index 750 - 759 */ | |
357 | 46600, 47000, 47400, 47800, 48200, 48600, 49000, 49400, 49800, | |
358 | 50200, | |
359 | /* Index 760 - 769 */ | |
360 | 50600, 51000, 51400, 51800, 52200, 52600, 53000, 53400, 53800, | |
361 | 54200, | |
362 | /* Index 770 - 779 */ | |
363 | 54600, 55000, 55400, 55900, 56500, 57000, 57400, 57800, 58200, | |
364 | 58600, | |
365 | /* Index 780 - 789 */ | |
366 | 59000, 59400, 59800, 60200, 60600, 61000, 61400, 61800, 62200, | |
367 | 62600, | |
368 | /* Index 790 - 799 */ | |
369 | 63000, 63400, 63800, 64200, 64600, 65000, 65400, 65800, 66200, | |
370 | 66600, | |
371 | /* Index 800 - 809 */ | |
372 | 67000, 67400, 67800, 68200, 68600, 69000, 69400, 69800, 70200, | |
373 | 70600, | |
374 | /* Index 810 - 819 */ | |
375 | 71000, 71500, 72100, 72600, 73000, 73400, 73800, 74200, 74600, | |
376 | 75000, | |
377 | /* Index 820 - 829 */ | |
378 | 75400, 75800, 76200, 76600, 77000, 77400, 77800, 78200, 78600, | |
379 | 79000, | |
380 | /* Index 830 - 839 */ | |
381 | 79400, 79800, 80200, 80600, 81000, 81400, 81800, 82200, 82600, | |
382 | 83000, | |
383 | /* Index 840 - 849 */ | |
384 | 83400, 83800, 84200, 84600, 85000, 85400, 85800, 86200, 86600, | |
385 | 87000, | |
386 | /* Index 850 - 859 */ | |
387 | 87400, 87800, 88200, 88600, 89000, 89400, 89800, 90200, 90600, | |
388 | 91000, | |
389 | /* Index 860 - 869 */ | |
390 | 91400, 91800, 92200, 92600, 93000, 93400, 93800, 94200, 94600, | |
391 | 95000, | |
392 | /* Index 870 - 879 */ | |
393 | 95400, 95800, 96200, 96600, 97000, 97500, 98100, 98600, 99000, | |
394 | 99400, | |
395 | /* Index 880 - 889 */ | |
396 | 99800, 100200, 100600, 101000, 101400, 101800, 102200, 102600, 103000, | |
397 | 103400, | |
398 | /* Index 890 - 899 */ | |
399 | 103800, 104200, 104600, 105000, 105400, 105800, 106200, 106600, 107000, | |
400 | 107400, | |
401 | /* Index 900 - 909 */ | |
402 | 107800, 108200, 108600, 109000, 109400, 109800, 110200, 110600, 111000, | |
403 | 111400, | |
404 | /* Index 910 - 919 */ | |
405 | 111800, 112200, 112600, 113000, 113400, 113800, 114200, 114600, 115000, | |
406 | 115400, | |
407 | /* Index 920 - 929 */ | |
408 | 115800, 116200, 116600, 117000, 117400, 117800, 118200, 118600, 119000, | |
409 | 119400, | |
410 | /* Index 930 - 939 */ | |
411 | 119800, 120200, 120600, 121000, 121400, 121800, 122200, 122600, 123000, | |
412 | 123400, | |
413 | /* Index 940 - 945 */ | |
414 | 123800, 124200, 124600, 124900, 125000, 125000, | |
415 | }; | |
416 | ||
417 | /* DRA752 data */ | |
418 | const struct ti_bandgap_data dra752_data = { | |
419 | .features = TI_BANDGAP_FEATURE_TSHUT_CONFIG | | |
420 | TI_BANDGAP_FEATURE_FREEZE_BIT | | |
421 | TI_BANDGAP_FEATURE_TALERT | | |
422 | TI_BANDGAP_FEATURE_COUNTER_DELAY | | |
79010636 K |
423 | TI_BANDGAP_FEATURE_HISTORY_BUFFER | |
424 | TI_BANDGAP_FEATURE_ERRATA_814, | |
8926fa4f EV |
425 | .fclock_name = "l3instr_ts_gclk_div", |
426 | .div_ck_name = "l3instr_ts_gclk_div", | |
427 | .conv_table = dra752_adc_to_temp, | |
428 | .adc_start_val = DRA752_ADC_START_VALUE, | |
429 | .adc_end_val = DRA752_ADC_END_VALUE, | |
430 | .expose_sensor = ti_thermal_expose_sensor, | |
431 | .remove_sensor = ti_thermal_remove_sensor, | |
432 | .sensors = { | |
433 | { | |
434 | .registers = &dra752_mpu_temp_sensor_registers, | |
435 | .ts_data = &dra752_mpu_temp_sensor_data, | |
436 | .domain = "cpu", | |
437 | .register_cooling = ti_thermal_register_cpu_cooling, | |
438 | .unregister_cooling = ti_thermal_unregister_cpu_cooling, | |
439 | .slope = DRA752_GRADIENT_SLOPE, | |
440 | .constant = DRA752_GRADIENT_CONST, | |
441 | .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB, | |
442 | .constant_pcb = DRA752_GRADIENT_CONST_W_PCB, | |
443 | }, | |
444 | { | |
445 | .registers = &dra752_gpu_temp_sensor_registers, | |
446 | .ts_data = &dra752_gpu_temp_sensor_data, | |
447 | .domain = "gpu", | |
448 | .slope = DRA752_GRADIENT_SLOPE, | |
449 | .constant = DRA752_GRADIENT_CONST, | |
450 | .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB, | |
451 | .constant_pcb = DRA752_GRADIENT_CONST_W_PCB, | |
452 | }, | |
453 | { | |
454 | .registers = &dra752_core_temp_sensor_registers, | |
455 | .ts_data = &dra752_core_temp_sensor_data, | |
456 | .domain = "core", | |
457 | .slope = DRA752_GRADIENT_SLOPE, | |
458 | .constant = DRA752_GRADIENT_CONST, | |
459 | .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB, | |
460 | .constant_pcb = DRA752_GRADIENT_CONST_W_PCB, | |
461 | }, | |
462 | { | |
463 | .registers = &dra752_dspeve_temp_sensor_registers, | |
464 | .ts_data = &dra752_dspeve_temp_sensor_data, | |
465 | .domain = "dspeve", | |
466 | .slope = DRA752_GRADIENT_SLOPE, | |
467 | .constant = DRA752_GRADIENT_CONST, | |
468 | .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB, | |
469 | .constant_pcb = DRA752_GRADIENT_CONST_W_PCB, | |
470 | }, | |
471 | { | |
472 | .registers = &dra752_iva_temp_sensor_registers, | |
473 | .ts_data = &dra752_iva_temp_sensor_data, | |
474 | .domain = "iva", | |
475 | .slope = DRA752_GRADIENT_SLOPE, | |
476 | .constant = DRA752_GRADIENT_CONST, | |
477 | .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB, | |
478 | .constant_pcb = DRA752_GRADIENT_CONST_W_PCB, | |
479 | }, | |
480 | }, | |
481 | .sensor_count = 5, | |
482 | }; |