Commit | Line | Data |
---|---|---|
9d97e5c8 | 1 | /* |
59dfa54c | 2 | * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit) |
9d97e5c8 | 3 | * |
3b6a1a80 LM |
4 | * Copyright (C) 2014 Samsung Electronics |
5 | * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> | |
6 | * Lukasz Majewski <l.majewski@samsung.com> | |
7 | * | |
9d97e5c8 DK |
8 | * Copyright (C) 2011 Samsung Electronics |
9 | * Donggeun Kim <dg77.kim@samsung.com> | |
c48cbba6 | 10 | * Amit Daniel Kachhap <amit.kachhap@linaro.org> |
9d97e5c8 DK |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
26 | */ | |
27 | ||
9d97e5c8 | 28 | #include <linux/clk.h> |
9d97e5c8 | 29 | #include <linux/io.h> |
1b678641 ADK |
30 | #include <linux/interrupt.h> |
31 | #include <linux/module.h> | |
fee88e2b | 32 | #include <linux/of_device.h> |
cebe7373 ADK |
33 | #include <linux/of_address.h> |
34 | #include <linux/of_irq.h> | |
1b678641 | 35 | #include <linux/platform_device.h> |
498d22f6 | 36 | #include <linux/regulator/consumer.h> |
1b678641 | 37 | |
7efd18a2 BZ |
38 | #include <dt-bindings/thermal/thermal_exynos.h> |
39 | ||
3b6a1a80 | 40 | #include "../thermal_core.h" |
2845f6ec BZ |
41 | |
42 | /* Exynos generic registers */ | |
43 | #define EXYNOS_TMU_REG_TRIMINFO 0x0 | |
44 | #define EXYNOS_TMU_REG_CONTROL 0x20 | |
45 | #define EXYNOS_TMU_REG_STATUS 0x28 | |
46 | #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40 | |
47 | #define EXYNOS_TMU_REG_INTEN 0x70 | |
48 | #define EXYNOS_TMU_REG_INTSTAT 0x74 | |
49 | #define EXYNOS_TMU_REG_INTCLEAR 0x78 | |
50 | ||
51 | #define EXYNOS_TMU_TEMP_MASK 0xff | |
52 | #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 | |
53 | #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f | |
54 | #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf | |
55 | #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 | |
56 | #define EXYNOS_TMU_CORE_EN_SHIFT 0 | |
57 | ||
58 | /* Exynos3250 specific registers */ | |
59 | #define EXYNOS_TMU_TRIMINFO_CON1 0x10 | |
60 | ||
61 | /* Exynos4210 specific registers */ | |
62 | #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44 | |
63 | #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50 | |
64 | ||
65 | /* Exynos5250, Exynos4412, Exynos3250 specific registers */ | |
66 | #define EXYNOS_TMU_TRIMINFO_CON2 0x14 | |
67 | #define EXYNOS_THD_TEMP_RISE 0x50 | |
68 | #define EXYNOS_THD_TEMP_FALL 0x54 | |
69 | #define EXYNOS_EMUL_CON 0x80 | |
70 | ||
71 | #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1 | |
72 | #define EXYNOS_TRIMINFO_25_SHIFT 0 | |
73 | #define EXYNOS_TRIMINFO_85_SHIFT 8 | |
74 | #define EXYNOS_TMU_TRIP_MODE_SHIFT 13 | |
75 | #define EXYNOS_TMU_TRIP_MODE_MASK 0x7 | |
76 | #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 | |
77 | ||
78 | #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 | |
2845f6ec BZ |
79 | #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 |
80 | ||
81 | #define EXYNOS_EMUL_TIME 0x57F0 | |
82 | #define EXYNOS_EMUL_TIME_MASK 0xffff | |
83 | #define EXYNOS_EMUL_TIME_SHIFT 16 | |
84 | #define EXYNOS_EMUL_DATA_SHIFT 8 | |
85 | #define EXYNOS_EMUL_DATA_MASK 0xFF | |
86 | #define EXYNOS_EMUL_ENABLE 0x1 | |
87 | ||
88 | /* Exynos5260 specific */ | |
89 | #define EXYNOS5260_TMU_REG_INTEN 0xC0 | |
90 | #define EXYNOS5260_TMU_REG_INTSTAT 0xC4 | |
91 | #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8 | |
92 | #define EXYNOS5260_EMUL_CON 0x100 | |
93 | ||
94 | /* Exynos4412 specific */ | |
95 | #define EXYNOS4412_MUX_ADDR_VALUE 6 | |
96 | #define EXYNOS4412_MUX_ADDR_SHIFT 20 | |
97 | ||
488c7455 | 98 | /* Exynos5433 specific registers */ |
488c7455 CC |
99 | #define EXYNOS5433_THD_TEMP_RISE3_0 0x050 |
100 | #define EXYNOS5433_THD_TEMP_RISE7_4 0x054 | |
101 | #define EXYNOS5433_THD_TEMP_FALL3_0 0x060 | |
102 | #define EXYNOS5433_THD_TEMP_FALL7_4 0x064 | |
103 | #define EXYNOS5433_TMU_REG_INTEN 0x0c0 | |
104 | #define EXYNOS5433_TMU_REG_INTPEND 0x0c8 | |
105 | #define EXYNOS5433_TMU_EMUL_CON 0x110 | |
106 | #define EXYNOS5433_TMU_PD_DET_EN 0x130 | |
107 | ||
108 | #define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT 16 | |
109 | #define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT 23 | |
110 | #define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK \ | |
111 | (0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT) | |
112 | #define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK BIT(23) | |
113 | ||
114 | #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING 0 | |
115 | #define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING 1 | |
116 | ||
117 | #define EXYNOS5433_PD_DET_EN 1 | |
118 | ||
61020d18 | 119 | #define EXYNOS5433_G3D_BASE 0x10070000 |
f22d9c03 | 120 | |
6c247393 AK |
121 | /* Exynos7 specific registers */ |
122 | #define EXYNOS7_THD_TEMP_RISE7_6 0x50 | |
123 | #define EXYNOS7_THD_TEMP_FALL7_6 0x60 | |
124 | #define EXYNOS7_TMU_REG_INTEN 0x110 | |
125 | #define EXYNOS7_TMU_REG_INTPEND 0x118 | |
126 | #define EXYNOS7_TMU_REG_EMUL_CON 0x160 | |
127 | ||
128 | #define EXYNOS7_TMU_TEMP_MASK 0x1ff | |
129 | #define EXYNOS7_PD_DET_EN_SHIFT 23 | |
130 | #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 | |
6c247393 AK |
131 | #define EXYNOS7_EMUL_DATA_SHIFT 7 |
132 | #define EXYNOS7_EMUL_DATA_MASK 0x1ff | |
133 | ||
718b4ca1 BZ |
134 | #define EXYNOS_FIRST_POINT_TRIM 25 |
135 | #define EXYNOS_SECOND_POINT_TRIM 85 | |
136 | ||
09d29426 BZ |
137 | #define EXYNOS_NOISE_CANCEL_MODE 4 |
138 | ||
3b6a1a80 | 139 | #define MCELSIUS 1000 |
7efd18a2 BZ |
140 | |
141 | enum soc_type { | |
142 | SOC_ARCH_EXYNOS3250 = 1, | |
143 | SOC_ARCH_EXYNOS4210, | |
144 | SOC_ARCH_EXYNOS4412, | |
145 | SOC_ARCH_EXYNOS5250, | |
146 | SOC_ARCH_EXYNOS5260, | |
147 | SOC_ARCH_EXYNOS5420, | |
148 | SOC_ARCH_EXYNOS5420_TRIMINFO, | |
149 | SOC_ARCH_EXYNOS5433, | |
7efd18a2 BZ |
150 | SOC_ARCH_EXYNOS7, |
151 | }; | |
152 | ||
cebe7373 ADK |
153 | /** |
154 | * struct exynos_tmu_data : A structure to hold the private data of the TMU | |
155 | driver | |
156 | * @id: identifier of the one instance of the TMU controller. | |
cebe7373 | 157 | * @base: base address of the single instance of the TMU controller. |
9025d563 | 158 | * @base_second: base address of the common registers of the TMU controller. |
cebe7373 ADK |
159 | * @irq: irq number of the TMU controller. |
160 | * @soc: id of the SOC type. | |
161 | * @irq_work: pointer to the irq work structure. | |
162 | * @lock: lock to implement synchronization. | |
163 | * @clk: pointer to the clock structure. | |
14a11dc7 | 164 | * @clk_sec: pointer to the clock structure for accessing the base_second. |
6c247393 | 165 | * @sclk: pointer to the clock structure for accessing the tmu special clk. |
199b3e3c | 166 | * @cal_type: calibration type for temperature |
e3ed3649 BZ |
167 | * @efuse_value: SoC defined fuse value |
168 | * @min_efuse_value: minimum valid trimming data | |
169 | * @max_efuse_value: maximum valid trimming data | |
cebe7373 ADK |
170 | * @temp_error1: fused value of the first point trim. |
171 | * @temp_error2: fused value of the second point trim. | |
fccfe099 BZ |
172 | * @gain: gain of amplifier in the positive-TC generator block |
173 | * 0 < gain <= 15 | |
61020d18 BZ |
174 | * @reference_voltage: reference voltage of amplifier |
175 | * in the positive-TC generator block | |
176 | * 0 < reference_voltage <= 31 | |
498d22f6 | 177 | * @regulator: pointer to the TMU regulator structure. |
cebe7373 | 178 | * @reg_conf: pointer to structure to register with core thermal. |
3a3a5f15 | 179 | * @ntrip: number of supported trip points. |
88fc6f73 | 180 | * @enabled: current status of TMU device |
72d1100b | 181 | * @tmu_initialize: SoC specific TMU initialization method |
37f9034f | 182 | * @tmu_control: SoC specific TMU control method |
b79985ca | 183 | * @tmu_read: SoC specific TMU temperature read method |
285d994a | 184 | * @tmu_set_emulation: SoC specific TMU emulation setting method |
a7331f72 | 185 | * @tmu_clear_irqs: SoC specific TMU interrupts clearing method |
cebe7373 | 186 | */ |
f22d9c03 | 187 | struct exynos_tmu_data { |
cebe7373 | 188 | int id; |
9d97e5c8 | 189 | void __iomem *base; |
9025d563 | 190 | void __iomem *base_second; |
9d97e5c8 | 191 | int irq; |
f22d9c03 | 192 | enum soc_type soc; |
9d97e5c8 DK |
193 | struct work_struct irq_work; |
194 | struct mutex lock; | |
6c247393 | 195 | struct clk *clk, *clk_sec, *sclk; |
199b3e3c | 196 | u32 cal_type; |
e3ed3649 BZ |
197 | u32 efuse_value; |
198 | u32 min_efuse_value; | |
199 | u32 max_efuse_value; | |
6c247393 | 200 | u16 temp_error1, temp_error2; |
fccfe099 | 201 | u8 gain; |
61020d18 | 202 | u8 reference_voltage; |
498d22f6 | 203 | struct regulator *regulator; |
3b6a1a80 | 204 | struct thermal_zone_device *tzd; |
3a3a5f15 | 205 | unsigned int ntrip; |
88fc6f73 | 206 | bool enabled; |
3b6a1a80 | 207 | |
c8f8f768 BZ |
208 | void (*tmu_set_trip_temp)(struct exynos_tmu_data *data, int trip, |
209 | u8 temp); | |
210 | void (*tmu_set_trip_hyst)(struct exynos_tmu_data *data, int trip, | |
211 | u8 temp, u8 hyst); | |
c35268f5 | 212 | void (*tmu_initialize)(struct platform_device *pdev); |
37f9034f | 213 | void (*tmu_control)(struct platform_device *pdev, bool on); |
b79985ca | 214 | int (*tmu_read)(struct exynos_tmu_data *data); |
17e8351a | 215 | void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp); |
a7331f72 | 216 | void (*tmu_clear_irqs)(struct exynos_tmu_data *data); |
9d97e5c8 DK |
217 | }; |
218 | ||
219 | /* | |
220 | * TMU treats temperature as a mapped temperature code. | |
221 | * The temperature is converted differently depending on the calibration type. | |
222 | */ | |
f22d9c03 | 223 | static int temp_to_code(struct exynos_tmu_data *data, u8 temp) |
9d97e5c8 | 224 | { |
199b3e3c | 225 | if (data->cal_type == TYPE_ONE_POINT_TRIMMING) |
718b4ca1 | 226 | return temp + data->temp_error1 - EXYNOS_FIRST_POINT_TRIM; |
ddb31d43 | 227 | |
718b4ca1 | 228 | return (temp - EXYNOS_FIRST_POINT_TRIM) * |
9c933b1b | 229 | (data->temp_error2 - data->temp_error1) / |
718b4ca1 | 230 | (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) + |
9c933b1b | 231 | data->temp_error1; |
9d97e5c8 DK |
232 | } |
233 | ||
234 | /* | |
235 | * Calculate a temperature value from a temperature code. | |
236 | * The unit of the temperature is degree Celsius. | |
237 | */ | |
6c247393 | 238 | static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code) |
9d97e5c8 | 239 | { |
199b3e3c | 240 | if (data->cal_type == TYPE_ONE_POINT_TRIMMING) |
718b4ca1 | 241 | return temp_code - data->temp_error1 + EXYNOS_FIRST_POINT_TRIM; |
ddb31d43 | 242 | |
9c933b1b | 243 | return (temp_code - data->temp_error1) * |
718b4ca1 | 244 | (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) / |
9c933b1b | 245 | (data->temp_error2 - data->temp_error1) + |
718b4ca1 | 246 | EXYNOS_FIRST_POINT_TRIM; |
9d97e5c8 DK |
247 | } |
248 | ||
8328a4b1 | 249 | static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info) |
9d97e5c8 | 250 | { |
aef27b65 BZ |
251 | u16 tmu_temp_mask = |
252 | (data->soc == SOC_ARCH_EXYNOS7) ? EXYNOS7_TMU_TEMP_MASK | |
253 | : EXYNOS_TMU_TEMP_MASK; | |
9d97e5c8 | 254 | |
aef27b65 | 255 | data->temp_error1 = trim_info & tmu_temp_mask; |
99d67fb9 | 256 | data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) & |
b8d582b9 | 257 | EXYNOS_TMU_TEMP_MASK); |
f22d9c03 | 258 | |
5000806c | 259 | if (!data->temp_error1 || |
e3ed3649 BZ |
260 | (data->min_efuse_value > data->temp_error1) || |
261 | (data->temp_error1 > data->max_efuse_value)) | |
262 | data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK; | |
5000806c ADK |
263 | |
264 | if (!data->temp_error2) | |
265 | data->temp_error2 = | |
e3ed3649 | 266 | (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) & |
5000806c | 267 | EXYNOS_TMU_TEMP_MASK; |
8328a4b1 | 268 | } |
f22d9c03 | 269 | |
f22d9c03 | 270 | static int exynos_tmu_initialize(struct platform_device *pdev) |
fe87789c | 271 | { |
f22d9c03 | 272 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
75e0f100 | 273 | struct thermal_zone_device *tzd = data->tzd; |
3b6a1a80 | 274 | const struct thermal_trip * const trips = |
75e0f100 | 275 | of_thermal_get_trip_points(tzd); |
97b3881b | 276 | unsigned int status; |
c8f8f768 | 277 | int ret = 0, temp, hyst; |
c65d3473 | 278 | |
3b6a1a80 | 279 | if (!trips) { |
75e0f100 BZ |
280 | dev_err(&pdev->dev, |
281 | "Cannot get trip points from device tree!\n"); | |
282 | return -ENODEV; | |
3b6a1a80 | 283 | } |
f22d9c03 | 284 | |
8f1c404b BZ |
285 | if (data->soc != SOC_ARCH_EXYNOS5433) /* FIXME */ |
286 | ret = tzd->ops->get_crit_temp(tzd, &temp); | |
287 | if (ret) { | |
288 | dev_err(&pdev->dev, | |
289 | "No CRITICAL trip point defined in device tree!\n"); | |
290 | goto out; | |
9d97e5c8 | 291 | } |
fe87789c | 292 | |
75e0f100 | 293 | if (of_thermal_get_ntrips(tzd) > data->ntrip) { |
3a3a5f15 KK |
294 | dev_info(&pdev->dev, |
295 | "More trip points than supported by this TMU.\n"); | |
296 | dev_info(&pdev->dev, | |
297 | "%d trip points should be configured in polling mode.\n", | |
75e0f100 | 298 | (of_thermal_get_ntrips(tzd) - data->ntrip)); |
3a3a5f15 KK |
299 | } |
300 | ||
9d97e5c8 DK |
301 | mutex_lock(&data->lock); |
302 | clk_enable(data->clk); | |
14a11dc7 NKC |
303 | if (!IS_ERR(data->clk_sec)) |
304 | clk_enable(data->clk_sec); | |
97b3881b BZ |
305 | |
306 | status = readb(data->base + EXYNOS_TMU_REG_STATUS); | |
fac36bac | 307 | if (!status) { |
97b3881b | 308 | ret = -EBUSY; |
fac36bac | 309 | } else { |
c8f8f768 BZ |
310 | int i, ntrips = |
311 | min_t(int, of_thermal_get_ntrips(tzd), data->ntrip); | |
312 | ||
c35268f5 | 313 | data->tmu_initialize(pdev); |
c8f8f768 BZ |
314 | |
315 | /* Write temperature code for rising and falling threshold */ | |
316 | for (i = 0; i < ntrips; i++) { | |
317 | /* Write temperature code for rising threshold */ | |
89335c20 BZ |
318 | ret = tzd->ops->get_trip_temp(tzd, i, &temp); |
319 | if (ret) | |
320 | goto err; | |
c8f8f768 BZ |
321 | temp /= MCELSIUS; |
322 | data->tmu_set_trip_temp(data, i, temp); | |
323 | ||
324 | /* Write temperature code for falling threshold */ | |
89335c20 BZ |
325 | ret = tzd->ops->get_trip_hyst(tzd, i, &hyst); |
326 | if (ret) | |
327 | goto err; | |
c8f8f768 BZ |
328 | hyst /= MCELSIUS; |
329 | data->tmu_set_trip_hyst(data, i, temp, hyst); | |
330 | } | |
331 | ||
fac36bac BZ |
332 | data->tmu_clear_irqs(data); |
333 | } | |
89335c20 | 334 | err: |
9d97e5c8 DK |
335 | clk_disable(data->clk); |
336 | mutex_unlock(&data->lock); | |
14a11dc7 NKC |
337 | if (!IS_ERR(data->clk_sec)) |
338 | clk_disable(data->clk_sec); | |
8f1c404b | 339 | out: |
9d97e5c8 DK |
340 | return ret; |
341 | } | |
342 | ||
d00671c3 | 343 | static u32 get_con_reg(struct exynos_tmu_data *data, u32 con) |
9d97e5c8 | 344 | { |
7575983c BZ |
345 | if (data->soc == SOC_ARCH_EXYNOS4412 || |
346 | data->soc == SOC_ARCH_EXYNOS3250) | |
347 | con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT); | |
86f5362e | 348 | |
99d67fb9 | 349 | con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT); |
61020d18 | 350 | con |= data->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT; |
d0a0ce3e | 351 | |
99d67fb9 | 352 | con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); |
fccfe099 | 353 | con |= (data->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); |
d0a0ce3e | 354 | |
09d29426 BZ |
355 | con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT); |
356 | con |= (EXYNOS_NOISE_CANCEL_MODE << EXYNOS_TMU_TRIP_MODE_SHIFT); | |
f22d9c03 | 357 | |
d00671c3 BZ |
358 | return con; |
359 | } | |
360 | ||
361 | static void exynos_tmu_control(struct platform_device *pdev, bool on) | |
362 | { | |
363 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | |
9d97e5c8 | 364 | |
d00671c3 BZ |
365 | mutex_lock(&data->lock); |
366 | clk_enable(data->clk); | |
37f9034f | 367 | data->tmu_control(pdev, on); |
88fc6f73 | 368 | data->enabled = on; |
9d97e5c8 DK |
369 | clk_disable(data->clk); |
370 | mutex_unlock(&data->lock); | |
371 | } | |
372 | ||
a503a10f BZ |
373 | static void exynos4210_tmu_set_trip_temp(struct exynos_tmu_data *data, |
374 | int trip, u8 temp) | |
9d97e5c8 | 375 | { |
3b6a1a80 | 376 | const struct thermal_trip * const trips = |
a503a10f BZ |
377 | of_thermal_get_trip_points(data->tzd); |
378 | u8 ref, th_code; | |
3b6a1a80 | 379 | |
a503a10f | 380 | ref = trips[0].temperature / MCELSIUS; |
9d97e5c8 | 381 | |
a503a10f BZ |
382 | if (trip == 0) { |
383 | th_code = temp_to_code(data, ref); | |
384 | writeb(th_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP); | |
72d1100b | 385 | } |
9d97e5c8 | 386 | |
a503a10f BZ |
387 | temp -= ref; |
388 | writeb(temp, data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + trip * 4); | |
389 | } | |
390 | ||
c8f8f768 BZ |
391 | /* failing thresholds are not supported on Exynos4210 */ |
392 | static void exynos4210_tmu_set_trip_hyst(struct exynos_tmu_data *data, | |
393 | int trip, u8 temp, u8 hyst) | |
394 | { | |
395 | } | |
396 | ||
c35268f5 | 397 | static void exynos4210_tmu_initialize(struct platform_device *pdev) |
9d97e5c8 | 398 | { |
72d1100b | 399 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
9d97e5c8 | 400 | |
72d1100b | 401 | sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO)); |
72d1100b | 402 | } |
9d97e5c8 | 403 | |
a503a10f BZ |
404 | static void exynos4412_tmu_set_trip_temp(struct exynos_tmu_data *data, |
405 | int trip, u8 temp) | |
406 | { | |
407 | u32 th, con; | |
72d1100b | 408 | |
a503a10f BZ |
409 | th = readl(data->base + EXYNOS_THD_TEMP_RISE); |
410 | th &= ~(0xff << 8 * trip); | |
411 | th |= temp_to_code(data, temp) << 8 * trip; | |
412 | writel(th, data->base + EXYNOS_THD_TEMP_RISE); | |
413 | ||
414 | if (trip == 3) { | |
415 | con = readl(data->base + EXYNOS_TMU_REG_CONTROL); | |
416 | con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT); | |
417 | writel(con, data->base + EXYNOS_TMU_REG_CONTROL); | |
3b6a1a80 | 418 | } |
a503a10f | 419 | } |
72d1100b | 420 | |
a503a10f BZ |
421 | static void exynos4412_tmu_set_trip_hyst(struct exynos_tmu_data *data, |
422 | int trip, u8 temp, u8 hyst) | |
423 | { | |
424 | u32 th; | |
425 | ||
426 | th = readl(data->base + EXYNOS_THD_TEMP_FALL); | |
427 | th &= ~(0xff << 8 * trip); | |
428 | if (hyst) | |
429 | th |= temp_to_code(data, temp - hyst) << 8 * trip; | |
430 | writel(th, data->base + EXYNOS_THD_TEMP_FALL); | |
72d1100b BZ |
431 | } |
432 | ||
c35268f5 | 433 | static void exynos4412_tmu_initialize(struct platform_device *pdev) |
72d1100b BZ |
434 | { |
435 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | |
a503a10f | 436 | unsigned int trim_info, ctrl; |
72d1100b BZ |
437 | |
438 | if (data->soc == SOC_ARCH_EXYNOS3250 || | |
439 | data->soc == SOC_ARCH_EXYNOS4412 || | |
440 | data->soc == SOC_ARCH_EXYNOS5250) { | |
441 | if (data->soc == SOC_ARCH_EXYNOS3250) { | |
442 | ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1); | |
443 | ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; | |
444 | writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1); | |
ddb31d43 | 445 | } |
72d1100b BZ |
446 | ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2); |
447 | ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; | |
448 | writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2); | |
449 | } | |
ddb31d43 | 450 | |
72d1100b BZ |
451 | /* On exynos5420 the triminfo register is in the shared space */ |
452 | if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) | |
453 | trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO); | |
454 | else | |
455 | trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); | |
456 | ||
457 | sanitize_temp_error(data, trim_info); | |
a503a10f | 458 | } |
72d1100b | 459 | |
a503a10f BZ |
460 | static void exynos5433_tmu_set_trip_temp(struct exynos_tmu_data *data, |
461 | int trip, u8 temp) | |
462 | { | |
463 | unsigned int reg_off, j; | |
464 | u32 th; | |
72d1100b | 465 | |
a503a10f BZ |
466 | if (trip > 3) { |
467 | reg_off = EXYNOS5433_THD_TEMP_RISE7_4; | |
468 | j = trip - 4; | |
469 | } else { | |
470 | reg_off = EXYNOS5433_THD_TEMP_RISE3_0; | |
471 | j = trip; | |
72d1100b | 472 | } |
3b6a1a80 | 473 | |
a503a10f BZ |
474 | th = readl(data->base + reg_off); |
475 | th &= ~(0xff << j * 8); | |
476 | th |= (temp_to_code(data, temp) << j * 8); | |
477 | writel(th, data->base + reg_off); | |
478 | } | |
3b6a1a80 | 479 | |
a503a10f BZ |
480 | static void exynos5433_tmu_set_trip_hyst(struct exynos_tmu_data *data, |
481 | int trip, u8 temp, u8 hyst) | |
482 | { | |
483 | unsigned int reg_off, j; | |
484 | u32 th; | |
3b6a1a80 | 485 | |
a503a10f BZ |
486 | if (trip > 3) { |
487 | reg_off = EXYNOS5433_THD_TEMP_FALL7_4; | |
488 | j = trip - 4; | |
489 | } else { | |
490 | reg_off = EXYNOS5433_THD_TEMP_FALL3_0; | |
491 | j = trip; | |
72d1100b | 492 | } |
3b6a1a80 | 493 | |
a503a10f BZ |
494 | th = readl(data->base + reg_off); |
495 | th &= ~(0xff << j * 8); | |
496 | th |= (temp_to_code(data, temp - hyst) << j * 8); | |
497 | writel(th, data->base + reg_off); | |
72d1100b | 498 | } |
9d97e5c8 | 499 | |
c35268f5 | 500 | static void exynos5433_tmu_initialize(struct platform_device *pdev) |
488c7455 CC |
501 | { |
502 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | |
97b3881b | 503 | unsigned int trim_info; |
c8f8f768 | 504 | int sensor_id, cal_type; |
488c7455 CC |
505 | |
506 | trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); | |
507 | sanitize_temp_error(data, trim_info); | |
508 | ||
509 | /* Read the temperature sensor id */ | |
510 | sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK) | |
511 | >> EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT; | |
512 | dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id); | |
513 | ||
514 | /* Read the calibration mode */ | |
515 | writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO); | |
516 | cal_type = (trim_info & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK) | |
517 | >> EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT; | |
518 | ||
519 | switch (cal_type) { | |
488c7455 | 520 | case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING: |
199b3e3c | 521 | data->cal_type = TYPE_TWO_POINT_TRIMMING; |
488c7455 | 522 | break; |
199b3e3c | 523 | case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING: |
488c7455 | 524 | default: |
199b3e3c | 525 | data->cal_type = TYPE_ONE_POINT_TRIMMING; |
488c7455 | 526 | break; |
baba1ebb | 527 | } |
488c7455 CC |
528 | |
529 | dev_info(&pdev->dev, "Calibration type is %d-point calibration\n", | |
530 | cal_type ? 2 : 1); | |
488c7455 CC |
531 | } |
532 | ||
a503a10f BZ |
533 | static void exynos7_tmu_set_trip_temp(struct exynos_tmu_data *data, |
534 | int trip, u8 temp) | |
72d1100b | 535 | { |
a503a10f BZ |
536 | unsigned int reg_off, bit_off; |
537 | u32 th; | |
72d1100b | 538 | |
a503a10f BZ |
539 | reg_off = ((7 - trip) / 2) * 4; |
540 | bit_off = ((8 - trip) % 2); | |
72d1100b | 541 | |
a503a10f BZ |
542 | th = readl(data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); |
543 | th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); | |
544 | th |= temp_to_code(data, temp) << (16 * bit_off); | |
545 | writel(th, data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); | |
546 | } | |
72d1100b | 547 | |
a503a10f BZ |
548 | static void exynos7_tmu_set_trip_hyst(struct exynos_tmu_data *data, |
549 | int trip, u8 temp, u8 hyst) | |
550 | { | |
551 | unsigned int reg_off, bit_off; | |
552 | u32 th; | |
72d1100b | 553 | |
a503a10f BZ |
554 | reg_off = ((7 - trip) / 2) * 4; |
555 | bit_off = ((8 - trip) % 2); | |
e35dbb4d | 556 | |
a503a10f BZ |
557 | th = readl(data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); |
558 | th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); | |
559 | th |= temp_to_code(data, temp - hyst) << (16 * bit_off); | |
560 | writel(th, data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); | |
9d97e5c8 DK |
561 | } |
562 | ||
c35268f5 | 563 | static void exynos7_tmu_initialize(struct platform_device *pdev) |
6c247393 AK |
564 | { |
565 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | |
97b3881b | 566 | unsigned int trim_info; |
6c247393 AK |
567 | |
568 | trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); | |
aef27b65 | 569 | sanitize_temp_error(data, trim_info); |
6c247393 AK |
570 | } |
571 | ||
37f9034f | 572 | static void exynos4210_tmu_control(struct platform_device *pdev, bool on) |
bffd1f8a | 573 | { |
37f9034f | 574 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
3b6a1a80 | 575 | struct thermal_zone_device *tz = data->tzd; |
64e94192 | 576 | unsigned int con, interrupt_en = 0, i; |
bffd1f8a | 577 | |
37f9034f | 578 | con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); |
bffd1f8a | 579 | |
37f9034f | 580 | if (on) { |
64e94192 BZ |
581 | for (i = 0; i < data->ntrip; i++) { |
582 | if (!of_thermal_is_trip_valid(tz, i)) | |
583 | continue; | |
584 | ||
585 | interrupt_en |= | |
586 | (1 << (EXYNOS_TMU_INTEN_RISE0_SHIFT + i * 4)); | |
587 | } | |
3b6a1a80 | 588 | |
e0761533 | 589 | if (data->soc != SOC_ARCH_EXYNOS4210) |
37f9034f BZ |
590 | interrupt_en |= |
591 | interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; | |
64e94192 BZ |
592 | |
593 | con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); | |
37f9034f BZ |
594 | } else { |
595 | con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); | |
37f9034f | 596 | } |
64e94192 | 597 | |
37f9034f BZ |
598 | writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); |
599 | writel(con, data->base + EXYNOS_TMU_REG_CONTROL); | |
600 | } | |
601 | ||
488c7455 CC |
602 | static void exynos5433_tmu_control(struct platform_device *pdev, bool on) |
603 | { | |
604 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | |
605 | struct thermal_zone_device *tz = data->tzd; | |
64e94192 | 606 | unsigned int con, interrupt_en = 0, pd_det_en, i; |
488c7455 CC |
607 | |
608 | con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); | |
609 | ||
610 | if (on) { | |
64e94192 BZ |
611 | for (i = 0; i < data->ntrip; i++) { |
612 | if (!of_thermal_is_trip_valid(tz, i)) | |
613 | continue; | |
614 | ||
615 | interrupt_en |= | |
616 | (1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i)); | |
617 | } | |
488c7455 CC |
618 | |
619 | interrupt_en |= | |
620 | interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; | |
64e94192 BZ |
621 | |
622 | con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); | |
623 | } else | |
488c7455 | 624 | con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); |
488c7455 CC |
625 | |
626 | pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0; | |
627 | ||
628 | writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN); | |
629 | writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN); | |
630 | writel(con, data->base + EXYNOS_TMU_REG_CONTROL); | |
631 | } | |
632 | ||
6c247393 AK |
633 | static void exynos7_tmu_control(struct platform_device *pdev, bool on) |
634 | { | |
635 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | |
636 | struct thermal_zone_device *tz = data->tzd; | |
64e94192 | 637 | unsigned int con, interrupt_en = 0, i; |
6c247393 AK |
638 | |
639 | con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); | |
640 | ||
641 | if (on) { | |
64e94192 BZ |
642 | for (i = 0; i < data->ntrip; i++) { |
643 | if (!of_thermal_is_trip_valid(tz, i)) | |
644 | continue; | |
645 | ||
646 | interrupt_en |= | |
647 | (1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i)); | |
648 | } | |
6c247393 AK |
649 | |
650 | interrupt_en |= | |
651 | interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; | |
64e94192 BZ |
652 | |
653 | con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); | |
654 | con |= (1 << EXYNOS7_PD_DET_EN_SHIFT); | |
6c247393 AK |
655 | } else { |
656 | con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); | |
42b696e8 | 657 | con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT); |
6c247393 | 658 | } |
6c247393 AK |
659 | |
660 | writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN); | |
661 | writel(con, data->base + EXYNOS_TMU_REG_CONTROL); | |
662 | } | |
663 | ||
17e8351a | 664 | static int exynos_get_temp(void *p, int *temp) |
9d97e5c8 | 665 | { |
3b6a1a80 | 666 | struct exynos_tmu_data *data = p; |
c8da6cde | 667 | int value, ret = 0; |
3b6a1a80 | 668 | |
3b5236cc | 669 | if (!data || !data->tmu_read) |
3b6a1a80 | 670 | return -EINVAL; |
ffe6e16f KK |
671 | else if (!data->enabled) |
672 | /* | |
673 | * Called too early, probably | |
674 | * from thermal_zone_of_sensor_register(). | |
675 | */ | |
676 | return -EAGAIN; | |
bffd1f8a ADK |
677 | |
678 | mutex_lock(&data->lock); | |
679 | clk_enable(data->clk); | |
3b6a1a80 | 680 | |
c8da6cde MS |
681 | value = data->tmu_read(data); |
682 | if (value < 0) | |
683 | ret = value; | |
684 | else | |
685 | *temp = code_to_temp(data, value) * MCELSIUS; | |
3b6a1a80 | 686 | |
9d97e5c8 DK |
687 | clk_disable(data->clk); |
688 | mutex_unlock(&data->lock); | |
bffd1f8a | 689 | |
c8da6cde | 690 | return ret; |
9d97e5c8 | 691 | } |
bffd1f8a | 692 | |
bffd1f8a | 693 | #ifdef CONFIG_THERMAL_EMULATION |
154013ea | 694 | static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, |
17e8351a | 695 | int temp) |
154013ea | 696 | { |
bffd1f8a ADK |
697 | if (temp) { |
698 | temp /= MCELSIUS; | |
699 | ||
8014220d KK |
700 | val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT); |
701 | val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT); | |
6c247393 AK |
702 | if (data->soc == SOC_ARCH_EXYNOS7) { |
703 | val &= ~(EXYNOS7_EMUL_DATA_MASK << | |
704 | EXYNOS7_EMUL_DATA_SHIFT); | |
705 | val |= (temp_to_code(data, temp) << | |
706 | EXYNOS7_EMUL_DATA_SHIFT) | | |
707 | EXYNOS_EMUL_ENABLE; | |
708 | } else { | |
709 | val &= ~(EXYNOS_EMUL_DATA_MASK << | |
710 | EXYNOS_EMUL_DATA_SHIFT); | |
711 | val |= (temp_to_code(data, temp) << | |
712 | EXYNOS_EMUL_DATA_SHIFT) | | |
713 | EXYNOS_EMUL_ENABLE; | |
714 | } | |
bffd1f8a | 715 | } else { |
b8d582b9 | 716 | val &= ~EXYNOS_EMUL_ENABLE; |
bffd1f8a ADK |
717 | } |
718 | ||
154013ea BZ |
719 | return val; |
720 | } | |
721 | ||
285d994a | 722 | static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, |
17e8351a | 723 | int temp) |
285d994a BZ |
724 | { |
725 | unsigned int val; | |
726 | u32 emul_con; | |
727 | ||
728 | if (data->soc == SOC_ARCH_EXYNOS5260) | |
729 | emul_con = EXYNOS5260_EMUL_CON; | |
b28fec13 | 730 | else if (data->soc == SOC_ARCH_EXYNOS5433) |
488c7455 | 731 | emul_con = EXYNOS5433_TMU_EMUL_CON; |
6c247393 AK |
732 | else if (data->soc == SOC_ARCH_EXYNOS7) |
733 | emul_con = EXYNOS7_TMU_REG_EMUL_CON; | |
285d994a BZ |
734 | else |
735 | emul_con = EXYNOS_EMUL_CON; | |
736 | ||
737 | val = readl(data->base + emul_con); | |
738 | val = get_emul_con_reg(data, val, temp); | |
739 | writel(val, data->base + emul_con); | |
740 | } | |
741 | ||
17e8351a | 742 | static int exynos_tmu_set_emulation(void *drv_data, int temp) |
bffd1f8a ADK |
743 | { |
744 | struct exynos_tmu_data *data = drv_data; | |
bffd1f8a ADK |
745 | int ret = -EINVAL; |
746 | ||
ef3f80fc | 747 | if (data->soc == SOC_ARCH_EXYNOS4210) |
bffd1f8a | 748 | goto out; |
bffd1f8a | 749 | |
bffd1f8a ADK |
750 | if (temp && temp < MCELSIUS) |
751 | goto out; | |
752 | ||
753 | mutex_lock(&data->lock); | |
754 | clk_enable(data->clk); | |
285d994a | 755 | data->tmu_set_emulation(data, temp); |
bffd1f8a ADK |
756 | clk_disable(data->clk); |
757 | mutex_unlock(&data->lock); | |
758 | return 0; | |
759 | out: | |
760 | return ret; | |
761 | } | |
762 | #else | |
285d994a | 763 | #define exynos4412_tmu_set_emulation NULL |
17e8351a | 764 | static int exynos_tmu_set_emulation(void *drv_data, int temp) |
bffd1f8a | 765 | { return -EINVAL; } |
afae1442 | 766 | #endif /* CONFIG_THERMAL_EMULATION */ |
bffd1f8a | 767 | |
b79985ca BZ |
768 | static int exynos4210_tmu_read(struct exynos_tmu_data *data) |
769 | { | |
770 | int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); | |
771 | ||
772 | /* "temp_code" should range between 75 and 175 */ | |
773 | return (ret < 75 || ret > 175) ? -ENODATA : ret; | |
774 | } | |
775 | ||
776 | static int exynos4412_tmu_read(struct exynos_tmu_data *data) | |
777 | { | |
778 | return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); | |
779 | } | |
780 | ||
6c247393 AK |
781 | static int exynos7_tmu_read(struct exynos_tmu_data *data) |
782 | { | |
783 | return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) & | |
784 | EXYNOS7_TMU_TEMP_MASK; | |
785 | } | |
786 | ||
f22d9c03 | 787 | static void exynos_tmu_work(struct work_struct *work) |
9d97e5c8 | 788 | { |
f22d9c03 ADK |
789 | struct exynos_tmu_data *data = container_of(work, |
790 | struct exynos_tmu_data, irq_work); | |
a0395eee | 791 | |
b43e3cfe BZ |
792 | thermal_zone_device_update(data->tzd, THERMAL_EVENT_UNSPECIFIED); |
793 | ||
9d97e5c8 DK |
794 | mutex_lock(&data->lock); |
795 | clk_enable(data->clk); | |
b8d582b9 | 796 | |
a4463c4f | 797 | /* TODO: take action based on particular interrupt */ |
a7331f72 | 798 | data->tmu_clear_irqs(data); |
b8d582b9 | 799 | |
9d97e5c8 DK |
800 | clk_disable(data->clk); |
801 | mutex_unlock(&data->lock); | |
f22d9c03 | 802 | enable_irq(data->irq); |
9d97e5c8 DK |
803 | } |
804 | ||
a7331f72 BZ |
805 | static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) |
806 | { | |
807 | unsigned int val_irq; | |
808 | u32 tmu_intstat, tmu_intclear; | |
809 | ||
810 | if (data->soc == SOC_ARCH_EXYNOS5260) { | |
811 | tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT; | |
812 | tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR; | |
6c247393 AK |
813 | } else if (data->soc == SOC_ARCH_EXYNOS7) { |
814 | tmu_intstat = EXYNOS7_TMU_REG_INTPEND; | |
815 | tmu_intclear = EXYNOS7_TMU_REG_INTPEND; | |
488c7455 CC |
816 | } else if (data->soc == SOC_ARCH_EXYNOS5433) { |
817 | tmu_intstat = EXYNOS5433_TMU_REG_INTPEND; | |
818 | tmu_intclear = EXYNOS5433_TMU_REG_INTPEND; | |
a7331f72 BZ |
819 | } else { |
820 | tmu_intstat = EXYNOS_TMU_REG_INTSTAT; | |
821 | tmu_intclear = EXYNOS_TMU_REG_INTCLEAR; | |
822 | } | |
823 | ||
824 | val_irq = readl(data->base + tmu_intstat); | |
825 | /* | |
826 | * Clear the interrupts. Please note that the documentation for | |
827 | * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly | |
828 | * states that INTCLEAR register has a different placing of bits | |
829 | * responsible for FALL IRQs than INTSTAT register. Exynos5420 | |
830 | * and Exynos5440 documentation is correct (Exynos4210 doesn't | |
831 | * support FALL IRQs at all). | |
832 | */ | |
833 | writel(val_irq, data->base + tmu_intclear); | |
834 | } | |
835 | ||
f22d9c03 | 836 | static irqreturn_t exynos_tmu_irq(int irq, void *id) |
9d97e5c8 | 837 | { |
f22d9c03 | 838 | struct exynos_tmu_data *data = id; |
9d97e5c8 DK |
839 | |
840 | disable_irq_nosync(irq); | |
841 | schedule_work(&data->irq_work); | |
842 | ||
843 | return IRQ_HANDLED; | |
844 | } | |
17be868e | 845 | |
17be868e | 846 | static const struct of_device_id exynos_tmu_match[] = { |
fee88e2b MP |
847 | { |
848 | .compatible = "samsung,exynos3250-tmu", | |
849 | .data = (const void *)SOC_ARCH_EXYNOS3250, | |
850 | }, { | |
851 | .compatible = "samsung,exynos4210-tmu", | |
852 | .data = (const void *)SOC_ARCH_EXYNOS4210, | |
853 | }, { | |
854 | .compatible = "samsung,exynos4412-tmu", | |
855 | .data = (const void *)SOC_ARCH_EXYNOS4412, | |
856 | }, { | |
857 | .compatible = "samsung,exynos5250-tmu", | |
858 | .data = (const void *)SOC_ARCH_EXYNOS5250, | |
859 | }, { | |
860 | .compatible = "samsung,exynos5260-tmu", | |
861 | .data = (const void *)SOC_ARCH_EXYNOS5260, | |
862 | }, { | |
863 | .compatible = "samsung,exynos5420-tmu", | |
864 | .data = (const void *)SOC_ARCH_EXYNOS5420, | |
865 | }, { | |
866 | .compatible = "samsung,exynos5420-tmu-ext-triminfo", | |
867 | .data = (const void *)SOC_ARCH_EXYNOS5420_TRIMINFO, | |
868 | }, { | |
869 | .compatible = "samsung,exynos5433-tmu", | |
870 | .data = (const void *)SOC_ARCH_EXYNOS5433, | |
fee88e2b MP |
871 | }, { |
872 | .compatible = "samsung,exynos7-tmu", | |
873 | .data = (const void *)SOC_ARCH_EXYNOS7, | |
874 | }, | |
875 | { }, | |
17be868e ADK |
876 | }; |
877 | MODULE_DEVICE_TABLE(of, exynos_tmu_match); | |
17be868e | 878 | |
cebe7373 | 879 | static int exynos_map_dt_data(struct platform_device *pdev) |
9d97e5c8 | 880 | { |
cebe7373 | 881 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
cebe7373 ADK |
882 | struct resource res; |
883 | ||
73b5b1d7 | 884 | if (!data || !pdev->dev.of_node) |
cebe7373 | 885 | return -ENODEV; |
9d97e5c8 | 886 | |
cebe7373 ADK |
887 | data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl"); |
888 | if (data->id < 0) | |
889 | data->id = 0; | |
17be868e | 890 | |
cebe7373 ADK |
891 | data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); |
892 | if (data->irq <= 0) { | |
893 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
894 | return -ENODEV; | |
895 | } | |
896 | ||
897 | if (of_address_to_resource(pdev->dev.of_node, 0, &res)) { | |
898 | dev_err(&pdev->dev, "failed to get Resource 0\n"); | |
899 | return -ENODEV; | |
900 | } | |
901 | ||
902 | data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); | |
903 | if (!data->base) { | |
904 | dev_err(&pdev->dev, "Failed to ioremap memory\n"); | |
905 | return -EADDRNOTAVAIL; | |
906 | } | |
907 | ||
fee88e2b | 908 | data->soc = (enum soc_type)of_device_get_match_data(&pdev->dev); |
56adb9ef BZ |
909 | |
910 | switch (data->soc) { | |
911 | case SOC_ARCH_EXYNOS4210: | |
c8f8f768 BZ |
912 | data->tmu_set_trip_temp = exynos4210_tmu_set_trip_temp; |
913 | data->tmu_set_trip_hyst = exynos4210_tmu_set_trip_hyst; | |
56adb9ef BZ |
914 | data->tmu_initialize = exynos4210_tmu_initialize; |
915 | data->tmu_control = exynos4210_tmu_control; | |
916 | data->tmu_read = exynos4210_tmu_read; | |
917 | data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; | |
3a3a5f15 | 918 | data->ntrip = 4; |
fccfe099 | 919 | data->gain = 15; |
61020d18 | 920 | data->reference_voltage = 7; |
e3ed3649 BZ |
921 | data->efuse_value = 55; |
922 | data->min_efuse_value = 40; | |
923 | data->max_efuse_value = 100; | |
56adb9ef BZ |
924 | break; |
925 | case SOC_ARCH_EXYNOS3250: | |
926 | case SOC_ARCH_EXYNOS4412: | |
927 | case SOC_ARCH_EXYNOS5250: | |
928 | case SOC_ARCH_EXYNOS5260: | |
929 | case SOC_ARCH_EXYNOS5420: | |
930 | case SOC_ARCH_EXYNOS5420_TRIMINFO: | |
c8f8f768 BZ |
931 | data->tmu_set_trip_temp = exynos4412_tmu_set_trip_temp; |
932 | data->tmu_set_trip_hyst = exynos4412_tmu_set_trip_hyst; | |
56adb9ef BZ |
933 | data->tmu_initialize = exynos4412_tmu_initialize; |
934 | data->tmu_control = exynos4210_tmu_control; | |
935 | data->tmu_read = exynos4412_tmu_read; | |
936 | data->tmu_set_emulation = exynos4412_tmu_set_emulation; | |
937 | data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; | |
3a3a5f15 | 938 | data->ntrip = 4; |
fccfe099 | 939 | data->gain = 8; |
61020d18 | 940 | data->reference_voltage = 16; |
e3ed3649 BZ |
941 | data->efuse_value = 55; |
942 | if (data->soc != SOC_ARCH_EXYNOS5420 && | |
943 | data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) | |
944 | data->min_efuse_value = 40; | |
945 | else | |
946 | data->min_efuse_value = 0; | |
947 | data->max_efuse_value = 100; | |
56adb9ef | 948 | break; |
488c7455 | 949 | case SOC_ARCH_EXYNOS5433: |
c8f8f768 BZ |
950 | data->tmu_set_trip_temp = exynos5433_tmu_set_trip_temp; |
951 | data->tmu_set_trip_hyst = exynos5433_tmu_set_trip_hyst; | |
488c7455 CC |
952 | data->tmu_initialize = exynos5433_tmu_initialize; |
953 | data->tmu_control = exynos5433_tmu_control; | |
954 | data->tmu_read = exynos4412_tmu_read; | |
955 | data->tmu_set_emulation = exynos4412_tmu_set_emulation; | |
956 | data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; | |
3a3a5f15 | 957 | data->ntrip = 8; |
fccfe099 | 958 | data->gain = 8; |
61020d18 BZ |
959 | if (res.start == EXYNOS5433_G3D_BASE) |
960 | data->reference_voltage = 23; | |
961 | else | |
962 | data->reference_voltage = 16; | |
e3ed3649 BZ |
963 | data->efuse_value = 75; |
964 | data->min_efuse_value = 40; | |
965 | data->max_efuse_value = 150; | |
56adb9ef | 966 | break; |
6c247393 | 967 | case SOC_ARCH_EXYNOS7: |
c8f8f768 BZ |
968 | data->tmu_set_trip_temp = exynos7_tmu_set_trip_temp; |
969 | data->tmu_set_trip_hyst = exynos7_tmu_set_trip_hyst; | |
6c247393 AK |
970 | data->tmu_initialize = exynos7_tmu_initialize; |
971 | data->tmu_control = exynos7_tmu_control; | |
972 | data->tmu_read = exynos7_tmu_read; | |
973 | data->tmu_set_emulation = exynos4412_tmu_set_emulation; | |
974 | data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; | |
3a3a5f15 | 975 | data->ntrip = 8; |
fccfe099 | 976 | data->gain = 9; |
61020d18 | 977 | data->reference_voltage = 17; |
e3ed3649 BZ |
978 | data->efuse_value = 75; |
979 | data->min_efuse_value = 15; | |
980 | data->max_efuse_value = 100; | |
6c247393 | 981 | break; |
56adb9ef BZ |
982 | default: |
983 | dev_err(&pdev->dev, "Platform not supported\n"); | |
984 | return -EINVAL; | |
985 | } | |
986 | ||
199b3e3c BZ |
987 | data->cal_type = TYPE_ONE_POINT_TRIMMING; |
988 | ||
d9b6ee14 ADK |
989 | /* |
990 | * Check if the TMU shares some registers and then try to map the | |
991 | * memory of common registers. | |
992 | */ | |
8014220d | 993 | if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) |
d9b6ee14 ADK |
994 | return 0; |
995 | ||
996 | if (of_address_to_resource(pdev->dev.of_node, 1, &res)) { | |
997 | dev_err(&pdev->dev, "failed to get Resource 1\n"); | |
998 | return -ENODEV; | |
999 | } | |
1000 | ||
9025d563 | 1001 | data->base_second = devm_ioremap(&pdev->dev, res.start, |
d9b6ee14 | 1002 | resource_size(&res)); |
9025d563 | 1003 | if (!data->base_second) { |
d9b6ee14 ADK |
1004 | dev_err(&pdev->dev, "Failed to ioremap memory\n"); |
1005 | return -ENOMEM; | |
1006 | } | |
cebe7373 ADK |
1007 | |
1008 | return 0; | |
1009 | } | |
1010 | ||
c3c04d9d | 1011 | static const struct thermal_zone_of_device_ops exynos_sensor_ops = { |
3b6a1a80 LM |
1012 | .get_temp = exynos_get_temp, |
1013 | .set_emul_temp = exynos_tmu_set_emulation, | |
1014 | }; | |
1015 | ||
cebe7373 ADK |
1016 | static int exynos_tmu_probe(struct platform_device *pdev) |
1017 | { | |
3b6a1a80 LM |
1018 | struct exynos_tmu_data *data; |
1019 | int ret; | |
cebe7373 | 1020 | |
79e093c3 ADK |
1021 | data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), |
1022 | GFP_KERNEL); | |
2a9675b3 | 1023 | if (!data) |
9d97e5c8 | 1024 | return -ENOMEM; |
9d97e5c8 | 1025 | |
cebe7373 ADK |
1026 | platform_set_drvdata(pdev, data); |
1027 | mutex_init(&data->lock); | |
9d97e5c8 | 1028 | |
824ead03 KK |
1029 | /* |
1030 | * Try enabling the regulator if found | |
1031 | * TODO: Add regulator as an SOC feature, so that regulator enable | |
1032 | * is a compulsory call. | |
1033 | */ | |
4d3583cd | 1034 | data->regulator = devm_regulator_get_optional(&pdev->dev, "vtmu"); |
824ead03 KK |
1035 | if (!IS_ERR(data->regulator)) { |
1036 | ret = regulator_enable(data->regulator); | |
1037 | if (ret) { | |
1038 | dev_err(&pdev->dev, "failed to enable vtmu\n"); | |
1039 | return ret; | |
1040 | } | |
1041 | } else { | |
ccb361d2 JMC |
1042 | if (PTR_ERR(data->regulator) == -EPROBE_DEFER) |
1043 | return -EPROBE_DEFER; | |
824ead03 | 1044 | dev_info(&pdev->dev, "Regulator node (vtmu) not found\n"); |
3b6a1a80 | 1045 | } |
824ead03 | 1046 | |
cebe7373 ADK |
1047 | ret = exynos_map_dt_data(pdev); |
1048 | if (ret) | |
3b6a1a80 | 1049 | goto err_sensor; |
9d97e5c8 | 1050 | |
cebe7373 | 1051 | INIT_WORK(&data->irq_work, exynos_tmu_work); |
9d97e5c8 | 1052 | |
2a16279c | 1053 | data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); |
9d97e5c8 | 1054 | if (IS_ERR(data->clk)) { |
9d97e5c8 | 1055 | dev_err(&pdev->dev, "Failed to get clock\n"); |
3b6a1a80 LM |
1056 | ret = PTR_ERR(data->clk); |
1057 | goto err_sensor; | |
9d97e5c8 DK |
1058 | } |
1059 | ||
14a11dc7 NKC |
1060 | data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif"); |
1061 | if (IS_ERR(data->clk_sec)) { | |
1062 | if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) { | |
1063 | dev_err(&pdev->dev, "Failed to get triminfo clock\n"); | |
3b6a1a80 LM |
1064 | ret = PTR_ERR(data->clk_sec); |
1065 | goto err_sensor; | |
14a11dc7 NKC |
1066 | } |
1067 | } else { | |
1068 | ret = clk_prepare(data->clk_sec); | |
1069 | if (ret) { | |
1070 | dev_err(&pdev->dev, "Failed to get clock\n"); | |
3b6a1a80 | 1071 | goto err_sensor; |
14a11dc7 NKC |
1072 | } |
1073 | } | |
1074 | ||
2a16279c | 1075 | ret = clk_prepare(data->clk); |
14a11dc7 NKC |
1076 | if (ret) { |
1077 | dev_err(&pdev->dev, "Failed to get clock\n"); | |
1078 | goto err_clk_sec; | |
1079 | } | |
2a16279c | 1080 | |
488c7455 CC |
1081 | switch (data->soc) { |
1082 | case SOC_ARCH_EXYNOS5433: | |
1083 | case SOC_ARCH_EXYNOS7: | |
6c247393 AK |
1084 | data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk"); |
1085 | if (IS_ERR(data->sclk)) { | |
1086 | dev_err(&pdev->dev, "Failed to get sclk\n"); | |
1087 | goto err_clk; | |
1088 | } else { | |
1089 | ret = clk_prepare_enable(data->sclk); | |
1090 | if (ret) { | |
1091 | dev_err(&pdev->dev, "Failed to enable sclk\n"); | |
1092 | goto err_clk; | |
1093 | } | |
1094 | } | |
488c7455 CC |
1095 | break; |
1096 | default: | |
1097 | break; | |
baba1ebb | 1098 | } |
6c247393 | 1099 | |
9e4249b4 KK |
1100 | /* |
1101 | * data->tzd must be registered before calling exynos_tmu_initialize(), | |
1102 | * requesting irq and calling exynos_tmu_control(). | |
1103 | */ | |
1104 | data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, | |
1105 | &exynos_sensor_ops); | |
1106 | if (IS_ERR(data->tzd)) { | |
1107 | ret = PTR_ERR(data->tzd); | |
1108 | dev_err(&pdev->dev, "Failed to register sensor: %d\n", ret); | |
1109 | goto err_sclk; | |
1110 | } | |
6c247393 | 1111 | |
f22d9c03 | 1112 | ret = exynos_tmu_initialize(pdev); |
9d97e5c8 DK |
1113 | if (ret) { |
1114 | dev_err(&pdev->dev, "Failed to initialize TMU\n"); | |
9e4249b4 | 1115 | goto err_thermal; |
9d97e5c8 DK |
1116 | } |
1117 | ||
cebe7373 ADK |
1118 | ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq, |
1119 | IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data); | |
1120 | if (ret) { | |
1121 | dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); | |
9e4249b4 | 1122 | goto err_thermal; |
cebe7373 | 1123 | } |
bbf63be4 | 1124 | |
3b6a1a80 | 1125 | exynos_tmu_control(pdev, true); |
9d97e5c8 | 1126 | return 0; |
9e4249b4 KK |
1127 | |
1128 | err_thermal: | |
1129 | thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); | |
6c247393 AK |
1130 | err_sclk: |
1131 | clk_disable_unprepare(data->sclk); | |
9d97e5c8 | 1132 | err_clk: |
2a16279c | 1133 | clk_unprepare(data->clk); |
14a11dc7 NKC |
1134 | err_clk_sec: |
1135 | if (!IS_ERR(data->clk_sec)) | |
1136 | clk_unprepare(data->clk_sec); | |
3b6a1a80 | 1137 | err_sensor: |
bfa26838 | 1138 | if (!IS_ERR(data->regulator)) |
5f09a5cb | 1139 | regulator_disable(data->regulator); |
3b6a1a80 | 1140 | |
9d97e5c8 DK |
1141 | return ret; |
1142 | } | |
1143 | ||
4eab7a9e | 1144 | static int exynos_tmu_remove(struct platform_device *pdev) |
9d97e5c8 | 1145 | { |
f22d9c03 | 1146 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
3b6a1a80 | 1147 | struct thermal_zone_device *tzd = data->tzd; |
9d97e5c8 | 1148 | |
3b6a1a80 | 1149 | thermal_zone_of_sensor_unregister(&pdev->dev, tzd); |
4215688e BZ |
1150 | exynos_tmu_control(pdev, false); |
1151 | ||
6c247393 | 1152 | clk_disable_unprepare(data->sclk); |
2a16279c | 1153 | clk_unprepare(data->clk); |
14a11dc7 NKC |
1154 | if (!IS_ERR(data->clk_sec)) |
1155 | clk_unprepare(data->clk_sec); | |
9d97e5c8 | 1156 | |
498d22f6 ADK |
1157 | if (!IS_ERR(data->regulator)) |
1158 | regulator_disable(data->regulator); | |
1159 | ||
9d97e5c8 DK |
1160 | return 0; |
1161 | } | |
1162 | ||
08cd6753 | 1163 | #ifdef CONFIG_PM_SLEEP |
f22d9c03 | 1164 | static int exynos_tmu_suspend(struct device *dev) |
9d97e5c8 | 1165 | { |
f22d9c03 | 1166 | exynos_tmu_control(to_platform_device(dev), false); |
9d97e5c8 DK |
1167 | |
1168 | return 0; | |
1169 | } | |
1170 | ||
f22d9c03 | 1171 | static int exynos_tmu_resume(struct device *dev) |
9d97e5c8 | 1172 | { |
08cd6753 RW |
1173 | struct platform_device *pdev = to_platform_device(dev); |
1174 | ||
f22d9c03 ADK |
1175 | exynos_tmu_initialize(pdev); |
1176 | exynos_tmu_control(pdev, true); | |
9d97e5c8 DK |
1177 | |
1178 | return 0; | |
1179 | } | |
08cd6753 | 1180 | |
f22d9c03 ADK |
1181 | static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, |
1182 | exynos_tmu_suspend, exynos_tmu_resume); | |
1183 | #define EXYNOS_TMU_PM (&exynos_tmu_pm) | |
9d97e5c8 | 1184 | #else |
f22d9c03 | 1185 | #define EXYNOS_TMU_PM NULL |
9d97e5c8 DK |
1186 | #endif |
1187 | ||
f22d9c03 | 1188 | static struct platform_driver exynos_tmu_driver = { |
9d97e5c8 | 1189 | .driver = { |
f22d9c03 | 1190 | .name = "exynos-tmu", |
f22d9c03 | 1191 | .pm = EXYNOS_TMU_PM, |
73b5b1d7 | 1192 | .of_match_table = exynos_tmu_match, |
9d97e5c8 | 1193 | }, |
f22d9c03 | 1194 | .probe = exynos_tmu_probe, |
4eab7a9e | 1195 | .remove = exynos_tmu_remove, |
9d97e5c8 DK |
1196 | }; |
1197 | ||
f22d9c03 | 1198 | module_platform_driver(exynos_tmu_driver); |
9d97e5c8 | 1199 | |
f22d9c03 | 1200 | MODULE_DESCRIPTION("EXYNOS TMU Driver"); |
9d97e5c8 DK |
1201 | MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); |
1202 | MODULE_LICENSE("GPL"); | |
f22d9c03 | 1203 | MODULE_ALIAS("platform:exynos-tmu"); |