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cbac8f63 | 1 | /* |
678065d5 | 2 | * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd |
20f0af75 CW |
3 | * Caesar Wang <wxt@rock-chips.com> |
4 | * | |
cbac8f63 CW |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | #include <linux/clk.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_address.h> | |
22 | #include <linux/of_irq.h> | |
23 | #include <linux/platform_device.h> | |
b9484763 | 24 | #include <linux/regmap.h> |
cbac8f63 CW |
25 | #include <linux/reset.h> |
26 | #include <linux/thermal.h> | |
b9484763 | 27 | #include <linux/mfd/syscon.h> |
c970872e | 28 | #include <linux/pinctrl/consumer.h> |
cbac8f63 CW |
29 | |
30 | /** | |
31 | * If the temperature over a period of time High, | |
32 | * the resulting TSHUT gave CRU module,let it reset the entire chip, | |
33 | * or via GPIO give PMIC. | |
34 | */ | |
35 | enum tshut_mode { | |
36 | TSHUT_MODE_CRU = 0, | |
37 | TSHUT_MODE_GPIO, | |
38 | }; | |
39 | ||
40 | /** | |
13c1cfda | 41 | * The system Temperature Sensors tshut(tshut) polarity |
cbac8f63 CW |
42 | * the bit 8 is tshut polarity. |
43 | * 0: low active, 1: high active | |
44 | */ | |
45 | enum tshut_polarity { | |
46 | TSHUT_LOW_ACTIVE = 0, | |
47 | TSHUT_HIGH_ACTIVE, | |
48 | }; | |
49 | ||
50 | /** | |
1d98b618 CW |
51 | * The system has two Temperature Sensors. |
52 | * sensor0 is for CPU, and sensor1 is for GPU. | |
cbac8f63 CW |
53 | */ |
54 | enum sensor_id { | |
1d98b618 | 55 | SENSOR_CPU = 0, |
cbac8f63 CW |
56 | SENSOR_GPU, |
57 | }; | |
58 | ||
020ba95d | 59 | /** |
13c1cfda | 60 | * The conversion table has the adc value and temperature. |
952418a3 CW |
61 | * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) |
62 | * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) | |
13c1cfda | 63 | */ |
020ba95d CW |
64 | enum adc_sort_mode { |
65 | ADC_DECREMENT = 0, | |
66 | ADC_INCREMENT, | |
67 | }; | |
68 | ||
1d98b618 CW |
69 | /** |
70 | * The max sensors is two in rockchip SoCs. | |
71 | * Two sensors: CPU and GPU sensor. | |
72 | */ | |
73 | #define SOC_MAX_SENSORS 2 | |
74 | ||
13c1cfda | 75 | /** |
678065d5 | 76 | * struct chip_tsadc_table - hold information about chip-specific differences |
13c1cfda CW |
77 | * @id: conversion table |
78 | * @length: size of conversion table | |
79 | * @data_mask: mask to apply on data inputs | |
80 | * @mode: sort mode of this adc variant (incrementing or decrementing) | |
81 | */ | |
ce74110d CW |
82 | struct chip_tsadc_table { |
83 | const struct tsadc_table *id; | |
ce74110d | 84 | unsigned int length; |
ce74110d | 85 | u32 data_mask; |
020ba95d | 86 | enum adc_sort_mode mode; |
ce74110d CW |
87 | }; |
88 | ||
678065d5 CW |
89 | /** |
90 | * struct rockchip_tsadc_chip - hold the private data of tsadc chip | |
91 | * @chn_id[SOC_MAX_SENSORS]: the sensor id of chip correspond to the channel | |
92 | * @chn_num: the channel number of tsadc chip | |
93 | * @tshut_temp: the hardware-controlled shutdown temperature value | |
94 | * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) | |
95 | * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) | |
96 | * @initialize: SoC special initialize tsadc controller method | |
97 | * @irq_ack: clear the interrupt | |
98 | * @get_temp: get the temperature | |
14848502 | 99 | * @set_alarm_temp: set the high temperature interrupt |
678065d5 CW |
100 | * @set_tshut_temp: set the hardware-controlled shutdown temperature |
101 | * @set_tshut_mode: set the hardware-controlled shutdown mode | |
102 | * @table: the chip-specific conversion table | |
103 | */ | |
cbac8f63 | 104 | struct rockchip_tsadc_chip { |
1d98b618 CW |
105 | /* The sensor id of chip correspond to the ADC channel */ |
106 | int chn_id[SOC_MAX_SENSORS]; | |
107 | int chn_num; | |
108 | ||
cbac8f63 | 109 | /* The hardware-controlled tshut property */ |
437df217 | 110 | int tshut_temp; |
cbac8f63 CW |
111 | enum tshut_mode tshut_mode; |
112 | enum tshut_polarity tshut_polarity; | |
113 | ||
114 | /* Chip-wide methods */ | |
b9484763 CW |
115 | void (*initialize)(struct regmap *grf, |
116 | void __iomem *reg, enum tshut_polarity p); | |
cbac8f63 CW |
117 | void (*irq_ack)(void __iomem *reg); |
118 | void (*control)(void __iomem *reg, bool on); | |
119 | ||
120 | /* Per-sensor methods */ | |
ce74110d CW |
121 | int (*get_temp)(struct chip_tsadc_table table, |
122 | int chn, void __iomem *reg, int *temp); | |
14848502 CW |
123 | void (*set_alarm_temp)(struct chip_tsadc_table table, |
124 | int chn, void __iomem *reg, int temp); | |
ce74110d | 125 | void (*set_tshut_temp)(struct chip_tsadc_table table, |
437df217 | 126 | int chn, void __iomem *reg, int temp); |
cbac8f63 | 127 | void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); |
ce74110d CW |
128 | |
129 | /* Per-table methods */ | |
130 | struct chip_tsadc_table table; | |
cbac8f63 CW |
131 | }; |
132 | ||
678065d5 CW |
133 | /** |
134 | * struct rockchip_thermal_sensor - hold the information of thermal sensor | |
135 | * @thermal: pointer to the platform/configuration data | |
136 | * @tzd: pointer to a thermal zone | |
137 | * @id: identifier of the thermal sensor | |
138 | */ | |
cbac8f63 CW |
139 | struct rockchip_thermal_sensor { |
140 | struct rockchip_thermal_data *thermal; | |
141 | struct thermal_zone_device *tzd; | |
1d98b618 | 142 | int id; |
cbac8f63 CW |
143 | }; |
144 | ||
678065d5 CW |
145 | /** |
146 | * struct rockchip_thermal_data - hold the private data of thermal driver | |
147 | * @chip: pointer to the platform/configuration data | |
148 | * @pdev: platform device of thermal | |
149 | * @reset: the reset controller of tsadc | |
150 | * @sensors[SOC_MAX_SENSORS]: the thermal sensor | |
151 | * @clk: the controller clock is divided by the exteral 24MHz | |
152 | * @pclk: the advanced peripherals bus clock | |
153 | * @grf: the general register file will be used to do static set by software | |
154 | * @regs: the base address of tsadc controller | |
155 | * @tshut_temp: the hardware-controlled shutdown temperature value | |
156 | * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) | |
157 | * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) | |
158 | */ | |
cbac8f63 CW |
159 | struct rockchip_thermal_data { |
160 | const struct rockchip_tsadc_chip *chip; | |
161 | struct platform_device *pdev; | |
162 | struct reset_control *reset; | |
163 | ||
1d98b618 | 164 | struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS]; |
cbac8f63 CW |
165 | |
166 | struct clk *clk; | |
167 | struct clk *pclk; | |
168 | ||
b9484763 | 169 | struct regmap *grf; |
cbac8f63 CW |
170 | void __iomem *regs; |
171 | ||
437df217 | 172 | int tshut_temp; |
cbac8f63 CW |
173 | enum tshut_mode tshut_mode; |
174 | enum tshut_polarity tshut_polarity; | |
175 | }; | |
176 | ||
952418a3 CW |
177 | /** |
178 | * TSADC Sensor Register description: | |
179 | * | |
180 | * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it. | |
181 | * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399) | |
182 | * | |
183 | */ | |
b9484763 | 184 | #define TSADCV2_USER_CON 0x00 |
cbac8f63 CW |
185 | #define TSADCV2_AUTO_CON 0x04 |
186 | #define TSADCV2_INT_EN 0x08 | |
187 | #define TSADCV2_INT_PD 0x0c | |
188 | #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) | |
14848502 | 189 | #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) |
cbac8f63 CW |
190 | #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) |
191 | #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 | |
192 | #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 | |
193 | #define TSADCV2_AUTO_PERIOD 0x68 | |
194 | #define TSADCV2_AUTO_PERIOD_HT 0x6c | |
195 | ||
196 | #define TSADCV2_AUTO_EN BIT(0) | |
cbac8f63 CW |
197 | #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) |
198 | #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) | |
678065d5 | 199 | |
7ea38c6c | 200 | #define TSADCV3_AUTO_Q_SEL_EN BIT(1) |
cbac8f63 CW |
201 | |
202 | #define TSADCV2_INT_SRC_EN(chn) BIT(chn) | |
203 | #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) | |
204 | #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) | |
205 | ||
452e01b3 | 206 | #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) |
952418a3 | 207 | #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) |
cbac8f63 CW |
208 | |
209 | #define TSADCV2_DATA_MASK 0xfff | |
20f0af75 CW |
210 | #define TSADCV3_DATA_MASK 0x3ff |
211 | ||
cbac8f63 CW |
212 | #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 |
213 | #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 | |
46667879 CW |
214 | #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */ |
215 | #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */ | |
5ef62de7 RH |
216 | #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */ |
217 | #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */ | |
46667879 | 218 | |
b9484763 CW |
219 | #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ |
220 | ||
221 | #define GRF_SARADC_TESTBIT 0x0e644 | |
222 | #define GRF_TSADC_TESTBIT_L 0x0e648 | |
223 | #define GRF_TSADC_TESTBIT_H 0x0e64c | |
224 | ||
b9484763 CW |
225 | #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) |
226 | #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) | |
23f75e48 RH |
227 | #define GRF_TSADC_VCM_EN_L (0x10001 << 7) |
228 | #define GRF_TSADC_VCM_EN_H (0x10001 << 7) | |
cbac8f63 | 229 | |
7b02a5e7 | 230 | /** |
678065d5 CW |
231 | * struct tsadc_table - code to temperature conversion table |
232 | * @code: the value of adc channel | |
233 | * @temp: the temperature | |
7b02a5e7 | 234 | * Note: |
678065d5 | 235 | * code to temperature mapping of the temperature sensor is a piece wise linear |
7b02a5e7 CW |
236 | * curve.Any temperature, code faling between to 2 give temperatures can be |
237 | * linearly interpolated. | |
678065d5 | 238 | * Code to Temperature mapping should be updated based on manufacturer results. |
7b02a5e7 | 239 | */ |
678065d5 CW |
240 | struct tsadc_table { |
241 | u32 code; | |
242 | int temp; | |
243 | }; | |
244 | ||
952418a3 | 245 | static const struct tsadc_table rk3228_code_table[] = { |
7ea38c6c CW |
246 | {0, -40000}, |
247 | {588, -40000}, | |
248 | {593, -35000}, | |
249 | {598, -30000}, | |
250 | {603, -25000}, | |
251 | {608, -20000}, | |
252 | {613, -15000}, | |
253 | {618, -10000}, | |
254 | {623, -5000}, | |
255 | {629, 0}, | |
256 | {634, 5000}, | |
257 | {639, 10000}, | |
258 | {644, 15000}, | |
259 | {649, 20000}, | |
260 | {654, 25000}, | |
261 | {660, 30000}, | |
262 | {665, 35000}, | |
263 | {670, 40000}, | |
264 | {675, 45000}, | |
265 | {681, 50000}, | |
266 | {686, 55000}, | |
267 | {691, 60000}, | |
268 | {696, 65000}, | |
269 | {702, 70000}, | |
270 | {707, 75000}, | |
271 | {712, 80000}, | |
272 | {717, 85000}, | |
273 | {723, 90000}, | |
274 | {728, 95000}, | |
275 | {733, 100000}, | |
276 | {738, 105000}, | |
277 | {744, 110000}, | |
278 | {749, 115000}, | |
279 | {754, 120000}, | |
280 | {760, 125000}, | |
281 | {TSADCV2_DATA_MASK, 125000}, | |
7b02a5e7 CW |
282 | }; |
283 | ||
952418a3 | 284 | static const struct tsadc_table rk3288_code_table[] = { |
cbac8f63 CW |
285 | {TSADCV2_DATA_MASK, -40000}, |
286 | {3800, -40000}, | |
287 | {3792, -35000}, | |
288 | {3783, -30000}, | |
289 | {3774, -25000}, | |
290 | {3765, -20000}, | |
291 | {3756, -15000}, | |
292 | {3747, -10000}, | |
293 | {3737, -5000}, | |
294 | {3728, 0}, | |
295 | {3718, 5000}, | |
296 | {3708, 10000}, | |
297 | {3698, 15000}, | |
298 | {3688, 20000}, | |
299 | {3678, 25000}, | |
300 | {3667, 30000}, | |
301 | {3656, 35000}, | |
302 | {3645, 40000}, | |
303 | {3634, 45000}, | |
304 | {3623, 50000}, | |
305 | {3611, 55000}, | |
306 | {3600, 60000}, | |
307 | {3588, 65000}, | |
308 | {3575, 70000}, | |
309 | {3563, 75000}, | |
310 | {3550, 80000}, | |
311 | {3537, 85000}, | |
312 | {3524, 90000}, | |
313 | {3510, 95000}, | |
314 | {3496, 100000}, | |
315 | {3482, 105000}, | |
316 | {3467, 110000}, | |
317 | {3452, 115000}, | |
318 | {3437, 120000}, | |
319 | {3421, 125000}, | |
cbac8f63 CW |
320 | }; |
321 | ||
952418a3 | 322 | static const struct tsadc_table rk3368_code_table[] = { |
20f0af75 CW |
323 | {0, -40000}, |
324 | {106, -40000}, | |
325 | {108, -35000}, | |
326 | {110, -30000}, | |
327 | {112, -25000}, | |
328 | {114, -20000}, | |
329 | {116, -15000}, | |
330 | {118, -10000}, | |
331 | {120, -5000}, | |
332 | {122, 0}, | |
333 | {124, 5000}, | |
334 | {126, 10000}, | |
335 | {128, 15000}, | |
336 | {130, 20000}, | |
337 | {132, 25000}, | |
338 | {134, 30000}, | |
339 | {136, 35000}, | |
340 | {138, 40000}, | |
341 | {140, 45000}, | |
342 | {142, 50000}, | |
343 | {144, 55000}, | |
344 | {146, 60000}, | |
345 | {148, 65000}, | |
346 | {150, 70000}, | |
347 | {152, 75000}, | |
348 | {154, 80000}, | |
349 | {156, 85000}, | |
350 | {158, 90000}, | |
351 | {160, 95000}, | |
352 | {162, 100000}, | |
353 | {163, 105000}, | |
354 | {165, 110000}, | |
355 | {167, 115000}, | |
356 | {169, 120000}, | |
357 | {171, 125000}, | |
358 | {TSADCV3_DATA_MASK, 125000}, | |
359 | }; | |
360 | ||
952418a3 | 361 | static const struct tsadc_table rk3399_code_table[] = { |
7ea38c6c | 362 | {0, -40000}, |
f762a35d CW |
363 | {402, -40000}, |
364 | {410, -35000}, | |
365 | {419, -30000}, | |
366 | {427, -25000}, | |
367 | {436, -20000}, | |
368 | {444, -15000}, | |
369 | {453, -10000}, | |
370 | {461, -5000}, | |
371 | {470, 0}, | |
372 | {478, 5000}, | |
373 | {487, 10000}, | |
374 | {496, 15000}, | |
375 | {504, 20000}, | |
376 | {513, 25000}, | |
377 | {521, 30000}, | |
378 | {530, 35000}, | |
379 | {538, 40000}, | |
380 | {547, 45000}, | |
381 | {555, 50000}, | |
382 | {564, 55000}, | |
383 | {573, 60000}, | |
384 | {581, 65000}, | |
385 | {590, 70000}, | |
386 | {599, 75000}, | |
387 | {607, 80000}, | |
388 | {616, 85000}, | |
389 | {624, 90000}, | |
390 | {633, 95000}, | |
391 | {642, 100000}, | |
392 | {650, 105000}, | |
393 | {659, 110000}, | |
394 | {668, 115000}, | |
395 | {677, 120000}, | |
396 | {685, 125000}, | |
7ea38c6c | 397 | {TSADCV3_DATA_MASK, 125000}, |
b0d70338 CW |
398 | }; |
399 | ||
ce74110d | 400 | static u32 rk_tsadcv2_temp_to_code(struct chip_tsadc_table table, |
437df217 | 401 | int temp) |
cbac8f63 CW |
402 | { |
403 | int high, low, mid; | |
1f09ba82 | 404 | u32 error = 0; |
cbac8f63 CW |
405 | |
406 | low = 0; | |
ce74110d | 407 | high = table.length - 1; |
cbac8f63 CW |
408 | mid = (high + low) / 2; |
409 | ||
1f09ba82 CW |
410 | /* Return mask code data when the temp is over table range */ |
411 | if (temp < table.id[low].temp || temp > table.id[high].temp) { | |
412 | error = table.data_mask; | |
413 | goto exit; | |
414 | } | |
cbac8f63 CW |
415 | |
416 | while (low <= high) { | |
ce74110d CW |
417 | if (temp == table.id[mid].temp) |
418 | return table.id[mid].code; | |
419 | else if (temp < table.id[mid].temp) | |
cbac8f63 CW |
420 | high = mid - 1; |
421 | else | |
422 | low = mid + 1; | |
423 | mid = (low + high) / 2; | |
424 | } | |
425 | ||
1f09ba82 | 426 | exit: |
e6ed1b4a BN |
427 | pr_err("%s: invalid temperature, temp=%d error=%d\n", |
428 | __func__, temp, error); | |
1f09ba82 | 429 | return error; |
cbac8f63 CW |
430 | } |
431 | ||
ce74110d CW |
432 | static int rk_tsadcv2_code_to_temp(struct chip_tsadc_table table, u32 code, |
433 | int *temp) | |
cbac8f63 | 434 | { |
d9a241cb | 435 | unsigned int low = 1; |
ce74110d | 436 | unsigned int high = table.length - 1; |
1e9a1aea CW |
437 | unsigned int mid = (low + high) / 2; |
438 | unsigned int num; | |
439 | unsigned long denom; | |
440 | ||
ce74110d | 441 | WARN_ON(table.length < 2); |
1e9a1aea | 442 | |
020ba95d CW |
443 | switch (table.mode) { |
444 | case ADC_DECREMENT: | |
445 | code &= table.data_mask; | |
446 | if (code < table.id[high].code) | |
447 | return -EAGAIN; /* Incorrect reading */ | |
448 | ||
449 | while (low <= high) { | |
450 | if (code >= table.id[mid].code && | |
451 | code < table.id[mid - 1].code) | |
452 | break; | |
453 | else if (code < table.id[mid].code) | |
454 | low = mid + 1; | |
455 | else | |
456 | high = mid - 1; | |
457 | ||
458 | mid = (low + high) / 2; | |
459 | } | |
460 | break; | |
461 | case ADC_INCREMENT: | |
462 | code &= table.data_mask; | |
463 | if (code < table.id[low].code) | |
464 | return -EAGAIN; /* Incorrect reading */ | |
465 | ||
466 | while (low <= high) { | |
a87dd797 CW |
467 | if (code <= table.id[mid].code && |
468 | code > table.id[mid - 1].code) | |
020ba95d CW |
469 | break; |
470 | else if (code > table.id[mid].code) | |
471 | low = mid + 1; | |
472 | else | |
473 | high = mid - 1; | |
474 | ||
475 | mid = (low + high) / 2; | |
476 | } | |
477 | break; | |
478 | default: | |
e6ed1b4a BN |
479 | pr_err("%s: unknown table mode: %d\n", __func__, table.mode); |
480 | return -EINVAL; | |
cbac8f63 CW |
481 | } |
482 | ||
1e9a1aea CW |
483 | /* |
484 | * The 5C granularity provided by the table is too much. Let's | |
485 | * assume that the relationship between sensor readings and | |
486 | * temperature between 2 table entries is linear and interpolate | |
487 | * to produce less granular result. | |
488 | */ | |
1d37a037 | 489 | num = table.id[mid].temp - table.id[mid - 1].temp; |
020ba95d CW |
490 | num *= abs(table.id[mid - 1].code - code); |
491 | denom = abs(table.id[mid - 1].code - table.id[mid].code); | |
ce74110d | 492 | *temp = table.id[mid - 1].temp + (num / denom); |
d9a241cb DT |
493 | |
494 | return 0; | |
cbac8f63 CW |
495 | } |
496 | ||
497 | /** | |
144c5565 CW |
498 | * rk_tsadcv2_initialize - initialize TASDC Controller. |
499 | * | |
500 | * (1) Set TSADC_V2_AUTO_PERIOD: | |
501 | * Configure the interleave between every two accessing of | |
502 | * TSADC in normal operation. | |
503 | * | |
504 | * (2) Set TSADCV2_AUTO_PERIOD_HT: | |
505 | * Configure the interleave between every two accessing of | |
506 | * TSADC after the temperature is higher than COM_SHUT or COM_INT. | |
507 | * | |
508 | * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: | |
509 | * If the temperature is higher than COMP_INT or COMP_SHUT for | |
510 | * "debounce" times, TSADC controller will generate interrupt or TSHUT. | |
cbac8f63 | 511 | */ |
b9484763 | 512 | static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs, |
cbac8f63 CW |
513 | enum tshut_polarity tshut_polarity) |
514 | { | |
515 | if (tshut_polarity == TSHUT_HIGH_ACTIVE) | |
452e01b3 | 516 | writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
cbac8f63 CW |
517 | regs + TSADCV2_AUTO_CON); |
518 | else | |
452e01b3 | 519 | writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
cbac8f63 CW |
520 | regs + TSADCV2_AUTO_CON); |
521 | ||
522 | writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); | |
523 | writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, | |
524 | regs + TSADCV2_HIGHT_INT_DEBOUNCE); | |
525 | writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, | |
526 | regs + TSADCV2_AUTO_PERIOD_HT); | |
527 | writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, | |
528 | regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); | |
b9484763 CW |
529 | } |
530 | ||
531 | /** | |
532 | * rk_tsadcv3_initialize - initialize TASDC Controller. | |
678065d5 | 533 | * |
b9484763 CW |
534 | * (1) The tsadc control power sequence. |
535 | * | |
536 | * (2) Set TSADC_V2_AUTO_PERIOD: | |
537 | * Configure the interleave between every two accessing of | |
538 | * TSADC in normal operation. | |
539 | * | |
540 | * (2) Set TSADCV2_AUTO_PERIOD_HT: | |
541 | * Configure the interleave between every two accessing of | |
542 | * TSADC after the temperature is higher than COM_SHUT or COM_INT. | |
543 | * | |
544 | * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: | |
545 | * If the temperature is higher than COMP_INT or COMP_SHUT for | |
546 | * "debounce" times, TSADC controller will generate interrupt or TSHUT. | |
547 | */ | |
548 | static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs, | |
549 | enum tshut_polarity tshut_polarity) | |
550 | { | |
551 | /* The tsadc control power sequence */ | |
552 | if (IS_ERR(grf)) { | |
553 | /* Set interleave value to workround ic time sync issue */ | |
554 | writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs + | |
555 | TSADCV2_USER_CON); | |
46667879 CW |
556 | |
557 | writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, | |
558 | regs + TSADCV2_AUTO_PERIOD); | |
559 | writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, | |
560 | regs + TSADCV2_HIGHT_INT_DEBOUNCE); | |
561 | writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, | |
562 | regs + TSADCV2_AUTO_PERIOD_HT); | |
563 | writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, | |
564 | regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); | |
565 | ||
b9484763 | 566 | } else { |
23f75e48 RH |
567 | /* Enable the voltage common mode feature */ |
568 | regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L); | |
569 | regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H); | |
570 | ||
2fe5c1b0 | 571 | usleep_range(15, 100); /* The spec note says at least 15 us */ |
b9484763 CW |
572 | regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON); |
573 | regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON); | |
2fe5c1b0 | 574 | usleep_range(90, 200); /* The spec note says at least 90 us */ |
46667879 CW |
575 | |
576 | writel_relaxed(TSADCV3_AUTO_PERIOD_TIME, | |
577 | regs + TSADCV2_AUTO_PERIOD); | |
578 | writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, | |
579 | regs + TSADCV2_HIGHT_INT_DEBOUNCE); | |
580 | writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME, | |
581 | regs + TSADCV2_AUTO_PERIOD_HT); | |
582 | writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, | |
583 | regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); | |
b9484763 CW |
584 | } |
585 | ||
586 | if (tshut_polarity == TSHUT_HIGH_ACTIVE) | |
587 | writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, | |
588 | regs + TSADCV2_AUTO_CON); | |
589 | else | |
590 | writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, | |
591 | regs + TSADCV2_AUTO_CON); | |
cbac8f63 CW |
592 | } |
593 | ||
952418a3 | 594 | static void rk_tsadcv2_irq_ack(void __iomem *regs) |
7b02a5e7 CW |
595 | { |
596 | u32 val; | |
597 | ||
598 | val = readl_relaxed(regs + TSADCV2_INT_PD); | |
952418a3 | 599 | writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); |
7b02a5e7 CW |
600 | } |
601 | ||
952418a3 | 602 | static void rk_tsadcv3_irq_ack(void __iomem *regs) |
cbac8f63 CW |
603 | { |
604 | u32 val; | |
605 | ||
606 | val = readl_relaxed(regs + TSADCV2_INT_PD); | |
952418a3 | 607 | writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); |
cbac8f63 CW |
608 | } |
609 | ||
610 | static void rk_tsadcv2_control(void __iomem *regs, bool enable) | |
611 | { | |
612 | u32 val; | |
613 | ||
614 | val = readl_relaxed(regs + TSADCV2_AUTO_CON); | |
615 | if (enable) | |
616 | val |= TSADCV2_AUTO_EN; | |
617 | else | |
618 | val &= ~TSADCV2_AUTO_EN; | |
619 | ||
620 | writel_relaxed(val, regs + TSADCV2_AUTO_CON); | |
621 | } | |
622 | ||
7ea38c6c | 623 | /** |
678065d5 CW |
624 | * rk_tsadcv3_control - the tsadc controller is enabled or disabled. |
625 | * | |
626 | * NOTE: TSADC controller works at auto mode, and some SoCs need set the | |
627 | * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output | |
628 | * adc value if setting this bit to enable. | |
7ea38c6c CW |
629 | */ |
630 | static void rk_tsadcv3_control(void __iomem *regs, bool enable) | |
631 | { | |
632 | u32 val; | |
633 | ||
634 | val = readl_relaxed(regs + TSADCV2_AUTO_CON); | |
635 | if (enable) | |
636 | val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; | |
637 | else | |
638 | val &= ~TSADCV2_AUTO_EN; | |
639 | ||
640 | writel_relaxed(val, regs + TSADCV2_AUTO_CON); | |
641 | } | |
642 | ||
ce74110d CW |
643 | static int rk_tsadcv2_get_temp(struct chip_tsadc_table table, |
644 | int chn, void __iomem *regs, int *temp) | |
cbac8f63 CW |
645 | { |
646 | u32 val; | |
647 | ||
cbac8f63 | 648 | val = readl_relaxed(regs + TSADCV2_DATA(chn)); |
cbac8f63 | 649 | |
ce74110d | 650 | return rk_tsadcv2_code_to_temp(table, val, temp); |
cbac8f63 CW |
651 | } |
652 | ||
14848502 CW |
653 | static void rk_tsadcv2_alarm_temp(struct chip_tsadc_table table, |
654 | int chn, void __iomem *regs, int temp) | |
655 | { | |
656 | u32 alarm_value, int_en; | |
657 | ||
1f09ba82 | 658 | /* Make sure the value is valid */ |
14848502 | 659 | alarm_value = rk_tsadcv2_temp_to_code(table, temp); |
1f09ba82 CW |
660 | if (alarm_value == table.data_mask) |
661 | return; | |
662 | ||
14848502 CW |
663 | writel_relaxed(alarm_value & table.data_mask, |
664 | regs + TSADCV2_COMP_INT(chn)); | |
665 | ||
666 | int_en = readl_relaxed(regs + TSADCV2_INT_EN); | |
667 | int_en |= TSADCV2_INT_SRC_EN(chn); | |
668 | writel_relaxed(int_en, regs + TSADCV2_INT_EN); | |
669 | } | |
670 | ||
ce74110d | 671 | static void rk_tsadcv2_tshut_temp(struct chip_tsadc_table table, |
437df217 | 672 | int chn, void __iomem *regs, int temp) |
cbac8f63 CW |
673 | { |
674 | u32 tshut_value, val; | |
675 | ||
1f09ba82 | 676 | /* Make sure the value is valid */ |
ce74110d | 677 | tshut_value = rk_tsadcv2_temp_to_code(table, temp); |
1f09ba82 CW |
678 | if (tshut_value == table.data_mask) |
679 | return; | |
680 | ||
cbac8f63 CW |
681 | writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn)); |
682 | ||
683 | /* TSHUT will be valid */ | |
684 | val = readl_relaxed(regs + TSADCV2_AUTO_CON); | |
685 | writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON); | |
686 | } | |
687 | ||
688 | static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, | |
689 | enum tshut_mode mode) | |
690 | { | |
691 | u32 val; | |
692 | ||
693 | val = readl_relaxed(regs + TSADCV2_INT_EN); | |
694 | if (mode == TSHUT_MODE_GPIO) { | |
695 | val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); | |
696 | val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); | |
697 | } else { | |
698 | val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); | |
699 | val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); | |
700 | } | |
701 | ||
702 | writel_relaxed(val, regs + TSADCV2_INT_EN); | |
703 | } | |
704 | ||
7b02a5e7 CW |
705 | static const struct rockchip_tsadc_chip rk3228_tsadc_data = { |
706 | .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ | |
707 | .chn_num = 1, /* one channel for tsadc */ | |
708 | ||
709 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ | |
710 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
711 | .tshut_temp = 95000, | |
712 | ||
713 | .initialize = rk_tsadcv2_initialize, | |
952418a3 | 714 | .irq_ack = rk_tsadcv3_irq_ack, |
7ea38c6c | 715 | .control = rk_tsadcv3_control, |
7b02a5e7 | 716 | .get_temp = rk_tsadcv2_get_temp, |
14848502 | 717 | .set_alarm_temp = rk_tsadcv2_alarm_temp, |
7b02a5e7 CW |
718 | .set_tshut_temp = rk_tsadcv2_tshut_temp, |
719 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
720 | ||
721 | .table = { | |
952418a3 CW |
722 | .id = rk3228_code_table, |
723 | .length = ARRAY_SIZE(rk3228_code_table), | |
7b02a5e7 | 724 | .data_mask = TSADCV3_DATA_MASK, |
7ea38c6c | 725 | .mode = ADC_INCREMENT, |
7b02a5e7 CW |
726 | }, |
727 | }; | |
728 | ||
cbac8f63 | 729 | static const struct rockchip_tsadc_chip rk3288_tsadc_data = { |
1d98b618 CW |
730 | .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ |
731 | .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ | |
732 | .chn_num = 2, /* two channels for tsadc */ | |
733 | ||
cbac8f63 CW |
734 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ |
735 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
736 | .tshut_temp = 95000, | |
737 | ||
738 | .initialize = rk_tsadcv2_initialize, | |
739 | .irq_ack = rk_tsadcv2_irq_ack, | |
740 | .control = rk_tsadcv2_control, | |
741 | .get_temp = rk_tsadcv2_get_temp, | |
14848502 | 742 | .set_alarm_temp = rk_tsadcv2_alarm_temp, |
cbac8f63 CW |
743 | .set_tshut_temp = rk_tsadcv2_tshut_temp, |
744 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
ce74110d CW |
745 | |
746 | .table = { | |
952418a3 CW |
747 | .id = rk3288_code_table, |
748 | .length = ARRAY_SIZE(rk3288_code_table), | |
ce74110d | 749 | .data_mask = TSADCV2_DATA_MASK, |
020ba95d | 750 | .mode = ADC_DECREMENT, |
ce74110d | 751 | }, |
cbac8f63 CW |
752 | }; |
753 | ||
1cd60269 EZ |
754 | static const struct rockchip_tsadc_chip rk3366_tsadc_data = { |
755 | .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ | |
756 | .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ | |
757 | .chn_num = 2, /* two channels for tsadc */ | |
758 | ||
759 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ | |
760 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
761 | .tshut_temp = 95000, | |
762 | ||
763 | .initialize = rk_tsadcv3_initialize, | |
764 | .irq_ack = rk_tsadcv3_irq_ack, | |
765 | .control = rk_tsadcv3_control, | |
766 | .get_temp = rk_tsadcv2_get_temp, | |
14848502 | 767 | .set_alarm_temp = rk_tsadcv2_alarm_temp, |
1cd60269 EZ |
768 | .set_tshut_temp = rk_tsadcv2_tshut_temp, |
769 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
770 | ||
771 | .table = { | |
772 | .id = rk3228_code_table, | |
773 | .length = ARRAY_SIZE(rk3228_code_table), | |
774 | .data_mask = TSADCV3_DATA_MASK, | |
775 | .mode = ADC_INCREMENT, | |
776 | }, | |
777 | }; | |
778 | ||
20f0af75 CW |
779 | static const struct rockchip_tsadc_chip rk3368_tsadc_data = { |
780 | .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ | |
781 | .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ | |
782 | .chn_num = 2, /* two channels for tsadc */ | |
783 | ||
784 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ | |
785 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
786 | .tshut_temp = 95000, | |
787 | ||
788 | .initialize = rk_tsadcv2_initialize, | |
789 | .irq_ack = rk_tsadcv2_irq_ack, | |
790 | .control = rk_tsadcv2_control, | |
791 | .get_temp = rk_tsadcv2_get_temp, | |
14848502 | 792 | .set_alarm_temp = rk_tsadcv2_alarm_temp, |
20f0af75 CW |
793 | .set_tshut_temp = rk_tsadcv2_tshut_temp, |
794 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
795 | ||
796 | .table = { | |
952418a3 CW |
797 | .id = rk3368_code_table, |
798 | .length = ARRAY_SIZE(rk3368_code_table), | |
20f0af75 CW |
799 | .data_mask = TSADCV3_DATA_MASK, |
800 | .mode = ADC_INCREMENT, | |
801 | }, | |
802 | }; | |
803 | ||
b0d70338 CW |
804 | static const struct rockchip_tsadc_chip rk3399_tsadc_data = { |
805 | .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ | |
806 | .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ | |
807 | .chn_num = 2, /* two channels for tsadc */ | |
808 | ||
809 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ | |
810 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
811 | .tshut_temp = 95000, | |
812 | ||
b9484763 | 813 | .initialize = rk_tsadcv3_initialize, |
952418a3 | 814 | .irq_ack = rk_tsadcv3_irq_ack, |
7ea38c6c | 815 | .control = rk_tsadcv3_control, |
b0d70338 | 816 | .get_temp = rk_tsadcv2_get_temp, |
14848502 | 817 | .set_alarm_temp = rk_tsadcv2_alarm_temp, |
b0d70338 CW |
818 | .set_tshut_temp = rk_tsadcv2_tshut_temp, |
819 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
820 | ||
821 | .table = { | |
952418a3 CW |
822 | .id = rk3399_code_table, |
823 | .length = ARRAY_SIZE(rk3399_code_table), | |
b0d70338 | 824 | .data_mask = TSADCV3_DATA_MASK, |
7ea38c6c | 825 | .mode = ADC_INCREMENT, |
b0d70338 CW |
826 | }, |
827 | }; | |
828 | ||
cbac8f63 | 829 | static const struct of_device_id of_rockchip_thermal_match[] = { |
7b02a5e7 CW |
830 | { |
831 | .compatible = "rockchip,rk3228-tsadc", | |
832 | .data = (void *)&rk3228_tsadc_data, | |
833 | }, | |
cbac8f63 CW |
834 | { |
835 | .compatible = "rockchip,rk3288-tsadc", | |
836 | .data = (void *)&rk3288_tsadc_data, | |
837 | }, | |
1cd60269 EZ |
838 | { |
839 | .compatible = "rockchip,rk3366-tsadc", | |
840 | .data = (void *)&rk3366_tsadc_data, | |
841 | }, | |
20f0af75 CW |
842 | { |
843 | .compatible = "rockchip,rk3368-tsadc", | |
844 | .data = (void *)&rk3368_tsadc_data, | |
845 | }, | |
b0d70338 CW |
846 | { |
847 | .compatible = "rockchip,rk3399-tsadc", | |
848 | .data = (void *)&rk3399_tsadc_data, | |
849 | }, | |
cbac8f63 CW |
850 | { /* end */ }, |
851 | }; | |
852 | MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match); | |
853 | ||
854 | static void | |
855 | rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on) | |
856 | { | |
857 | struct thermal_zone_device *tzd = sensor->tzd; | |
858 | ||
859 | tzd->ops->set_mode(tzd, | |
860 | on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED); | |
861 | } | |
862 | ||
863 | static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev) | |
864 | { | |
865 | struct rockchip_thermal_data *thermal = dev; | |
866 | int i; | |
867 | ||
868 | dev_dbg(&thermal->pdev->dev, "thermal alarm\n"); | |
869 | ||
870 | thermal->chip->irq_ack(thermal->regs); | |
871 | ||
1d98b618 | 872 | for (i = 0; i < thermal->chip->chn_num; i++) |
0e70f466 SP |
873 | thermal_zone_device_update(thermal->sensors[i].tzd, |
874 | THERMAL_EVENT_UNSPECIFIED); | |
cbac8f63 CW |
875 | |
876 | return IRQ_HANDLED; | |
877 | } | |
878 | ||
14848502 CW |
879 | static int rockchip_thermal_set_trips(void *_sensor, int low, int high) |
880 | { | |
881 | struct rockchip_thermal_sensor *sensor = _sensor; | |
882 | struct rockchip_thermal_data *thermal = sensor->thermal; | |
883 | const struct rockchip_tsadc_chip *tsadc = thermal->chip; | |
884 | ||
885 | dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n", | |
886 | __func__, sensor->id, low, high); | |
887 | ||
888 | tsadc->set_alarm_temp(tsadc->table, | |
889 | sensor->id, thermal->regs, high); | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
17e8351a | 894 | static int rockchip_thermal_get_temp(void *_sensor, int *out_temp) |
cbac8f63 CW |
895 | { |
896 | struct rockchip_thermal_sensor *sensor = _sensor; | |
897 | struct rockchip_thermal_data *thermal = sensor->thermal; | |
898 | const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip; | |
899 | int retval; | |
900 | ||
ce74110d CW |
901 | retval = tsadc->get_temp(tsadc->table, |
902 | sensor->id, thermal->regs, out_temp); | |
17e8351a | 903 | dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n", |
cbac8f63 CW |
904 | sensor->id, *out_temp, retval); |
905 | ||
906 | return retval; | |
907 | } | |
908 | ||
909 | static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = { | |
910 | .get_temp = rockchip_thermal_get_temp, | |
14848502 | 911 | .set_trips = rockchip_thermal_set_trips, |
cbac8f63 CW |
912 | }; |
913 | ||
914 | static int rockchip_configure_from_dt(struct device *dev, | |
915 | struct device_node *np, | |
916 | struct rockchip_thermal_data *thermal) | |
917 | { | |
918 | u32 shut_temp, tshut_mode, tshut_polarity; | |
919 | ||
920 | if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) { | |
921 | dev_warn(dev, | |
437df217 | 922 | "Missing tshut temp property, using default %d\n", |
cbac8f63 CW |
923 | thermal->chip->tshut_temp); |
924 | thermal->tshut_temp = thermal->chip->tshut_temp; | |
925 | } else { | |
43b4eb9f CW |
926 | if (shut_temp > INT_MAX) { |
927 | dev_err(dev, "Invalid tshut temperature specified: %d\n", | |
928 | shut_temp); | |
929 | return -ERANGE; | |
930 | } | |
cbac8f63 CW |
931 | thermal->tshut_temp = shut_temp; |
932 | } | |
933 | ||
cbac8f63 CW |
934 | if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) { |
935 | dev_warn(dev, | |
936 | "Missing tshut mode property, using default (%s)\n", | |
937 | thermal->chip->tshut_mode == TSHUT_MODE_GPIO ? | |
938 | "gpio" : "cru"); | |
939 | thermal->tshut_mode = thermal->chip->tshut_mode; | |
940 | } else { | |
941 | thermal->tshut_mode = tshut_mode; | |
942 | } | |
943 | ||
944 | if (thermal->tshut_mode > 1) { | |
945 | dev_err(dev, "Invalid tshut mode specified: %d\n", | |
946 | thermal->tshut_mode); | |
947 | return -EINVAL; | |
948 | } | |
949 | ||
950 | if (of_property_read_u32(np, "rockchip,hw-tshut-polarity", | |
951 | &tshut_polarity)) { | |
952 | dev_warn(dev, | |
953 | "Missing tshut-polarity property, using default (%s)\n", | |
954 | thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ? | |
955 | "low" : "high"); | |
956 | thermal->tshut_polarity = thermal->chip->tshut_polarity; | |
957 | } else { | |
958 | thermal->tshut_polarity = tshut_polarity; | |
959 | } | |
960 | ||
961 | if (thermal->tshut_polarity > 1) { | |
962 | dev_err(dev, "Invalid tshut-polarity specified: %d\n", | |
963 | thermal->tshut_polarity); | |
964 | return -EINVAL; | |
965 | } | |
966 | ||
b9484763 CW |
967 | /* The tsadc wont to handle the error in here since some SoCs didn't |
968 | * need this property. | |
969 | */ | |
970 | thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); | |
ce62abae SL |
971 | if (IS_ERR(thermal->grf)) |
972 | dev_warn(dev, "Missing rockchip,grf property\n"); | |
b9484763 | 973 | |
cbac8f63 CW |
974 | return 0; |
975 | } | |
976 | ||
977 | static int | |
978 | rockchip_thermal_register_sensor(struct platform_device *pdev, | |
979 | struct rockchip_thermal_data *thermal, | |
980 | struct rockchip_thermal_sensor *sensor, | |
1d98b618 | 981 | int id) |
cbac8f63 CW |
982 | { |
983 | const struct rockchip_tsadc_chip *tsadc = thermal->chip; | |
984 | int error; | |
985 | ||
986 | tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); | |
ce74110d CW |
987 | tsadc->set_tshut_temp(tsadc->table, id, thermal->regs, |
988 | thermal->tshut_temp); | |
cbac8f63 CW |
989 | |
990 | sensor->thermal = thermal; | |
991 | sensor->id = id; | |
2633ad19 EV |
992 | sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id, |
993 | sensor, &rockchip_of_thermal_ops); | |
cbac8f63 CW |
994 | if (IS_ERR(sensor->tzd)) { |
995 | error = PTR_ERR(sensor->tzd); | |
996 | dev_err(&pdev->dev, "failed to register sensor %d: %d\n", | |
997 | id, error); | |
998 | return error; | |
999 | } | |
1000 | ||
1001 | return 0; | |
1002 | } | |
1003 | ||
13c1cfda | 1004 | /** |
cbac8f63 CW |
1005 | * Reset TSADC Controller, reset all tsadc registers. |
1006 | */ | |
1007 | static void rockchip_thermal_reset_controller(struct reset_control *reset) | |
1008 | { | |
1009 | reset_control_assert(reset); | |
1010 | usleep_range(10, 20); | |
1011 | reset_control_deassert(reset); | |
1012 | } | |
1013 | ||
1014 | static int rockchip_thermal_probe(struct platform_device *pdev) | |
1015 | { | |
1016 | struct device_node *np = pdev->dev.of_node; | |
1017 | struct rockchip_thermal_data *thermal; | |
1018 | const struct of_device_id *match; | |
1019 | struct resource *res; | |
1020 | int irq; | |
2633ad19 | 1021 | int i; |
cbac8f63 CW |
1022 | int error; |
1023 | ||
1024 | match = of_match_node(of_rockchip_thermal_match, np); | |
1025 | if (!match) | |
1026 | return -ENXIO; | |
1027 | ||
1028 | irq = platform_get_irq(pdev, 0); | |
1029 | if (irq < 0) { | |
1030 | dev_err(&pdev->dev, "no irq resource?\n"); | |
1031 | return -EINVAL; | |
1032 | } | |
1033 | ||
1034 | thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data), | |
1035 | GFP_KERNEL); | |
1036 | if (!thermal) | |
1037 | return -ENOMEM; | |
1038 | ||
1039 | thermal->pdev = pdev; | |
1040 | ||
1041 | thermal->chip = (const struct rockchip_tsadc_chip *)match->data; | |
1042 | if (!thermal->chip) | |
1043 | return -EINVAL; | |
1044 | ||
1045 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1046 | thermal->regs = devm_ioremap_resource(&pdev->dev, res); | |
1047 | if (IS_ERR(thermal->regs)) | |
1048 | return PTR_ERR(thermal->regs); | |
1049 | ||
1050 | thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb"); | |
1051 | if (IS_ERR(thermal->reset)) { | |
1052 | error = PTR_ERR(thermal->reset); | |
1053 | dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); | |
1054 | return error; | |
1055 | } | |
1056 | ||
1057 | thermal->clk = devm_clk_get(&pdev->dev, "tsadc"); | |
1058 | if (IS_ERR(thermal->clk)) { | |
1059 | error = PTR_ERR(thermal->clk); | |
1060 | dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); | |
1061 | return error; | |
1062 | } | |
1063 | ||
1064 | thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); | |
1065 | if (IS_ERR(thermal->pclk)) { | |
0d0a2bf6 | 1066 | error = PTR_ERR(thermal->pclk); |
cbac8f63 CW |
1067 | dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", |
1068 | error); | |
1069 | return error; | |
1070 | } | |
1071 | ||
1072 | error = clk_prepare_enable(thermal->clk); | |
1073 | if (error) { | |
1074 | dev_err(&pdev->dev, "failed to enable converter clock: %d\n", | |
1075 | error); | |
1076 | return error; | |
1077 | } | |
1078 | ||
1079 | error = clk_prepare_enable(thermal->pclk); | |
1080 | if (error) { | |
1081 | dev_err(&pdev->dev, "failed to enable pclk: %d\n", error); | |
1082 | goto err_disable_clk; | |
1083 | } | |
1084 | ||
1085 | rockchip_thermal_reset_controller(thermal->reset); | |
1086 | ||
1087 | error = rockchip_configure_from_dt(&pdev->dev, np, thermal); | |
1088 | if (error) { | |
1089 | dev_err(&pdev->dev, "failed to parse device tree data: %d\n", | |
1090 | error); | |
1091 | goto err_disable_pclk; | |
1092 | } | |
1093 | ||
b9484763 CW |
1094 | thermal->chip->initialize(thermal->grf, thermal->regs, |
1095 | thermal->tshut_polarity); | |
cbac8f63 | 1096 | |
1d98b618 CW |
1097 | for (i = 0; i < thermal->chip->chn_num; i++) { |
1098 | error = rockchip_thermal_register_sensor(pdev, thermal, | |
1099 | &thermal->sensors[i], | |
1100 | thermal->chip->chn_id[i]); | |
1101 | if (error) { | |
1102 | dev_err(&pdev->dev, | |
1103 | "failed to register sensor[%d] : error = %d\n", | |
1104 | i, error); | |
1d98b618 CW |
1105 | goto err_disable_pclk; |
1106 | } | |
cbac8f63 CW |
1107 | } |
1108 | ||
1109 | error = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1110 | &rockchip_thermal_alarm_irq_thread, | |
1111 | IRQF_ONESHOT, | |
1112 | "rockchip_thermal", thermal); | |
1113 | if (error) { | |
1114 | dev_err(&pdev->dev, | |
1115 | "failed to request tsadc irq: %d\n", error); | |
2633ad19 | 1116 | goto err_disable_pclk; |
cbac8f63 CW |
1117 | } |
1118 | ||
1119 | thermal->chip->control(thermal->regs, true); | |
1120 | ||
1d98b618 | 1121 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
1122 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); |
1123 | ||
1124 | platform_set_drvdata(pdev, thermal); | |
1125 | ||
1126 | return 0; | |
1127 | ||
cbac8f63 CW |
1128 | err_disable_pclk: |
1129 | clk_disable_unprepare(thermal->pclk); | |
1130 | err_disable_clk: | |
1131 | clk_disable_unprepare(thermal->clk); | |
1132 | ||
1133 | return error; | |
1134 | } | |
1135 | ||
1136 | static int rockchip_thermal_remove(struct platform_device *pdev) | |
1137 | { | |
1138 | struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); | |
1139 | int i; | |
1140 | ||
1d98b618 | 1141 | for (i = 0; i < thermal->chip->chn_num; i++) { |
cbac8f63 CW |
1142 | struct rockchip_thermal_sensor *sensor = &thermal->sensors[i]; |
1143 | ||
1144 | rockchip_thermal_toggle_sensor(sensor, false); | |
cbac8f63 CW |
1145 | } |
1146 | ||
1147 | thermal->chip->control(thermal->regs, false); | |
1148 | ||
1149 | clk_disable_unprepare(thermal->pclk); | |
1150 | clk_disable_unprepare(thermal->clk); | |
1151 | ||
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | static int __maybe_unused rockchip_thermal_suspend(struct device *dev) | |
1156 | { | |
1157 | struct platform_device *pdev = to_platform_device(dev); | |
1158 | struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); | |
1159 | int i; | |
1160 | ||
1d98b618 | 1161 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
1162 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], false); |
1163 | ||
1164 | thermal->chip->control(thermal->regs, false); | |
1165 | ||
1166 | clk_disable(thermal->pclk); | |
1167 | clk_disable(thermal->clk); | |
1168 | ||
7e38a5b1 CW |
1169 | pinctrl_pm_select_sleep_state(dev); |
1170 | ||
cbac8f63 CW |
1171 | return 0; |
1172 | } | |
1173 | ||
1174 | static int __maybe_unused rockchip_thermal_resume(struct device *dev) | |
1175 | { | |
1176 | struct platform_device *pdev = to_platform_device(dev); | |
1177 | struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); | |
1178 | int i; | |
1179 | int error; | |
1180 | ||
1181 | error = clk_enable(thermal->clk); | |
1182 | if (error) | |
1183 | return error; | |
1184 | ||
1185 | error = clk_enable(thermal->pclk); | |
ab5b52f1 SL |
1186 | if (error) { |
1187 | clk_disable(thermal->clk); | |
cbac8f63 | 1188 | return error; |
ab5b52f1 | 1189 | } |
cbac8f63 CW |
1190 | |
1191 | rockchip_thermal_reset_controller(thermal->reset); | |
1192 | ||
b9484763 CW |
1193 | thermal->chip->initialize(thermal->grf, thermal->regs, |
1194 | thermal->tshut_polarity); | |
cbac8f63 | 1195 | |
1d98b618 CW |
1196 | for (i = 0; i < thermal->chip->chn_num; i++) { |
1197 | int id = thermal->sensors[i].id; | |
cbac8f63 CW |
1198 | |
1199 | thermal->chip->set_tshut_mode(id, thermal->regs, | |
1200 | thermal->tshut_mode); | |
ce74110d CW |
1201 | thermal->chip->set_tshut_temp(thermal->chip->table, |
1202 | id, thermal->regs, | |
cbac8f63 CW |
1203 | thermal->tshut_temp); |
1204 | } | |
1205 | ||
1206 | thermal->chip->control(thermal->regs, true); | |
1207 | ||
1d98b618 | 1208 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
1209 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); |
1210 | ||
7e38a5b1 CW |
1211 | pinctrl_pm_select_default_state(dev); |
1212 | ||
cbac8f63 CW |
1213 | return 0; |
1214 | } | |
1215 | ||
1216 | static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops, | |
1217 | rockchip_thermal_suspend, rockchip_thermal_resume); | |
1218 | ||
1219 | static struct platform_driver rockchip_thermal_driver = { | |
1220 | .driver = { | |
1221 | .name = "rockchip-thermal", | |
cbac8f63 CW |
1222 | .pm = &rockchip_thermal_pm_ops, |
1223 | .of_match_table = of_rockchip_thermal_match, | |
1224 | }, | |
1225 | .probe = rockchip_thermal_probe, | |
1226 | .remove = rockchip_thermal_remove, | |
1227 | }; | |
1228 | ||
1229 | module_platform_driver(rockchip_thermal_driver); | |
1230 | ||
1231 | MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver"); | |
1232 | MODULE_AUTHOR("Rockchip, Inc."); | |
1233 | MODULE_LICENSE("GPL v2"); | |
1234 | MODULE_ALIAS("platform:rockchip-thermal"); |