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cbac8f63 CW |
1 | /* |
2 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | |
3 | * | |
20f0af75 CW |
4 | * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd |
5 | * Caesar Wang <wxt@rock-chips.com> | |
6 | * | |
cbac8f63 CW |
7 | * This program is free software; you can redistribute it and/or modify it |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | */ | |
16 | ||
17 | #include <linux/clk.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
24 | #include <linux/of_irq.h> | |
25 | #include <linux/platform_device.h> | |
b9484763 | 26 | #include <linux/regmap.h> |
cbac8f63 CW |
27 | #include <linux/reset.h> |
28 | #include <linux/thermal.h> | |
b9484763 | 29 | #include <linux/mfd/syscon.h> |
c970872e | 30 | #include <linux/pinctrl/consumer.h> |
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31 | |
32 | /** | |
33 | * If the temperature over a period of time High, | |
34 | * the resulting TSHUT gave CRU module,let it reset the entire chip, | |
35 | * or via GPIO give PMIC. | |
36 | */ | |
37 | enum tshut_mode { | |
38 | TSHUT_MODE_CRU = 0, | |
39 | TSHUT_MODE_GPIO, | |
40 | }; | |
41 | ||
42 | /** | |
13c1cfda | 43 | * The system Temperature Sensors tshut(tshut) polarity |
cbac8f63 CW |
44 | * the bit 8 is tshut polarity. |
45 | * 0: low active, 1: high active | |
46 | */ | |
47 | enum tshut_polarity { | |
48 | TSHUT_LOW_ACTIVE = 0, | |
49 | TSHUT_HIGH_ACTIVE, | |
50 | }; | |
51 | ||
52 | /** | |
1d98b618 CW |
53 | * The system has two Temperature Sensors. |
54 | * sensor0 is for CPU, and sensor1 is for GPU. | |
cbac8f63 CW |
55 | */ |
56 | enum sensor_id { | |
1d98b618 | 57 | SENSOR_CPU = 0, |
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58 | SENSOR_GPU, |
59 | }; | |
60 | ||
020ba95d | 61 | /** |
13c1cfda | 62 | * The conversion table has the adc value and temperature. |
952418a3 CW |
63 | * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) |
64 | * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) | |
13c1cfda | 65 | */ |
020ba95d CW |
66 | enum adc_sort_mode { |
67 | ADC_DECREMENT = 0, | |
68 | ADC_INCREMENT, | |
69 | }; | |
70 | ||
1d98b618 CW |
71 | /** |
72 | * The max sensors is two in rockchip SoCs. | |
73 | * Two sensors: CPU and GPU sensor. | |
74 | */ | |
75 | #define SOC_MAX_SENSORS 2 | |
76 | ||
13c1cfda CW |
77 | /** |
78 | * struct chip_tsadc_table: hold information about chip-specific differences | |
79 | * @id: conversion table | |
80 | * @length: size of conversion table | |
81 | * @data_mask: mask to apply on data inputs | |
82 | * @mode: sort mode of this adc variant (incrementing or decrementing) | |
83 | */ | |
ce74110d CW |
84 | struct chip_tsadc_table { |
85 | const struct tsadc_table *id; | |
ce74110d | 86 | unsigned int length; |
ce74110d | 87 | u32 data_mask; |
020ba95d | 88 | enum adc_sort_mode mode; |
ce74110d CW |
89 | }; |
90 | ||
cbac8f63 | 91 | struct rockchip_tsadc_chip { |
1d98b618 CW |
92 | /* The sensor id of chip correspond to the ADC channel */ |
93 | int chn_id[SOC_MAX_SENSORS]; | |
94 | int chn_num; | |
95 | ||
cbac8f63 | 96 | /* The hardware-controlled tshut property */ |
437df217 | 97 | int tshut_temp; |
cbac8f63 CW |
98 | enum tshut_mode tshut_mode; |
99 | enum tshut_polarity tshut_polarity; | |
100 | ||
101 | /* Chip-wide methods */ | |
b9484763 CW |
102 | void (*initialize)(struct regmap *grf, |
103 | void __iomem *reg, enum tshut_polarity p); | |
cbac8f63 CW |
104 | void (*irq_ack)(void __iomem *reg); |
105 | void (*control)(void __iomem *reg, bool on); | |
106 | ||
107 | /* Per-sensor methods */ | |
ce74110d CW |
108 | int (*get_temp)(struct chip_tsadc_table table, |
109 | int chn, void __iomem *reg, int *temp); | |
110 | void (*set_tshut_temp)(struct chip_tsadc_table table, | |
437df217 | 111 | int chn, void __iomem *reg, int temp); |
cbac8f63 | 112 | void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); |
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113 | |
114 | /* Per-table methods */ | |
115 | struct chip_tsadc_table table; | |
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116 | }; |
117 | ||
118 | struct rockchip_thermal_sensor { | |
119 | struct rockchip_thermal_data *thermal; | |
120 | struct thermal_zone_device *tzd; | |
1d98b618 | 121 | int id; |
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122 | }; |
123 | ||
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124 | struct rockchip_thermal_data { |
125 | const struct rockchip_tsadc_chip *chip; | |
126 | struct platform_device *pdev; | |
127 | struct reset_control *reset; | |
128 | ||
1d98b618 | 129 | struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS]; |
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130 | |
131 | struct clk *clk; | |
132 | struct clk *pclk; | |
133 | ||
b9484763 | 134 | struct regmap *grf; |
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135 | void __iomem *regs; |
136 | ||
437df217 | 137 | int tshut_temp; |
cbac8f63 CW |
138 | enum tshut_mode tshut_mode; |
139 | enum tshut_polarity tshut_polarity; | |
140 | }; | |
141 | ||
952418a3 CW |
142 | /** |
143 | * TSADC Sensor Register description: | |
144 | * | |
145 | * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it. | |
146 | * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399) | |
147 | * | |
148 | */ | |
b9484763 | 149 | #define TSADCV2_USER_CON 0x00 |
cbac8f63 CW |
150 | #define TSADCV2_AUTO_CON 0x04 |
151 | #define TSADCV2_INT_EN 0x08 | |
152 | #define TSADCV2_INT_PD 0x0c | |
153 | #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) | |
154 | #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) | |
155 | #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 | |
156 | #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 | |
157 | #define TSADCV2_AUTO_PERIOD 0x68 | |
158 | #define TSADCV2_AUTO_PERIOD_HT 0x6c | |
159 | ||
160 | #define TSADCV2_AUTO_EN BIT(0) | |
cbac8f63 CW |
161 | #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) |
162 | #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) | |
7ea38c6c CW |
163 | /** |
164 | * TSADCV1_AUTO_Q_SEL_EN: | |
165 | * whether select (1024 - tsadc_q) as output | |
166 | * 1'b0:use tsadc_q as output(temperature-code is rising sequence) | |
167 | * 1'b1:use(1024 - tsadc_q) as output (temperature-code is falling sequence) | |
168 | */ | |
169 | #define TSADCV3_AUTO_Q_SEL_EN BIT(1) | |
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170 | |
171 | #define TSADCV2_INT_SRC_EN(chn) BIT(chn) | |
172 | #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) | |
173 | #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) | |
174 | ||
452e01b3 | 175 | #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) |
952418a3 | 176 | #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) |
cbac8f63 CW |
177 | |
178 | #define TSADCV2_DATA_MASK 0xfff | |
20f0af75 CW |
179 | #define TSADCV3_DATA_MASK 0x3ff |
180 | ||
cbac8f63 CW |
181 | #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 |
182 | #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 | |
183 | #define TSADCV2_AUTO_PERIOD_TIME 250 /* msec */ | |
184 | #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* msec */ | |
b9484763 CW |
185 | #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ |
186 | ||
187 | #define GRF_SARADC_TESTBIT 0x0e644 | |
188 | #define GRF_TSADC_TESTBIT_L 0x0e648 | |
189 | #define GRF_TSADC_TESTBIT_H 0x0e64c | |
190 | ||
191 | #define GRF_TSADC_TSEN_PD_ON (0x30003 << 0) | |
192 | #define GRF_TSADC_TSEN_PD_OFF (0x30000 << 0) | |
193 | #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) | |
194 | #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) | |
cbac8f63 CW |
195 | |
196 | struct tsadc_table { | |
d9a241cb | 197 | u32 code; |
437df217 | 198 | int temp; |
cbac8f63 CW |
199 | }; |
200 | ||
7b02a5e7 CW |
201 | /** |
202 | * Note: | |
203 | * Code to Temperature mapping of the Temperature sensor is a piece wise linear | |
204 | * curve.Any temperature, code faling between to 2 give temperatures can be | |
205 | * linearly interpolated. | |
206 | * Code to Temperature mapping should be updated based on sillcon results. | |
207 | */ | |
952418a3 | 208 | static const struct tsadc_table rk3228_code_table[] = { |
7ea38c6c CW |
209 | {0, -40000}, |
210 | {588, -40000}, | |
211 | {593, -35000}, | |
212 | {598, -30000}, | |
213 | {603, -25000}, | |
214 | {608, -20000}, | |
215 | {613, -15000}, | |
216 | {618, -10000}, | |
217 | {623, -5000}, | |
218 | {629, 0}, | |
219 | {634, 5000}, | |
220 | {639, 10000}, | |
221 | {644, 15000}, | |
222 | {649, 20000}, | |
223 | {654, 25000}, | |
224 | {660, 30000}, | |
225 | {665, 35000}, | |
226 | {670, 40000}, | |
227 | {675, 45000}, | |
228 | {681, 50000}, | |
229 | {686, 55000}, | |
230 | {691, 60000}, | |
231 | {696, 65000}, | |
232 | {702, 70000}, | |
233 | {707, 75000}, | |
234 | {712, 80000}, | |
235 | {717, 85000}, | |
236 | {723, 90000}, | |
237 | {728, 95000}, | |
238 | {733, 100000}, | |
239 | {738, 105000}, | |
240 | {744, 110000}, | |
241 | {749, 115000}, | |
242 | {754, 120000}, | |
243 | {760, 125000}, | |
244 | {TSADCV2_DATA_MASK, 125000}, | |
7b02a5e7 CW |
245 | }; |
246 | ||
952418a3 | 247 | static const struct tsadc_table rk3288_code_table[] = { |
cbac8f63 CW |
248 | {TSADCV2_DATA_MASK, -40000}, |
249 | {3800, -40000}, | |
250 | {3792, -35000}, | |
251 | {3783, -30000}, | |
252 | {3774, -25000}, | |
253 | {3765, -20000}, | |
254 | {3756, -15000}, | |
255 | {3747, -10000}, | |
256 | {3737, -5000}, | |
257 | {3728, 0}, | |
258 | {3718, 5000}, | |
259 | {3708, 10000}, | |
260 | {3698, 15000}, | |
261 | {3688, 20000}, | |
262 | {3678, 25000}, | |
263 | {3667, 30000}, | |
264 | {3656, 35000}, | |
265 | {3645, 40000}, | |
266 | {3634, 45000}, | |
267 | {3623, 50000}, | |
268 | {3611, 55000}, | |
269 | {3600, 60000}, | |
270 | {3588, 65000}, | |
271 | {3575, 70000}, | |
272 | {3563, 75000}, | |
273 | {3550, 80000}, | |
274 | {3537, 85000}, | |
275 | {3524, 90000}, | |
276 | {3510, 95000}, | |
277 | {3496, 100000}, | |
278 | {3482, 105000}, | |
279 | {3467, 110000}, | |
280 | {3452, 115000}, | |
281 | {3437, 120000}, | |
282 | {3421, 125000}, | |
cbac8f63 CW |
283 | }; |
284 | ||
952418a3 | 285 | static const struct tsadc_table rk3368_code_table[] = { |
20f0af75 CW |
286 | {0, -40000}, |
287 | {106, -40000}, | |
288 | {108, -35000}, | |
289 | {110, -30000}, | |
290 | {112, -25000}, | |
291 | {114, -20000}, | |
292 | {116, -15000}, | |
293 | {118, -10000}, | |
294 | {120, -5000}, | |
295 | {122, 0}, | |
296 | {124, 5000}, | |
297 | {126, 10000}, | |
298 | {128, 15000}, | |
299 | {130, 20000}, | |
300 | {132, 25000}, | |
301 | {134, 30000}, | |
302 | {136, 35000}, | |
303 | {138, 40000}, | |
304 | {140, 45000}, | |
305 | {142, 50000}, | |
306 | {144, 55000}, | |
307 | {146, 60000}, | |
308 | {148, 65000}, | |
309 | {150, 70000}, | |
310 | {152, 75000}, | |
311 | {154, 80000}, | |
312 | {156, 85000}, | |
313 | {158, 90000}, | |
314 | {160, 95000}, | |
315 | {162, 100000}, | |
316 | {163, 105000}, | |
317 | {165, 110000}, | |
318 | {167, 115000}, | |
319 | {169, 120000}, | |
320 | {171, 125000}, | |
321 | {TSADCV3_DATA_MASK, 125000}, | |
322 | }; | |
323 | ||
952418a3 | 324 | static const struct tsadc_table rk3399_code_table[] = { |
7ea38c6c | 325 | {0, -40000}, |
f762a35d CW |
326 | {402, -40000}, |
327 | {410, -35000}, | |
328 | {419, -30000}, | |
329 | {427, -25000}, | |
330 | {436, -20000}, | |
331 | {444, -15000}, | |
332 | {453, -10000}, | |
333 | {461, -5000}, | |
334 | {470, 0}, | |
335 | {478, 5000}, | |
336 | {487, 10000}, | |
337 | {496, 15000}, | |
338 | {504, 20000}, | |
339 | {513, 25000}, | |
340 | {521, 30000}, | |
341 | {530, 35000}, | |
342 | {538, 40000}, | |
343 | {547, 45000}, | |
344 | {555, 50000}, | |
345 | {564, 55000}, | |
346 | {573, 60000}, | |
347 | {581, 65000}, | |
348 | {590, 70000}, | |
349 | {599, 75000}, | |
350 | {607, 80000}, | |
351 | {616, 85000}, | |
352 | {624, 90000}, | |
353 | {633, 95000}, | |
354 | {642, 100000}, | |
355 | {650, 105000}, | |
356 | {659, 110000}, | |
357 | {668, 115000}, | |
358 | {677, 120000}, | |
359 | {685, 125000}, | |
7ea38c6c | 360 | {TSADCV3_DATA_MASK, 125000}, |
b0d70338 CW |
361 | }; |
362 | ||
ce74110d | 363 | static u32 rk_tsadcv2_temp_to_code(struct chip_tsadc_table table, |
437df217 | 364 | int temp) |
cbac8f63 CW |
365 | { |
366 | int high, low, mid; | |
367 | ||
368 | low = 0; | |
ce74110d | 369 | high = table.length - 1; |
cbac8f63 CW |
370 | mid = (high + low) / 2; |
371 | ||
ce74110d | 372 | if (temp < table.id[low].temp || temp > table.id[high].temp) |
cbac8f63 CW |
373 | return 0; |
374 | ||
375 | while (low <= high) { | |
ce74110d CW |
376 | if (temp == table.id[mid].temp) |
377 | return table.id[mid].code; | |
378 | else if (temp < table.id[mid].temp) | |
cbac8f63 CW |
379 | high = mid - 1; |
380 | else | |
381 | low = mid + 1; | |
382 | mid = (low + high) / 2; | |
383 | } | |
384 | ||
385 | return 0; | |
386 | } | |
387 | ||
ce74110d CW |
388 | static int rk_tsadcv2_code_to_temp(struct chip_tsadc_table table, u32 code, |
389 | int *temp) | |
cbac8f63 | 390 | { |
d9a241cb | 391 | unsigned int low = 1; |
ce74110d | 392 | unsigned int high = table.length - 1; |
1e9a1aea CW |
393 | unsigned int mid = (low + high) / 2; |
394 | unsigned int num; | |
395 | unsigned long denom; | |
396 | ||
ce74110d | 397 | WARN_ON(table.length < 2); |
1e9a1aea | 398 | |
020ba95d CW |
399 | switch (table.mode) { |
400 | case ADC_DECREMENT: | |
401 | code &= table.data_mask; | |
402 | if (code < table.id[high].code) | |
403 | return -EAGAIN; /* Incorrect reading */ | |
404 | ||
405 | while (low <= high) { | |
406 | if (code >= table.id[mid].code && | |
407 | code < table.id[mid - 1].code) | |
408 | break; | |
409 | else if (code < table.id[mid].code) | |
410 | low = mid + 1; | |
411 | else | |
412 | high = mid - 1; | |
413 | ||
414 | mid = (low + high) / 2; | |
415 | } | |
416 | break; | |
417 | case ADC_INCREMENT: | |
418 | code &= table.data_mask; | |
419 | if (code < table.id[low].code) | |
420 | return -EAGAIN; /* Incorrect reading */ | |
421 | ||
422 | while (low <= high) { | |
a87dd797 CW |
423 | if (code <= table.id[mid].code && |
424 | code > table.id[mid - 1].code) | |
020ba95d CW |
425 | break; |
426 | else if (code > table.id[mid].code) | |
427 | low = mid + 1; | |
428 | else | |
429 | high = mid - 1; | |
430 | ||
431 | mid = (low + high) / 2; | |
432 | } | |
433 | break; | |
434 | default: | |
435 | pr_err("Invalid the conversion table\n"); | |
cbac8f63 CW |
436 | } |
437 | ||
1e9a1aea CW |
438 | /* |
439 | * The 5C granularity provided by the table is too much. Let's | |
440 | * assume that the relationship between sensor readings and | |
441 | * temperature between 2 table entries is linear and interpolate | |
442 | * to produce less granular result. | |
443 | */ | |
1d37a037 | 444 | num = table.id[mid].temp - table.id[mid - 1].temp; |
020ba95d CW |
445 | num *= abs(table.id[mid - 1].code - code); |
446 | denom = abs(table.id[mid - 1].code - table.id[mid].code); | |
ce74110d | 447 | *temp = table.id[mid - 1].temp + (num / denom); |
d9a241cb DT |
448 | |
449 | return 0; | |
cbac8f63 CW |
450 | } |
451 | ||
452 | /** | |
144c5565 CW |
453 | * rk_tsadcv2_initialize - initialize TASDC Controller. |
454 | * | |
455 | * (1) Set TSADC_V2_AUTO_PERIOD: | |
456 | * Configure the interleave between every two accessing of | |
457 | * TSADC in normal operation. | |
458 | * | |
459 | * (2) Set TSADCV2_AUTO_PERIOD_HT: | |
460 | * Configure the interleave between every two accessing of | |
461 | * TSADC after the temperature is higher than COM_SHUT or COM_INT. | |
462 | * | |
463 | * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: | |
464 | * If the temperature is higher than COMP_INT or COMP_SHUT for | |
465 | * "debounce" times, TSADC controller will generate interrupt or TSHUT. | |
cbac8f63 | 466 | */ |
b9484763 | 467 | static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs, |
cbac8f63 CW |
468 | enum tshut_polarity tshut_polarity) |
469 | { | |
470 | if (tshut_polarity == TSHUT_HIGH_ACTIVE) | |
452e01b3 | 471 | writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
cbac8f63 CW |
472 | regs + TSADCV2_AUTO_CON); |
473 | else | |
452e01b3 | 474 | writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
cbac8f63 CW |
475 | regs + TSADCV2_AUTO_CON); |
476 | ||
477 | writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); | |
478 | writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, | |
479 | regs + TSADCV2_HIGHT_INT_DEBOUNCE); | |
480 | writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, | |
481 | regs + TSADCV2_AUTO_PERIOD_HT); | |
482 | writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, | |
483 | regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); | |
b9484763 CW |
484 | |
485 | if (IS_ERR(grf)) { | |
486 | pr_warn("%s: Missing rockchip,grf property\n", __func__); | |
487 | return; | |
488 | } | |
489 | } | |
490 | ||
491 | /** | |
492 | * rk_tsadcv3_initialize - initialize TASDC Controller. | |
493 | * (1) The tsadc control power sequence. | |
494 | * | |
495 | * (2) Set TSADC_V2_AUTO_PERIOD: | |
496 | * Configure the interleave between every two accessing of | |
497 | * TSADC in normal operation. | |
498 | * | |
499 | * (2) Set TSADCV2_AUTO_PERIOD_HT: | |
500 | * Configure the interleave between every two accessing of | |
501 | * TSADC after the temperature is higher than COM_SHUT or COM_INT. | |
502 | * | |
503 | * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: | |
504 | * If the temperature is higher than COMP_INT or COMP_SHUT for | |
505 | * "debounce" times, TSADC controller will generate interrupt or TSHUT. | |
506 | */ | |
507 | static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs, | |
508 | enum tshut_polarity tshut_polarity) | |
509 | { | |
510 | /* The tsadc control power sequence */ | |
511 | if (IS_ERR(grf)) { | |
512 | /* Set interleave value to workround ic time sync issue */ | |
513 | writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs + | |
514 | TSADCV2_USER_CON); | |
515 | } else { | |
516 | regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_TSEN_PD_ON); | |
517 | mdelay(10); | |
518 | regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_TSEN_PD_OFF); | |
519 | udelay(100); /* The spec note says at least 15 us */ | |
520 | regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON); | |
521 | regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON); | |
522 | udelay(200); /* The spec note says at least 90 us */ | |
523 | } | |
524 | ||
525 | if (tshut_polarity == TSHUT_HIGH_ACTIVE) | |
526 | writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, | |
527 | regs + TSADCV2_AUTO_CON); | |
528 | else | |
529 | writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, | |
530 | regs + TSADCV2_AUTO_CON); | |
531 | ||
532 | writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); | |
533 | writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, | |
534 | regs + TSADCV2_HIGHT_INT_DEBOUNCE); | |
535 | writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, | |
536 | regs + TSADCV2_AUTO_PERIOD_HT); | |
537 | writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, | |
538 | regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); | |
cbac8f63 CW |
539 | } |
540 | ||
952418a3 | 541 | static void rk_tsadcv2_irq_ack(void __iomem *regs) |
7b02a5e7 CW |
542 | { |
543 | u32 val; | |
544 | ||
545 | val = readl_relaxed(regs + TSADCV2_INT_PD); | |
952418a3 | 546 | writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); |
7b02a5e7 CW |
547 | } |
548 | ||
952418a3 | 549 | static void rk_tsadcv3_irq_ack(void __iomem *regs) |
cbac8f63 CW |
550 | { |
551 | u32 val; | |
552 | ||
553 | val = readl_relaxed(regs + TSADCV2_INT_PD); | |
952418a3 | 554 | writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); |
cbac8f63 CW |
555 | } |
556 | ||
557 | static void rk_tsadcv2_control(void __iomem *regs, bool enable) | |
558 | { | |
559 | u32 val; | |
560 | ||
561 | val = readl_relaxed(regs + TSADCV2_AUTO_CON); | |
562 | if (enable) | |
563 | val |= TSADCV2_AUTO_EN; | |
564 | else | |
565 | val &= ~TSADCV2_AUTO_EN; | |
566 | ||
567 | writel_relaxed(val, regs + TSADCV2_AUTO_CON); | |
568 | } | |
569 | ||
7ea38c6c CW |
570 | /** |
571 | * @rk_tsadcv3_control: | |
572 | * TSADC controller works at auto mode, and some SoCs need set the tsadc_q_sel | |
573 | * bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output adc value if | |
574 | * setting this bit to enable. | |
575 | */ | |
576 | static void rk_tsadcv3_control(void __iomem *regs, bool enable) | |
577 | { | |
578 | u32 val; | |
579 | ||
580 | val = readl_relaxed(regs + TSADCV2_AUTO_CON); | |
581 | if (enable) | |
582 | val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; | |
583 | else | |
584 | val &= ~TSADCV2_AUTO_EN; | |
585 | ||
586 | writel_relaxed(val, regs + TSADCV2_AUTO_CON); | |
587 | } | |
588 | ||
ce74110d CW |
589 | static int rk_tsadcv2_get_temp(struct chip_tsadc_table table, |
590 | int chn, void __iomem *regs, int *temp) | |
cbac8f63 CW |
591 | { |
592 | u32 val; | |
593 | ||
cbac8f63 | 594 | val = readl_relaxed(regs + TSADCV2_DATA(chn)); |
cbac8f63 | 595 | |
ce74110d | 596 | return rk_tsadcv2_code_to_temp(table, val, temp); |
cbac8f63 CW |
597 | } |
598 | ||
ce74110d | 599 | static void rk_tsadcv2_tshut_temp(struct chip_tsadc_table table, |
437df217 | 600 | int chn, void __iomem *regs, int temp) |
cbac8f63 CW |
601 | { |
602 | u32 tshut_value, val; | |
603 | ||
ce74110d | 604 | tshut_value = rk_tsadcv2_temp_to_code(table, temp); |
cbac8f63 CW |
605 | writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn)); |
606 | ||
607 | /* TSHUT will be valid */ | |
608 | val = readl_relaxed(regs + TSADCV2_AUTO_CON); | |
609 | writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON); | |
610 | } | |
611 | ||
612 | static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, | |
613 | enum tshut_mode mode) | |
614 | { | |
615 | u32 val; | |
616 | ||
617 | val = readl_relaxed(regs + TSADCV2_INT_EN); | |
618 | if (mode == TSHUT_MODE_GPIO) { | |
619 | val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); | |
620 | val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); | |
621 | } else { | |
622 | val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); | |
623 | val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); | |
624 | } | |
625 | ||
626 | writel_relaxed(val, regs + TSADCV2_INT_EN); | |
627 | } | |
628 | ||
7b02a5e7 CW |
629 | static const struct rockchip_tsadc_chip rk3228_tsadc_data = { |
630 | .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ | |
631 | .chn_num = 1, /* one channel for tsadc */ | |
632 | ||
633 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ | |
634 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
635 | .tshut_temp = 95000, | |
636 | ||
637 | .initialize = rk_tsadcv2_initialize, | |
952418a3 | 638 | .irq_ack = rk_tsadcv3_irq_ack, |
7ea38c6c | 639 | .control = rk_tsadcv3_control, |
7b02a5e7 CW |
640 | .get_temp = rk_tsadcv2_get_temp, |
641 | .set_tshut_temp = rk_tsadcv2_tshut_temp, | |
642 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
643 | ||
644 | .table = { | |
952418a3 CW |
645 | .id = rk3228_code_table, |
646 | .length = ARRAY_SIZE(rk3228_code_table), | |
7b02a5e7 | 647 | .data_mask = TSADCV3_DATA_MASK, |
7ea38c6c | 648 | .mode = ADC_INCREMENT, |
7b02a5e7 CW |
649 | }, |
650 | }; | |
651 | ||
cbac8f63 | 652 | static const struct rockchip_tsadc_chip rk3288_tsadc_data = { |
1d98b618 CW |
653 | .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ |
654 | .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ | |
655 | .chn_num = 2, /* two channels for tsadc */ | |
656 | ||
cbac8f63 CW |
657 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ |
658 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
659 | .tshut_temp = 95000, | |
660 | ||
661 | .initialize = rk_tsadcv2_initialize, | |
662 | .irq_ack = rk_tsadcv2_irq_ack, | |
663 | .control = rk_tsadcv2_control, | |
664 | .get_temp = rk_tsadcv2_get_temp, | |
665 | .set_tshut_temp = rk_tsadcv2_tshut_temp, | |
666 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
ce74110d CW |
667 | |
668 | .table = { | |
952418a3 CW |
669 | .id = rk3288_code_table, |
670 | .length = ARRAY_SIZE(rk3288_code_table), | |
ce74110d | 671 | .data_mask = TSADCV2_DATA_MASK, |
020ba95d | 672 | .mode = ADC_DECREMENT, |
ce74110d | 673 | }, |
cbac8f63 CW |
674 | }; |
675 | ||
20f0af75 CW |
676 | static const struct rockchip_tsadc_chip rk3368_tsadc_data = { |
677 | .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ | |
678 | .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ | |
679 | .chn_num = 2, /* two channels for tsadc */ | |
680 | ||
681 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ | |
682 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
683 | .tshut_temp = 95000, | |
684 | ||
685 | .initialize = rk_tsadcv2_initialize, | |
686 | .irq_ack = rk_tsadcv2_irq_ack, | |
687 | .control = rk_tsadcv2_control, | |
688 | .get_temp = rk_tsadcv2_get_temp, | |
689 | .set_tshut_temp = rk_tsadcv2_tshut_temp, | |
690 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
691 | ||
692 | .table = { | |
952418a3 CW |
693 | .id = rk3368_code_table, |
694 | .length = ARRAY_SIZE(rk3368_code_table), | |
20f0af75 CW |
695 | .data_mask = TSADCV3_DATA_MASK, |
696 | .mode = ADC_INCREMENT, | |
697 | }, | |
698 | }; | |
699 | ||
b0d70338 CW |
700 | static const struct rockchip_tsadc_chip rk3399_tsadc_data = { |
701 | .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ | |
702 | .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ | |
703 | .chn_num = 2, /* two channels for tsadc */ | |
704 | ||
705 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ | |
706 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
707 | .tshut_temp = 95000, | |
708 | ||
b9484763 | 709 | .initialize = rk_tsadcv3_initialize, |
952418a3 | 710 | .irq_ack = rk_tsadcv3_irq_ack, |
7ea38c6c | 711 | .control = rk_tsadcv3_control, |
b0d70338 CW |
712 | .get_temp = rk_tsadcv2_get_temp, |
713 | .set_tshut_temp = rk_tsadcv2_tshut_temp, | |
714 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
715 | ||
716 | .table = { | |
952418a3 CW |
717 | .id = rk3399_code_table, |
718 | .length = ARRAY_SIZE(rk3399_code_table), | |
b0d70338 | 719 | .data_mask = TSADCV3_DATA_MASK, |
7ea38c6c | 720 | .mode = ADC_INCREMENT, |
b0d70338 CW |
721 | }, |
722 | }; | |
723 | ||
cbac8f63 | 724 | static const struct of_device_id of_rockchip_thermal_match[] = { |
7b02a5e7 CW |
725 | { |
726 | .compatible = "rockchip,rk3228-tsadc", | |
727 | .data = (void *)&rk3228_tsadc_data, | |
728 | }, | |
cbac8f63 CW |
729 | { |
730 | .compatible = "rockchip,rk3288-tsadc", | |
731 | .data = (void *)&rk3288_tsadc_data, | |
732 | }, | |
20f0af75 CW |
733 | { |
734 | .compatible = "rockchip,rk3368-tsadc", | |
735 | .data = (void *)&rk3368_tsadc_data, | |
736 | }, | |
b0d70338 CW |
737 | { |
738 | .compatible = "rockchip,rk3399-tsadc", | |
739 | .data = (void *)&rk3399_tsadc_data, | |
740 | }, | |
cbac8f63 CW |
741 | { /* end */ }, |
742 | }; | |
743 | MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match); | |
744 | ||
745 | static void | |
746 | rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on) | |
747 | { | |
748 | struct thermal_zone_device *tzd = sensor->tzd; | |
749 | ||
750 | tzd->ops->set_mode(tzd, | |
751 | on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED); | |
752 | } | |
753 | ||
754 | static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev) | |
755 | { | |
756 | struct rockchip_thermal_data *thermal = dev; | |
757 | int i; | |
758 | ||
759 | dev_dbg(&thermal->pdev->dev, "thermal alarm\n"); | |
760 | ||
761 | thermal->chip->irq_ack(thermal->regs); | |
762 | ||
1d98b618 | 763 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
764 | thermal_zone_device_update(thermal->sensors[i].tzd); |
765 | ||
766 | return IRQ_HANDLED; | |
767 | } | |
768 | ||
17e8351a | 769 | static int rockchip_thermal_get_temp(void *_sensor, int *out_temp) |
cbac8f63 CW |
770 | { |
771 | struct rockchip_thermal_sensor *sensor = _sensor; | |
772 | struct rockchip_thermal_data *thermal = sensor->thermal; | |
773 | const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip; | |
774 | int retval; | |
775 | ||
ce74110d CW |
776 | retval = tsadc->get_temp(tsadc->table, |
777 | sensor->id, thermal->regs, out_temp); | |
17e8351a | 778 | dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n", |
cbac8f63 CW |
779 | sensor->id, *out_temp, retval); |
780 | ||
781 | return retval; | |
782 | } | |
783 | ||
784 | static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = { | |
785 | .get_temp = rockchip_thermal_get_temp, | |
786 | }; | |
787 | ||
788 | static int rockchip_configure_from_dt(struct device *dev, | |
789 | struct device_node *np, | |
790 | struct rockchip_thermal_data *thermal) | |
791 | { | |
792 | u32 shut_temp, tshut_mode, tshut_polarity; | |
793 | ||
794 | if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) { | |
795 | dev_warn(dev, | |
437df217 | 796 | "Missing tshut temp property, using default %d\n", |
cbac8f63 CW |
797 | thermal->chip->tshut_temp); |
798 | thermal->tshut_temp = thermal->chip->tshut_temp; | |
799 | } else { | |
43b4eb9f CW |
800 | if (shut_temp > INT_MAX) { |
801 | dev_err(dev, "Invalid tshut temperature specified: %d\n", | |
802 | shut_temp); | |
803 | return -ERANGE; | |
804 | } | |
cbac8f63 CW |
805 | thermal->tshut_temp = shut_temp; |
806 | } | |
807 | ||
cbac8f63 CW |
808 | if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) { |
809 | dev_warn(dev, | |
810 | "Missing tshut mode property, using default (%s)\n", | |
811 | thermal->chip->tshut_mode == TSHUT_MODE_GPIO ? | |
812 | "gpio" : "cru"); | |
813 | thermal->tshut_mode = thermal->chip->tshut_mode; | |
814 | } else { | |
815 | thermal->tshut_mode = tshut_mode; | |
816 | } | |
817 | ||
818 | if (thermal->tshut_mode > 1) { | |
819 | dev_err(dev, "Invalid tshut mode specified: %d\n", | |
820 | thermal->tshut_mode); | |
821 | return -EINVAL; | |
822 | } | |
823 | ||
824 | if (of_property_read_u32(np, "rockchip,hw-tshut-polarity", | |
825 | &tshut_polarity)) { | |
826 | dev_warn(dev, | |
827 | "Missing tshut-polarity property, using default (%s)\n", | |
828 | thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ? | |
829 | "low" : "high"); | |
830 | thermal->tshut_polarity = thermal->chip->tshut_polarity; | |
831 | } else { | |
832 | thermal->tshut_polarity = tshut_polarity; | |
833 | } | |
834 | ||
835 | if (thermal->tshut_polarity > 1) { | |
836 | dev_err(dev, "Invalid tshut-polarity specified: %d\n", | |
837 | thermal->tshut_polarity); | |
838 | return -EINVAL; | |
839 | } | |
840 | ||
b9484763 CW |
841 | /* The tsadc wont to handle the error in here since some SoCs didn't |
842 | * need this property. | |
843 | */ | |
844 | thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); | |
845 | ||
cbac8f63 CW |
846 | return 0; |
847 | } | |
848 | ||
849 | static int | |
850 | rockchip_thermal_register_sensor(struct platform_device *pdev, | |
851 | struct rockchip_thermal_data *thermal, | |
852 | struct rockchip_thermal_sensor *sensor, | |
1d98b618 | 853 | int id) |
cbac8f63 CW |
854 | { |
855 | const struct rockchip_tsadc_chip *tsadc = thermal->chip; | |
856 | int error; | |
857 | ||
858 | tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); | |
ce74110d CW |
859 | tsadc->set_tshut_temp(tsadc->table, id, thermal->regs, |
860 | thermal->tshut_temp); | |
cbac8f63 CW |
861 | |
862 | sensor->thermal = thermal; | |
863 | sensor->id = id; | |
2633ad19 EV |
864 | sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id, |
865 | sensor, &rockchip_of_thermal_ops); | |
cbac8f63 CW |
866 | if (IS_ERR(sensor->tzd)) { |
867 | error = PTR_ERR(sensor->tzd); | |
868 | dev_err(&pdev->dev, "failed to register sensor %d: %d\n", | |
869 | id, error); | |
870 | return error; | |
871 | } | |
872 | ||
873 | return 0; | |
874 | } | |
875 | ||
13c1cfda | 876 | /** |
cbac8f63 CW |
877 | * Reset TSADC Controller, reset all tsadc registers. |
878 | */ | |
879 | static void rockchip_thermal_reset_controller(struct reset_control *reset) | |
880 | { | |
881 | reset_control_assert(reset); | |
882 | usleep_range(10, 20); | |
883 | reset_control_deassert(reset); | |
884 | } | |
885 | ||
886 | static int rockchip_thermal_probe(struct platform_device *pdev) | |
887 | { | |
888 | struct device_node *np = pdev->dev.of_node; | |
889 | struct rockchip_thermal_data *thermal; | |
890 | const struct of_device_id *match; | |
891 | struct resource *res; | |
892 | int irq; | |
2633ad19 | 893 | int i; |
cbac8f63 CW |
894 | int error; |
895 | ||
896 | match = of_match_node(of_rockchip_thermal_match, np); | |
897 | if (!match) | |
898 | return -ENXIO; | |
899 | ||
900 | irq = platform_get_irq(pdev, 0); | |
901 | if (irq < 0) { | |
902 | dev_err(&pdev->dev, "no irq resource?\n"); | |
903 | return -EINVAL; | |
904 | } | |
905 | ||
906 | thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data), | |
907 | GFP_KERNEL); | |
908 | if (!thermal) | |
909 | return -ENOMEM; | |
910 | ||
911 | thermal->pdev = pdev; | |
912 | ||
913 | thermal->chip = (const struct rockchip_tsadc_chip *)match->data; | |
914 | if (!thermal->chip) | |
915 | return -EINVAL; | |
916 | ||
917 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
918 | thermal->regs = devm_ioremap_resource(&pdev->dev, res); | |
919 | if (IS_ERR(thermal->regs)) | |
920 | return PTR_ERR(thermal->regs); | |
921 | ||
922 | thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb"); | |
923 | if (IS_ERR(thermal->reset)) { | |
924 | error = PTR_ERR(thermal->reset); | |
925 | dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); | |
926 | return error; | |
927 | } | |
928 | ||
929 | thermal->clk = devm_clk_get(&pdev->dev, "tsadc"); | |
930 | if (IS_ERR(thermal->clk)) { | |
931 | error = PTR_ERR(thermal->clk); | |
932 | dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); | |
933 | return error; | |
934 | } | |
935 | ||
936 | thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); | |
937 | if (IS_ERR(thermal->pclk)) { | |
0d0a2bf6 | 938 | error = PTR_ERR(thermal->pclk); |
cbac8f63 CW |
939 | dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", |
940 | error); | |
941 | return error; | |
942 | } | |
943 | ||
944 | error = clk_prepare_enable(thermal->clk); | |
945 | if (error) { | |
946 | dev_err(&pdev->dev, "failed to enable converter clock: %d\n", | |
947 | error); | |
948 | return error; | |
949 | } | |
950 | ||
951 | error = clk_prepare_enable(thermal->pclk); | |
952 | if (error) { | |
953 | dev_err(&pdev->dev, "failed to enable pclk: %d\n", error); | |
954 | goto err_disable_clk; | |
955 | } | |
956 | ||
957 | rockchip_thermal_reset_controller(thermal->reset); | |
958 | ||
959 | error = rockchip_configure_from_dt(&pdev->dev, np, thermal); | |
960 | if (error) { | |
961 | dev_err(&pdev->dev, "failed to parse device tree data: %d\n", | |
962 | error); | |
963 | goto err_disable_pclk; | |
964 | } | |
965 | ||
b9484763 CW |
966 | thermal->chip->initialize(thermal->grf, thermal->regs, |
967 | thermal->tshut_polarity); | |
cbac8f63 | 968 | |
1d98b618 CW |
969 | for (i = 0; i < thermal->chip->chn_num; i++) { |
970 | error = rockchip_thermal_register_sensor(pdev, thermal, | |
971 | &thermal->sensors[i], | |
972 | thermal->chip->chn_id[i]); | |
973 | if (error) { | |
974 | dev_err(&pdev->dev, | |
975 | "failed to register sensor[%d] : error = %d\n", | |
976 | i, error); | |
1d98b618 CW |
977 | goto err_disable_pclk; |
978 | } | |
cbac8f63 CW |
979 | } |
980 | ||
981 | error = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
982 | &rockchip_thermal_alarm_irq_thread, | |
983 | IRQF_ONESHOT, | |
984 | "rockchip_thermal", thermal); | |
985 | if (error) { | |
986 | dev_err(&pdev->dev, | |
987 | "failed to request tsadc irq: %d\n", error); | |
2633ad19 | 988 | goto err_disable_pclk; |
cbac8f63 CW |
989 | } |
990 | ||
991 | thermal->chip->control(thermal->regs, true); | |
992 | ||
1d98b618 | 993 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
994 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); |
995 | ||
996 | platform_set_drvdata(pdev, thermal); | |
997 | ||
998 | return 0; | |
999 | ||
cbac8f63 CW |
1000 | err_disable_pclk: |
1001 | clk_disable_unprepare(thermal->pclk); | |
1002 | err_disable_clk: | |
1003 | clk_disable_unprepare(thermal->clk); | |
1004 | ||
1005 | return error; | |
1006 | } | |
1007 | ||
1008 | static int rockchip_thermal_remove(struct platform_device *pdev) | |
1009 | { | |
1010 | struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); | |
1011 | int i; | |
1012 | ||
1d98b618 | 1013 | for (i = 0; i < thermal->chip->chn_num; i++) { |
cbac8f63 CW |
1014 | struct rockchip_thermal_sensor *sensor = &thermal->sensors[i]; |
1015 | ||
1016 | rockchip_thermal_toggle_sensor(sensor, false); | |
cbac8f63 CW |
1017 | } |
1018 | ||
1019 | thermal->chip->control(thermal->regs, false); | |
1020 | ||
1021 | clk_disable_unprepare(thermal->pclk); | |
1022 | clk_disable_unprepare(thermal->clk); | |
1023 | ||
1024 | return 0; | |
1025 | } | |
1026 | ||
1027 | static int __maybe_unused rockchip_thermal_suspend(struct device *dev) | |
1028 | { | |
1029 | struct platform_device *pdev = to_platform_device(dev); | |
1030 | struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); | |
1031 | int i; | |
1032 | ||
1d98b618 | 1033 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
1034 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], false); |
1035 | ||
1036 | thermal->chip->control(thermal->regs, false); | |
1037 | ||
1038 | clk_disable(thermal->pclk); | |
1039 | clk_disable(thermal->clk); | |
1040 | ||
7e38a5b1 CW |
1041 | pinctrl_pm_select_sleep_state(dev); |
1042 | ||
cbac8f63 CW |
1043 | return 0; |
1044 | } | |
1045 | ||
1046 | static int __maybe_unused rockchip_thermal_resume(struct device *dev) | |
1047 | { | |
1048 | struct platform_device *pdev = to_platform_device(dev); | |
1049 | struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); | |
1050 | int i; | |
1051 | int error; | |
1052 | ||
1053 | error = clk_enable(thermal->clk); | |
1054 | if (error) | |
1055 | return error; | |
1056 | ||
1057 | error = clk_enable(thermal->pclk); | |
ab5b52f1 SL |
1058 | if (error) { |
1059 | clk_disable(thermal->clk); | |
cbac8f63 | 1060 | return error; |
ab5b52f1 | 1061 | } |
cbac8f63 CW |
1062 | |
1063 | rockchip_thermal_reset_controller(thermal->reset); | |
1064 | ||
b9484763 CW |
1065 | thermal->chip->initialize(thermal->grf, thermal->regs, |
1066 | thermal->tshut_polarity); | |
cbac8f63 | 1067 | |
1d98b618 CW |
1068 | for (i = 0; i < thermal->chip->chn_num; i++) { |
1069 | int id = thermal->sensors[i].id; | |
cbac8f63 CW |
1070 | |
1071 | thermal->chip->set_tshut_mode(id, thermal->regs, | |
1072 | thermal->tshut_mode); | |
ce74110d CW |
1073 | thermal->chip->set_tshut_temp(thermal->chip->table, |
1074 | id, thermal->regs, | |
cbac8f63 CW |
1075 | thermal->tshut_temp); |
1076 | } | |
1077 | ||
1078 | thermal->chip->control(thermal->regs, true); | |
1079 | ||
1d98b618 | 1080 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
1081 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); |
1082 | ||
7e38a5b1 CW |
1083 | pinctrl_pm_select_default_state(dev); |
1084 | ||
cbac8f63 CW |
1085 | return 0; |
1086 | } | |
1087 | ||
1088 | static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops, | |
1089 | rockchip_thermal_suspend, rockchip_thermal_resume); | |
1090 | ||
1091 | static struct platform_driver rockchip_thermal_driver = { | |
1092 | .driver = { | |
1093 | .name = "rockchip-thermal", | |
cbac8f63 CW |
1094 | .pm = &rockchip_thermal_pm_ops, |
1095 | .of_match_table = of_rockchip_thermal_match, | |
1096 | }, | |
1097 | .probe = rockchip_thermal_probe, | |
1098 | .remove = rockchip_thermal_remove, | |
1099 | }; | |
1100 | ||
1101 | module_platform_driver(rockchip_thermal_driver); | |
1102 | ||
1103 | MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver"); | |
1104 | MODULE_AUTHOR("Rockchip, Inc."); | |
1105 | MODULE_LICENSE("GPL v2"); | |
1106 | MODULE_ALIAS("platform:rockchip-thermal"); |