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d316522d | 1 | // SPDX-License-Identifier: GPL-2.0 |
564e73d2 WS |
2 | /* |
3 | * R-Car Gen3 THS thermal sensor driver | |
4 | * Based on rcar_thermal.c and work from Hien Dang and Khiem Nguyen. | |
5 | * | |
6 | * Copyright (C) 2016 Renesas Electronics Corporation. | |
7 | * Copyright (C) 2016 Sang Engineering | |
564e73d2 WS |
8 | */ |
9 | #include <linux/delay.h> | |
10 | #include <linux/err.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/module.h> | |
564e73d2 WS |
14 | #include <linux/of_device.h> |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/pm_runtime.h> | |
d668c807 | 17 | #include <linux/sys_soc.h> |
564e73d2 WS |
18 | #include <linux/thermal.h> |
19 | ||
7d4b2697 | 20 | #include "thermal_core.h" |
6269e9f7 | 21 | #include "thermal_hwmon.h" |
7d4b2697 | 22 | |
564e73d2 WS |
23 | /* Register offsets */ |
24 | #define REG_GEN3_IRQSTR 0x04 | |
25 | #define REG_GEN3_IRQMSK 0x08 | |
26 | #define REG_GEN3_IRQCTL 0x0C | |
27 | #define REG_GEN3_IRQEN 0x10 | |
28 | #define REG_GEN3_IRQTEMP1 0x14 | |
29 | #define REG_GEN3_IRQTEMP2 0x18 | |
30 | #define REG_GEN3_IRQTEMP3 0x1C | |
31 | #define REG_GEN3_CTSR 0x20 | |
32 | #define REG_GEN3_THCTR 0x20 | |
33 | #define REG_GEN3_TEMP 0x28 | |
34 | #define REG_GEN3_THCODE1 0x50 | |
35 | #define REG_GEN3_THCODE2 0x54 | |
36 | #define REG_GEN3_THCODE3 0x58 | |
37 | ||
7d4b2697 NS |
38 | /* IRQ{STR,MSK,EN} bits */ |
39 | #define IRQ_TEMP1 BIT(0) | |
40 | #define IRQ_TEMP2 BIT(1) | |
41 | #define IRQ_TEMP3 BIT(2) | |
42 | #define IRQ_TEMPD1 BIT(3) | |
43 | #define IRQ_TEMPD2 BIT(4) | |
44 | #define IRQ_TEMPD3 BIT(5) | |
45 | ||
564e73d2 WS |
46 | /* CTSR bits */ |
47 | #define CTSR_PONM BIT(8) | |
48 | #define CTSR_AOUT BIT(7) | |
49 | #define CTSR_THBGR BIT(5) | |
50 | #define CTSR_VMEN BIT(4) | |
51 | #define CTSR_VMST BIT(1) | |
52 | #define CTSR_THSST BIT(0) | |
53 | ||
54 | /* THCTR bits */ | |
55 | #define THCTR_PONM BIT(6) | |
56 | #define THCTR_THSST BIT(0) | |
57 | ||
58 | #define CTEMP_MASK 0xFFF | |
59 | ||
60 | #define MCELSIUS(temp) ((temp) * 1000) | |
61 | #define GEN3_FUSE_MASK 0xFFF | |
62 | ||
e854da4f | 63 | #define TSC_MAX_NUM 4 |
564e73d2 | 64 | |
6a310f8f | 65 | /* default THCODE values if FUSEs are missing */ |
679d10df | 66 | static const int thcodes[TSC_MAX_NUM][3] = { |
6a310f8f YK |
67 | { 3397, 2800, 2221 }, |
68 | { 3393, 2795, 2216 }, | |
69 | { 3389, 2805, 2237 }, | |
e854da4f | 70 | { 3415, 2694, 2195 }, |
6a310f8f YK |
71 | }; |
72 | ||
564e73d2 WS |
73 | /* Structure for thermal temperature calculation */ |
74 | struct equation_coefs { | |
75 | int a1; | |
76 | int b1; | |
77 | int a2; | |
78 | int b2; | |
79 | }; | |
80 | ||
81 | struct rcar_gen3_thermal_tsc { | |
82 | void __iomem *base; | |
83 | struct thermal_zone_device *zone; | |
84 | struct equation_coefs coef; | |
bdc4480a | 85 | int tj_t; |
6a310f8f | 86 | int id; /* thermal channel id */ |
564e73d2 WS |
87 | }; |
88 | ||
89 | struct rcar_gen3_thermal_priv { | |
90 | struct rcar_gen3_thermal_tsc *tscs[TSC_MAX_NUM]; | |
97dad1f1 | 91 | unsigned int num_tscs; |
564e73d2 WS |
92 | void (*thermal_init)(struct rcar_gen3_thermal_tsc *tsc); |
93 | }; | |
94 | ||
95 | static inline u32 rcar_gen3_thermal_read(struct rcar_gen3_thermal_tsc *tsc, | |
96 | u32 reg) | |
97 | { | |
98 | return ioread32(tsc->base + reg); | |
99 | } | |
100 | ||
101 | static inline void rcar_gen3_thermal_write(struct rcar_gen3_thermal_tsc *tsc, | |
102 | u32 reg, u32 data) | |
103 | { | |
104 | iowrite32(data, tsc->base + reg); | |
105 | } | |
106 | ||
107 | /* | |
108 | * Linear approximation for temperature | |
109 | * | |
110 | * [reg] = [temp] * a + b => [temp] = ([reg] - b) / a | |
111 | * | |
112 | * The constants a and b are calculated using two triplets of int values PTAT | |
113 | * and THCODE. PTAT and THCODE can either be read from hardware or use hard | |
114 | * coded values from driver. The formula to calculate a and b are taken from | |
115 | * BSP and sparsely documented and understood. | |
116 | * | |
117 | * Examining the linear formula and the formula used to calculate constants a | |
118 | * and b while knowing that the span for PTAT and THCODE values are between | |
119 | * 0x000 and 0xfff the largest integer possible is 0xfff * 0xfff == 0xffe001. | |
120 | * Integer also needs to be signed so that leaves 7 bits for binary | |
121 | * fixed point scaling. | |
122 | */ | |
123 | ||
124 | #define FIXPT_SHIFT 7 | |
125 | #define FIXPT_INT(_x) ((_x) << FIXPT_SHIFT) | |
7d4b2697 | 126 | #define INT_FIXPT(_x) ((_x) >> FIXPT_SHIFT) |
564e73d2 WS |
127 | #define FIXPT_DIV(_a, _b) DIV_ROUND_CLOSEST(((_a) << FIXPT_SHIFT), (_b)) |
128 | #define FIXPT_TO_MCELSIUS(_x) ((_x) * 1000 >> FIXPT_SHIFT) | |
129 | ||
130 | #define RCAR3_THERMAL_GRAN 500 /* mili Celsius */ | |
131 | ||
132 | /* no idea where these constants come from */ | |
564e73d2 WS |
133 | #define TJ_3 -41 |
134 | ||
bdc4480a | 135 | static void rcar_gen3_thermal_calc_coefs(struct rcar_gen3_thermal_tsc *tsc, |
6a310f8f | 136 | int *ptat, const int *thcode, |
4eb39f79 | 137 | int ths_tj_1) |
564e73d2 | 138 | { |
564e73d2 WS |
139 | /* TODO: Find documentation and document constant calculation formula */ |
140 | ||
141 | /* | |
142 | * Division is not scaled in BSP and if scaled it might overflow | |
143 | * the dividend (4095 * 4095 << 14 > INT_MAX) so keep it unscaled | |
144 | */ | |
bdc4480a YK |
145 | tsc->tj_t = (FIXPT_INT((ptat[1] - ptat[2]) * 157) |
146 | / (ptat[0] - ptat[2])) + FIXPT_INT(TJ_3); | |
564e73d2 | 147 | |
bdc4480a YK |
148 | tsc->coef.a1 = FIXPT_DIV(FIXPT_INT(thcode[1] - thcode[2]), |
149 | tsc->tj_t - FIXPT_INT(TJ_3)); | |
150 | tsc->coef.b1 = FIXPT_INT(thcode[2]) - tsc->coef.a1 * TJ_3; | |
564e73d2 | 151 | |
bdc4480a YK |
152 | tsc->coef.a2 = FIXPT_DIV(FIXPT_INT(thcode[1] - thcode[0]), |
153 | tsc->tj_t - FIXPT_INT(ths_tj_1)); | |
154 | tsc->coef.b2 = FIXPT_INT(thcode[0]) - tsc->coef.a2 * ths_tj_1; | |
564e73d2 WS |
155 | } |
156 | ||
157 | static int rcar_gen3_thermal_round(int temp) | |
158 | { | |
159 | int result, round_offs; | |
160 | ||
161 | round_offs = temp >= 0 ? RCAR3_THERMAL_GRAN / 2 : | |
162 | -RCAR3_THERMAL_GRAN / 2; | |
163 | result = (temp + round_offs) / RCAR3_THERMAL_GRAN; | |
164 | return result * RCAR3_THERMAL_GRAN; | |
165 | } | |
166 | ||
167 | static int rcar_gen3_thermal_get_temp(void *devdata, int *temp) | |
168 | { | |
169 | struct rcar_gen3_thermal_tsc *tsc = devdata; | |
6a310f8f | 170 | int mcelsius, val; |
5f8f0642 | 171 | int reg; |
564e73d2 WS |
172 | |
173 | /* Read register and convert to mili Celsius */ | |
564e73d2 WS |
174 | reg = rcar_gen3_thermal_read(tsc, REG_GEN3_TEMP) & CTEMP_MASK; |
175 | ||
679d10df | 176 | if (reg <= thcodes[tsc->id][1]) |
6a310f8f YK |
177 | val = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b1, |
178 | tsc->coef.a1); | |
179 | else | |
180 | val = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b2, | |
181 | tsc->coef.a2); | |
182 | mcelsius = FIXPT_TO_MCELSIUS(val); | |
564e73d2 | 183 | |
0f510a24 | 184 | /* Guaranteed operating range is -40C to 125C. */ |
564e73d2 WS |
185 | |
186 | /* Round value to device granularity setting */ | |
187 | *temp = rcar_gen3_thermal_round(mcelsius); | |
188 | ||
189 | return 0; | |
190 | } | |
191 | ||
a0def10b | 192 | static const struct thermal_zone_of_device_ops rcar_gen3_tz_of_ops = { |
564e73d2 WS |
193 | .get_temp = rcar_gen3_thermal_get_temp, |
194 | }; | |
195 | ||
d668c807 NS |
196 | static const struct soc_device_attribute r8a7795es1[] = { |
197 | { .soc_id = "r8a7795", .revision = "ES1.*" }, | |
198 | { /* sentinel */ } | |
199 | }; | |
200 | ||
201 | static void rcar_gen3_thermal_init_r8a7795es1(struct rcar_gen3_thermal_tsc *tsc) | |
564e73d2 WS |
202 | { |
203 | rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR, CTSR_THBGR); | |
204 | rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR, 0x0); | |
205 | ||
206 | usleep_range(1000, 2000); | |
207 | ||
208 | rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR, CTSR_PONM); | |
7d4b2697 | 209 | |
564e73d2 | 210 | rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0x3F); |
7d4b2697 | 211 | rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0); |
7d4b2697 | 212 | |
564e73d2 WS |
213 | rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR, |
214 | CTSR_PONM | CTSR_AOUT | CTSR_THBGR | CTSR_VMEN); | |
215 | ||
216 | usleep_range(100, 200); | |
217 | ||
218 | rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR, | |
219 | CTSR_PONM | CTSR_AOUT | CTSR_THBGR | CTSR_VMEN | | |
220 | CTSR_VMST | CTSR_THSST); | |
221 | ||
222 | usleep_range(1000, 2000); | |
223 | } | |
224 | ||
d668c807 | 225 | static void rcar_gen3_thermal_init(struct rcar_gen3_thermal_tsc *tsc) |
564e73d2 WS |
226 | { |
227 | u32 reg_val; | |
228 | ||
229 | reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR); | |
230 | reg_val &= ~THCTR_PONM; | |
231 | rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val); | |
232 | ||
233 | usleep_range(1000, 2000); | |
234 | ||
ed1b1ac1 | 235 | rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0); |
7d4b2697 | 236 | rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0); |
7d4b2697 | 237 | |
564e73d2 WS |
238 | reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR); |
239 | reg_val |= THCTR_THSST; | |
240 | rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val); | |
78aefd2d NS |
241 | |
242 | usleep_range(1000, 2000); | |
564e73d2 WS |
243 | } |
244 | ||
4eb39f79 YK |
245 | static const int rcar_gen3_ths_tj_1 = 126; |
246 | static const int rcar_gen3_ths_tj_1_m3_w = 116; | |
564e73d2 | 247 | static const struct of_device_id rcar_gen3_thermal_dt_ids[] = { |
4eb39f79 YK |
248 | { |
249 | .compatible = "renesas,r8a774a1-thermal", | |
250 | .data = &rcar_gen3_ths_tj_1_m3_w, | |
251 | }, | |
1a005912 BD |
252 | { |
253 | .compatible = "renesas,r8a774b1-thermal", | |
254 | .data = &rcar_gen3_ths_tj_1, | |
255 | }, | |
947d85f0 MCR |
256 | { |
257 | .compatible = "renesas,r8a774e1-thermal", | |
258 | .data = &rcar_gen3_ths_tj_1, | |
259 | }, | |
4eb39f79 YK |
260 | { |
261 | .compatible = "renesas,r8a7795-thermal", | |
262 | .data = &rcar_gen3_ths_tj_1, | |
263 | }, | |
264 | { | |
265 | .compatible = "renesas,r8a7796-thermal", | |
266 | .data = &rcar_gen3_ths_tj_1_m3_w, | |
267 | }, | |
8d74bf79 GU |
268 | { |
269 | .compatible = "renesas,r8a77961-thermal", | |
270 | .data = &rcar_gen3_ths_tj_1_m3_w, | |
271 | }, | |
4eb39f79 YK |
272 | { |
273 | .compatible = "renesas,r8a77965-thermal", | |
274 | .data = &rcar_gen3_ths_tj_1, | |
275 | }, | |
276 | { | |
277 | .compatible = "renesas,r8a77980-thermal", | |
278 | .data = &rcar_gen3_ths_tj_1, | |
279 | }, | |
e854da4f NS |
280 | { |
281 | .compatible = "renesas,r8a779a0-thermal", | |
282 | .data = &rcar_gen3_ths_tj_1, | |
283 | }, | |
564e73d2 WS |
284 | {}, |
285 | }; | |
286 | MODULE_DEVICE_TABLE(of, rcar_gen3_thermal_dt_ids); | |
287 | ||
288 | static int rcar_gen3_thermal_remove(struct platform_device *pdev) | |
289 | { | |
290 | struct device *dev = &pdev->dev; | |
291 | ||
292 | pm_runtime_put(dev); | |
293 | pm_runtime_disable(dev); | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
6269e9f7 MV |
298 | static void rcar_gen3_hwmon_action(void *data) |
299 | { | |
300 | struct thermal_zone_device *zone = data; | |
301 | ||
302 | thermal_remove_hwmon_sysfs(zone); | |
303 | } | |
304 | ||
564e73d2 WS |
305 | static int rcar_gen3_thermal_probe(struct platform_device *pdev) |
306 | { | |
307 | struct rcar_gen3_thermal_priv *priv; | |
308 | struct device *dev = &pdev->dev; | |
4eb39f79 | 309 | const int *rcar_gen3_ths_tj_1 = of_device_get_match_data(dev); |
564e73d2 WS |
310 | struct resource *res; |
311 | struct thermal_zone_device *zone; | |
1b57b959 | 312 | int ret, i; |
564e73d2 WS |
313 | |
314 | /* default values if FUSEs are missing */ | |
315 | /* TODO: Read values from hardware on supported platforms */ | |
fc66ddff | 316 | int ptat[3] = { 2631, 1509, 435 }; |
564e73d2 WS |
317 | |
318 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
319 | if (!priv) | |
320 | return -ENOMEM; | |
321 | ||
d668c807 NS |
322 | priv->thermal_init = rcar_gen3_thermal_init; |
323 | if (soc_device_match(r8a7795es1)) | |
324 | priv->thermal_init = rcar_gen3_thermal_init_r8a7795es1; | |
cc4d072b | 325 | |
564e73d2 WS |
326 | platform_set_drvdata(pdev, priv); |
327 | ||
328 | pm_runtime_enable(dev); | |
329 | pm_runtime_get_sync(dev); | |
330 | ||
331 | for (i = 0; i < TSC_MAX_NUM; i++) { | |
332 | struct rcar_gen3_thermal_tsc *tsc; | |
333 | ||
d51546c0 NS |
334 | res = platform_get_resource(pdev, IORESOURCE_MEM, i); |
335 | if (!res) | |
336 | break; | |
337 | ||
564e73d2 WS |
338 | tsc = devm_kzalloc(dev, sizeof(*tsc), GFP_KERNEL); |
339 | if (!tsc) { | |
340 | ret = -ENOMEM; | |
341 | goto error_unregister; | |
342 | } | |
343 | ||
564e73d2 WS |
344 | tsc->base = devm_ioremap_resource(dev, res); |
345 | if (IS_ERR(tsc->base)) { | |
346 | ret = PTR_ERR(tsc->base); | |
347 | goto error_unregister; | |
348 | } | |
6a310f8f | 349 | tsc->id = i; |
564e73d2 WS |
350 | |
351 | priv->tscs[i] = tsc; | |
564e73d2 | 352 | |
d668c807 | 353 | priv->thermal_init(tsc); |
679d10df | 354 | rcar_gen3_thermal_calc_coefs(tsc, ptat, thcodes[i], |
4eb39f79 | 355 | *rcar_gen3_ths_tj_1); |
564e73d2 WS |
356 | |
357 | zone = devm_thermal_zone_of_sensor_register(dev, i, tsc, | |
358 | &rcar_gen3_tz_of_ops); | |
359 | if (IS_ERR(zone)) { | |
360 | dev_err(dev, "Can't register thermal zone\n"); | |
361 | ret = PTR_ERR(zone); | |
362 | goto error_unregister; | |
363 | } | |
364 | tsc->zone = zone; | |
7d4b2697 | 365 | |
6269e9f7 MV |
366 | tsc->zone->tzp->no_hwmon = false; |
367 | ret = thermal_add_hwmon_sysfs(tsc->zone); | |
368 | if (ret) | |
369 | goto error_unregister; | |
370 | ||
b9cd1663 | 371 | ret = devm_add_action_or_reset(dev, rcar_gen3_hwmon_action, zone); |
d543c842 | 372 | if (ret) |
6269e9f7 | 373 | goto error_unregister; |
6269e9f7 | 374 | |
e380ea81 JW |
375 | ret = of_thermal_get_ntrips(tsc->zone); |
376 | if (ret < 0) | |
377 | goto error_unregister; | |
378 | ||
7d4b2697 | 379 | dev_info(dev, "TSC%d: Loaded %d trip points\n", i, ret); |
564e73d2 WS |
380 | } |
381 | ||
97dad1f1 NS |
382 | priv->num_tscs = i; |
383 | ||
384 | if (!priv->num_tscs) { | |
385 | ret = -ENODEV; | |
386 | goto error_unregister; | |
387 | } | |
388 | ||
564e73d2 WS |
389 | return 0; |
390 | ||
391 | error_unregister: | |
392 | rcar_gen3_thermal_remove(pdev); | |
393 | ||
394 | return ret; | |
395 | } | |
396 | ||
75f78d6d NS |
397 | static int __maybe_unused rcar_gen3_thermal_resume(struct device *dev) |
398 | { | |
399 | struct rcar_gen3_thermal_priv *priv = dev_get_drvdata(dev); | |
400 | unsigned int i; | |
401 | ||
402 | for (i = 0; i < priv->num_tscs; i++) { | |
403 | struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i]; | |
404 | ||
d668c807 | 405 | priv->thermal_init(tsc); |
75f78d6d NS |
406 | } |
407 | ||
75f78d6d NS |
408 | return 0; |
409 | } | |
410 | ||
1b57b959 | 411 | static SIMPLE_DEV_PM_OPS(rcar_gen3_thermal_pm_ops, NULL, |
75f78d6d NS |
412 | rcar_gen3_thermal_resume); |
413 | ||
564e73d2 WS |
414 | static struct platform_driver rcar_gen3_thermal_driver = { |
415 | .driver = { | |
416 | .name = "rcar_gen3_thermal", | |
75f78d6d | 417 | .pm = &rcar_gen3_thermal_pm_ops, |
564e73d2 WS |
418 | .of_match_table = rcar_gen3_thermal_dt_ids, |
419 | }, | |
420 | .probe = rcar_gen3_thermal_probe, | |
421 | .remove = rcar_gen3_thermal_remove, | |
422 | }; | |
423 | module_platform_driver(rcar_gen3_thermal_driver); | |
424 | ||
425 | MODULE_LICENSE("GPL v2"); | |
426 | MODULE_DESCRIPTION("R-Car Gen3 THS thermal sensor driver"); | |
427 | MODULE_AUTHOR("Wolfram Sang <wsa+renesas@sang-engineering.com>"); |