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d316522d | 1 | // SPDX-License-Identifier: GPL-2.0 |
564e73d2 WS |
2 | /* |
3 | * R-Car Gen3 THS thermal sensor driver | |
4 | * Based on rcar_thermal.c and work from Hien Dang and Khiem Nguyen. | |
5 | * | |
6 | * Copyright (C) 2016 Renesas Electronics Corporation. | |
7 | * Copyright (C) 2016 Sang Engineering | |
564e73d2 WS |
8 | */ |
9 | #include <linux/delay.h> | |
10 | #include <linux/err.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/module.h> | |
564e73d2 WS |
14 | #include <linux/of_device.h> |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/pm_runtime.h> | |
d668c807 | 17 | #include <linux/sys_soc.h> |
564e73d2 WS |
18 | #include <linux/thermal.h> |
19 | ||
6269e9f7 | 20 | #include "thermal_hwmon.h" |
7d4b2697 | 21 | |
564e73d2 WS |
22 | /* Register offsets */ |
23 | #define REG_GEN3_IRQSTR 0x04 | |
24 | #define REG_GEN3_IRQMSK 0x08 | |
25 | #define REG_GEN3_IRQCTL 0x0C | |
26 | #define REG_GEN3_IRQEN 0x10 | |
27 | #define REG_GEN3_IRQTEMP1 0x14 | |
28 | #define REG_GEN3_IRQTEMP2 0x18 | |
29 | #define REG_GEN3_IRQTEMP3 0x1C | |
30 | #define REG_GEN3_CTSR 0x20 | |
31 | #define REG_GEN3_THCTR 0x20 | |
32 | #define REG_GEN3_TEMP 0x28 | |
33 | #define REG_GEN3_THCODE1 0x50 | |
34 | #define REG_GEN3_THCODE2 0x54 | |
35 | #define REG_GEN3_THCODE3 0x58 | |
c3131bd5 NS |
36 | #define REG_GEN3_PTAT1 0x5c |
37 | #define REG_GEN3_PTAT2 0x60 | |
38 | #define REG_GEN3_PTAT3 0x64 | |
39 | #define REG_GEN3_THSCP 0x68 | |
564e73d2 | 40 | |
7d4b2697 NS |
41 | /* IRQ{STR,MSK,EN} bits */ |
42 | #define IRQ_TEMP1 BIT(0) | |
43 | #define IRQ_TEMP2 BIT(1) | |
44 | #define IRQ_TEMP3 BIT(2) | |
45 | #define IRQ_TEMPD1 BIT(3) | |
46 | #define IRQ_TEMPD2 BIT(4) | |
47 | #define IRQ_TEMPD3 BIT(5) | |
48 | ||
564e73d2 WS |
49 | /* CTSR bits */ |
50 | #define CTSR_PONM BIT(8) | |
51 | #define CTSR_AOUT BIT(7) | |
52 | #define CTSR_THBGR BIT(5) | |
53 | #define CTSR_VMEN BIT(4) | |
54 | #define CTSR_VMST BIT(1) | |
55 | #define CTSR_THSST BIT(0) | |
56 | ||
57 | /* THCTR bits */ | |
58 | #define THCTR_PONM BIT(6) | |
59 | #define THCTR_THSST BIT(0) | |
60 | ||
c3131bd5 NS |
61 | /* THSCP bits */ |
62 | #define THSCP_COR_PARA_VLD (BIT(15) | BIT(14)) | |
63 | ||
564e73d2 WS |
64 | #define CTEMP_MASK 0xFFF |
65 | ||
66 | #define MCELSIUS(temp) ((temp) * 1000) | |
67 | #define GEN3_FUSE_MASK 0xFFF | |
68 | ||
7fd49ca0 | 69 | #define TSC_MAX_NUM 5 |
564e73d2 WS |
70 | |
71 | /* Structure for thermal temperature calculation */ | |
72 | struct equation_coefs { | |
73 | int a1; | |
74 | int b1; | |
75 | int a2; | |
76 | int b2; | |
77 | }; | |
78 | ||
79 | struct rcar_gen3_thermal_tsc { | |
80 | void __iomem *base; | |
81 | struct thermal_zone_device *zone; | |
82 | struct equation_coefs coef; | |
bdc4480a | 83 | int tj_t; |
b8aaf141 | 84 | int thcode[3]; |
564e73d2 WS |
85 | }; |
86 | ||
87 | struct rcar_gen3_thermal_priv { | |
88 | struct rcar_gen3_thermal_tsc *tscs[TSC_MAX_NUM]; | |
aef43e04 | 89 | struct thermal_zone_device_ops ops; |
97dad1f1 | 90 | unsigned int num_tscs; |
47b2d3d2 NS |
91 | void (*thermal_init)(struct rcar_gen3_thermal_priv *priv, |
92 | struct rcar_gen3_thermal_tsc *tsc); | |
b8aaf141 | 93 | int ptat[3]; |
564e73d2 WS |
94 | }; |
95 | ||
96 | static inline u32 rcar_gen3_thermal_read(struct rcar_gen3_thermal_tsc *tsc, | |
97 | u32 reg) | |
98 | { | |
99 | return ioread32(tsc->base + reg); | |
100 | } | |
101 | ||
102 | static inline void rcar_gen3_thermal_write(struct rcar_gen3_thermal_tsc *tsc, | |
103 | u32 reg, u32 data) | |
104 | { | |
105 | iowrite32(data, tsc->base + reg); | |
106 | } | |
107 | ||
108 | /* | |
109 | * Linear approximation for temperature | |
110 | * | |
111 | * [reg] = [temp] * a + b => [temp] = ([reg] - b) / a | |
112 | * | |
113 | * The constants a and b are calculated using two triplets of int values PTAT | |
114 | * and THCODE. PTAT and THCODE can either be read from hardware or use hard | |
115 | * coded values from driver. The formula to calculate a and b are taken from | |
116 | * BSP and sparsely documented and understood. | |
117 | * | |
118 | * Examining the linear formula and the formula used to calculate constants a | |
119 | * and b while knowing that the span for PTAT and THCODE values are between | |
120 | * 0x000 and 0xfff the largest integer possible is 0xfff * 0xfff == 0xffe001. | |
121 | * Integer also needs to be signed so that leaves 7 bits for binary | |
122 | * fixed point scaling. | |
123 | */ | |
124 | ||
125 | #define FIXPT_SHIFT 7 | |
126 | #define FIXPT_INT(_x) ((_x) << FIXPT_SHIFT) | |
7d4b2697 | 127 | #define INT_FIXPT(_x) ((_x) >> FIXPT_SHIFT) |
564e73d2 WS |
128 | #define FIXPT_DIV(_a, _b) DIV_ROUND_CLOSEST(((_a) << FIXPT_SHIFT), (_b)) |
129 | #define FIXPT_TO_MCELSIUS(_x) ((_x) * 1000 >> FIXPT_SHIFT) | |
130 | ||
131 | #define RCAR3_THERMAL_GRAN 500 /* mili Celsius */ | |
132 | ||
133 | /* no idea where these constants come from */ | |
564e73d2 WS |
134 | #define TJ_3 -41 |
135 | ||
b8aaf141 NS |
136 | static void rcar_gen3_thermal_calc_coefs(struct rcar_gen3_thermal_priv *priv, |
137 | struct rcar_gen3_thermal_tsc *tsc, | |
4eb39f79 | 138 | int ths_tj_1) |
564e73d2 | 139 | { |
564e73d2 WS |
140 | /* TODO: Find documentation and document constant calculation formula */ |
141 | ||
142 | /* | |
143 | * Division is not scaled in BSP and if scaled it might overflow | |
144 | * the dividend (4095 * 4095 << 14 > INT_MAX) so keep it unscaled | |
145 | */ | |
b8aaf141 NS |
146 | tsc->tj_t = (FIXPT_INT((priv->ptat[1] - priv->ptat[2]) * (ths_tj_1 - TJ_3)) |
147 | / (priv->ptat[0] - priv->ptat[2])) + FIXPT_INT(TJ_3); | |
564e73d2 | 148 | |
b8aaf141 | 149 | tsc->coef.a1 = FIXPT_DIV(FIXPT_INT(tsc->thcode[1] - tsc->thcode[2]), |
bdc4480a | 150 | tsc->tj_t - FIXPT_INT(TJ_3)); |
b8aaf141 | 151 | tsc->coef.b1 = FIXPT_INT(tsc->thcode[2]) - tsc->coef.a1 * TJ_3; |
564e73d2 | 152 | |
b8aaf141 | 153 | tsc->coef.a2 = FIXPT_DIV(FIXPT_INT(tsc->thcode[1] - tsc->thcode[0]), |
bdc4480a | 154 | tsc->tj_t - FIXPT_INT(ths_tj_1)); |
b8aaf141 | 155 | tsc->coef.b2 = FIXPT_INT(tsc->thcode[0]) - tsc->coef.a2 * ths_tj_1; |
564e73d2 WS |
156 | } |
157 | ||
158 | static int rcar_gen3_thermal_round(int temp) | |
159 | { | |
160 | int result, round_offs; | |
161 | ||
162 | round_offs = temp >= 0 ? RCAR3_THERMAL_GRAN / 2 : | |
163 | -RCAR3_THERMAL_GRAN / 2; | |
164 | result = (temp + round_offs) / RCAR3_THERMAL_GRAN; | |
165 | return result * RCAR3_THERMAL_GRAN; | |
166 | } | |
167 | ||
2ebd4f2f | 168 | static int rcar_gen3_thermal_get_temp(struct thermal_zone_device *tz, int *temp) |
564e73d2 | 169 | { |
5f68d078 | 170 | struct rcar_gen3_thermal_tsc *tsc = thermal_zone_device_priv(tz); |
6a310f8f | 171 | int mcelsius, val; |
5f8f0642 | 172 | int reg; |
564e73d2 WS |
173 | |
174 | /* Read register and convert to mili Celsius */ | |
564e73d2 WS |
175 | reg = rcar_gen3_thermal_read(tsc, REG_GEN3_TEMP) & CTEMP_MASK; |
176 | ||
b8aaf141 | 177 | if (reg <= tsc->thcode[1]) |
6a310f8f YK |
178 | val = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b1, |
179 | tsc->coef.a1); | |
180 | else | |
181 | val = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b2, | |
182 | tsc->coef.a2); | |
183 | mcelsius = FIXPT_TO_MCELSIUS(val); | |
564e73d2 | 184 | |
0f510a24 | 185 | /* Guaranteed operating range is -40C to 125C. */ |
564e73d2 WS |
186 | |
187 | /* Round value to device granularity setting */ | |
188 | *temp = rcar_gen3_thermal_round(mcelsius); | |
189 | ||
190 | return 0; | |
191 | } | |
192 | ||
47cf09e0 NS |
193 | static int rcar_gen3_thermal_mcelsius_to_temp(struct rcar_gen3_thermal_tsc *tsc, |
194 | int mcelsius) | |
195 | { | |
196 | int celsius, val; | |
197 | ||
198 | celsius = DIV_ROUND_CLOSEST(mcelsius, 1000); | |
199 | if (celsius <= INT_FIXPT(tsc->tj_t)) | |
200 | val = celsius * tsc->coef.a1 + tsc->coef.b1; | |
201 | else | |
202 | val = celsius * tsc->coef.a2 + tsc->coef.b2; | |
203 | ||
204 | return INT_FIXPT(val); | |
205 | } | |
206 | ||
2ebd4f2f | 207 | static int rcar_gen3_thermal_set_trips(struct thermal_zone_device *tz, int low, int high) |
47cf09e0 | 208 | { |
5f68d078 | 209 | struct rcar_gen3_thermal_tsc *tsc = thermal_zone_device_priv(tz); |
47cf09e0 NS |
210 | u32 irqmsk = 0; |
211 | ||
212 | if (low != -INT_MAX) { | |
213 | irqmsk |= IRQ_TEMPD1; | |
214 | rcar_gen3_thermal_write(tsc, REG_GEN3_IRQTEMP1, | |
215 | rcar_gen3_thermal_mcelsius_to_temp(tsc, low)); | |
216 | } | |
217 | ||
218 | if (high != INT_MAX) { | |
219 | irqmsk |= IRQ_TEMP2; | |
220 | rcar_gen3_thermal_write(tsc, REG_GEN3_IRQTEMP2, | |
221 | rcar_gen3_thermal_mcelsius_to_temp(tsc, high)); | |
222 | } | |
223 | ||
224 | rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, irqmsk); | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
aef43e04 | 229 | static const struct thermal_zone_device_ops rcar_gen3_tz_of_ops = { |
564e73d2 | 230 | .get_temp = rcar_gen3_thermal_get_temp, |
47cf09e0 | 231 | .set_trips = rcar_gen3_thermal_set_trips, |
564e73d2 WS |
232 | }; |
233 | ||
47cf09e0 NS |
234 | static irqreturn_t rcar_gen3_thermal_irq(int irq, void *data) |
235 | { | |
236 | struct rcar_gen3_thermal_priv *priv = data; | |
237 | unsigned int i; | |
238 | u32 status; | |
239 | ||
240 | for (i = 0; i < priv->num_tscs; i++) { | |
241 | status = rcar_gen3_thermal_read(priv->tscs[i], REG_GEN3_IRQSTR); | |
242 | rcar_gen3_thermal_write(priv->tscs[i], REG_GEN3_IRQSTR, 0); | |
47b2d3d2 | 243 | if (status && priv->tscs[i]->zone) |
47cf09e0 NS |
244 | thermal_zone_device_update(priv->tscs[i]->zone, |
245 | THERMAL_EVENT_UNSPECIFIED); | |
246 | } | |
247 | ||
248 | return IRQ_HANDLED; | |
249 | } | |
250 | ||
d668c807 NS |
251 | static const struct soc_device_attribute r8a7795es1[] = { |
252 | { .soc_id = "r8a7795", .revision = "ES1.*" }, | |
253 | { /* sentinel */ } | |
254 | }; | |
255 | ||
c3131bd5 NS |
256 | static bool rcar_gen3_thermal_read_fuses(struct rcar_gen3_thermal_priv *priv) |
257 | { | |
258 | unsigned int i; | |
259 | u32 thscp; | |
260 | ||
261 | /* If fuses are not set, fallback to pseudo values. */ | |
262 | thscp = rcar_gen3_thermal_read(priv->tscs[0], REG_GEN3_THSCP); | |
263 | if ((thscp & THSCP_COR_PARA_VLD) != THSCP_COR_PARA_VLD) { | |
264 | /* Default THCODE values in case FUSEs are not set. */ | |
265 | static const int thcodes[TSC_MAX_NUM][3] = { | |
266 | { 3397, 2800, 2221 }, | |
267 | { 3393, 2795, 2216 }, | |
268 | { 3389, 2805, 2237 }, | |
269 | { 3415, 2694, 2195 }, | |
270 | { 3356, 2724, 2244 }, | |
271 | }; | |
272 | ||
273 | priv->ptat[0] = 2631; | |
274 | priv->ptat[1] = 1509; | |
275 | priv->ptat[2] = 435; | |
276 | ||
277 | for (i = 0; i < priv->num_tscs; i++) { | |
278 | struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i]; | |
279 | ||
280 | tsc->thcode[0] = thcodes[i][0]; | |
281 | tsc->thcode[1] = thcodes[i][1]; | |
282 | tsc->thcode[2] = thcodes[i][2]; | |
283 | } | |
284 | ||
285 | return false; | |
286 | } | |
287 | ||
288 | /* | |
289 | * Set the pseudo calibration points with fused values. | |
290 | * PTAT is shared between all TSCs but only fused for the first | |
291 | * TSC while THCODEs are fused for each TSC. | |
292 | */ | |
293 | priv->ptat[0] = rcar_gen3_thermal_read(priv->tscs[0], REG_GEN3_PTAT1) & | |
294 | GEN3_FUSE_MASK; | |
295 | priv->ptat[1] = rcar_gen3_thermal_read(priv->tscs[0], REG_GEN3_PTAT2) & | |
296 | GEN3_FUSE_MASK; | |
297 | priv->ptat[2] = rcar_gen3_thermal_read(priv->tscs[0], REG_GEN3_PTAT3) & | |
298 | GEN3_FUSE_MASK; | |
299 | ||
300 | for (i = 0; i < priv->num_tscs; i++) { | |
301 | struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i]; | |
302 | ||
303 | tsc->thcode[0] = rcar_gen3_thermal_read(tsc, REG_GEN3_THCODE1) & | |
304 | GEN3_FUSE_MASK; | |
305 | tsc->thcode[1] = rcar_gen3_thermal_read(tsc, REG_GEN3_THCODE2) & | |
306 | GEN3_FUSE_MASK; | |
307 | tsc->thcode[2] = rcar_gen3_thermal_read(tsc, REG_GEN3_THCODE3) & | |
308 | GEN3_FUSE_MASK; | |
309 | } | |
310 | ||
311 | return true; | |
312 | } | |
313 | ||
47b2d3d2 NS |
314 | static void rcar_gen3_thermal_init_r8a7795es1(struct rcar_gen3_thermal_priv *priv, |
315 | struct rcar_gen3_thermal_tsc *tsc) | |
564e73d2 WS |
316 | { |
317 | rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR, CTSR_THBGR); | |
318 | rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR, 0x0); | |
319 | ||
320 | usleep_range(1000, 2000); | |
321 | ||
322 | rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR, CTSR_PONM); | |
7d4b2697 | 323 | |
564e73d2 | 324 | rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0x3F); |
7d4b2697 | 325 | rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0); |
47b2d3d2 | 326 | if (priv->ops.set_trips) |
47cf09e0 NS |
327 | rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, |
328 | IRQ_TEMPD1 | IRQ_TEMP2); | |
7d4b2697 | 329 | |
564e73d2 WS |
330 | rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR, |
331 | CTSR_PONM | CTSR_AOUT | CTSR_THBGR | CTSR_VMEN); | |
332 | ||
333 | usleep_range(100, 200); | |
334 | ||
335 | rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR, | |
336 | CTSR_PONM | CTSR_AOUT | CTSR_THBGR | CTSR_VMEN | | |
337 | CTSR_VMST | CTSR_THSST); | |
338 | ||
339 | usleep_range(1000, 2000); | |
340 | } | |
341 | ||
47b2d3d2 NS |
342 | static void rcar_gen3_thermal_init(struct rcar_gen3_thermal_priv *priv, |
343 | struct rcar_gen3_thermal_tsc *tsc) | |
564e73d2 WS |
344 | { |
345 | u32 reg_val; | |
346 | ||
347 | reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR); | |
348 | reg_val &= ~THCTR_PONM; | |
349 | rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val); | |
350 | ||
351 | usleep_range(1000, 2000); | |
352 | ||
ed1b1ac1 | 353 | rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0); |
7d4b2697 | 354 | rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0); |
47b2d3d2 | 355 | if (priv->ops.set_trips) |
47cf09e0 NS |
356 | rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, |
357 | IRQ_TEMPD1 | IRQ_TEMP2); | |
7d4b2697 | 358 | |
564e73d2 WS |
359 | reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR); |
360 | reg_val |= THCTR_THSST; | |
361 | rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val); | |
78aefd2d NS |
362 | |
363 | usleep_range(1000, 2000); | |
564e73d2 WS |
364 | } |
365 | ||
4eb39f79 YK |
366 | static const int rcar_gen3_ths_tj_1 = 126; |
367 | static const int rcar_gen3_ths_tj_1_m3_w = 116; | |
564e73d2 | 368 | static const struct of_device_id rcar_gen3_thermal_dt_ids[] = { |
4eb39f79 YK |
369 | { |
370 | .compatible = "renesas,r8a774a1-thermal", | |
371 | .data = &rcar_gen3_ths_tj_1_m3_w, | |
372 | }, | |
1a005912 BD |
373 | { |
374 | .compatible = "renesas,r8a774b1-thermal", | |
375 | .data = &rcar_gen3_ths_tj_1, | |
376 | }, | |
947d85f0 MCR |
377 | { |
378 | .compatible = "renesas,r8a774e1-thermal", | |
379 | .data = &rcar_gen3_ths_tj_1, | |
380 | }, | |
4eb39f79 YK |
381 | { |
382 | .compatible = "renesas,r8a7795-thermal", | |
383 | .data = &rcar_gen3_ths_tj_1, | |
384 | }, | |
385 | { | |
386 | .compatible = "renesas,r8a7796-thermal", | |
387 | .data = &rcar_gen3_ths_tj_1_m3_w, | |
388 | }, | |
8d74bf79 GU |
389 | { |
390 | .compatible = "renesas,r8a77961-thermal", | |
391 | .data = &rcar_gen3_ths_tj_1_m3_w, | |
392 | }, | |
4eb39f79 YK |
393 | { |
394 | .compatible = "renesas,r8a77965-thermal", | |
395 | .data = &rcar_gen3_ths_tj_1, | |
396 | }, | |
397 | { | |
398 | .compatible = "renesas,r8a77980-thermal", | |
399 | .data = &rcar_gen3_ths_tj_1, | |
400 | }, | |
e854da4f NS |
401 | { |
402 | .compatible = "renesas,r8a779a0-thermal", | |
403 | .data = &rcar_gen3_ths_tj_1, | |
404 | }, | |
5b2ca9bc WS |
405 | { |
406 | .compatible = "renesas,r8a779f0-thermal", | |
407 | .data = &rcar_gen3_ths_tj_1, | |
408 | }, | |
883d1552 GU |
409 | { |
410 | .compatible = "renesas,r8a779g0-thermal", | |
411 | .data = &rcar_gen3_ths_tj_1, | |
412 | }, | |
564e73d2 WS |
413 | {}, |
414 | }; | |
415 | MODULE_DEVICE_TABLE(of, rcar_gen3_thermal_dt_ids); | |
416 | ||
417 | static int rcar_gen3_thermal_remove(struct platform_device *pdev) | |
418 | { | |
419 | struct device *dev = &pdev->dev; | |
420 | ||
421 | pm_runtime_put(dev); | |
422 | pm_runtime_disable(dev); | |
423 | ||
424 | return 0; | |
425 | } | |
426 | ||
6269e9f7 MV |
427 | static void rcar_gen3_hwmon_action(void *data) |
428 | { | |
429 | struct thermal_zone_device *zone = data; | |
430 | ||
431 | thermal_remove_hwmon_sysfs(zone); | |
432 | } | |
433 | ||
47cf09e0 NS |
434 | static int rcar_gen3_thermal_request_irqs(struct rcar_gen3_thermal_priv *priv, |
435 | struct platform_device *pdev) | |
436 | { | |
437 | struct device *dev = &pdev->dev; | |
438 | unsigned int i; | |
439 | char *irqname; | |
440 | int ret, irq; | |
441 | ||
442 | for (i = 0; i < 2; i++) { | |
443 | irq = platform_get_irq_optional(pdev, i); | |
444 | if (irq < 0) | |
445 | return irq; | |
446 | ||
447 | irqname = devm_kasprintf(dev, GFP_KERNEL, "%s:ch%d", | |
448 | dev_name(dev), i); | |
449 | if (!irqname) | |
450 | return -ENOMEM; | |
451 | ||
452 | ret = devm_request_threaded_irq(dev, irq, NULL, | |
453 | rcar_gen3_thermal_irq, | |
454 | IRQF_ONESHOT, irqname, priv); | |
455 | if (ret) | |
456 | return ret; | |
457 | } | |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
564e73d2 WS |
462 | static int rcar_gen3_thermal_probe(struct platform_device *pdev) |
463 | { | |
464 | struct rcar_gen3_thermal_priv *priv; | |
465 | struct device *dev = &pdev->dev; | |
3ae5950d | 466 | const int *ths_tj_1 = of_device_get_match_data(dev); |
564e73d2 WS |
467 | struct resource *res; |
468 | struct thermal_zone_device *zone; | |
d3a2328e NS |
469 | unsigned int i; |
470 | int ret; | |
564e73d2 | 471 | |
564e73d2 WS |
472 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
473 | if (!priv) | |
474 | return -ENOMEM; | |
475 | ||
aef43e04 | 476 | priv->ops = rcar_gen3_tz_of_ops; |
d668c807 NS |
477 | priv->thermal_init = rcar_gen3_thermal_init; |
478 | if (soc_device_match(r8a7795es1)) | |
479 | priv->thermal_init = rcar_gen3_thermal_init_r8a7795es1; | |
cc4d072b | 480 | |
564e73d2 WS |
481 | platform_set_drvdata(pdev, priv); |
482 | ||
47cf09e0 | 483 | if (rcar_gen3_thermal_request_irqs(priv, pdev)) |
aef43e04 | 484 | priv->ops.set_trips = NULL; |
47cf09e0 | 485 | |
564e73d2 WS |
486 | pm_runtime_enable(dev); |
487 | pm_runtime_get_sync(dev); | |
488 | ||
489 | for (i = 0; i < TSC_MAX_NUM; i++) { | |
490 | struct rcar_gen3_thermal_tsc *tsc; | |
491 | ||
d51546c0 NS |
492 | res = platform_get_resource(pdev, IORESOURCE_MEM, i); |
493 | if (!res) | |
494 | break; | |
495 | ||
564e73d2 WS |
496 | tsc = devm_kzalloc(dev, sizeof(*tsc), GFP_KERNEL); |
497 | if (!tsc) { | |
498 | ret = -ENOMEM; | |
499 | goto error_unregister; | |
500 | } | |
501 | ||
564e73d2 WS |
502 | tsc->base = devm_ioremap_resource(dev, res); |
503 | if (IS_ERR(tsc->base)) { | |
504 | ret = PTR_ERR(tsc->base); | |
505 | goto error_unregister; | |
506 | } | |
b8aaf141 | 507 | |
564e73d2 | 508 | priv->tscs[i] = tsc; |
c3131bd5 NS |
509 | } |
510 | ||
511 | priv->num_tscs = i; | |
512 | ||
513 | if (!rcar_gen3_thermal_read_fuses(priv)) | |
514 | dev_info(dev, "No calibration values fused, fallback to driver values\n"); | |
515 | ||
516 | for (i = 0; i < priv->num_tscs; i++) { | |
517 | struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i]; | |
564e73d2 | 518 | |
47b2d3d2 NS |
519 | priv->thermal_init(priv, tsc); |
520 | rcar_gen3_thermal_calc_coefs(priv, tsc, *ths_tj_1); | |
521 | ||
aef43e04 | 522 | zone = devm_thermal_of_zone_register(dev, i, tsc, &priv->ops); |
564e73d2 | 523 | if (IS_ERR(zone)) { |
404dd7df | 524 | dev_err(dev, "Sensor %u: Can't register thermal zone\n", i); |
564e73d2 WS |
525 | ret = PTR_ERR(zone); |
526 | goto error_unregister; | |
527 | } | |
528 | tsc->zone = zone; | |
7d4b2697 | 529 | |
6269e9f7 MV |
530 | tsc->zone->tzp->no_hwmon = false; |
531 | ret = thermal_add_hwmon_sysfs(tsc->zone); | |
532 | if (ret) | |
533 | goto error_unregister; | |
534 | ||
b9cd1663 | 535 | ret = devm_add_action_or_reset(dev, rcar_gen3_hwmon_action, zone); |
d543c842 | 536 | if (ret) |
6269e9f7 | 537 | goto error_unregister; |
6269e9f7 | 538 | |
d5299c1b | 539 | ret = thermal_zone_get_num_trips(tsc->zone); |
e380ea81 JW |
540 | if (ret < 0) |
541 | goto error_unregister; | |
542 | ||
404dd7df | 543 | dev_info(dev, "Sensor %u: Loaded %d trip points\n", i, ret); |
564e73d2 WS |
544 | } |
545 | ||
97dad1f1 NS |
546 | if (!priv->num_tscs) { |
547 | ret = -ENODEV; | |
548 | goto error_unregister; | |
549 | } | |
550 | ||
564e73d2 WS |
551 | return 0; |
552 | ||
553 | error_unregister: | |
554 | rcar_gen3_thermal_remove(pdev); | |
555 | ||
556 | return ret; | |
557 | } | |
558 | ||
75f78d6d NS |
559 | static int __maybe_unused rcar_gen3_thermal_resume(struct device *dev) |
560 | { | |
561 | struct rcar_gen3_thermal_priv *priv = dev_get_drvdata(dev); | |
562 | unsigned int i; | |
563 | ||
564 | for (i = 0; i < priv->num_tscs; i++) { | |
565 | struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i]; | |
566 | ||
47b2d3d2 | 567 | priv->thermal_init(priv, tsc); |
75f78d6d NS |
568 | } |
569 | ||
75f78d6d NS |
570 | return 0; |
571 | } | |
572 | ||
1b57b959 | 573 | static SIMPLE_DEV_PM_OPS(rcar_gen3_thermal_pm_ops, NULL, |
75f78d6d NS |
574 | rcar_gen3_thermal_resume); |
575 | ||
564e73d2 WS |
576 | static struct platform_driver rcar_gen3_thermal_driver = { |
577 | .driver = { | |
578 | .name = "rcar_gen3_thermal", | |
75f78d6d | 579 | .pm = &rcar_gen3_thermal_pm_ops, |
564e73d2 WS |
580 | .of_match_table = rcar_gen3_thermal_dt_ids, |
581 | }, | |
582 | .probe = rcar_gen3_thermal_probe, | |
583 | .remove = rcar_gen3_thermal_remove, | |
584 | }; | |
585 | module_platform_driver(rcar_gen3_thermal_driver); | |
586 | ||
587 | MODULE_LICENSE("GPL v2"); | |
588 | MODULE_DESCRIPTION("R-Car Gen3 THS thermal sensor driver"); | |
589 | MODULE_AUTHOR("Wolfram Sang <wsa+renesas@sang-engineering.com>"); |