[linux-block.git] / drivers / thermal / qoriq_thermal.c

// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2016 Freescale Semiconductor, Inc.

#include <linux/clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/sizes.h>
#include <linux/thermal.h>

#include "thermal_core.h"
#include "thermal_hwmon.h"

#define SITES_MAX		16
#define TMR_DISABLE		0x0
#define TMR_ME			0x80000000
#define TMR_ALPF		0x0c000000
#define TMR_ALPF_V2		0x03000000
#define TMTMIR_DEFAULT	0x0000000f
#define TIER_DISABLE	0x0
#define TEUMR0_V2		0x51009c00
#define TMU_VER1		0x1
#define TMU_VER2		0x2

#define REGS_TMR	0x000	/* Mode Register */
#define TMR_DISABLE	0x0
#define TMR_ME		0x80000000
#define TMR_ALPF	0x0c000000
#define TMR_MSITE_ALL	GENMASK(15, 0)

#define REGS_TMTMIR	0x008	/* Temperature measurement interval Register */
#define TMTMIR_DEFAULT	0x0000000f

#define REGS_V2_TMSR	0x008	/* monitor site register */

#define REGS_V2_TMTMIR	0x00c	/* Temperature measurement interval Register */

#define REGS_TIER	0x020	/* Interrupt Enable Register */
#define TIER_DISABLE	0x0


#define REGS_TTCFGR	0x080	/* Temperature Configuration Register */
#define REGS_TSCFGR	0x084	/* Sensor Configuration Register */

#define REGS_TRITSR(n)	(0x100 + 16 * (n)) /* Immediate Temperature
					    * Site Register
					    */
#define TRITSR_V	BIT(31)
#define REGS_TTRnCR(n)	(0xf10 + 4 * (n)) /* Temperature Range n
					   * Control Register
					   */
#define REGS_IPBRR(n)		(0xbf8 + 4 * (n)) /* IP Block Revision
						   * Register n
						   */
#define REGS_V2_TEUMR(n)	(0xf00 + 4 * (n))

/*
 * Thermal zone data
 */
struct qoriq_sensor {
	int				id;
};

struct qoriq_tmu_data {
	int ver;
	struct regmap *regmap;
	struct clk *clk;
	struct qoriq_sensor	sensor[SITES_MAX];
};

static struct qoriq_tmu_data *qoriq_sensor_to_data(struct qoriq_sensor *s)
{
	return container_of(s, struct qoriq_tmu_data, sensor[s->id]);
}

static int tmu_get_temp(void *p, int *temp)
{
	struct qoriq_sensor *qsensor = p;
	struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor);
	u32 val;
	/*
	 * REGS_TRITSR(id) has the following layout:
	 *
	 * 31  ... 7 6 5 4 3 2 1 0
	 *  V          TEMP
	 *
	 * Where V bit signifies if the measurement is ready and is
	 * within sensor range. TEMP is an 8 bit value representing
	 * temperature in C.
	 */
	if (regmap_read_poll_timeout(qdata->regmap,
				     REGS_TRITSR(qsensor->id),
				     val,
				     val & TRITSR_V,
				     USEC_PER_MSEC,
				     10 * USEC_PER_MSEC))
		return -ENODATA;

	*temp = (val & 0xff) * 1000;

	return 0;
}

static const struct thermal_zone_of_device_ops tmu_tz_ops = {
	.get_temp = tmu_get_temp,
};

static int qoriq_tmu_register_tmu_zone(struct device *dev,
				       struct qoriq_tmu_data *qdata)
{
	int id;

	if (qdata->ver == TMU_VER1) {
		regmap_write(qdata->regmap, REGS_TMR,
			     TMR_MSITE_ALL | TMR_ME | TMR_ALPF);
	} else {
		regmap_write(qdata->regmap, REGS_V2_TMSR, TMR_MSITE_ALL);
		regmap_write(qdata->regmap, REGS_TMR, TMR_ME | TMR_ALPF_V2);
	}

	for (id = 0; id < SITES_MAX; id++) {
		struct thermal_zone_device *tzd;
		struct qoriq_sensor *sensor = &qdata->sensor[id];
		int ret;

		sensor->id = id;

		tzd = devm_thermal_zone_of_sensor_register(dev, id,
							   sensor,
							   &tmu_tz_ops);
		ret = PTR_ERR_OR_ZERO(tzd);
		if (ret) {
			if (ret == -ENODEV)
				continue;

			regmap_write(qdata->regmap, REGS_TMR, TMR_DISABLE);
			return ret;
		}

		if (devm_thermal_add_hwmon_sysfs(tzd))
			dev_warn(dev,
				 "Failed to add hwmon sysfs attributes\n");

	}

	return 0;
}

static int qoriq_tmu_calibration(struct device *dev,
				 struct qoriq_tmu_data *data)
{
	int i, val, len;
	u32 range[4];
	const u32 *calibration;
	struct device_node *np = dev->of_node;

	len = of_property_count_u32_elems(np, "fsl,tmu-range");
	if (len < 0 || len > 4) {
		dev_err(dev, "invalid range data.\n");
		return len;
	}

	val = of_property_read_u32_array(np, "fsl,tmu-range", range, len);
	if (val != 0) {
		dev_err(dev, "failed to read range data.\n");
		return val;
	}

	/* Init temperature range registers */
	for (i = 0; i < len; i++)
		regmap_write(data->regmap, REGS_TTRnCR(i), range[i]);

	calibration = of_get_property(np, "fsl,tmu-calibration", &len);
	if (calibration == NULL || len % 8) {
		dev_err(dev, "invalid calibration data.\n");
		return -ENODEV;
	}

	for (i = 0; i < len; i += 8, calibration += 2) {
		val = of_read_number(calibration, 1);
		regmap_write(data->regmap, REGS_TTCFGR, val);
		val = of_read_number(calibration + 1, 1);
		regmap_write(data->regmap, REGS_TSCFGR, val);
	}

	return 0;
}

static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
{
	/* Disable interrupt, using polling instead */
	regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);

	/* Set update_interval */

	if (data->ver == TMU_VER1) {
		regmap_write(data->regmap, REGS_TMTMIR, TMTMIR_DEFAULT);
	} else {
		regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT);
		regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2);
	}

	/* Disable monitoring */
	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
}

static const struct regmap_range qoriq_yes_ranges[] = {
	regmap_reg_range(REGS_TMR, REGS_TSCFGR),
	regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(3)),
	regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
	regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
	/* Read only registers below */
	regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
};

static const struct regmap_access_table qoriq_wr_table = {
	.yes_ranges	= qoriq_yes_ranges,
	.n_yes_ranges	= ARRAY_SIZE(qoriq_yes_ranges) - 1,
};

static const struct regmap_access_table qoriq_rd_table = {
	.yes_ranges	= qoriq_yes_ranges,
	.n_yes_ranges	= ARRAY_SIZE(qoriq_yes_ranges),
};

static void qoriq_tmu_action(void *p)
{
	struct qoriq_tmu_data *data = p;

	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
	clk_disable_unprepare(data->clk);
}

static int qoriq_tmu_probe(struct platform_device *pdev)
{
	int ret;
	u32 ver;
	struct qoriq_tmu_data *data;
	struct device_node *np = pdev->dev.of_node;
	struct device *dev = &pdev->dev;
	const bool little_endian = of_property_read_bool(np, "little-endian");
	const enum regmap_endian format_endian =
		little_endian ? REGMAP_ENDIAN_LITTLE : REGMAP_ENDIAN_BIG;
	const struct regmap_config regmap_config = {
		.reg_bits		= 32,
		.val_bits		= 32,
		.reg_stride		= 4,
		.rd_table		= &qoriq_rd_table,
		.wr_table		= &qoriq_wr_table,
		.val_format_endian	= format_endian,
		.max_register		= SZ_4K,
	};
	void __iomem *base;

	data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data),
			    GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	base = devm_platform_ioremap_resource(pdev, 0);
	ret = PTR_ERR_OR_ZERO(base);
	if (ret) {
		dev_err(dev, "Failed to get memory region\n");
		return ret;
	}

	data->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
	ret = PTR_ERR_OR_ZERO(data->regmap);
	if (ret) {
		dev_err(dev, "Failed to init regmap (%d)\n", ret);
		return ret;
	}

	data->clk = devm_clk_get_optional(dev, NULL);
	if (IS_ERR(data->clk))
		return PTR_ERR(data->clk);

	ret = clk_prepare_enable(data->clk);
	if (ret) {
		dev_err(dev, "Failed to enable clock\n");
		return ret;
	}

	ret = devm_add_action_or_reset(dev, qoriq_tmu_action, data);
	if (ret)
		return ret;

	/* version register offset at: 0xbf8 on both v1 and v2 */
	ret = regmap_read(data->regmap, REGS_IPBRR(0), &ver);
	if (ret) {
		dev_err(&pdev->dev, "Failed to read IP block version\n");
		return ret;
	}
	data->ver = (ver >> 8) & 0xff;

	qoriq_tmu_init_device(data);	/* TMU initialization */

	ret = qoriq_tmu_calibration(dev, data);	/* TMU calibration */
	if (ret < 0)
		return ret;

	ret = qoriq_tmu_register_tmu_zone(dev, data);
	if (ret < 0) {
		dev_err(dev, "Failed to register sensors\n");
		return ret;
	}

	platform_set_drvdata(pdev, data);

	return 0;
}

static int __maybe_unused qoriq_tmu_suspend(struct device *dev)
{
	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
	int ret;

	ret = regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, 0);
	if (ret)
		return ret;

	clk_disable_unprepare(data->clk);

	return 0;
}

static int __maybe_unused qoriq_tmu_resume(struct device *dev)
{
	int ret;
	struct qoriq_tmu_data *data = dev_get_drvdata(dev);

	ret = clk_prepare_enable(data->clk);
	if (ret)
		return ret;

	/* Enable monitoring */
	return regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, TMR_ME);
}

static SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
			 qoriq_tmu_suspend, qoriq_tmu_resume);

static const struct of_device_id qoriq_tmu_match[] = {
	{ .compatible = "fsl,qoriq-tmu", },
	{ .compatible = "fsl,imx8mq-tmu", },
	{},
};
MODULE_DEVICE_TABLE(of, qoriq_tmu_match);

static struct platform_driver qoriq_tmu = {
	.driver	= {
		.name		= "qoriq_thermal",
		.pm		= &qoriq_tmu_pm_ops,
		.of_match_table	= qoriq_tmu_match,
	},
	.probe	= qoriq_tmu_probe,
};
module_platform_driver(qoriq_tmu);

MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>");
MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2dfef650 FE	1	// SPDX-License-Identifier: GPL-2.0
	2	//
	3	// Copyright 2016 Freescale Semiconductor, Inc.
43528445	4
51904045	5	#include <linux/clk.h>
43528445 JH	6	#include <linux/module.h>
	7	#include <linux/platform_device.h>
	8	#include <linux/err.h>
	9	#include <linux/io.h>
	10	#include <linux/of.h>
	11	#include <linux/of_address.h>
4316237b AS	12	#include <linux/regmap.h>
4316237b AS	13	#include <linux/sizes.h>
43528445 JH	14	#include <linux/thermal.h>
	15
	16	#include "thermal_core.h"
fd843309	17	#include "thermal_hwmon.h"
43528445	18
9809797b YT	19	#define SITES_MAX 16
	20	#define TMR_DISABLE 0x0
	21	#define TMR_ME 0x80000000
	22	#define TMR_ALPF 0x0c000000
	23	#define TMR_ALPF_V2 0x03000000
	24	#define TMTMIR_DEFAULT 0x0000000f
	25	#define TIER_DISABLE 0x0
	26	#define TEUMR0_V2 0x51009c00
	27	#define TMU_VER1 0x1
	28	#define TMU_VER2 0x2
43528445	29
4316237b AS	30	#define REGS_TMR 0x000 /* Mode Register */
	31	#define TMR_DISABLE 0x0
	32	#define TMR_ME 0x80000000
	33	#define TMR_ALPF 0x0c000000
45038e03	34	#define TMR_MSITE_ALL GENMASK(15, 0)
43528445	35
4316237b AS	36	#define REGS_TMTMIR 0x008 /* Temperature measurement interval Register */
4316237b AS	37	#define TMTMIR_DEFAULT 0x0000000f
9809797b	38
4316237b AS	39	#define REGS_V2_TMSR 0x008 /* monitor site register */
	40
	41	#define REGS_V2_TMTMIR 0x00c /* Temperature measurement interval Register */
	42
	43	#define REGS_TIER 0x020 /* Interrupt Enable Register */
	44	#define TIER_DISABLE 0x0
	45
	46
	47	#define REGS_TTCFGR 0x080 /* Temperature Configuration Register */
	48	#define REGS_TSCFGR 0x084 /* Sensor Configuration Register */
	49
	50	#define REGS_TRITSR(n) (0x100 + 16 * (n)) /* Immediate Temperature
	51	* Site Register
	52	*/
36564d7e	53	#define TRITSR_V BIT(31)
4316237b AS	54	#define REGS_TTRnCR(n) (0xf10 + 4 * (n)) /* Temperature Range n
	55	* Control Register
	56	*/
	57	#define REGS_IPBRR(n) (0xbf8 + 4 * (n)) /* IP Block Revision
	58	* Register n
	59	*/
	60	#define REGS_V2_TEUMR(n) (0xf00 + 4 * (n))
43528445 JH	61
	62	/*
	63	* Thermal zone data
	64	*/
7797ff42	65	struct qoriq_sensor {
7797ff42 YT	66	int id;
	67	};
	68
43528445	69	struct qoriq_tmu_data {
9809797b	70	int ver;
4316237b	71	struct regmap *regmap;
51904045	72	struct clk *clk;
b319da1b	73	struct qoriq_sensor sensor[SITES_MAX];
43528445 JH	74	};
43528445 JH	75
b319da1b AS	76	static struct qoriq_tmu_data qoriq_sensor_to_data(struct qoriq_sensor s)
	77	{
	78	return container_of(s, struct qoriq_tmu_data, sensor[s->id]);
	79	}
	80
43528445 JH	81	static int tmu_get_temp(void p, int temp)
43528445 JH	82	{
7797ff42	83	struct qoriq_sensor *qsensor = p;
b319da1b	84	struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor);
43528445	85	u32 val;
36564d7e AS	86	/*
	87	* REGS_TRITSR(id) has the following layout:
	88	*
	89	* 31 ... 7 6 5 4 3 2 1 0
	90	* V TEMP
	91	*
	92	* Where V bit signifies if the measurement is ready and is
	93	* within sensor range. TEMP is an 8 bit value representing
	94	* temperature in C.
	95	*/
	96	if (regmap_read_poll_timeout(qdata->regmap,
	97	REGS_TRITSR(qsensor->id),
	98	val,
	99	val & TRITSR_V,
	100	USEC_PER_MSEC,
	101	10 * USEC_PER_MSEC))
	102	return -ENODATA;
43528445	103
43528445 JH	104	temp = (val & 0xff) 1000;
	105
	106	return 0;
	107	}
	108
7797ff42 YT	109	static const struct thermal_zone_of_device_ops tmu_tz_ops = {
	110	.get_temp = tmu_get_temp,
	111	};
43528445	112
03036625 AS	113	static int qoriq_tmu_register_tmu_zone(struct device *dev,
03036625 AS	114	struct qoriq_tmu_data *qdata)
7797ff42	115	{
45038e03 AS	116	int id;
	117
	118	if (qdata->ver == TMU_VER1) {
	119	regmap_write(qdata->regmap, REGS_TMR,
	120	TMR_MSITE_ALL \| TMR_ME \| TMR_ALPF);
	121	} else {
	122	regmap_write(qdata->regmap, REGS_V2_TMSR, TMR_MSITE_ALL);
	123	regmap_write(qdata->regmap, REGS_TMR, TMR_ME \| TMR_ALPF_V2);
	124	}
7797ff42 YT	125
7797ff42 YT	126	for (id = 0; id < SITES_MAX; id++) {
11ef00f7	127	struct thermal_zone_device *tzd;
b319da1b	128	struct qoriq_sensor *sensor = &qdata->sensor[id];
11ef00f7 AS	129	int ret;
11ef00f7 AS	130
d6fb0564	131	sensor->id = id;
11ef00f7	132
03036625	133	tzd = devm_thermal_zone_of_sensor_register(dev, id,
d6fb0564	134	sensor,
11ef00f7 AS	135	&tmu_tz_ops);
	136	ret = PTR_ERR_OR_ZERO(tzd);
	137	if (ret) {
	138	if (ret == -ENODEV)
7797ff42	139	continue;
43528445	140
45038e03 AS	141	regmap_write(qdata->regmap, REGS_TMR, TMR_DISABLE);
45038e03 AS	142	return ret;
9809797b	143	}
fd843309 AS	144
	145	if (devm_thermal_add_hwmon_sysfs(tzd))
	146	dev_warn(dev,
	147	"Failed to add hwmon sysfs attributes\n");
	148
9809797b	149	}
43528445	150
7797ff42	151	return 0;
43528445 JH	152	}
43528445 JH	153
8e1cda35 AS	154	static int qoriq_tmu_calibration(struct device *dev,
8e1cda35 AS	155	struct qoriq_tmu_data *data)
43528445 JH	156	{
	157	int i, val, len;
	158	u32 range[4];
	159	const u32 *calibration;
8e1cda35	160	struct device_node *np = dev->of_node;
43528445	161
9809797b YT	162	len = of_property_count_u32_elems(np, "fsl,tmu-range");
9809797b YT	163	if (len < 0 \|\| len > 4) {
8e1cda35	164	dev_err(dev, "invalid range data.\n");
9809797b YT	165	return len;
	166	}
	167
	168	val = of_property_read_u32_array(np, "fsl,tmu-range", range, len);
	169	if (val != 0) {
8e1cda35	170	dev_err(dev, "failed to read range data.\n");
9809797b	171	return val;
43528445 JH	172	}
	173
	174	/* Init temperature range registers */
9809797b	175	for (i = 0; i < len; i++)
4316237b	176	regmap_write(data->regmap, REGS_TTRnCR(i), range[i]);
43528445 JH	177
	178	calibration = of_get_property(np, "fsl,tmu-calibration", &len);
	179	if (calibration == NULL \|\| len % 8) {
8e1cda35	180	dev_err(dev, "invalid calibration data.\n");
43528445 JH	181	return -ENODEV;
	182	}
	183
	184	for (i = 0; i < len; i += 8, calibration += 2) {
	185	val = of_read_number(calibration, 1);
4316237b	186	regmap_write(data->regmap, REGS_TTCFGR, val);
43528445	187	val = of_read_number(calibration + 1, 1);
4316237b	188	regmap_write(data->regmap, REGS_TSCFGR, val);
43528445 JH	189	}
	190
	191	return 0;
	192	}
	193
	194	static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
	195	{
	196	/* Disable interrupt, using polling instead */
4316237b	197	regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);
43528445 JH	198
43528445 JH	199	/* Set update_interval */
4316237b	200
9809797b	201	if (data->ver == TMU_VER1) {
4316237b	202	regmap_write(data->regmap, REGS_TMTMIR, TMTMIR_DEFAULT);
9809797b	203	} else {
4316237b AS	204	regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT);
4316237b AS	205	regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2);
9809797b	206	}
43528445 JH	207
43528445 JH	208	/* Disable monitoring */
4316237b	209	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
43528445 JH	210	}
43528445 JH	211
4316237b AS	212	static const struct regmap_range qoriq_yes_ranges[] = {
	213	regmap_reg_range(REGS_TMR, REGS_TSCFGR),
	214	regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(3)),
	215	regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
	216	regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
	217	/* Read only registers below */
	218	regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
	219	};
	220
	221	static const struct regmap_access_table qoriq_wr_table = {
	222	.yes_ranges = qoriq_yes_ranges,
	223	.n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges) - 1,
	224	};
	225
	226	static const struct regmap_access_table qoriq_rd_table = {
	227	.yes_ranges = qoriq_yes_ranges,
	228	.n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges),
	229	};
	230
85f0b61a AH	231	static void qoriq_tmu_action(void *p)
	232	{
	233	struct qoriq_tmu_data *data = p;
	234
	235	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
	236	clk_disable_unprepare(data->clk);
	237	}
	238
43528445 JH	239	static int qoriq_tmu_probe(struct platform_device *pdev)
	240	{
	241	int ret;
9809797b	242	u32 ver;
43528445 JH	243	struct qoriq_tmu_data *data;
43528445 JH	244	struct device_node *np = pdev->dev.of_node;
e167dc43	245	struct device *dev = &pdev->dev;
4316237b AS	246	const bool little_endian = of_property_read_bool(np, "little-endian");
	247	const enum regmap_endian format_endian =
	248	little_endian ? REGMAP_ENDIAN_LITTLE : REGMAP_ENDIAN_BIG;
	249	const struct regmap_config regmap_config = {
	250	.reg_bits = 32,
	251	.val_bits = 32,
	252	.reg_stride = 4,
	253	.rd_table = &qoriq_rd_table,
	254	.wr_table = &qoriq_wr_table,
	255	.val_format_endian = format_endian,
	256	.max_register = SZ_4K,
	257	};
	258	void __iomem *base;
43528445	259
e167dc43	260	data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data),
43528445 JH	261	GFP_KERNEL);
	262	if (!data)
	263	return -ENOMEM;
	264
4316237b AS	265	base = devm_platform_ioremap_resource(pdev, 0);
	266	ret = PTR_ERR_OR_ZERO(base);
	267	if (ret) {
e167dc43	268	dev_err(dev, "Failed to get memory region\n");
4316237b AS	269	return ret;
	270	}
	271
	272	data->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
	273	ret = PTR_ERR_OR_ZERO(data->regmap);
	274	if (ret) {
	275	dev_err(dev, "Failed to init regmap (%d)\n", ret);
	276	return ret;
43528445 JH	277	}
43528445 JH	278
e167dc43	279	data->clk = devm_clk_get_optional(dev, NULL);
51904045 AH	280	if (IS_ERR(data->clk))
	281	return PTR_ERR(data->clk);
	282
	283	ret = clk_prepare_enable(data->clk);
	284	if (ret) {
e167dc43	285	dev_err(dev, "Failed to enable clock\n");
51904045 AH	286	return ret;
	287	}
	288
85f0b61a AH	289	ret = devm_add_action_or_reset(dev, qoriq_tmu_action, data);
	290	if (ret)
	291	return ret;
	292
9809797b	293	/* version register offset at: 0xbf8 on both v1 and v2 */
4316237b AS	294	ret = regmap_read(data->regmap, REGS_IPBRR(0), &ver);
	295	if (ret) {
	296	dev_err(&pdev->dev, "Failed to read IP block version\n");
	297	return ret;
	298	}
9809797b	299	data->ver = (ver >> 8) & 0xff;
9809797b	300
43528445 JH	301	qoriq_tmu_init_device(data); /* TMU initialization */
43528445 JH	302
8e1cda35	303	ret = qoriq_tmu_calibration(dev, data); /* TMU calibration */
43528445	304	if (ret < 0)
85f0b61a	305	return ret;
43528445	306
03036625	307	ret = qoriq_tmu_register_tmu_zone(dev, data);
7797ff42	308	if (ret < 0) {
e167dc43	309	dev_err(dev, "Failed to register sensors\n");
85f0b61a	310	return ret;
43528445 JH	311	}
43528445 JH	312
8e1cda35 AS	313	platform_set_drvdata(pdev, data);
8e1cda35 AS	314
43528445 JH	315	return 0;
	316	}
	317
aea59197	318	static int __maybe_unused qoriq_tmu_suspend(struct device *dev)
43528445	319	{
43528445	320	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
4316237b	321	int ret;
43528445	322
4316237b AS	323	ret = regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, 0);
	324	if (ret)
	325	return ret;
43528445	326
51904045 AH	327	clk_disable_unprepare(data->clk);
51904045 AH	328
43528445 JH	329	return 0;
	330	}
	331
aea59197	332	static int __maybe_unused qoriq_tmu_resume(struct device *dev)
43528445	333	{
51904045	334	int ret;
43528445 JH	335	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
43528445 JH	336
51904045 AH	337	ret = clk_prepare_enable(data->clk);
	338	if (ret)
	339	return ret;
	340
43528445	341	/* Enable monitoring */
4316237b	342	return regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, TMR_ME);
43528445	343	}
43528445 JH	344
	345	static SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
	346	qoriq_tmu_suspend, qoriq_tmu_resume);
	347
	348	static const struct of_device_id qoriq_tmu_match[] = {
	349	{ .compatible = "fsl,qoriq-tmu", },
6017e2a9	350	{ .compatible = "fsl,imx8mq-tmu", },
43528445 JH	351	{},
	352	};
	353	MODULE_DEVICE_TABLE(of, qoriq_tmu_match);
	354
	355	static struct platform_driver qoriq_tmu = {
	356	.driver = {
	357	.name = "qoriq_thermal",
	358	.pm = &qoriq_tmu_pm_ops,
	359	.of_match_table = qoriq_tmu_match,
	360	},
	361	.probe = qoriq_tmu_probe,
43528445 JH	362	};
	363	module_platform_driver(qoriq_tmu);
	364
	365	MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>");
	366	MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver");
	367	MODULE_LICENSE("GPL v2");