[linux-block.git] / drivers / thermal / qoriq_thermal.c

// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2016 Freescale Semiconductor, Inc.

#include <linux/clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/sizes.h>
#include <linux/thermal.h>

#include "thermal_core.h"

#define SITES_MAX		16
#define TMR_DISABLE		0x0
#define TMR_ME			0x80000000
#define TMR_ALPF		0x0c000000
#define TMR_ALPF_V2		0x03000000
#define TMTMIR_DEFAULT	0x0000000f
#define TIER_DISABLE	0x0
#define TEUMR0_V2		0x51009c00
#define TMU_VER1		0x1
#define TMU_VER2		0x2

#define REGS_TMR	0x000	/* Mode Register */
#define TMR_DISABLE	0x0
#define TMR_ME		0x80000000
#define TMR_ALPF	0x0c000000
#define TMR_MSITE_ALL	GENMASK(15, 0)

#define REGS_TMTMIR	0x008	/* Temperature measurement interval Register */
#define TMTMIR_DEFAULT	0x0000000f

#define REGS_V2_TMSR	0x008	/* monitor site register */

#define REGS_V2_TMTMIR	0x00c	/* Temperature measurement interval Register */

#define REGS_TIER	0x020	/* Interrupt Enable Register */
#define TIER_DISABLE	0x0


#define REGS_TTCFGR	0x080	/* Temperature Configuration Register */
#define REGS_TSCFGR	0x084	/* Sensor Configuration Register */

#define REGS_TRITSR(n)	(0x100 + 16 * (n)) /* Immediate Temperature
					    * Site Register
					    */
#define REGS_TTRnCR(n)	(0xf10 + 4 * (n)) /* Temperature Range n
					   * Control Register
					   */
#define REGS_IPBRR(n)		(0xbf8 + 4 * (n)) /* IP Block Revision
						   * Register n
						   */
#define REGS_V2_TEUMR(n)	(0xf00 + 4 * (n))

/*
 * Thermal zone data
 */
struct qoriq_sensor {
	int				id;
};

struct qoriq_tmu_data {
	int ver;
	struct regmap *regmap;
	struct clk *clk;
	struct qoriq_sensor	sensor[SITES_MAX];
};

static struct qoriq_tmu_data *qoriq_sensor_to_data(struct qoriq_sensor *s)
{
	return container_of(s, struct qoriq_tmu_data, sensor[s->id]);
}

static int tmu_get_temp(void *p, int *temp)
{
	struct qoriq_sensor *qsensor = p;
	struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor);
	u32 val;

	regmap_read(qdata->regmap, REGS_TRITSR(qsensor->id), &val);
	*temp = (val & 0xff) * 1000;

	return 0;
}

static const struct thermal_zone_of_device_ops tmu_tz_ops = {
	.get_temp = tmu_get_temp,
};

static int qoriq_tmu_register_tmu_zone(struct device *dev,
				       struct qoriq_tmu_data *qdata)
{
	int id;

	if (qdata->ver == TMU_VER1) {
		regmap_write(qdata->regmap, REGS_TMR,
			     TMR_MSITE_ALL | TMR_ME | TMR_ALPF);
	} else {
		regmap_write(qdata->regmap, REGS_V2_TMSR, TMR_MSITE_ALL);
		regmap_write(qdata->regmap, REGS_TMR, TMR_ME | TMR_ALPF_V2);
	}

	for (id = 0; id < SITES_MAX; id++) {
		struct thermal_zone_device *tzd;
		struct qoriq_sensor *sensor = &qdata->sensor[id];
		int ret;

		sensor->id = id;

		tzd = devm_thermal_zone_of_sensor_register(dev, id,
							   sensor,
							   &tmu_tz_ops);
		ret = PTR_ERR_OR_ZERO(tzd);
		if (ret) {
			if (ret == -ENODEV)
				continue;

			regmap_write(qdata->regmap, REGS_TMR, TMR_DISABLE);
			return ret;
		}
	}

	return 0;
}

static int qoriq_tmu_calibration(struct device *dev,
				 struct qoriq_tmu_data *data)
{
	int i, val, len;
	u32 range[4];
	const u32 *calibration;
	struct device_node *np = dev->of_node;

	len = of_property_count_u32_elems(np, "fsl,tmu-range");
	if (len < 0 || len > 4) {
		dev_err(dev, "invalid range data.\n");
		return len;
	}

	val = of_property_read_u32_array(np, "fsl,tmu-range", range, len);
	if (val != 0) {
		dev_err(dev, "failed to read range data.\n");
		return val;
	}

	/* Init temperature range registers */
	for (i = 0; i < len; i++)
		regmap_write(data->regmap, REGS_TTRnCR(i), range[i]);

	calibration = of_get_property(np, "fsl,tmu-calibration", &len);
	if (calibration == NULL || len % 8) {
		dev_err(dev, "invalid calibration data.\n");
		return -ENODEV;
	}

	for (i = 0; i < len; i += 8, calibration += 2) {
		val = of_read_number(calibration, 1);
		regmap_write(data->regmap, REGS_TTCFGR, val);
		val = of_read_number(calibration + 1, 1);
		regmap_write(data->regmap, REGS_TSCFGR, val);
	}

	return 0;
}

static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
{
	/* Disable interrupt, using polling instead */
	regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);

	/* Set update_interval */

	if (data->ver == TMU_VER1) {
		regmap_write(data->regmap, REGS_TMTMIR, TMTMIR_DEFAULT);
	} else {
		regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT);
		regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2);
	}

	/* Disable monitoring */
	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
}

static const struct regmap_range qoriq_yes_ranges[] = {
	regmap_reg_range(REGS_TMR, REGS_TSCFGR),
	regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(3)),
	regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
	regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
	/* Read only registers below */
	regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
};

static const struct regmap_access_table qoriq_wr_table = {
	.yes_ranges	= qoriq_yes_ranges,
	.n_yes_ranges	= ARRAY_SIZE(qoriq_yes_ranges) - 1,
};

static const struct regmap_access_table qoriq_rd_table = {
	.yes_ranges	= qoriq_yes_ranges,
	.n_yes_ranges	= ARRAY_SIZE(qoriq_yes_ranges),
};

static int qoriq_tmu_probe(struct platform_device *pdev)
{
	int ret;
	u32 ver;
	struct qoriq_tmu_data *data;
	struct device_node *np = pdev->dev.of_node;
	struct device *dev = &pdev->dev;
	const bool little_endian = of_property_read_bool(np, "little-endian");
	const enum regmap_endian format_endian =
		little_endian ? REGMAP_ENDIAN_LITTLE : REGMAP_ENDIAN_BIG;
	const struct regmap_config regmap_config = {
		.reg_bits		= 32,
		.val_bits		= 32,
		.reg_stride		= 4,
		.rd_table		= &qoriq_rd_table,
		.wr_table		= &qoriq_wr_table,
		.val_format_endian	= format_endian,
		.max_register		= SZ_4K,
	};
	void __iomem *base;

	data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data),
			    GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	base = devm_platform_ioremap_resource(pdev, 0);
	ret = PTR_ERR_OR_ZERO(base);
	if (ret) {
		dev_err(dev, "Failed to get memory region\n");
		return ret;
	}

	data->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
	ret = PTR_ERR_OR_ZERO(data->regmap);
	if (ret) {
		dev_err(dev, "Failed to init regmap (%d)\n", ret);
		return ret;
	}

	data->clk = devm_clk_get_optional(dev, NULL);
	if (IS_ERR(data->clk))
		return PTR_ERR(data->clk);

	ret = clk_prepare_enable(data->clk);
	if (ret) {
		dev_err(dev, "Failed to enable clock\n");
		return ret;
	}

	/* version register offset at: 0xbf8 on both v1 and v2 */
	ret = regmap_read(data->regmap, REGS_IPBRR(0), &ver);
	if (ret) {
		dev_err(&pdev->dev, "Failed to read IP block version\n");
		return ret;
	}
	data->ver = (ver >> 8) & 0xff;

	qoriq_tmu_init_device(data);	/* TMU initialization */

	ret = qoriq_tmu_calibration(dev, data);	/* TMU calibration */
	if (ret < 0)
		goto err;

	ret = qoriq_tmu_register_tmu_zone(dev, data);
	if (ret < 0) {
		dev_err(dev, "Failed to register sensors\n");
		ret = -ENODEV;
		goto err;
	}

	platform_set_drvdata(pdev, data);

	return 0;

err:
	clk_disable_unprepare(data->clk);

	return ret;
}

static int qoriq_tmu_remove(struct platform_device *pdev)
{
	struct qoriq_tmu_data *data = platform_get_drvdata(pdev);

	/* Disable monitoring */
	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);

	clk_disable_unprepare(data->clk);

	return 0;
}

static int __maybe_unused qoriq_tmu_suspend(struct device *dev)
{
	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
	int ret;

	ret = regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, 0);
	if (ret)
		return ret;

	clk_disable_unprepare(data->clk);

	return 0;
}

static int __maybe_unused qoriq_tmu_resume(struct device *dev)
{
	int ret;
	struct qoriq_tmu_data *data = dev_get_drvdata(dev);

	ret = clk_prepare_enable(data->clk);
	if (ret)
		return ret;

	/* Enable monitoring */
	return regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, TMR_ME);
}

static SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
			 qoriq_tmu_suspend, qoriq_tmu_resume);

static const struct of_device_id qoriq_tmu_match[] = {
	{ .compatible = "fsl,qoriq-tmu", },
	{ .compatible = "fsl,imx8mq-tmu", },
	{},
};
MODULE_DEVICE_TABLE(of, qoriq_tmu_match);

static struct platform_driver qoriq_tmu = {
	.driver	= {
		.name		= "qoriq_thermal",
		.pm		= &qoriq_tmu_pm_ops,
		.of_match_table	= qoriq_tmu_match,
	},
	.probe	= qoriq_tmu_probe,
	.remove	= qoriq_tmu_remove,
};
module_platform_driver(qoriq_tmu);

MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>");
MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2dfef650 FE	1	// SPDX-License-Identifier: GPL-2.0
	2	//
	3	// Copyright 2016 Freescale Semiconductor, Inc.
43528445	4
51904045	5	#include <linux/clk.h>
43528445 JH	6	#include <linux/module.h>
	7	#include <linux/platform_device.h>
	8	#include <linux/err.h>
	9	#include <linux/io.h>
	10	#include <linux/of.h>
	11	#include <linux/of_address.h>
4316237b AS	12	#include <linux/regmap.h>
4316237b AS	13	#include <linux/sizes.h>
43528445 JH	14	#include <linux/thermal.h>
	15
	16	#include "thermal_core.h"
	17
9809797b YT	18	#define SITES_MAX 16
	19	#define TMR_DISABLE 0x0
	20	#define TMR_ME 0x80000000
	21	#define TMR_ALPF 0x0c000000
	22	#define TMR_ALPF_V2 0x03000000
	23	#define TMTMIR_DEFAULT 0x0000000f
	24	#define TIER_DISABLE 0x0
	25	#define TEUMR0_V2 0x51009c00
	26	#define TMU_VER1 0x1
	27	#define TMU_VER2 0x2
43528445	28
4316237b AS	29	#define REGS_TMR 0x000 /* Mode Register */
	30	#define TMR_DISABLE 0x0
	31	#define TMR_ME 0x80000000
	32	#define TMR_ALPF 0x0c000000
45038e03	33	#define TMR_MSITE_ALL GENMASK(15, 0)
43528445	34
4316237b AS	35	#define REGS_TMTMIR 0x008 /* Temperature measurement interval Register */
4316237b AS	36	#define TMTMIR_DEFAULT 0x0000000f
9809797b	37
4316237b AS	38	#define REGS_V2_TMSR 0x008 /* monitor site register */
	39
	40	#define REGS_V2_TMTMIR 0x00c /* Temperature measurement interval Register */
	41
	42	#define REGS_TIER 0x020 /* Interrupt Enable Register */
	43	#define TIER_DISABLE 0x0
	44
	45
	46	#define REGS_TTCFGR 0x080 /* Temperature Configuration Register */
	47	#define REGS_TSCFGR 0x084 /* Sensor Configuration Register */
	48
	49	#define REGS_TRITSR(n) (0x100 + 16 * (n)) /* Immediate Temperature
	50	* Site Register
	51	*/
	52	#define REGS_TTRnCR(n) (0xf10 + 4 * (n)) /* Temperature Range n
	53	* Control Register
	54	*/
	55	#define REGS_IPBRR(n) (0xbf8 + 4 * (n)) /* IP Block Revision
	56	* Register n
	57	*/
	58	#define REGS_V2_TEUMR(n) (0xf00 + 4 * (n))
43528445 JH	59
	60	/*
	61	* Thermal zone data
	62	*/
7797ff42	63	struct qoriq_sensor {
7797ff42 YT	64	int id;
	65	};
	66
43528445	67	struct qoriq_tmu_data {
9809797b	68	int ver;
4316237b	69	struct regmap *regmap;
51904045	70	struct clk *clk;
b319da1b	71	struct qoriq_sensor sensor[SITES_MAX];
43528445 JH	72	};
43528445 JH	73
b319da1b AS	74	static struct qoriq_tmu_data qoriq_sensor_to_data(struct qoriq_sensor s)
	75	{
	76	return container_of(s, struct qoriq_tmu_data, sensor[s->id]);
	77	}
	78
43528445 JH	79	static int tmu_get_temp(void p, int temp)
43528445 JH	80	{
7797ff42	81	struct qoriq_sensor *qsensor = p;
b319da1b	82	struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor);
43528445	83	u32 val;
43528445	84
4316237b	85	regmap_read(qdata->regmap, REGS_TRITSR(qsensor->id), &val);
43528445 JH	86	temp = (val & 0xff) 1000;
	87
	88	return 0;
	89	}
	90
7797ff42 YT	91	static const struct thermal_zone_of_device_ops tmu_tz_ops = {
	92	.get_temp = tmu_get_temp,
	93	};
43528445	94
03036625 AS	95	static int qoriq_tmu_register_tmu_zone(struct device *dev,
03036625 AS	96	struct qoriq_tmu_data *qdata)
7797ff42	97	{
45038e03 AS	98	int id;
	99
	100	if (qdata->ver == TMU_VER1) {
	101	regmap_write(qdata->regmap, REGS_TMR,
	102	TMR_MSITE_ALL \| TMR_ME \| TMR_ALPF);
	103	} else {
	104	regmap_write(qdata->regmap, REGS_V2_TMSR, TMR_MSITE_ALL);
	105	regmap_write(qdata->regmap, REGS_TMR, TMR_ME \| TMR_ALPF_V2);
	106	}
7797ff42 YT	107
7797ff42 YT	108	for (id = 0; id < SITES_MAX; id++) {
11ef00f7	109	struct thermal_zone_device *tzd;
b319da1b	110	struct qoriq_sensor *sensor = &qdata->sensor[id];
11ef00f7 AS	111	int ret;
11ef00f7 AS	112
d6fb0564	113	sensor->id = id;
11ef00f7	114
03036625	115	tzd = devm_thermal_zone_of_sensor_register(dev, id,
d6fb0564	116	sensor,
11ef00f7 AS	117	&tmu_tz_ops);
	118	ret = PTR_ERR_OR_ZERO(tzd);
	119	if (ret) {
	120	if (ret == -ENODEV)
7797ff42	121	continue;
43528445	122
45038e03 AS	123	regmap_write(qdata->regmap, REGS_TMR, TMR_DISABLE);
45038e03 AS	124	return ret;
9809797b YT	125	}
9809797b YT	126	}
43528445	127
7797ff42	128	return 0;
43528445 JH	129	}
43528445 JH	130
8e1cda35 AS	131	static int qoriq_tmu_calibration(struct device *dev,
8e1cda35 AS	132	struct qoriq_tmu_data *data)
43528445 JH	133	{
	134	int i, val, len;
	135	u32 range[4];
	136	const u32 *calibration;
8e1cda35	137	struct device_node *np = dev->of_node;
43528445	138
9809797b YT	139	len = of_property_count_u32_elems(np, "fsl,tmu-range");
9809797b YT	140	if (len < 0 \|\| len > 4) {
8e1cda35	141	dev_err(dev, "invalid range data.\n");
9809797b YT	142	return len;
	143	}
	144
	145	val = of_property_read_u32_array(np, "fsl,tmu-range", range, len);
	146	if (val != 0) {
8e1cda35	147	dev_err(dev, "failed to read range data.\n");
9809797b	148	return val;
43528445 JH	149	}
	150
	151	/* Init temperature range registers */
9809797b	152	for (i = 0; i < len; i++)
4316237b	153	regmap_write(data->regmap, REGS_TTRnCR(i), range[i]);
43528445 JH	154
	155	calibration = of_get_property(np, "fsl,tmu-calibration", &len);
	156	if (calibration == NULL \|\| len % 8) {
8e1cda35	157	dev_err(dev, "invalid calibration data.\n");
43528445 JH	158	return -ENODEV;
	159	}
	160
	161	for (i = 0; i < len; i += 8, calibration += 2) {
	162	val = of_read_number(calibration, 1);
4316237b	163	regmap_write(data->regmap, REGS_TTCFGR, val);
43528445	164	val = of_read_number(calibration + 1, 1);
4316237b	165	regmap_write(data->regmap, REGS_TSCFGR, val);
43528445 JH	166	}
	167
	168	return 0;
	169	}
	170
	171	static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
	172	{
	173	/* Disable interrupt, using polling instead */
4316237b	174	regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);
43528445 JH	175
43528445 JH	176	/* Set update_interval */
4316237b	177
9809797b	178	if (data->ver == TMU_VER1) {
4316237b	179	regmap_write(data->regmap, REGS_TMTMIR, TMTMIR_DEFAULT);
9809797b	180	} else {
4316237b AS	181	regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT);
4316237b AS	182	regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2);
9809797b	183	}
43528445 JH	184
43528445 JH	185	/* Disable monitoring */
4316237b	186	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
43528445 JH	187	}
43528445 JH	188
4316237b AS	189	static const struct regmap_range qoriq_yes_ranges[] = {
	190	regmap_reg_range(REGS_TMR, REGS_TSCFGR),
	191	regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(3)),
	192	regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
	193	regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
	194	/* Read only registers below */
	195	regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
	196	};
	197
	198	static const struct regmap_access_table qoriq_wr_table = {
	199	.yes_ranges = qoriq_yes_ranges,
	200	.n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges) - 1,
	201	};
	202
	203	static const struct regmap_access_table qoriq_rd_table = {
	204	.yes_ranges = qoriq_yes_ranges,
	205	.n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges),
	206	};
	207
43528445 JH	208	static int qoriq_tmu_probe(struct platform_device *pdev)
	209	{
	210	int ret;
9809797b	211	u32 ver;
43528445 JH	212	struct qoriq_tmu_data *data;
43528445 JH	213	struct device_node *np = pdev->dev.of_node;
e167dc43	214	struct device *dev = &pdev->dev;
4316237b AS	215	const bool little_endian = of_property_read_bool(np, "little-endian");
	216	const enum regmap_endian format_endian =
	217	little_endian ? REGMAP_ENDIAN_LITTLE : REGMAP_ENDIAN_BIG;
	218	const struct regmap_config regmap_config = {
	219	.reg_bits = 32,
	220	.val_bits = 32,
	221	.reg_stride = 4,
	222	.rd_table = &qoriq_rd_table,
	223	.wr_table = &qoriq_wr_table,
	224	.val_format_endian = format_endian,
	225	.max_register = SZ_4K,
	226	};
	227	void __iomem *base;
43528445	228
e167dc43	229	data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data),
43528445 JH	230	GFP_KERNEL);
	231	if (!data)
	232	return -ENOMEM;
	233
4316237b AS	234	base = devm_platform_ioremap_resource(pdev, 0);
	235	ret = PTR_ERR_OR_ZERO(base);
	236	if (ret) {
e167dc43	237	dev_err(dev, "Failed to get memory region\n");
4316237b AS	238	return ret;
	239	}
	240
	241	data->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
	242	ret = PTR_ERR_OR_ZERO(data->regmap);
	243	if (ret) {
	244	dev_err(dev, "Failed to init regmap (%d)\n", ret);
	245	return ret;
43528445 JH	246	}
43528445 JH	247
e167dc43	248	data->clk = devm_clk_get_optional(dev, NULL);
51904045 AH	249	if (IS_ERR(data->clk))
	250	return PTR_ERR(data->clk);
	251
	252	ret = clk_prepare_enable(data->clk);
	253	if (ret) {
e167dc43	254	dev_err(dev, "Failed to enable clock\n");
51904045 AH	255	return ret;
	256	}
	257
9809797b	258	/* version register offset at: 0xbf8 on both v1 and v2 */
4316237b AS	259	ret = regmap_read(data->regmap, REGS_IPBRR(0), &ver);
	260	if (ret) {
	261	dev_err(&pdev->dev, "Failed to read IP block version\n");
	262	return ret;
	263	}
9809797b	264	data->ver = (ver >> 8) & 0xff;
9809797b	265
43528445 JH	266	qoriq_tmu_init_device(data); /* TMU initialization */
43528445 JH	267
8e1cda35	268	ret = qoriq_tmu_calibration(dev, data); /* TMU calibration */
43528445	269	if (ret < 0)
4d82000a	270	goto err;
43528445	271
03036625	272	ret = qoriq_tmu_register_tmu_zone(dev, data);
7797ff42	273	if (ret < 0) {
e167dc43	274	dev_err(dev, "Failed to register sensors\n");
7797ff42	275	ret = -ENODEV;
4d82000a	276	goto err;
43528445 JH	277	}
43528445 JH	278
8e1cda35 AS	279	platform_set_drvdata(pdev, data);
8e1cda35 AS	280
43528445 JH	281	return 0;
43528445 JH	282
4d82000a	283	err:
51904045	284	clk_disable_unprepare(data->clk);
43528445 JH	285
	286	return ret;
	287	}
	288
	289	static int qoriq_tmu_remove(struct platform_device *pdev)
	290	{
	291	struct qoriq_tmu_data *data = platform_get_drvdata(pdev);
	292
43528445	293	/* Disable monitoring */
4316237b	294	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
43528445	295
51904045 AH	296	clk_disable_unprepare(data->clk);
51904045 AH	297
43528445 JH	298	return 0;
	299	}
	300
aea59197	301	static int __maybe_unused qoriq_tmu_suspend(struct device *dev)
43528445	302	{
43528445	303	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
4316237b	304	int ret;
43528445	305
4316237b AS	306	ret = regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, 0);
	307	if (ret)
	308	return ret;
43528445	309
51904045 AH	310	clk_disable_unprepare(data->clk);
51904045 AH	311
43528445 JH	312	return 0;
	313	}
	314
aea59197	315	static int __maybe_unused qoriq_tmu_resume(struct device *dev)
43528445	316	{
51904045	317	int ret;
43528445 JH	318	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
43528445 JH	319
51904045 AH	320	ret = clk_prepare_enable(data->clk);
	321	if (ret)
	322	return ret;
	323
43528445	324	/* Enable monitoring */
4316237b	325	return regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, TMR_ME);
43528445	326	}
43528445 JH	327
	328	static SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
	329	qoriq_tmu_suspend, qoriq_tmu_resume);
	330
	331	static const struct of_device_id qoriq_tmu_match[] = {
	332	{ .compatible = "fsl,qoriq-tmu", },
6017e2a9	333	{ .compatible = "fsl,imx8mq-tmu", },
43528445 JH	334	{},
	335	};
	336	MODULE_DEVICE_TABLE(of, qoriq_tmu_match);
	337
	338	static struct platform_driver qoriq_tmu = {
	339	.driver = {
	340	.name = "qoriq_thermal",
	341	.pm = &qoriq_tmu_pm_ops,
	342	.of_match_table = qoriq_tmu_match,
	343	},
	344	.probe = qoriq_tmu_probe,
	345	.remove = qoriq_tmu_remove,
	346	};
	347	module_platform_driver(qoriq_tmu);
	348
	349	MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>");
	350	MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver");
	351	MODULE_LICENSE("GPL v2");