[linux-block.git] / drivers / thermal / qoriq_thermal.c

// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2016 Freescale Semiconductor, Inc.

#include <linux/clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/thermal.h>

#include "thermal_core.h"

#define SITES_MAX		16
#define TMR_DISABLE		0x0
#define TMR_ME			0x80000000
#define TMR_ALPF		0x0c000000
#define TMR_ALPF_V2		0x03000000
#define TMTMIR_DEFAULT	0x0000000f
#define TIER_DISABLE	0x0
#define TEUMR0_V2		0x51009c00
#define TMU_VER1		0x1
#define TMU_VER2		0x2

/*
 * QorIQ TMU Registers
 */
struct qoriq_tmu_site_regs {
	u32 tritsr;		/* Immediate Temperature Site Register */
	u32 tratsr;		/* Average Temperature Site Register */
	u8 res0[0x8];
};

struct qoriq_tmu_regs_v1 {
	u32 tmr;		/* Mode Register */
	u32 tsr;		/* Status Register */
	u32 tmtmir;		/* Temperature measurement interval Register */
	u8 res0[0x14];
	u32 tier;		/* Interrupt Enable Register */
	u32 tidr;		/* Interrupt Detect Register */
	u32 tiscr;		/* Interrupt Site Capture Register */
	u32 ticscr;		/* Interrupt Critical Site Capture Register */
	u8 res1[0x10];
	u32 tmhtcrh;		/* High Temperature Capture Register */
	u32 tmhtcrl;		/* Low Temperature Capture Register */
	u8 res2[0x8];
	u32 tmhtitr;		/* High Temperature Immediate Threshold */
	u32 tmhtatr;		/* High Temperature Average Threshold */
	u32 tmhtactr;	/* High Temperature Average Crit Threshold */
	u8 res3[0x24];
	u32 ttcfgr;		/* Temperature Configuration Register */
	u32 tscfgr;		/* Sensor Configuration Register */
	u8 res4[0x78];
	struct qoriq_tmu_site_regs site[SITES_MAX];
	u8 res5[0x9f8];
	u32 ipbrr0;		/* IP Block Revision Register 0 */
	u32 ipbrr1;		/* IP Block Revision Register 1 */
	u8 res6[0x310];
	u32 ttrcr[4];		/* Temperature Range Control Register */
};

struct qoriq_tmu_regs_v2 {
	u32 tmr;		/* Mode Register */
	u32 tsr;		/* Status Register */
	u32 tmsr;		/* monitor site register */
	u32 tmtmir;		/* Temperature measurement interval Register */
	u8 res0[0x10];
	u32 tier;		/* Interrupt Enable Register */
	u32 tidr;		/* Interrupt Detect Register */
	u8 res1[0x8];
	u32 tiiscr;		/* interrupt immediate site capture register */
	u32 tiascr;		/* interrupt average site capture register */
	u32 ticscr;		/* Interrupt Critical Site Capture Register */
	u32 res2;
	u32 tmhtcr;		/* monitor high temperature capture register */
	u32 tmltcr;		/* monitor low temperature capture register */
	u32 tmrtrcr;	/* monitor rising temperature rate capture register */
	u32 tmftrcr;	/* monitor falling temperature rate capture register */
	u32 tmhtitr;	/* High Temperature Immediate Threshold */
	u32 tmhtatr;	/* High Temperature Average Threshold */
	u32 tmhtactr;	/* High Temperature Average Crit Threshold */
	u32 res3;
	u32 tmltitr;	/* monitor low temperature immediate threshold */
	u32 tmltatr;	/* monitor low temperature average threshold register */
	u32 tmltactr;	/* monitor low temperature average critical threshold */
	u32 res4;
	u32 tmrtrctr;	/* monitor rising temperature rate critical threshold */
	u32 tmftrctr;	/* monitor falling temperature rate critical threshold*/
	u8 res5[0x8];
	u32 ttcfgr;	/* Temperature Configuration Register */
	u32 tscfgr;	/* Sensor Configuration Register */
	u8 res6[0x78];
	struct qoriq_tmu_site_regs site[SITES_MAX];
	u8 res7[0x9f8];
	u32 ipbrr0;		/* IP Block Revision Register 0 */
	u32 ipbrr1;		/* IP Block Revision Register 1 */
	u8 res8[0x300];
	u32 teumr0;
	u32 teumr1;
	u32 teumr2;
	u32 res9;
	u32 ttrcr[4];	/* Temperature Range Control Register */
};

/*
 * Thermal zone data
 */
struct qoriq_sensor {
	int				id;
};

struct qoriq_tmu_data {
	int ver;
	struct qoriq_tmu_regs_v1 __iomem *regs;
	struct qoriq_tmu_regs_v2 __iomem *regs_v2;
	struct clk *clk;
	bool little_endian;
	struct qoriq_sensor	sensor[SITES_MAX];
};

static struct qoriq_tmu_data *qoriq_sensor_to_data(struct qoriq_sensor *s)
{
	return container_of(s, struct qoriq_tmu_data, sensor[s->id]);
}

static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem *addr)
{
	if (p->little_endian)
		iowrite32(val, addr);
	else
		iowrite32be(val, addr);
}

static u32 tmu_read(struct qoriq_tmu_data *p, void __iomem *addr)
{
	if (p->little_endian)
		return ioread32(addr);
	else
		return ioread32be(addr);
}

static int tmu_get_temp(void *p, int *temp)
{
	struct qoriq_sensor *qsensor = p;
	struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor);
	u32 val;

	val = tmu_read(qdata, &qdata->regs->site[qsensor->id].tritsr);
	*temp = (val & 0xff) * 1000;

	return 0;
}

static const struct thermal_zone_of_device_ops tmu_tz_ops = {
	.get_temp = tmu_get_temp,
};

static int qoriq_tmu_register_tmu_zone(struct device *dev,
				       struct qoriq_tmu_data *qdata)
{
	int id, sites = 0;

	for (id = 0; id < SITES_MAX; id++) {
		struct thermal_zone_device *tzd;
		struct qoriq_sensor *sensor = &qdata->sensor[id];
		int ret;

		sensor->id = id;

		tzd = devm_thermal_zone_of_sensor_register(dev, id,
							   sensor,
							   &tmu_tz_ops);
		ret = PTR_ERR_OR_ZERO(tzd);
		if (ret) {
			if (ret == -ENODEV)
				continue;
			else
				return ret;
		}

		if (qdata->ver == TMU_VER1)
			sites |= 0x1 << (15 - id);
		else
			sites |= 0x1 << id;
	}

	/* Enable monitoring */
	if (sites != 0) {
		if (qdata->ver == TMU_VER1) {
			tmu_write(qdata, sites | TMR_ME | TMR_ALPF,
					&qdata->regs->tmr);
		} else {
			tmu_write(qdata, sites, &qdata->regs_v2->tmsr);
			tmu_write(qdata, TMR_ME | TMR_ALPF_V2,
					&qdata->regs_v2->tmr);
		}
	}

	return 0;
}

static int qoriq_tmu_calibration(struct platform_device *pdev)
{
	int i, val, len;
	u32 range[4];
	const u32 *calibration;
	struct device_node *np = pdev->dev.of_node;
	struct qoriq_tmu_data *data = platform_get_drvdata(pdev);

	len = of_property_count_u32_elems(np, "fsl,tmu-range");
	if (len < 0 || len > 4) {
		dev_err(&pdev->dev, "invalid range data.\n");
		return len;
	}

	val = of_property_read_u32_array(np, "fsl,tmu-range", range, len);
	if (val != 0) {
		dev_err(&pdev->dev, "failed to read range data.\n");
		return val;
	}

	/* Init temperature range registers */
	for (i = 0; i < len; i++)
		tmu_write(data, range[i], &data->regs->ttrcr[i]);

	calibration = of_get_property(np, "fsl,tmu-calibration", &len);
	if (calibration == NULL || len % 8) {
		dev_err(&pdev->dev, "invalid calibration data.\n");
		return -ENODEV;
	}

	for (i = 0; i < len; i += 8, calibration += 2) {
		val = of_read_number(calibration, 1);
		tmu_write(data, val, &data->regs->ttcfgr);
		val = of_read_number(calibration + 1, 1);
		tmu_write(data, val, &data->regs->tscfgr);
	}

	return 0;
}

static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
{
	/* Disable interrupt, using polling instead */
	tmu_write(data, TIER_DISABLE, &data->regs->tier);

	/* Set update_interval */
	if (data->ver == TMU_VER1) {
		tmu_write(data, TMTMIR_DEFAULT, &data->regs->tmtmir);
	} else {
		tmu_write(data, TMTMIR_DEFAULT, &data->regs_v2->tmtmir);
		tmu_write(data, TEUMR0_V2, &data->regs_v2->teumr0);
	}

	/* Disable monitoring */
	tmu_write(data, TMR_DISABLE, &data->regs->tmr);
}

static int qoriq_tmu_probe(struct platform_device *pdev)
{
	int ret;
	u32 ver;
	struct qoriq_tmu_data *data;
	struct device_node *np = pdev->dev.of_node;
	struct device *dev = &pdev->dev;

	data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data),
			    GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	platform_set_drvdata(pdev, data);

	data->little_endian = of_property_read_bool(np, "little-endian");

	data->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(data->regs)) {
		dev_err(dev, "Failed to get memory region\n");
		return PTR_ERR(data->regs);
	}

	data->clk = devm_clk_get_optional(dev, NULL);
	if (IS_ERR(data->clk))
		return PTR_ERR(data->clk);

	ret = clk_prepare_enable(data->clk);
	if (ret) {
		dev_err(dev, "Failed to enable clock\n");
		return ret;
	}

	/* version register offset at: 0xbf8 on both v1 and v2 */
	ver = tmu_read(data, &data->regs->ipbrr0);
	data->ver = (ver >> 8) & 0xff;
	if (data->ver == TMU_VER2)
		data->regs_v2 = (void __iomem *)data->regs;

	qoriq_tmu_init_device(data);	/* TMU initialization */

	ret = qoriq_tmu_calibration(pdev);	/* TMU calibration */
	if (ret < 0)
		goto err;

	ret = qoriq_tmu_register_tmu_zone(dev, data);
	if (ret < 0) {
		dev_err(dev, "Failed to register sensors\n");
		ret = -ENODEV;
		goto err;
	}

	return 0;

err:
	clk_disable_unprepare(data->clk);
	platform_set_drvdata(pdev, NULL);

	return ret;
}

static int qoriq_tmu_remove(struct platform_device *pdev)
{
	struct qoriq_tmu_data *data = platform_get_drvdata(pdev);

	/* Disable monitoring */
	tmu_write(data, TMR_DISABLE, &data->regs->tmr);

	clk_disable_unprepare(data->clk);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

static int __maybe_unused qoriq_tmu_suspend(struct device *dev)
{
	u32 tmr;
	struct qoriq_tmu_data *data = dev_get_drvdata(dev);

	/* Disable monitoring */
	tmr = tmu_read(data, &data->regs->tmr);
	tmr &= ~TMR_ME;
	tmu_write(data, tmr, &data->regs->tmr);

	clk_disable_unprepare(data->clk);

	return 0;
}

static int __maybe_unused qoriq_tmu_resume(struct device *dev)
{
	u32 tmr;
	int ret;
	struct qoriq_tmu_data *data = dev_get_drvdata(dev);

	ret = clk_prepare_enable(data->clk);
	if (ret)
		return ret;

	/* Enable monitoring */
	tmr = tmu_read(data, &data->regs->tmr);
	tmr |= TMR_ME;
	tmu_write(data, tmr, &data->regs->tmr);

	return 0;
}

static SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
			 qoriq_tmu_suspend, qoriq_tmu_resume);

static const struct of_device_id qoriq_tmu_match[] = {
	{ .compatible = "fsl,qoriq-tmu", },
	{ .compatible = "fsl,imx8mq-tmu", },
	{},
};
MODULE_DEVICE_TABLE(of, qoriq_tmu_match);

static struct platform_driver qoriq_tmu = {
	.driver	= {
		.name		= "qoriq_thermal",
		.pm		= &qoriq_tmu_pm_ops,
		.of_match_table	= qoriq_tmu_match,
	},
	.probe	= qoriq_tmu_probe,
	.remove	= qoriq_tmu_remove,
};
module_platform_driver(qoriq_tmu);

MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>");
MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2dfef650 FE	1	// SPDX-License-Identifier: GPL-2.0
	2	//
	3	// Copyright 2016 Freescale Semiconductor, Inc.
43528445	4
51904045	5	#include <linux/clk.h>
43528445 JH	6	#include <linux/module.h>
	7	#include <linux/platform_device.h>
	8	#include <linux/err.h>
	9	#include <linux/io.h>
	10	#include <linux/of.h>
	11	#include <linux/of_address.h>
	12	#include <linux/thermal.h>
	13
	14	#include "thermal_core.h"
	15
9809797b YT	16	#define SITES_MAX 16
	17	#define TMR_DISABLE 0x0
	18	#define TMR_ME 0x80000000
	19	#define TMR_ALPF 0x0c000000
	20	#define TMR_ALPF_V2 0x03000000
	21	#define TMTMIR_DEFAULT 0x0000000f
	22	#define TIER_DISABLE 0x0
	23	#define TEUMR0_V2 0x51009c00
	24	#define TMU_VER1 0x1
	25	#define TMU_VER2 0x2
43528445 JH	26
	27	/*
	28	* QorIQ TMU Registers
	29	*/
	30	struct qoriq_tmu_site_regs {
	31	u32 tritsr; /* Immediate Temperature Site Register */
	32	u32 tratsr; /* Average Temperature Site Register */
	33	u8 res0[0x8];
	34	};
	35
9809797b	36	struct qoriq_tmu_regs_v1 {
43528445	37	u32 tmr; /* Mode Register */
43528445 JH	38	u32 tsr; /* Status Register */
43528445 JH	39	u32 tmtmir; /* Temperature measurement interval Register */
43528445 JH	40	u8 res0[0x14];
43528445 JH	41	u32 tier; /* Interrupt Enable Register */
43528445 JH	42	u32 tidr; /* Interrupt Detect Register */
	43	u32 tiscr; /* Interrupt Site Capture Register */
	44	u32 ticscr; /* Interrupt Critical Site Capture Register */
	45	u8 res1[0x10];
	46	u32 tmhtcrh; /* High Temperature Capture Register */
	47	u32 tmhtcrl; /* Low Temperature Capture Register */
	48	u8 res2[0x8];
	49	u32 tmhtitr; /* High Temperature Immediate Threshold */
	50	u32 tmhtatr; /* High Temperature Average Threshold */
	51	u32 tmhtactr; /* High Temperature Average Crit Threshold */
	52	u8 res3[0x24];
	53	u32 ttcfgr; /* Temperature Configuration Register */
	54	u32 tscfgr; /* Sensor Configuration Register */
	55	u8 res4[0x78];
	56	struct qoriq_tmu_site_regs site[SITES_MAX];
	57	u8 res5[0x9f8];
	58	u32 ipbrr0; /* IP Block Revision Register 0 */
	59	u32 ipbrr1; /* IP Block Revision Register 1 */
	60	u8 res6[0x310];
9809797b YT	61	u32 ttrcr[4]; /* Temperature Range Control Register */
	62	};
	63
	64	struct qoriq_tmu_regs_v2 {
	65	u32 tmr; /* Mode Register */
	66	u32 tsr; /* Status Register */
	67	u32 tmsr; /* monitor site register */
	68	u32 tmtmir; /* Temperature measurement interval Register */
	69	u8 res0[0x10];
	70	u32 tier; /* Interrupt Enable Register */
	71	u32 tidr; /* Interrupt Detect Register */
	72	u8 res1[0x8];
	73	u32 tiiscr; /* interrupt immediate site capture register */
	74	u32 tiascr; /* interrupt average site capture register */
	75	u32 ticscr; /* Interrupt Critical Site Capture Register */
	76	u32 res2;
	77	u32 tmhtcr; /* monitor high temperature capture register */
	78	u32 tmltcr; /* monitor low temperature capture register */
	79	u32 tmrtrcr; /* monitor rising temperature rate capture register */
	80	u32 tmftrcr; /* monitor falling temperature rate capture register */
	81	u32 tmhtitr; /* High Temperature Immediate Threshold */
	82	u32 tmhtatr; /* High Temperature Average Threshold */
	83	u32 tmhtactr; /* High Temperature Average Crit Threshold */
	84	u32 res3;
	85	u32 tmltitr; /* monitor low temperature immediate threshold */
	86	u32 tmltatr; /* monitor low temperature average threshold register */
	87	u32 tmltactr; /* monitor low temperature average critical threshold */
	88	u32 res4;
	89	u32 tmrtrctr; /* monitor rising temperature rate critical threshold */
	90	u32 tmftrctr; /* monitor falling temperature rate critical threshold*/
	91	u8 res5[0x8];
	92	u32 ttcfgr; /* Temperature Configuration Register */
	93	u32 tscfgr; /* Sensor Configuration Register */
	94	u8 res6[0x78];
	95	struct qoriq_tmu_site_regs site[SITES_MAX];
	96	u8 res7[0x9f8];
	97	u32 ipbrr0; /* IP Block Revision Register 0 */
	98	u32 ipbrr1; /* IP Block Revision Register 1 */
	99	u8 res8[0x300];
	100	u32 teumr0;
	101	u32 teumr1;
	102	u32 teumr2;
	103	u32 res9;
	104	u32 ttrcr[4]; /* Temperature Range Control Register */
43528445 JH	105	};
	106
	107	/*
	108	* Thermal zone data
	109	*/
7797ff42	110	struct qoriq_sensor {
7797ff42 YT	111	int id;
	112	};
	113
43528445	114	struct qoriq_tmu_data {
9809797b YT	115	int ver;
	116	struct qoriq_tmu_regs_v1 __iomem *regs;
	117	struct qoriq_tmu_regs_v2 __iomem *regs_v2;
51904045	118	struct clk *clk;
43528445	119	bool little_endian;
b319da1b	120	struct qoriq_sensor sensor[SITES_MAX];
43528445 JH	121	};
43528445 JH	122
b319da1b AS	123	static struct qoriq_tmu_data qoriq_sensor_to_data(struct qoriq_sensor s)
	124	{
	125	return container_of(s, struct qoriq_tmu_data, sensor[s->id]);
	126	}
	127
43528445 JH	128	static void tmu_write(struct qoriq_tmu_data p, u32 val, void __iomem addr)
	129	{
	130	if (p->little_endian)
	131	iowrite32(val, addr);
	132	else
	133	iowrite32be(val, addr);
	134	}
	135
	136	static u32 tmu_read(struct qoriq_tmu_data p, void __iomem addr)
	137	{
	138	if (p->little_endian)
	139	return ioread32(addr);
	140	else
	141	return ioread32be(addr);
	142	}
	143
	144	static int tmu_get_temp(void p, int temp)
	145	{
7797ff42	146	struct qoriq_sensor *qsensor = p;
b319da1b	147	struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor);
43528445	148	u32 val;
43528445	149
7797ff42	150	val = tmu_read(qdata, &qdata->regs->site[qsensor->id].tritsr);
43528445 JH	151	temp = (val & 0xff) 1000;
	152
	153	return 0;
	154	}
	155
7797ff42 YT	156	static const struct thermal_zone_of_device_ops tmu_tz_ops = {
	157	.get_temp = tmu_get_temp,
	158	};
43528445	159
03036625 AS	160	static int qoriq_tmu_register_tmu_zone(struct device *dev,
03036625 AS	161	struct qoriq_tmu_data *qdata)
7797ff42	162	{
7797ff42 YT	163	int id, sites = 0;
	164
	165	for (id = 0; id < SITES_MAX; id++) {
11ef00f7	166	struct thermal_zone_device *tzd;
b319da1b	167	struct qoriq_sensor *sensor = &qdata->sensor[id];
11ef00f7 AS	168	int ret;
11ef00f7 AS	169
d6fb0564	170	sensor->id = id;
11ef00f7	171
03036625	172	tzd = devm_thermal_zone_of_sensor_register(dev, id,
d6fb0564	173	sensor,
11ef00f7 AS	174	&tmu_tz_ops);
	175	ret = PTR_ERR_OR_ZERO(tzd);
	176	if (ret) {
	177	if (ret == -ENODEV)
7797ff42 YT	178	continue;
7797ff42 YT	179	else
11ef00f7	180	return ret;
7797ff42 YT	181	}
7797ff42 YT	182
9809797b YT	183	if (qdata->ver == TMU_VER1)
	184	sites \|= 0x1 << (15 - id);
	185	else
	186	sites \|= 0x1 << id;
43528445 JH	187	}
43528445 JH	188
7797ff42	189	/* Enable monitoring */
9809797b YT	190	if (sites != 0) {
	191	if (qdata->ver == TMU_VER1) {
	192	tmu_write(qdata, sites \| TMR_ME \| TMR_ALPF,
	193	&qdata->regs->tmr);
	194	} else {
	195	tmu_write(qdata, sites, &qdata->regs_v2->tmsr);
	196	tmu_write(qdata, TMR_ME \| TMR_ALPF_V2,
	197	&qdata->regs_v2->tmr);
	198	}
	199	}
43528445	200
7797ff42	201	return 0;
43528445 JH	202	}
	203
	204	static int qoriq_tmu_calibration(struct platform_device *pdev)
	205	{
	206	int i, val, len;
	207	u32 range[4];
	208	const u32 *calibration;
	209	struct device_node *np = pdev->dev.of_node;
	210	struct qoriq_tmu_data *data = platform_get_drvdata(pdev);
	211
9809797b YT	212	len = of_property_count_u32_elems(np, "fsl,tmu-range");
	213	if (len < 0 \|\| len > 4) {
	214	dev_err(&pdev->dev, "invalid range data.\n");
	215	return len;
	216	}
	217
	218	val = of_property_read_u32_array(np, "fsl,tmu-range", range, len);
	219	if (val != 0) {
	220	dev_err(&pdev->dev, "failed to read range data.\n");
	221	return val;
43528445 JH	222	}
	223
	224	/* Init temperature range registers */
9809797b YT	225	for (i = 0; i < len; i++)
9809797b YT	226	tmu_write(data, range[i], &data->regs->ttrcr[i]);
43528445 JH	227
	228	calibration = of_get_property(np, "fsl,tmu-calibration", &len);
	229	if (calibration == NULL \|\| len % 8) {
	230	dev_err(&pdev->dev, "invalid calibration data.\n");
	231	return -ENODEV;
	232	}
	233
	234	for (i = 0; i < len; i += 8, calibration += 2) {
	235	val = of_read_number(calibration, 1);
	236	tmu_write(data, val, &data->regs->ttcfgr);
	237	val = of_read_number(calibration + 1, 1);
	238	tmu_write(data, val, &data->regs->tscfgr);
	239	}
	240
	241	return 0;
	242	}
	243
	244	static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
	245	{
	246	/* Disable interrupt, using polling instead */
	247	tmu_write(data, TIER_DISABLE, &data->regs->tier);
	248
	249	/* Set update_interval */
9809797b YT	250	if (data->ver == TMU_VER1) {
	251	tmu_write(data, TMTMIR_DEFAULT, &data->regs->tmtmir);
	252	} else {
	253	tmu_write(data, TMTMIR_DEFAULT, &data->regs_v2->tmtmir);
	254	tmu_write(data, TEUMR0_V2, &data->regs_v2->teumr0);
	255	}
43528445 JH	256
	257	/* Disable monitoring */
	258	tmu_write(data, TMR_DISABLE, &data->regs->tmr);
	259	}
	260
43528445 JH	261	static int qoriq_tmu_probe(struct platform_device *pdev)
	262	{
	263	int ret;
9809797b	264	u32 ver;
43528445 JH	265	struct qoriq_tmu_data *data;
43528445 JH	266	struct device_node *np = pdev->dev.of_node;
e167dc43	267	struct device *dev = &pdev->dev;
43528445	268
e167dc43	269	data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data),
43528445 JH	270	GFP_KERNEL);
	271	if (!data)
	272	return -ENOMEM;
	273
	274	platform_set_drvdata(pdev, data);
	275
	276	data->little_endian = of_property_read_bool(np, "little-endian");
	277
4d82000a AH	278	data->regs = devm_platform_ioremap_resource(pdev, 0);
4d82000a AH	279	if (IS_ERR(data->regs)) {
e167dc43	280	dev_err(dev, "Failed to get memory region\n");
4d82000a	281	return PTR_ERR(data->regs);
43528445 JH	282	}
43528445 JH	283
e167dc43	284	data->clk = devm_clk_get_optional(dev, NULL);
51904045 AH	285	if (IS_ERR(data->clk))
	286	return PTR_ERR(data->clk);
	287
	288	ret = clk_prepare_enable(data->clk);
	289	if (ret) {
e167dc43	290	dev_err(dev, "Failed to enable clock\n");
51904045 AH	291	return ret;
	292	}
	293
9809797b YT	294	/* version register offset at: 0xbf8 on both v1 and v2 */
	295	ver = tmu_read(data, &data->regs->ipbrr0);
	296	data->ver = (ver >> 8) & 0xff;
	297	if (data->ver == TMU_VER2)
	298	data->regs_v2 = (void __iomem *)data->regs;
	299
43528445 JH	300	qoriq_tmu_init_device(data); /* TMU initialization */
	301
	302	ret = qoriq_tmu_calibration(pdev); /* TMU calibration */
	303	if (ret < 0)
4d82000a	304	goto err;
43528445	305
03036625	306	ret = qoriq_tmu_register_tmu_zone(dev, data);
7797ff42	307	if (ret < 0) {
e167dc43	308	dev_err(dev, "Failed to register sensors\n");
7797ff42	309	ret = -ENODEV;
4d82000a	310	goto err;
43528445 JH	311	}
43528445 JH	312
43528445 JH	313	return 0;
43528445 JH	314
4d82000a	315	err:
51904045	316	clk_disable_unprepare(data->clk);
43528445 JH	317	platform_set_drvdata(pdev, NULL);
	318
	319	return ret;
	320	}
	321
	322	static int qoriq_tmu_remove(struct platform_device *pdev)
	323	{
	324	struct qoriq_tmu_data *data = platform_get_drvdata(pdev);
	325
43528445 JH	326	/* Disable monitoring */
	327	tmu_write(data, TMR_DISABLE, &data->regs->tmr);
	328
51904045 AH	329	clk_disable_unprepare(data->clk);
51904045 AH	330
43528445 JH	331	platform_set_drvdata(pdev, NULL);
	332
	333	return 0;
	334	}
	335
aea59197	336	static int __maybe_unused qoriq_tmu_suspend(struct device *dev)
43528445 JH	337	{
	338	u32 tmr;
	339	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
	340
	341	/* Disable monitoring */
	342	tmr = tmu_read(data, &data->regs->tmr);
	343	tmr &= ~TMR_ME;
	344	tmu_write(data, tmr, &data->regs->tmr);
	345
51904045 AH	346	clk_disable_unprepare(data->clk);
51904045 AH	347
43528445 JH	348	return 0;
	349	}
	350
aea59197	351	static int __maybe_unused qoriq_tmu_resume(struct device *dev)
43528445 JH	352	{
43528445 JH	353	u32 tmr;
51904045	354	int ret;
43528445 JH	355	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
43528445 JH	356
51904045 AH	357	ret = clk_prepare_enable(data->clk);
	358	if (ret)
	359	return ret;
	360
43528445 JH	361	/* Enable monitoring */
	362	tmr = tmu_read(data, &data->regs->tmr);
	363	tmr \|= TMR_ME;
	364	tmu_write(data, tmr, &data->regs->tmr);
	365
	366	return 0;
	367	}
43528445 JH	368
	369	static SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
	370	qoriq_tmu_suspend, qoriq_tmu_resume);
	371
	372	static const struct of_device_id qoriq_tmu_match[] = {
	373	{ .compatible = "fsl,qoriq-tmu", },
6017e2a9	374	{ .compatible = "fsl,imx8mq-tmu", },
43528445 JH	375	{},
	376	};
	377	MODULE_DEVICE_TABLE(of, qoriq_tmu_match);
	378
	379	static struct platform_driver qoriq_tmu = {
	380	.driver = {
	381	.name = "qoriq_thermal",
	382	.pm = &qoriq_tmu_pm_ops,
	383	.of_match_table = qoriq_tmu_match,
	384	},
	385	.probe = qoriq_tmu_probe,
	386	.remove = qoriq_tmu_remove,
	387	};
	388	module_platform_driver(qoriq_tmu);
	389
	390	MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>");
	391	MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver");
	392	MODULE_LICENSE("GPL v2");