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[linux-2.6-block.git] / drivers / thermal / qcom / tsens-v0_1.c
CommitLineData
2d71d8de 1// SPDX-License-Identifier: GPL-2.0
840a5bd3
RN		 2/*
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
840a5bd3
RN		 4 */
5
6#include <linux/platform_device.h>
7#include "tsens.h"
8
c1997054
AK		 9/* ----- SROT ------ */
10#define SROT_CTRL_OFF 0x0000
11
12/* ----- TM ------ */
13#define TM_INT_EN_OFF 0x0000
14#define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004
15#define TM_Sn_STATUS_OFF 0x0030
16#define TM_TRDY_OFF 0x005c
17
840a5bd3 18/* eeprom layout data for 8916 */
774ccb08
AK		 19#define MSM8916_BASE0_MASK 0x0000007f
20#define MSM8916_BASE1_MASK 0xfe000000
21#define MSM8916_BASE0_SHIFT 0
22#define MSM8916_BASE1_SHIFT 25
23
24#define MSM8916_S0_P1_MASK 0x00000f80
25#define MSM8916_S1_P1_MASK 0x003e0000
26#define MSM8916_S2_P1_MASK 0xf8000000
27#define MSM8916_S3_P1_MASK 0x000003e0
28#define MSM8916_S4_P1_MASK 0x000f8000
29
30#define MSM8916_S0_P2_MASK 0x0001f000
31#define MSM8916_S1_P2_MASK 0x07c00000
32#define MSM8916_S2_P2_MASK 0x0000001f
33#define MSM8916_S3_P2_MASK 0x00007c00
34#define MSM8916_S4_P2_MASK 0x01f00000
35
36#define MSM8916_S0_P1_SHIFT 7
37#define MSM8916_S1_P1_SHIFT 17
38#define MSM8916_S2_P1_SHIFT 27
39#define MSM8916_S3_P1_SHIFT 5
40#define MSM8916_S4_P1_SHIFT 15
41
42#define MSM8916_S0_P2_SHIFT 12
43#define MSM8916_S1_P2_SHIFT 22
44#define MSM8916_S2_P2_SHIFT 0
45#define MSM8916_S3_P2_SHIFT 10
46#define MSM8916_S4_P2_SHIFT 20
47
48#define MSM8916_CAL_SEL_MASK 0xe0000000
49#define MSM8916_CAL_SEL_SHIFT 29
840a5bd3 50
332bc8eb
SG		 51/* eeprom layout data for 8939 */
52#define MSM8939_BASE0_MASK 0x000000ff
53#define MSM8939_BASE1_MASK 0xff000000
54#define MSM8939_BASE0_SHIFT 0
55#define MSM8939_BASE1_SHIFT 24
56
57#define MSM8939_S0_P1_MASK 0x000001f8
58#define MSM8939_S1_P1_MASK 0x001f8000
59#define MSM8939_S2_P1_MASK_0_4 0xf8000000
60#define MSM8939_S2_P1_MASK_5 0x00000001
61#define MSM8939_S3_P1_MASK 0x00001f80
62#define MSM8939_S4_P1_MASK 0x01f80000
63#define MSM8939_S5_P1_MASK 0x00003f00
64#define MSM8939_S6_P1_MASK 0x03f00000
65#define MSM8939_S7_P1_MASK 0x0000003f
66#define MSM8939_S8_P1_MASK 0x0003f000
67#define MSM8939_S9_P1_MASK 0x07e00000
68
69#define MSM8939_S0_P2_MASK 0x00007e00
70#define MSM8939_S1_P2_MASK 0x07e00000
71#define MSM8939_S2_P2_MASK 0x0000007e
72#define MSM8939_S3_P2_MASK 0x0007e000
73#define MSM8939_S4_P2_MASK 0x7e000000
74#define MSM8939_S5_P2_MASK 0x000fc000
75#define MSM8939_S6_P2_MASK 0xfc000000
76#define MSM8939_S7_P2_MASK 0x00000fc0
77#define MSM8939_S8_P2_MASK 0x00fc0000
78#define MSM8939_S9_P2_MASK_0_4 0xf8000000
79#define MSM8939_S9_P2_MASK_5 0x00002000
80
81#define MSM8939_S0_P1_SHIFT 3
82#define MSM8939_S1_P1_SHIFT 15
83#define MSM8939_S2_P1_SHIFT_0_4 27
84#define MSM8939_S2_P1_SHIFT_5 0
85#define MSM8939_S3_P1_SHIFT 7
86#define MSM8939_S4_P1_SHIFT 19
87#define MSM8939_S5_P1_SHIFT 8
88#define MSM8939_S6_P1_SHIFT 20
89#define MSM8939_S7_P1_SHIFT 0
90#define MSM8939_S8_P1_SHIFT 12
91#define MSM8939_S9_P1_SHIFT 21
92
93#define MSM8939_S0_P2_SHIFT 9
94#define MSM8939_S1_P2_SHIFT 21
95#define MSM8939_S2_P2_SHIFT 1
96#define MSM8939_S3_P2_SHIFT 13
97#define MSM8939_S4_P2_SHIFT 25
98#define MSM8939_S5_P2_SHIFT 14
99#define MSM8939_S6_P2_SHIFT 26
100#define MSM8939_S7_P2_SHIFT 6
101#define MSM8939_S8_P2_SHIFT 18
102#define MSM8939_S9_P2_SHIFT_0_4 27
103#define MSM8939_S9_P2_SHIFT_5 13
104
105#define MSM8939_CAL_SEL_MASK 0x7
106#define MSM8939_CAL_SEL_SHIFT 0
107
582a0c41
AK		 108/* eeprom layout data for 8974 */
109#define BASE1_MASK 0xff
110#define S0_P1_MASK 0x3f00
111#define S1_P1_MASK 0xfc000
112#define S2_P1_MASK 0x3f00000
113#define S3_P1_MASK 0xfc000000
114#define S4_P1_MASK 0x3f
115#define S5_P1_MASK 0xfc0
116#define S6_P1_MASK 0x3f000
117#define S7_P1_MASK 0xfc0000
118#define S8_P1_MASK 0x3f000000
119#define S8_P1_MASK_BKP 0x3f
120#define S9_P1_MASK 0x3f
121#define S9_P1_MASK_BKP 0xfc0
122#define S10_P1_MASK 0xfc0
123#define S10_P1_MASK_BKP 0x3f000
124#define CAL_SEL_0_1 0xc0000000
125#define CAL_SEL_2 0x40000000
126#define CAL_SEL_SHIFT 30
127#define CAL_SEL_SHIFT_2 28
128
129#define S0_P1_SHIFT 8
130#define S1_P1_SHIFT 14
131#define S2_P1_SHIFT 20
132#define S3_P1_SHIFT 26
133#define S5_P1_SHIFT 6
134#define S6_P1_SHIFT 12
135#define S7_P1_SHIFT 18
136#define S8_P1_SHIFT 24
137#define S9_P1_BKP_SHIFT 6
138#define S10_P1_SHIFT 6
139#define S10_P1_BKP_SHIFT 12
140
141#define BASE2_SHIFT 12
142#define BASE2_BKP_SHIFT 18
143#define S0_P2_SHIFT 20
144#define S0_P2_BKP_SHIFT 26
145#define S1_P2_SHIFT 26
146#define S2_P2_BKP_SHIFT 6
147#define S3_P2_SHIFT 6
148#define S3_P2_BKP_SHIFT 12
149#define S4_P2_SHIFT 12
150#define S4_P2_BKP_SHIFT 18
151#define S5_P2_SHIFT 18
152#define S5_P2_BKP_SHIFT 24
153#define S6_P2_SHIFT 24
154#define S7_P2_BKP_SHIFT 6
155#define S8_P2_SHIFT 6
156#define S8_P2_BKP_SHIFT 12
157#define S9_P2_SHIFT 12
158#define S9_P2_BKP_SHIFT 18
159#define S10_P2_SHIFT 18
160#define S10_P2_BKP_SHIFT 24
161
162#define BASE2_MASK 0xff000
163#define BASE2_BKP_MASK 0xfc0000
164#define S0_P2_MASK 0x3f00000
165#define S0_P2_BKP_MASK 0xfc000000
166#define S1_P2_MASK 0xfc000000
167#define S1_P2_BKP_MASK 0x3f
168#define S2_P2_MASK 0x3f
169#define S2_P2_BKP_MASK 0xfc0
170#define S3_P2_MASK 0xfc0
171#define S3_P2_BKP_MASK 0x3f000
172#define S4_P2_MASK 0x3f000
173#define S4_P2_BKP_MASK 0xfc0000
174#define S5_P2_MASK 0xfc0000
175#define S5_P2_BKP_MASK 0x3f000000
176#define S6_P2_MASK 0x3f000000
177#define S6_P2_BKP_MASK 0x3f
178#define S7_P2_MASK 0x3f
179#define S7_P2_BKP_MASK 0xfc0
180#define S8_P2_MASK 0xfc0
181#define S8_P2_BKP_MASK 0x3f000
182#define S9_P2_MASK 0x3f000
183#define S9_P2_BKP_MASK 0xfc0000
184#define S10_P2_MASK 0xfc0000
185#define S10_P2_BKP_MASK 0x3f000000
186
187#define BKP_SEL 0x3
188#define BKP_REDUN_SEL 0xe0000000
189#define BKP_REDUN_SHIFT 29
190
191#define BIT_APPEND 0x3
192
69b628ac 193static int calibrate_8916(struct tsens_priv *priv)
840a5bd3
RN		 194{
195 int base0 = 0, base1 = 0, i;
196 u32 p1[5], p2[5];
197 int mode = 0;
198 u32 *qfprom_cdata, *qfprom_csel;
199
69b628ac 200 qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
840a5bd3
RN		 201 if (IS_ERR(qfprom_cdata))
202 return PTR_ERR(qfprom_cdata);
203
69b628ac 204 qfprom_csel = (u32 *)qfprom_read(priv->dev, "calib_sel");
6b8249ab
SK		 205 if (IS_ERR(qfprom_csel)) {
206 kfree(qfprom_cdata);
840a5bd3 207 return PTR_ERR(qfprom_csel);
6b8249ab 208 }
840a5bd3 209
774ccb08 210 mode = (qfprom_csel[0] & MSM8916_CAL_SEL_MASK) >> MSM8916_CAL_SEL_SHIFT;
69b628ac 211 dev_dbg(priv->dev, "calibration mode is %d\n", mode);
840a5bd3
RN		 212
213 switch (mode) {
214 case TWO_PT_CALIB:
774ccb08
AK		 215 base1 = (qfprom_cdata[1] & MSM8916_BASE1_MASK) >> MSM8916_BASE1_SHIFT;
216 p2[0] = (qfprom_cdata[0] & MSM8916_S0_P2_MASK) >> MSM8916_S0_P2_SHIFT;
217 p2[1] = (qfprom_cdata[0] & MSM8916_S1_P2_MASK) >> MSM8916_S1_P2_SHIFT;
218 p2[2] = (qfprom_cdata[1] & MSM8916_S2_P2_MASK) >> MSM8916_S2_P2_SHIFT;
219 p2[3] = (qfprom_cdata[1] & MSM8916_S3_P2_MASK) >> MSM8916_S3_P2_SHIFT;
220 p2[4] = (qfprom_cdata[1] & MSM8916_S4_P2_MASK) >> MSM8916_S4_P2_SHIFT;
69b628ac 221 for (i = 0; i < priv->num_sensors; i++)
840a5bd3 222 p2[i] = ((base1 + p2[i]) << 3);
df561f66 223 fallthrough;
840a5bd3 224 case ONE_PT_CALIB2:
774ccb08
AK		 225 base0 = (qfprom_cdata[0] & MSM8916_BASE0_MASK);
226 p1[0] = (qfprom_cdata[0] & MSM8916_S0_P1_MASK) >> MSM8916_S0_P1_SHIFT;
227 p1[1] = (qfprom_cdata[0] & MSM8916_S1_P1_MASK) >> MSM8916_S1_P1_SHIFT;
228 p1[2] = (qfprom_cdata[0] & MSM8916_S2_P1_MASK) >> MSM8916_S2_P1_SHIFT;
229 p1[3] = (qfprom_cdata[1] & MSM8916_S3_P1_MASK) >> MSM8916_S3_P1_SHIFT;
230 p1[4] = (qfprom_cdata[1] & MSM8916_S4_P1_MASK) >> MSM8916_S4_P1_SHIFT;
69b628ac 231 for (i = 0; i < priv->num_sensors; i++)
840a5bd3
RN		 232 p1[i] = (((base0) + p1[i]) << 3);
233 break;
234 default:
69b628ac 235 for (i = 0; i < priv->num_sensors; i++) {
840a5bd3
RN		 236 p1[i] = 500;
237 p2[i] = 780;
238 }
239 break;
240 }
241
69b628ac 242 compute_intercept_slope(priv, p1, p2, mode);
6b8249ab
SK		 243 kfree(qfprom_cdata);
244 kfree(qfprom_csel);
840a5bd3
RN		 245
246 return 0;
247}
248
332bc8eb
SG		 249static int calibrate_8939(struct tsens_priv *priv)
250{
251 int base0 = 0, base1 = 0, i;
252 u32 p1[10], p2[10];
253 int mode = 0;
254 u32 *qfprom_cdata;
255 u32 cdata[6];
256
257 qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
258 if (IS_ERR(qfprom_cdata))
259 return PTR_ERR(qfprom_cdata);
260
261 /* Mapping between qfprom nvmem and calibration data */
262 cdata[0] = qfprom_cdata[12];
263 cdata[1] = qfprom_cdata[13];
264 cdata[2] = qfprom_cdata[0];
265 cdata[3] = qfprom_cdata[1];
266 cdata[4] = qfprom_cdata[22];
267 cdata[5] = qfprom_cdata[21];
268
269 mode = (cdata[0] & MSM8939_CAL_SEL_MASK) >> MSM8939_CAL_SEL_SHIFT;
270 dev_dbg(priv->dev, "calibration mode is %d\n", mode);
271
272 switch (mode) {
273 case TWO_PT_CALIB:
274 base1 = (cdata[3] & MSM8939_BASE1_MASK) >> MSM8939_BASE1_SHIFT;
275 p2[0] = (cdata[0] & MSM8939_S0_P2_MASK) >> MSM8939_S0_P2_SHIFT;
276 p2[1] = (cdata[0] & MSM8939_S1_P2_MASK) >> MSM8939_S1_P2_SHIFT;
277 p2[2] = (cdata[1] & MSM8939_S2_P2_MASK) >> MSM8939_S2_P2_SHIFT;
278 p2[3] = (cdata[1] & MSM8939_S3_P2_MASK) >> MSM8939_S3_P2_SHIFT;
279 p2[4] = (cdata[1] & MSM8939_S4_P2_MASK) >> MSM8939_S4_P2_SHIFT;
280 p2[5] = (cdata[2] & MSM8939_S5_P2_MASK) >> MSM8939_S5_P2_SHIFT;
281 p2[6] = (cdata[2] & MSM8939_S6_P2_MASK) >> MSM8939_S6_P2_SHIFT;
282 p2[7] = (cdata[3] & MSM8939_S7_P2_MASK) >> MSM8939_S7_P2_SHIFT;
283 p2[8] = (cdata[3] & MSM8939_S8_P2_MASK) >> MSM8939_S8_P2_SHIFT;
284 p2[9] = (cdata[4] & MSM8939_S9_P2_MASK_0_4) >> MSM8939_S9_P2_SHIFT_0_4;
285 p2[9] |= ((cdata[5] & MSM8939_S9_P2_MASK_5) >> MSM8939_S9_P2_SHIFT_5) << 5;
286 for (i = 0; i < priv->num_sensors; i++)
287 p2[i] = (base1 + p2[i]) << 2;
288 fallthrough;
289 case ONE_PT_CALIB2:
290 base0 = (cdata[2] & MSM8939_BASE0_MASK) >> MSM8939_BASE0_SHIFT;
291 p1[0] = (cdata[0] & MSM8939_S0_P1_MASK) >> MSM8939_S0_P1_SHIFT;
292 p1[1] = (cdata[0] & MSM8939_S1_P1_MASK) >> MSM8939_S1_P1_SHIFT;
293 p1[2] = (cdata[0] & MSM8939_S2_P1_MASK_0_4) >> MSM8939_S2_P1_SHIFT_0_4;
294 p1[2] |= ((cdata[1] & MSM8939_S2_P1_MASK_5) >> MSM8939_S2_P1_SHIFT_5) << 5;
295 p1[3] = (cdata[1] & MSM8939_S3_P1_MASK) >> MSM8939_S3_P1_SHIFT;
296 p1[4] = (cdata[1] & MSM8939_S4_P1_MASK) >> MSM8939_S4_P1_SHIFT;
297 p1[5] = (cdata[2] & MSM8939_S5_P1_MASK) >> MSM8939_S5_P1_SHIFT;
298 p1[6] = (cdata[2] & MSM8939_S6_P1_MASK) >> MSM8939_S6_P1_SHIFT;
299 p1[7] = (cdata[3] & MSM8939_S7_P1_MASK) >> MSM8939_S7_P1_SHIFT;
300 p1[8] = (cdata[3] & MSM8939_S8_P1_MASK) >> MSM8939_S8_P1_SHIFT;
301 p1[9] = (cdata[4] & MSM8939_S9_P1_MASK) >> MSM8939_S9_P1_SHIFT;
302 for (i = 0; i < priv->num_sensors; i++)
303 p1[i] = ((base0) + p1[i]) << 2;
304 break;
305 default:
306 for (i = 0; i < priv->num_sensors; i++) {
307 p1[i] = 500;
308 p2[i] = 780;
309 }
310 break;
311 }
312
313 compute_intercept_slope(priv, p1, p2, mode);
314 kfree(qfprom_cdata);
315
316 return 0;
317}
318
582a0c41
AK		 319static int calibrate_8974(struct tsens_priv *priv)
320{
321 int base1 = 0, base2 = 0, i;
322 u32 p1[11], p2[11];
323 int mode = 0;
324 u32 *calib, *bkp;
325 u32 calib_redun_sel;
326
327 calib = (u32 *)qfprom_read(priv->dev, "calib");
328 if (IS_ERR(calib))
329 return PTR_ERR(calib);
330
331 bkp = (u32 *)qfprom_read(priv->dev, "calib_backup");
6b8249ab
SK		 332 if (IS_ERR(bkp)) {
333 kfree(calib);
582a0c41 334 return PTR_ERR(bkp);
6b8249ab 335 }
582a0c41
AK		 336
337 calib_redun_sel = bkp[1] & BKP_REDUN_SEL;
338 calib_redun_sel >>= BKP_REDUN_SHIFT;
339
340 if (calib_redun_sel == BKP_SEL) {
341 mode = (calib[4] & CAL_SEL_0_1) >> CAL_SEL_SHIFT;
342 mode |= (calib[5] & CAL_SEL_2) >> CAL_SEL_SHIFT_2;
343
344 switch (mode) {
345 case TWO_PT_CALIB:
346 base2 = (bkp[2] & BASE2_BKP_MASK) >> BASE2_BKP_SHIFT;
347 p2[0] = (bkp[2] & S0_P2_BKP_MASK) >> S0_P2_BKP_SHIFT;
348 p2[1] = (bkp[3] & S1_P2_BKP_MASK);
349 p2[2] = (bkp[3] & S2_P2_BKP_MASK) >> S2_P2_BKP_SHIFT;
350 p2[3] = (bkp[3] & S3_P2_BKP_MASK) >> S3_P2_BKP_SHIFT;
351 p2[4] = (bkp[3] & S4_P2_BKP_MASK) >> S4_P2_BKP_SHIFT;
352 p2[5] = (calib[4] & S5_P2_BKP_MASK) >> S5_P2_BKP_SHIFT;
353 p2[6] = (calib[5] & S6_P2_BKP_MASK);
354 p2[7] = (calib[5] & S7_P2_BKP_MASK) >> S7_P2_BKP_SHIFT;
355 p2[8] = (calib[5] & S8_P2_BKP_MASK) >> S8_P2_BKP_SHIFT;
356 p2[9] = (calib[5] & S9_P2_BKP_MASK) >> S9_P2_BKP_SHIFT;
357 p2[10] = (calib[5] & S10_P2_BKP_MASK) >> S10_P2_BKP_SHIFT;
df561f66 358 fallthrough;
582a0c41
AK		 359 case ONE_PT_CALIB:
360 case ONE_PT_CALIB2:
361 base1 = bkp[0] & BASE1_MASK;
362 p1[0] = (bkp[0] & S0_P1_MASK) >> S0_P1_SHIFT;
363 p1[1] = (bkp[0] & S1_P1_MASK) >> S1_P1_SHIFT;
364 p1[2] = (bkp[0] & S2_P1_MASK) >> S2_P1_SHIFT;
365 p1[3] = (bkp[0] & S3_P1_MASK) >> S3_P1_SHIFT;
366 p1[4] = (bkp[1] & S4_P1_MASK);
367 p1[5] = (bkp[1] & S5_P1_MASK) >> S5_P1_SHIFT;
368 p1[6] = (bkp[1] & S6_P1_MASK) >> S6_P1_SHIFT;
369 p1[7] = (bkp[1] & S7_P1_MASK) >> S7_P1_SHIFT;
370 p1[8] = (bkp[2] & S8_P1_MASK_BKP) >> S8_P1_SHIFT;
371 p1[9] = (bkp[2] & S9_P1_MASK_BKP) >> S9_P1_BKP_SHIFT;
372 p1[10] = (bkp[2] & S10_P1_MASK_BKP) >> S10_P1_BKP_SHIFT;
373 break;
374 }
375 } else {
376 mode = (calib[1] & CAL_SEL_0_1) >> CAL_SEL_SHIFT;
377 mode |= (calib[3] & CAL_SEL_2) >> CAL_SEL_SHIFT_2;
378
379 switch (mode) {
380 case TWO_PT_CALIB:
381 base2 = (calib[2] & BASE2_MASK) >> BASE2_SHIFT;
382 p2[0] = (calib[2] & S0_P2_MASK) >> S0_P2_SHIFT;
383 p2[1] = (calib[2] & S1_P2_MASK) >> S1_P2_SHIFT;
384 p2[2] = (calib[3] & S2_P2_MASK);
385 p2[3] = (calib[3] & S3_P2_MASK) >> S3_P2_SHIFT;
386 p2[4] = (calib[3] & S4_P2_MASK) >> S4_P2_SHIFT;
387 p2[5] = (calib[3] & S5_P2_MASK) >> S5_P2_SHIFT;
388 p2[6] = (calib[3] & S6_P2_MASK) >> S6_P2_SHIFT;
389 p2[7] = (calib[4] & S7_P2_MASK);
390 p2[8] = (calib[4] & S8_P2_MASK) >> S8_P2_SHIFT;
391 p2[9] = (calib[4] & S9_P2_MASK) >> S9_P2_SHIFT;
392 p2[10] = (calib[4] & S10_P2_MASK) >> S10_P2_SHIFT;
df561f66 393 fallthrough;
582a0c41
AK		 394 case ONE_PT_CALIB:
395 case ONE_PT_CALIB2:
396 base1 = calib[0] & BASE1_MASK;
397 p1[0] = (calib[0] & S0_P1_MASK) >> S0_P1_SHIFT;
398 p1[1] = (calib[0] & S1_P1_MASK) >> S1_P1_SHIFT;
399 p1[2] = (calib[0] & S2_P1_MASK) >> S2_P1_SHIFT;
400 p1[3] = (calib[0] & S3_P1_MASK) >> S3_P1_SHIFT;
401 p1[4] = (calib[1] & S4_P1_MASK);
402 p1[5] = (calib[1] & S5_P1_MASK) >> S5_P1_SHIFT;
403 p1[6] = (calib[1] & S6_P1_MASK) >> S6_P1_SHIFT;
404 p1[7] = (calib[1] & S7_P1_MASK) >> S7_P1_SHIFT;
405 p1[8] = (calib[1] & S8_P1_MASK) >> S8_P1_SHIFT;
406 p1[9] = (calib[2] & S9_P1_MASK);
407 p1[10] = (calib[2] & S10_P1_MASK) >> S10_P1_SHIFT;
408 break;
409 }
410 }
411
412 switch (mode) {
413 case ONE_PT_CALIB:
414 for (i = 0; i < priv->num_sensors; i++)
415 p1[i] += (base1 << 2) | BIT_APPEND;
416 break;
417 case TWO_PT_CALIB:
418 for (i = 0; i < priv->num_sensors; i++) {
419 p2[i] += base2;
420 p2[i] <<= 2;
421 p2[i] |= BIT_APPEND;
422 }
df561f66 423 fallthrough;
582a0c41
AK		 424 case ONE_PT_CALIB2:
425 for (i = 0; i < priv->num_sensors; i++) {
426 p1[i] += base1;
427 p1[i] <<= 2;
428 p1[i] |= BIT_APPEND;
429 }
430 break;
431 default:
432 for (i = 0; i < priv->num_sensors; i++)
433 p2[i] = 780;
434 p1[0] = 502;
435 p1[1] = 509;
436 p1[2] = 503;
437 p1[3] = 509;
438 p1[4] = 505;
439 p1[5] = 509;
440 p1[6] = 507;
441 p1[7] = 510;
442 p1[8] = 508;
443 p1[9] = 509;
444 p1[10] = 508;
445 break;
446 }
447
448 compute_intercept_slope(priv, p1, p2, mode);
6b8249ab
SK		 449 kfree(calib);
450 kfree(bkp);
582a0c41
AK		 451
452 return 0;
453}
454
332bc8eb 455/* v0.1: 8916, 8939, 8974 */
c1997054 456
0aef1ee5 457static struct tsens_features tsens_v0_1_feat = {
c1997054
AK		 458 .ver_major = VER_0_1,
459 .crit_int = 0,
460 .adc = 1,
461 .srot_split = 1,
1b6e3e51 462 .max_sensors = 11,
c1997054
AK		 463};
464
465static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = {
466 /* ----- SROT ------ */
467 /* No VERSION information */
468
469 /* CTRL_OFFSET */
470 [TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0),
471 [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1),
472
473 /* ----- TM ------ */
474 /* INTERRUPT ENABLE */
475 [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0),
476
634e11d5
AK		 477 /* UPPER/LOWER TEMPERATURE THRESHOLDS */
478 REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9),
479 REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19),
480
481 /* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */
482 REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20),
483 REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21),
484
485 /* NO CRITICAL INTERRUPT SUPPORT on v0.1 */
486
c1997054
AK		 487 /* Sn_STATUS */
488 REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9),
489 /* No VALID field on v0.1 */
634e11d5 490 /* xxx_STATUS bits: 1 == threshold violated */
c1997054
AK		 491 REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10),
492 REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11),
493 REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12),
494 /* No CRITICAL field on v0.1 */
495 REG_FIELD_FOR_EACH_SENSOR11(MAX_STATUS, TM_Sn_STATUS_OFF, 13, 13),
496
497 /* TRDY: 1=ready, 0=in progress */
498 [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0),
499};
500
032d4057 501static const struct tsens_ops ops_8916 = {
840a5bd3
RN		 502 .init = init_common,
503 .calibrate = calibrate_8916,
504 .get_temp = get_temp_common,
505};
506
0aef1ee5 507struct tsens_plat_data data_8916 = {
840a5bd3
RN		 508 .num_sensors = 5,
509 .ops = &ops_8916,
510 .hw_ids = (unsigned int []){0, 1, 2, 4, 5 },
c1997054
AK		 511
512 .feat = &tsens_v0_1_feat,
513 .fields = tsens_v0_1_regfields,
840a5bd3 514};
582a0c41 515
332bc8eb
SG		 516static const struct tsens_ops ops_8939 = {
517 .init = init_common,
518 .calibrate = calibrate_8939,
519 .get_temp = get_temp_common,
520};
521
522struct tsens_plat_data data_8939 = {
523 .num_sensors = 10,
524 .ops = &ops_8939,
525 .hw_ids = (unsigned int []){ 0, 1, 2, 4, 5, 6, 7, 8, 9, 10 },
526
527 .feat = &tsens_v0_1_feat,
528 .fields = tsens_v0_1_regfields,
529};
530
582a0c41
AK		 531static const struct tsens_ops ops_8974 = {
532 .init = init_common,
533 .calibrate = calibrate_8974,
534 .get_temp = get_temp_common,
535};
536
0aef1ee5 537struct tsens_plat_data data_8974 = {
582a0c41
AK		 538 .num_sensors = 11,
539 .ops = &ops_8974,
c1997054
AK		 540 .feat = &tsens_v0_1_feat,
541 .fields = tsens_v0_1_regfields,
582a0c41 542};
Linux 6.x block layer and io_uring tree(s)