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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
a92db1c8 SH |
2 | /* |
3 | * Copyright (c) 2015 MediaTek Inc. | |
4 | * Author: Hanyi Wu <hanyi.wu@mediatek.com> | |
5 | * Sascha Hauer <s.hauer@pengutronix.de> | |
b7cf0053 | 6 | * Dawei Chien <dawei.chien@mediatek.com> |
6cf7f002 | 7 | * Louis Yu <louis.yu@mediatek.com> |
a92db1c8 SH |
8 | */ |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/nvmem-consumer.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/of_address.h> | |
b7cf0053 | 18 | #include <linux/of_device.h> |
a92db1c8 SH |
19 | #include <linux/platform_device.h> |
20 | #include <linux/slab.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/thermal.h> | |
23 | #include <linux/reset.h> | |
24 | #include <linux/types.h> | |
a92db1c8 SH |
25 | |
26 | /* AUXADC Registers */ | |
a92db1c8 SH |
27 | #define AUXADC_CON1_SET_V 0x008 |
28 | #define AUXADC_CON1_CLR_V 0x00c | |
29 | #define AUXADC_CON2_V 0x010 | |
30 | #define AUXADC_DATA(channel) (0x14 + (channel) * 4) | |
a92db1c8 SH |
31 | |
32 | #define APMIXED_SYS_TS_CON1 0x604 | |
33 | ||
34 | /* Thermal Controller Registers */ | |
35 | #define TEMP_MONCTL0 0x000 | |
36 | #define TEMP_MONCTL1 0x004 | |
37 | #define TEMP_MONCTL2 0x008 | |
38 | #define TEMP_MONIDET0 0x014 | |
39 | #define TEMP_MONIDET1 0x018 | |
40 | #define TEMP_MSRCTL0 0x038 | |
89945047 | 41 | #define TEMP_MSRCTL1 0x03c |
a92db1c8 SH |
42 | #define TEMP_AHBPOLL 0x040 |
43 | #define TEMP_AHBTO 0x044 | |
44 | #define TEMP_ADCPNP0 0x048 | |
45 | #define TEMP_ADCPNP1 0x04c | |
46 | #define TEMP_ADCPNP2 0x050 | |
47 | #define TEMP_ADCPNP3 0x0b4 | |
48 | ||
49 | #define TEMP_ADCMUX 0x054 | |
50 | #define TEMP_ADCEN 0x060 | |
51 | #define TEMP_PNPMUXADDR 0x064 | |
52 | #define TEMP_ADCMUXADDR 0x068 | |
53 | #define TEMP_ADCENADDR 0x074 | |
54 | #define TEMP_ADCVALIDADDR 0x078 | |
55 | #define TEMP_ADCVOLTADDR 0x07c | |
56 | #define TEMP_RDCTRL 0x080 | |
57 | #define TEMP_ADCVALIDMASK 0x084 | |
58 | #define TEMP_ADCVOLTAGESHIFT 0x088 | |
59 | #define TEMP_ADCWRITECTRL 0x08c | |
60 | #define TEMP_MSR0 0x090 | |
61 | #define TEMP_MSR1 0x094 | |
62 | #define TEMP_MSR2 0x098 | |
63 | #define TEMP_MSR3 0x0B8 | |
64 | ||
65 | #define TEMP_SPARE0 0x0f0 | |
66 | ||
a4ffe6b5 MK |
67 | #define TEMP_ADCPNP0_1 0x148 |
68 | #define TEMP_ADCPNP1_1 0x14c | |
69 | #define TEMP_ADCPNP2_1 0x150 | |
70 | #define TEMP_MSR0_1 0x190 | |
71 | #define TEMP_MSR1_1 0x194 | |
72 | #define TEMP_MSR2_1 0x198 | |
73 | #define TEMP_ADCPNP3_1 0x1b4 | |
74 | #define TEMP_MSR3_1 0x1B8 | |
75 | ||
a92db1c8 SH |
76 | #define PTPCORESEL 0x400 |
77 | ||
78 | #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) | |
79 | ||
eb4fc33e | 80 | #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16) |
a92db1c8 SH |
81 | #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) |
82 | ||
83 | #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) | |
84 | ||
85 | #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) | |
86 | #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) | |
87 | ||
88 | #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) | |
89 | #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) | |
90 | ||
b7cf0053 | 91 | /* MT8173 thermal sensors */ |
a92db1c8 SH |
92 | #define MT8173_TS1 0 |
93 | #define MT8173_TS2 1 | |
94 | #define MT8173_TS3 2 | |
95 | #define MT8173_TS4 3 | |
96 | #define MT8173_TSABB 4 | |
97 | ||
98 | /* AUXADC channel 11 is used for the temperature sensors */ | |
99 | #define MT8173_TEMP_AUXADC_CHANNEL 11 | |
100 | ||
101 | /* The total number of temperature sensors in the MT8173 */ | |
102 | #define MT8173_NUM_SENSORS 5 | |
103 | ||
104 | /* The number of banks in the MT8173 */ | |
105 | #define MT8173_NUM_ZONES 4 | |
106 | ||
107 | /* The number of sensing points per bank */ | |
108 | #define MT8173_NUM_SENSORS_PER_ZONE 4 | |
109 | ||
bd940394 MK |
110 | /* The number of controller in the MT8173 */ |
111 | #define MT8173_NUM_CONTROLLER 1 | |
112 | ||
f8451476 MK |
113 | /* The calibration coefficient of sensor */ |
114 | #define MT8173_CALIBRATION 165 | |
115 | ||
b7cf0053 | 116 | /* |
117 | * Layout of the fuses providing the calibration data | |
a4ffe6b5 MK |
118 | * These macros could be used for MT8183, MT8173, MT2701, and MT2712. |
119 | * MT8183 has 6 sensors and needs 6 VTS calibration data. | |
0a068993 LY |
120 | * MT8173 has 5 sensors and needs 5 VTS calibration data. |
121 | * MT2701 has 3 sensors and needs 3 VTS calibration data. | |
122 | * MT2712 has 4 sensors and needs 4 VTS calibration data. | |
b7cf0053 | 123 | */ |
54bf1e5a HY |
124 | #define CALIB_BUF0_VALID_V1 BIT(0) |
125 | #define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff) | |
126 | #define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff) | |
127 | #define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff) | |
128 | #define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff) | |
129 | #define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff) | |
130 | #define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff) | |
131 | #define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff) | |
132 | #define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f) | |
133 | #define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f) | |
134 | #define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1) | |
135 | #define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1) | |
1d081945 | 136 | |
89945047 HY |
137 | /* |
138 | * Layout of the fuses providing the calibration data | |
139 | * These macros could be used for MT7622. | |
140 | */ | |
141 | #define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff) | |
142 | #define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff) | |
143 | #define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f) | |
144 | #define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f) | |
145 | #define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff) | |
146 | #define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff) | |
147 | #define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff) | |
148 | #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) | |
149 | #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) | |
1d081945 MK |
150 | |
151 | enum { | |
152 | VTS1, | |
153 | VTS2, | |
154 | VTS3, | |
155 | VTS4, | |
a4ffe6b5 | 156 | VTS5, |
1d081945 MK |
157 | VTSABB, |
158 | MAX_NUM_VTS, | |
159 | }; | |
a92db1c8 | 160 | |
89945047 HY |
161 | enum mtk_thermal_version { |
162 | MTK_THERMAL_V1 = 1, | |
163 | MTK_THERMAL_V2, | |
164 | }; | |
165 | ||
b7cf0053 | 166 | /* MT2701 thermal sensors */ |
167 | #define MT2701_TS1 0 | |
168 | #define MT2701_TS2 1 | |
169 | #define MT2701_TSABB 2 | |
170 | ||
171 | /* AUXADC channel 11 is used for the temperature sensors */ | |
172 | #define MT2701_TEMP_AUXADC_CHANNEL 11 | |
173 | ||
174 | /* The total number of temperature sensors in the MT2701 */ | |
175 | #define MT2701_NUM_SENSORS 3 | |
176 | ||
b7cf0053 | 177 | /* The number of sensing points per bank */ |
178 | #define MT2701_NUM_SENSORS_PER_ZONE 3 | |
179 | ||
bd940394 MK |
180 | /* The number of controller in the MT2701 */ |
181 | #define MT2701_NUM_CONTROLLER 1 | |
182 | ||
f8451476 MK |
183 | /* The calibration coefficient of sensor */ |
184 | #define MT2701_CALIBRATION 165 | |
185 | ||
6cf7f002 LY |
186 | /* MT2712 thermal sensors */ |
187 | #define MT2712_TS1 0 | |
188 | #define MT2712_TS2 1 | |
189 | #define MT2712_TS3 2 | |
190 | #define MT2712_TS4 3 | |
191 | ||
192 | /* AUXADC channel 11 is used for the temperature sensors */ | |
193 | #define MT2712_TEMP_AUXADC_CHANNEL 11 | |
194 | ||
195 | /* The total number of temperature sensors in the MT2712 */ | |
196 | #define MT2712_NUM_SENSORS 4 | |
197 | ||
198 | /* The number of sensing points per bank */ | |
199 | #define MT2712_NUM_SENSORS_PER_ZONE 4 | |
200 | ||
bd940394 MK |
201 | /* The number of controller in the MT2712 */ |
202 | #define MT2712_NUM_CONTROLLER 1 | |
203 | ||
f8451476 MK |
204 | /* The calibration coefficient of sensor */ |
205 | #define MT2712_CALIBRATION 165 | |
206 | ||
3966be3c SW |
207 | #define MT7622_TEMP_AUXADC_CHANNEL 11 |
208 | #define MT7622_NUM_SENSORS 1 | |
209 | #define MT7622_NUM_ZONES 1 | |
210 | #define MT7622_NUM_SENSORS_PER_ZONE 1 | |
211 | #define MT7622_TS1 0 | |
bd940394 | 212 | #define MT7622_NUM_CONTROLLER 1 |
3966be3c | 213 | |
fb4d83f2 PHS |
214 | /* The maximum number of banks */ |
215 | #define MAX_NUM_ZONES 8 | |
216 | ||
f8451476 MK |
217 | /* The calibration coefficient of sensor */ |
218 | #define MT7622_CALIBRATION 165 | |
219 | ||
a4ffe6b5 MK |
220 | /* MT8183 thermal sensors */ |
221 | #define MT8183_TS1 0 | |
222 | #define MT8183_TS2 1 | |
223 | #define MT8183_TS3 2 | |
224 | #define MT8183_TS4 3 | |
225 | #define MT8183_TS5 4 | |
226 | #define MT8183_TSABB 5 | |
227 | ||
228 | /* AUXADC channel is used for the temperature sensors */ | |
229 | #define MT8183_TEMP_AUXADC_CHANNEL 11 | |
230 | ||
231 | /* The total number of temperature sensors in the MT8183 */ | |
232 | #define MT8183_NUM_SENSORS 6 | |
233 | ||
14533a5a MK |
234 | /* The number of banks in the MT8183 */ |
235 | #define MT8183_NUM_ZONES 1 | |
236 | ||
a4ffe6b5 MK |
237 | /* The number of sensing points per bank */ |
238 | #define MT8183_NUM_SENSORS_PER_ZONE 6 | |
239 | ||
240 | /* The number of controller in the MT8183 */ | |
241 | #define MT8183_NUM_CONTROLLER 2 | |
242 | ||
243 | /* The calibration coefficient of sensor */ | |
244 | #define MT8183_CALIBRATION 153 | |
245 | ||
a92db1c8 SH |
246 | struct mtk_thermal; |
247 | ||
b7cf0053 | 248 | struct thermal_bank_cfg { |
249 | unsigned int num_sensors; | |
250 | const int *sensors; | |
251 | }; | |
252 | ||
a92db1c8 SH |
253 | struct mtk_thermal_bank { |
254 | struct mtk_thermal *mt; | |
255 | int id; | |
256 | }; | |
257 | ||
b7cf0053 | 258 | struct mtk_thermal_data { |
259 | s32 num_banks; | |
260 | s32 num_sensors; | |
261 | s32 auxadc_channel; | |
1d081945 | 262 | const int *vts_index; |
b7cf0053 | 263 | const int *sensor_mux_values; |
264 | const int *msr; | |
265 | const int *adcpnp; | |
f8451476 | 266 | const int cali_val; |
bd940394 MK |
267 | const int num_controller; |
268 | const int *controller_offset; | |
cb82aaad | 269 | bool need_switch_bank; |
fb4d83f2 | 270 | struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; |
89945047 | 271 | enum mtk_thermal_version version; |
b7cf0053 | 272 | }; |
273 | ||
a92db1c8 SH |
274 | struct mtk_thermal { |
275 | struct device *dev; | |
276 | void __iomem *thermal_base; | |
277 | ||
278 | struct clk *clk_peri_therm; | |
279 | struct clk *clk_auxadc; | |
eb4fc33e | 280 | /* lock: for getting and putting banks */ |
a92db1c8 SH |
281 | struct mutex lock; |
282 | ||
283 | /* Calibration values */ | |
284 | s32 adc_ge; | |
89945047 | 285 | s32 adc_oe; |
a92db1c8 SH |
286 | s32 degc_cali; |
287 | s32 o_slope; | |
89945047 | 288 | s32 o_slope_sign; |
1d081945 | 289 | s32 vts[MAX_NUM_VTS]; |
a92db1c8 | 290 | |
b7cf0053 | 291 | const struct mtk_thermal_data *conf; |
fb4d83f2 | 292 | struct mtk_thermal_bank banks[MAX_NUM_ZONES]; |
a92db1c8 SH |
293 | }; |
294 | ||
a4ffe6b5 MK |
295 | /* MT8183 thermal sensor data */ |
296 | static const int mt8183_bank_data[MT8183_NUM_SENSORS] = { | |
297 | MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB | |
298 | }; | |
299 | ||
300 | static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = { | |
301 | TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1 | |
302 | }; | |
303 | ||
304 | static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = { | |
305 | TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1, | |
306 | TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1 | |
307 | }; | |
308 | ||
309 | static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 }; | |
310 | static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100}; | |
311 | ||
312 | static const int mt8183_vts_index[MT8183_NUM_SENSORS] = { | |
313 | VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB | |
314 | }; | |
315 | ||
b7cf0053 | 316 | /* MT8173 thermal sensor data */ |
992edf39 | 317 | static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = { |
b7cf0053 | 318 | { MT8173_TS2, MT8173_TS3 }, |
319 | { MT8173_TS2, MT8173_TS4 }, | |
320 | { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, | |
321 | { MT8173_TS2 }, | |
a92db1c8 SH |
322 | }; |
323 | ||
992edf39 | 324 | static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = { |
05d7839a | 325 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 |
b7cf0053 | 326 | }; |
a92db1c8 | 327 | |
992edf39 | 328 | static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = { |
b7cf0053 | 329 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 |
330 | }; | |
331 | ||
992edf39 | 332 | static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; |
bd940394 | 333 | static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, }; |
b7cf0053 | 334 | |
1d081945 MK |
335 | static const int mt8173_vts_index[MT8173_NUM_SENSORS] = { |
336 | VTS1, VTS2, VTS3, VTS4, VTSABB | |
337 | }; | |
338 | ||
b7cf0053 | 339 | /* MT2701 thermal sensor data */ |
992edf39 | 340 | static const int mt2701_bank_data[MT2701_NUM_SENSORS] = { |
b7cf0053 | 341 | MT2701_TS1, MT2701_TS2, MT2701_TSABB |
342 | }; | |
343 | ||
992edf39 | 344 | static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = { |
b7cf0053 | 345 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 |
346 | }; | |
347 | ||
992edf39 | 348 | static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = { |
b7cf0053 | 349 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 |
350 | }; | |
351 | ||
992edf39 | 352 | static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 }; |
bd940394 | 353 | static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, }; |
b7cf0053 | 354 | |
1d081945 MK |
355 | static const int mt2701_vts_index[MT2701_NUM_SENSORS] = { |
356 | VTS1, VTS2, VTS3 | |
357 | }; | |
358 | ||
6cf7f002 LY |
359 | /* MT2712 thermal sensor data */ |
360 | static const int mt2712_bank_data[MT2712_NUM_SENSORS] = { | |
361 | MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4 | |
362 | }; | |
363 | ||
364 | static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = { | |
365 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 | |
366 | }; | |
367 | ||
368 | static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = { | |
369 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 | |
370 | }; | |
371 | ||
372 | static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 }; | |
bd940394 | 373 | static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, }; |
6cf7f002 | 374 | |
1d081945 MK |
375 | static const int mt2712_vts_index[MT2712_NUM_SENSORS] = { |
376 | VTS1, VTS2, VTS3, VTS4 | |
377 | }; | |
378 | ||
3966be3c SW |
379 | /* MT7622 thermal sensor data */ |
380 | static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, }; | |
381 | static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; | |
382 | static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; | |
383 | static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, }; | |
1d081945 | 384 | static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; |
bd940394 | 385 | static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; |
3966be3c | 386 | |
3772bb42 | 387 | /* |
a92db1c8 SH |
388 | * The MT8173 thermal controller has four banks. Each bank can read up to |
389 | * four temperature sensors simultaneously. The MT8173 has a total of 5 | |
390 | * temperature sensors. We use each bank to measure a certain area of the | |
391 | * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple | |
392 | * areas, hence is used in different banks. | |
393 | * | |
394 | * The thermal core only gets the maximum temperature of all banks, so | |
395 | * the bank concept wouldn't be necessary here. However, the SVS (Smart | |
396 | * Voltage Scaling) unit makes its decisions based on the same bank | |
397 | * data, and this indeed needs the temperatures of the individual banks | |
398 | * for making better decisions. | |
399 | */ | |
b7cf0053 | 400 | static const struct mtk_thermal_data mt8173_thermal_data = { |
401 | .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL, | |
402 | .num_banks = MT8173_NUM_ZONES, | |
403 | .num_sensors = MT8173_NUM_SENSORS, | |
1d081945 | 404 | .vts_index = mt8173_vts_index, |
f8451476 | 405 | .cali_val = MT8173_CALIBRATION, |
bd940394 MK |
406 | .num_controller = MT8173_NUM_CONTROLLER, |
407 | .controller_offset = mt8173_tc_offset, | |
cb82aaad | 408 | .need_switch_bank = true, |
b7cf0053 | 409 | .bank_data = { |
410 | { | |
411 | .num_sensors = 2, | |
412 | .sensors = mt8173_bank_data[0], | |
413 | }, { | |
414 | .num_sensors = 2, | |
415 | .sensors = mt8173_bank_data[1], | |
416 | }, { | |
417 | .num_sensors = 3, | |
418 | .sensors = mt8173_bank_data[2], | |
419 | }, { | |
420 | .num_sensors = 1, | |
421 | .sensors = mt8173_bank_data[3], | |
422 | }, | |
a92db1c8 | 423 | }, |
b7cf0053 | 424 | .msr = mt8173_msr, |
425 | .adcpnp = mt8173_adcpnp, | |
426 | .sensor_mux_values = mt8173_mux_values, | |
89945047 | 427 | .version = MTK_THERMAL_V1, |
a92db1c8 SH |
428 | }; |
429 | ||
3772bb42 | 430 | /* |
b7cf0053 | 431 | * The MT2701 thermal controller has one bank, which can read up to |
432 | * three temperature sensors simultaneously. The MT2701 has a total of 3 | |
433 | * temperature sensors. | |
434 | * | |
435 | * The thermal core only gets the maximum temperature of this one bank, | |
436 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart | |
437 | * Voltage Scaling) unit makes its decisions based on the same bank | |
438 | * data. | |
439 | */ | |
440 | static const struct mtk_thermal_data mt2701_thermal_data = { | |
441 | .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL, | |
442 | .num_banks = 1, | |
443 | .num_sensors = MT2701_NUM_SENSORS, | |
1d081945 | 444 | .vts_index = mt2701_vts_index, |
f8451476 | 445 | .cali_val = MT2701_CALIBRATION, |
bd940394 MK |
446 | .num_controller = MT2701_NUM_CONTROLLER, |
447 | .controller_offset = mt2701_tc_offset, | |
cb82aaad | 448 | .need_switch_bank = true, |
b7cf0053 | 449 | .bank_data = { |
450 | { | |
451 | .num_sensors = 3, | |
452 | .sensors = mt2701_bank_data, | |
453 | }, | |
a92db1c8 | 454 | }, |
b7cf0053 | 455 | .msr = mt2701_msr, |
456 | .adcpnp = mt2701_adcpnp, | |
457 | .sensor_mux_values = mt2701_mux_values, | |
89945047 | 458 | .version = MTK_THERMAL_V1, |
a92db1c8 SH |
459 | }; |
460 | ||
3772bb42 | 461 | /* |
6cf7f002 LY |
462 | * The MT2712 thermal controller has one bank, which can read up to |
463 | * four temperature sensors simultaneously. The MT2712 has a total of 4 | |
464 | * temperature sensors. | |
465 | * | |
466 | * The thermal core only gets the maximum temperature of this one bank, | |
467 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart | |
468 | * Voltage Scaling) unit makes its decisions based on the same bank | |
469 | * data. | |
470 | */ | |
471 | static const struct mtk_thermal_data mt2712_thermal_data = { | |
472 | .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL, | |
473 | .num_banks = 1, | |
474 | .num_sensors = MT2712_NUM_SENSORS, | |
1d081945 | 475 | .vts_index = mt2712_vts_index, |
f8451476 | 476 | .cali_val = MT2712_CALIBRATION, |
bd940394 MK |
477 | .num_controller = MT2712_NUM_CONTROLLER, |
478 | .controller_offset = mt2712_tc_offset, | |
cb82aaad | 479 | .need_switch_bank = true, |
6cf7f002 LY |
480 | .bank_data = { |
481 | { | |
482 | .num_sensors = 4, | |
483 | .sensors = mt2712_bank_data, | |
484 | }, | |
485 | }, | |
486 | .msr = mt2712_msr, | |
487 | .adcpnp = mt2712_adcpnp, | |
488 | .sensor_mux_values = mt2712_mux_values, | |
89945047 | 489 | .version = MTK_THERMAL_V1, |
6cf7f002 LY |
490 | }; |
491 | ||
3966be3c SW |
492 | /* |
493 | * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data | |
494 | * access. | |
495 | */ | |
496 | static const struct mtk_thermal_data mt7622_thermal_data = { | |
497 | .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL, | |
498 | .num_banks = MT7622_NUM_ZONES, | |
499 | .num_sensors = MT7622_NUM_SENSORS, | |
1d081945 | 500 | .vts_index = mt7622_vts_index, |
f8451476 | 501 | .cali_val = MT7622_CALIBRATION, |
bd940394 MK |
502 | .num_controller = MT7622_NUM_CONTROLLER, |
503 | .controller_offset = mt7622_tc_offset, | |
cb82aaad | 504 | .need_switch_bank = true, |
3966be3c SW |
505 | .bank_data = { |
506 | { | |
507 | .num_sensors = 1, | |
508 | .sensors = mt7622_bank_data, | |
509 | }, | |
510 | }, | |
511 | .msr = mt7622_msr, | |
512 | .adcpnp = mt7622_adcpnp, | |
513 | .sensor_mux_values = mt7622_mux_values, | |
89945047 | 514 | .version = MTK_THERMAL_V2, |
3966be3c SW |
515 | }; |
516 | ||
3772bb42 | 517 | /* |
a4ffe6b5 MK |
518 | * The MT8183 thermal controller has one bank for the current SW framework. |
519 | * The MT8183 has a total of 6 temperature sensors. | |
520 | * There are two thermal controller to control the six sensor. | |
521 | * The first one bind 2 sensor, and the other bind 4 sensors. | |
522 | * The thermal core only gets the maximum temperature of all sensor, so | |
523 | * the bank concept wouldn't be necessary here. However, the SVS (Smart | |
524 | * Voltage Scaling) unit makes its decisions based on the same bank | |
525 | * data, and this indeed needs the temperatures of the individual banks | |
526 | * for making better decisions. | |
527 | */ | |
a4ffe6b5 MK |
528 | static const struct mtk_thermal_data mt8183_thermal_data = { |
529 | .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL, | |
14533a5a | 530 | .num_banks = MT8183_NUM_ZONES, |
a4ffe6b5 MK |
531 | .num_sensors = MT8183_NUM_SENSORS, |
532 | .vts_index = mt8183_vts_index, | |
533 | .cali_val = MT8183_CALIBRATION, | |
534 | .num_controller = MT8183_NUM_CONTROLLER, | |
535 | .controller_offset = mt8183_tc_offset, | |
536 | .need_switch_bank = false, | |
537 | .bank_data = { | |
538 | { | |
539 | .num_sensors = 6, | |
540 | .sensors = mt8183_bank_data, | |
541 | }, | |
542 | }, | |
543 | ||
544 | .msr = mt8183_msr, | |
545 | .adcpnp = mt8183_adcpnp, | |
546 | .sensor_mux_values = mt8183_mux_values, | |
89945047 | 547 | .version = MTK_THERMAL_V1, |
a4ffe6b5 MK |
548 | }; |
549 | ||
a92db1c8 SH |
550 | /** |
551 | * raw_to_mcelsius - convert a raw ADC value to mcelsius | |
3772bb42 AK |
552 | * @mt: The thermal controller |
553 | * @sensno: sensor number | |
a92db1c8 SH |
554 | * @raw: raw ADC value |
555 | * | |
556 | * This converts the raw ADC value to mcelsius using the SoC specific | |
557 | * calibration constants | |
558 | */ | |
54bf1e5a | 559 | static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw) |
a92db1c8 SH |
560 | { |
561 | s32 tmp; | |
562 | ||
563 | raw &= 0xfff; | |
564 | ||
565 | tmp = 203450520 << 3; | |
f8451476 | 566 | tmp /= mt->conf->cali_val + mt->o_slope; |
a92db1c8 SH |
567 | tmp /= 10000 + mt->adc_ge; |
568 | tmp *= raw - mt->vts[sensno] - 3350; | |
569 | tmp >>= 3; | |
570 | ||
571 | return mt->degc_cali * 500 - tmp; | |
572 | } | |
573 | ||
89945047 HY |
574 | static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw) |
575 | { | |
576 | s32 format_1 = 0; | |
577 | s32 format_2 = 0; | |
578 | s32 g_oe = 1; | |
579 | s32 g_gain = 1; | |
580 | s32 g_x_roomt = 0; | |
581 | s32 tmp = 0; | |
582 | ||
583 | if (raw == 0) | |
584 | return 0; | |
585 | ||
586 | raw &= 0xfff; | |
587 | g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12); | |
588 | g_oe = mt->adc_oe - 512; | |
589 | format_1 = mt->vts[VTS2] + 3105 - g_oe; | |
590 | format_2 = (mt->degc_cali * 10) >> 1; | |
591 | g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain; | |
592 | ||
593 | tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt; | |
594 | tmp = tmp * 10 * 100 / 11; | |
595 | ||
596 | if (mt->o_slope_sign == 0) | |
597 | tmp = tmp / (165 - mt->o_slope); | |
598 | else | |
599 | tmp = tmp / (165 + mt->o_slope); | |
600 | ||
601 | return (format_2 - tmp) * 100; | |
602 | } | |
603 | ||
a92db1c8 SH |
604 | /** |
605 | * mtk_thermal_get_bank - get bank | |
606 | * @bank: The bank | |
607 | * | |
608 | * The bank registers are banked, we have to select a bank in the | |
609 | * PTPCORESEL register to access it. | |
610 | */ | |
611 | static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) | |
612 | { | |
613 | struct mtk_thermal *mt = bank->mt; | |
614 | u32 val; | |
615 | ||
cb82aaad MK |
616 | if (mt->conf->need_switch_bank) { |
617 | mutex_lock(&mt->lock); | |
a92db1c8 | 618 | |
cb82aaad MK |
619 | val = readl(mt->thermal_base + PTPCORESEL); |
620 | val &= ~0xf; | |
621 | val |= bank->id; | |
622 | writel(val, mt->thermal_base + PTPCORESEL); | |
623 | } | |
a92db1c8 SH |
624 | } |
625 | ||
626 | /** | |
627 | * mtk_thermal_put_bank - release bank | |
628 | * @bank: The bank | |
629 | * | |
630 | * release a bank previously taken with mtk_thermal_get_bank, | |
631 | */ | |
632 | static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) | |
633 | { | |
634 | struct mtk_thermal *mt = bank->mt; | |
635 | ||
cb82aaad MK |
636 | if (mt->conf->need_switch_bank) |
637 | mutex_unlock(&mt->lock); | |
a92db1c8 SH |
638 | } |
639 | ||
640 | /** | |
641 | * mtk_thermal_bank_temperature - get the temperature of a bank | |
642 | * @bank: The bank | |
643 | * | |
644 | * The temperature of a bank is considered the maximum temperature of | |
645 | * the sensors associated to the bank. | |
646 | */ | |
647 | static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) | |
648 | { | |
649 | struct mtk_thermal *mt = bank->mt; | |
b7cf0053 | 650 | const struct mtk_thermal_data *conf = mt->conf; |
eb4fc33e | 651 | int i, temp = INT_MIN, max = INT_MIN; |
a92db1c8 SH |
652 | u32 raw; |
653 | ||
b7cf0053 | 654 | for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { |
a8f62f18 | 655 | raw = readl(mt->thermal_base + conf->msr[i]); |
a92db1c8 | 656 | |
89945047 HY |
657 | if (mt->conf->version == MTK_THERMAL_V1) { |
658 | temp = raw_to_mcelsius_v1( | |
659 | mt, conf->bank_data[bank->id].sensors[i], raw); | |
660 | } else { | |
661 | temp = raw_to_mcelsius_v2( | |
662 | mt, conf->bank_data[bank->id].sensors[i], raw); | |
663 | } | |
a92db1c8 SH |
664 | |
665 | /* | |
666 | * The first read of a sensor often contains very high bogus | |
667 | * temperature value. Filter these out so that the system does | |
668 | * not immediately shut down. | |
669 | */ | |
670 | if (temp > 200000) | |
671 | temp = 0; | |
672 | ||
673 | if (temp > max) | |
674 | max = temp; | |
675 | } | |
676 | ||
677 | return max; | |
678 | } | |
679 | ||
680 | static int mtk_read_temp(void *data, int *temperature) | |
681 | { | |
682 | struct mtk_thermal *mt = data; | |
683 | int i; | |
684 | int tempmax = INT_MIN; | |
685 | ||
b7cf0053 | 686 | for (i = 0; i < mt->conf->num_banks; i++) { |
a92db1c8 SH |
687 | struct mtk_thermal_bank *bank = &mt->banks[i]; |
688 | ||
689 | mtk_thermal_get_bank(bank); | |
690 | ||
691 | tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); | |
692 | ||
693 | mtk_thermal_put_bank(bank); | |
694 | } | |
695 | ||
696 | *temperature = tempmax; | |
697 | ||
698 | return 0; | |
699 | } | |
700 | ||
701 | static const struct thermal_zone_of_device_ops mtk_thermal_ops = { | |
702 | .get_temp = mtk_read_temp, | |
703 | }; | |
704 | ||
705 | static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, | |
bd940394 MK |
706 | u32 apmixed_phys_base, u32 auxadc_phys_base, |
707 | int ctrl_id) | |
a92db1c8 SH |
708 | { |
709 | struct mtk_thermal_bank *bank = &mt->banks[num]; | |
b7cf0053 | 710 | const struct mtk_thermal_data *conf = mt->conf; |
a92db1c8 SH |
711 | int i; |
712 | ||
bd940394 MK |
713 | int offset = mt->conf->controller_offset[ctrl_id]; |
714 | void __iomem *controller_base = mt->thermal_base + offset; | |
715 | ||
a92db1c8 SH |
716 | bank->id = num; |
717 | bank->mt = mt; | |
718 | ||
719 | mtk_thermal_get_bank(bank); | |
720 | ||
721 | /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ | |
bd940394 | 722 | writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1); |
a92db1c8 SH |
723 | |
724 | /* | |
725 | * filt interval is 1 * 46.540us = 46.54us, | |
726 | * sen interval is 429 * 46.540us = 19.96ms | |
727 | */ | |
728 | writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | | |
729 | TEMP_MONCTL2_SENSOR_INTERVAL(429), | |
bd940394 | 730 | controller_base + TEMP_MONCTL2); |
a92db1c8 SH |
731 | |
732 | /* poll is set to 10u */ | |
733 | writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), | |
bd940394 | 734 | controller_base + TEMP_AHBPOLL); |
a92db1c8 SH |
735 | |
736 | /* temperature sampling control, 1 sample */ | |
bd940394 | 737 | writel(0x0, controller_base + TEMP_MSRCTL0); |
a92db1c8 SH |
738 | |
739 | /* exceed this polling time, IRQ would be inserted */ | |
bd940394 | 740 | writel(0xffffffff, controller_base + TEMP_AHBTO); |
a92db1c8 SH |
741 | |
742 | /* number of interrupts per event, 1 is enough */ | |
bd940394 MK |
743 | writel(0x0, controller_base + TEMP_MONIDET0); |
744 | writel(0x0, controller_base + TEMP_MONIDET1); | |
a92db1c8 SH |
745 | |
746 | /* | |
747 | * The MT8173 thermal controller does not have its own ADC. Instead it | |
748 | * uses AHB bus accesses to control the AUXADC. To do this the thermal | |
749 | * controller has to be programmed with the physical addresses of the | |
750 | * AUXADC registers and with the various bit positions in the AUXADC. | |
751 | * Also the thermal controller controls a mux in the APMIXEDSYS register | |
752 | * space. | |
753 | */ | |
754 | ||
755 | /* | |
756 | * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) | |
757 | * automatically by hw | |
758 | */ | |
bd940394 | 759 | writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX); |
a92db1c8 SH |
760 | |
761 | /* AHB address for auxadc mux selection */ | |
762 | writel(auxadc_phys_base + AUXADC_CON1_CLR_V, | |
bd940394 | 763 | controller_base + TEMP_ADCMUXADDR); |
a92db1c8 | 764 | |
89945047 HY |
765 | if (mt->conf->version == MTK_THERMAL_V1) { |
766 | /* AHB address for pnp sensor mux selection */ | |
767 | writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, | |
768 | controller_base + TEMP_PNPMUXADDR); | |
769 | } | |
a92db1c8 SH |
770 | |
771 | /* AHB value for auxadc enable */ | |
bd940394 | 772 | writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN); |
a92db1c8 SH |
773 | |
774 | /* AHB address for auxadc enable (channel 0 immediate mode selected) */ | |
775 | writel(auxadc_phys_base + AUXADC_CON1_SET_V, | |
bd940394 | 776 | controller_base + TEMP_ADCENADDR); |
a92db1c8 SH |
777 | |
778 | /* AHB address for auxadc valid bit */ | |
b7cf0053 | 779 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
bd940394 | 780 | controller_base + TEMP_ADCVALIDADDR); |
a92db1c8 SH |
781 | |
782 | /* AHB address for auxadc voltage output */ | |
b7cf0053 | 783 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
bd940394 | 784 | controller_base + TEMP_ADCVOLTADDR); |
a92db1c8 SH |
785 | |
786 | /* read valid & voltage are at the same register */ | |
bd940394 | 787 | writel(0x0, controller_base + TEMP_RDCTRL); |
a92db1c8 SH |
788 | |
789 | /* indicate where the valid bit is */ | |
790 | writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), | |
bd940394 | 791 | controller_base + TEMP_ADCVALIDMASK); |
a92db1c8 SH |
792 | |
793 | /* no shift */ | |
bd940394 | 794 | writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT); |
a92db1c8 SH |
795 | |
796 | /* enable auxadc mux write transaction */ | |
797 | writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, | |
bd940394 | 798 | controller_base + TEMP_ADCWRITECTRL); |
a92db1c8 | 799 | |
b7cf0053 | 800 | for (i = 0; i < conf->bank_data[num].num_sensors; i++) |
801 | writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]], | |
a8f62f18 | 802 | mt->thermal_base + conf->adcpnp[i]); |
a92db1c8 | 803 | |
b7cf0053 | 804 | writel((1 << conf->bank_data[num].num_sensors) - 1, |
bd940394 | 805 | controller_base + TEMP_MONCTL0); |
a92db1c8 | 806 | |
eb4fc33e EV |
807 | writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | |
808 | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, | |
bd940394 | 809 | controller_base + TEMP_ADCWRITECTRL); |
a92db1c8 SH |
810 | |
811 | mtk_thermal_put_bank(bank); | |
812 | } | |
813 | ||
814 | static u64 of_get_phys_base(struct device_node *np) | |
815 | { | |
816 | u64 size64; | |
817 | const __be32 *regaddr_p; | |
818 | ||
819 | regaddr_p = of_get_address(np, 0, &size64, NULL); | |
820 | if (!regaddr_p) | |
821 | return OF_BAD_ADDR; | |
822 | ||
823 | return of_translate_address(np, regaddr_p); | |
824 | } | |
825 | ||
54bf1e5a HY |
826 | static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf) |
827 | { | |
828 | int i; | |
829 | ||
830 | if (!(buf[0] & CALIB_BUF0_VALID_V1)) | |
831 | return -EINVAL; | |
832 | ||
833 | mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]); | |
834 | ||
835 | for (i = 0; i < mt->conf->num_sensors; i++) { | |
836 | switch (mt->conf->vts_index[i]) { | |
837 | case VTS1: | |
838 | mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]); | |
839 | break; | |
840 | case VTS2: | |
841 | mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]); | |
842 | break; | |
843 | case VTS3: | |
844 | mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]); | |
845 | break; | |
846 | case VTS4: | |
847 | mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]); | |
848 | break; | |
849 | case VTS5: | |
850 | mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]); | |
851 | break; | |
852 | case VTSABB: | |
853 | mt->vts[VTSABB] = | |
854 | CALIB_BUF2_VTS_TSABB_V1(buf[2]); | |
855 | break; | |
856 | default: | |
857 | break; | |
858 | } | |
859 | } | |
860 | ||
861 | mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]); | |
862 | if (CALIB_BUF1_ID_V1(buf[1]) & | |
863 | CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0])) | |
864 | mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]); | |
865 | else | |
866 | mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]); | |
867 | ||
868 | return 0; | |
869 | } | |
870 | ||
89945047 HY |
871 | static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf) |
872 | { | |
873 | if (!CALIB_BUF1_VALID_V2(buf[1])) | |
874 | return -EINVAL; | |
875 | ||
876 | mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]); | |
877 | mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]); | |
878 | mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]); | |
879 | mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]); | |
880 | mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]); | |
881 | mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]); | |
882 | mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]); | |
883 | mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]); | |
884 | ||
885 | return 0; | |
886 | } | |
887 | ||
eb4fc33e EV |
888 | static int mtk_thermal_get_calibration_data(struct device *dev, |
889 | struct mtk_thermal *mt) | |
a92db1c8 SH |
890 | { |
891 | struct nvmem_cell *cell; | |
892 | u32 *buf; | |
893 | size_t len; | |
894 | int i, ret = 0; | |
895 | ||
896 | /* Start with default values */ | |
897 | mt->adc_ge = 512; | |
b7cf0053 | 898 | for (i = 0; i < mt->conf->num_sensors; i++) |
a92db1c8 SH |
899 | mt->vts[i] = 260; |
900 | mt->degc_cali = 40; | |
901 | mt->o_slope = 0; | |
902 | ||
903 | cell = nvmem_cell_get(dev, "calibration-data"); | |
904 | if (IS_ERR(cell)) { | |
905 | if (PTR_ERR(cell) == -EPROBE_DEFER) | |
906 | return PTR_ERR(cell); | |
907 | return 0; | |
908 | } | |
909 | ||
910 | buf = (u32 *)nvmem_cell_read(cell, &len); | |
911 | ||
912 | nvmem_cell_put(cell); | |
913 | ||
914 | if (IS_ERR(buf)) | |
915 | return PTR_ERR(buf); | |
916 | ||
917 | if (len < 3 * sizeof(u32)) { | |
918 | dev_warn(dev, "invalid calibration data\n"); | |
919 | ret = -EINVAL; | |
920 | goto out; | |
921 | } | |
922 | ||
89945047 HY |
923 | if (mt->conf->version == MTK_THERMAL_V1) |
924 | ret = mtk_thermal_extract_efuse_v1(mt, buf); | |
925 | else | |
926 | ret = mtk_thermal_extract_efuse_v2(mt, buf); | |
1d081945 | 927 | |
89945047 | 928 | if (ret) { |
a92db1c8 | 929 | dev_info(dev, "Device not calibrated, using default calibration values\n"); |
89945047 | 930 | ret = 0; |
a92db1c8 SH |
931 | } |
932 | ||
933 | out: | |
934 | kfree(buf); | |
935 | ||
936 | return ret; | |
937 | } | |
938 | ||
b7cf0053 | 939 | static const struct of_device_id mtk_thermal_of_match[] = { |
940 | { | |
941 | .compatible = "mediatek,mt8173-thermal", | |
942 | .data = (void *)&mt8173_thermal_data, | |
943 | }, | |
944 | { | |
945 | .compatible = "mediatek,mt2701-thermal", | |
946 | .data = (void *)&mt2701_thermal_data, | |
6cf7f002 LY |
947 | }, |
948 | { | |
949 | .compatible = "mediatek,mt2712-thermal", | |
950 | .data = (void *)&mt2712_thermal_data, | |
3966be3c SW |
951 | }, |
952 | { | |
953 | .compatible = "mediatek,mt7622-thermal", | |
954 | .data = (void *)&mt7622_thermal_data, | |
a4ffe6b5 MK |
955 | }, |
956 | { | |
957 | .compatible = "mediatek,mt8183-thermal", | |
958 | .data = (void *)&mt8183_thermal_data, | |
b7cf0053 | 959 | }, { |
960 | }, | |
961 | }; | |
962 | MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); | |
963 | ||
89945047 HY |
964 | static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base) |
965 | { | |
966 | int tmp; | |
967 | ||
968 | tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1); | |
969 | tmp &= ~(0x37); | |
970 | tmp |= 0x1; | |
971 | writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1); | |
972 | udelay(200); | |
973 | } | |
974 | ||
975 | static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt, | |
976 | void __iomem *auxadc_base) | |
977 | { | |
978 | int tmp; | |
979 | ||
980 | writel(0x800, auxadc_base + AUXADC_CON1_SET_V); | |
981 | writel(0x1, mt->thermal_base + TEMP_MONCTL0); | |
982 | tmp = readl(mt->thermal_base + TEMP_MSRCTL1); | |
983 | writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1); | |
984 | } | |
985 | ||
a92db1c8 SH |
986 | static int mtk_thermal_probe(struct platform_device *pdev) |
987 | { | |
bd940394 | 988 | int ret, i, ctrl_id; |
a92db1c8 SH |
989 | struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; |
990 | struct mtk_thermal *mt; | |
991 | struct resource *res; | |
992 | u64 auxadc_phys_base, apmixed_phys_base; | |
1f6b0889 | 993 | struct thermal_zone_device *tzdev; |
89945047 | 994 | void __iomem *apmixed_base, *auxadc_base; |
a92db1c8 SH |
995 | |
996 | mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); | |
997 | if (!mt) | |
998 | return -ENOMEM; | |
999 | ||
9efc58df | 1000 | mt->conf = of_device_get_match_data(&pdev->dev); |
b7cf0053 | 1001 | |
a92db1c8 SH |
1002 | mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); |
1003 | if (IS_ERR(mt->clk_peri_therm)) | |
1004 | return PTR_ERR(mt->clk_peri_therm); | |
1005 | ||
1006 | mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); | |
1007 | if (IS_ERR(mt->clk_auxadc)) | |
1008 | return PTR_ERR(mt->clk_auxadc); | |
1009 | ||
1010 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1011 | mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); | |
1012 | if (IS_ERR(mt->thermal_base)) | |
1013 | return PTR_ERR(mt->thermal_base); | |
1014 | ||
1015 | ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); | |
1016 | if (ret) | |
1017 | return ret; | |
1018 | ||
1019 | mutex_init(&mt->lock); | |
1020 | ||
1021 | mt->dev = &pdev->dev; | |
1022 | ||
1023 | auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); | |
1024 | if (!auxadc) { | |
1025 | dev_err(&pdev->dev, "missing auxadc node\n"); | |
1026 | return -ENODEV; | |
1027 | } | |
1028 | ||
89945047 | 1029 | auxadc_base = of_iomap(auxadc, 0); |
a92db1c8 SH |
1030 | auxadc_phys_base = of_get_phys_base(auxadc); |
1031 | ||
1032 | of_node_put(auxadc); | |
1033 | ||
1034 | if (auxadc_phys_base == OF_BAD_ADDR) { | |
1035 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); | |
1036 | return -EINVAL; | |
1037 | } | |
1038 | ||
1039 | apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); | |
1040 | if (!apmixedsys) { | |
1041 | dev_err(&pdev->dev, "missing apmixedsys node\n"); | |
1042 | return -ENODEV; | |
1043 | } | |
1044 | ||
89945047 | 1045 | apmixed_base = of_iomap(apmixedsys, 0); |
a92db1c8 SH |
1046 | apmixed_phys_base = of_get_phys_base(apmixedsys); |
1047 | ||
1048 | of_node_put(apmixedsys); | |
1049 | ||
1050 | if (apmixed_phys_base == OF_BAD_ADDR) { | |
1051 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); | |
1052 | return -EINVAL; | |
1053 | } | |
1054 | ||
703456ba | 1055 | ret = device_reset_optional(&pdev->dev); |
6760f3f7 LY |
1056 | if (ret) |
1057 | return ret; | |
1058 | ||
a92db1c8 SH |
1059 | ret = clk_prepare_enable(mt->clk_auxadc); |
1060 | if (ret) { | |
1061 | dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); | |
1062 | return ret; | |
1063 | } | |
1064 | ||
a92db1c8 SH |
1065 | ret = clk_prepare_enable(mt->clk_peri_therm); |
1066 | if (ret) { | |
1067 | dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); | |
1068 | goto err_disable_clk_auxadc; | |
1069 | } | |
1070 | ||
89945047 HY |
1071 | if (mt->conf->version == MTK_THERMAL_V2) { |
1072 | mtk_thermal_turn_on_buffer(apmixed_base); | |
1073 | mtk_thermal_release_periodic_ts(mt, auxadc_base); | |
1074 | } | |
1075 | ||
bd940394 MK |
1076 | for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) |
1077 | for (i = 0; i < mt->conf->num_banks; i++) | |
1078 | mtk_thermal_init_bank(mt, i, apmixed_phys_base, | |
1079 | auxadc_phys_base, ctrl_id); | |
a92db1c8 SH |
1080 | |
1081 | platform_set_drvdata(pdev, mt); | |
1082 | ||
1f6b0889 AL |
1083 | tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt, |
1084 | &mtk_thermal_ops); | |
1085 | if (IS_ERR(tzdev)) { | |
1086 | ret = PTR_ERR(tzdev); | |
1087 | goto err_disable_clk_peri_therm; | |
1088 | } | |
a92db1c8 SH |
1089 | |
1090 | return 0; | |
1091 | ||
1f6b0889 AL |
1092 | err_disable_clk_peri_therm: |
1093 | clk_disable_unprepare(mt->clk_peri_therm); | |
a92db1c8 SH |
1094 | err_disable_clk_auxadc: |
1095 | clk_disable_unprepare(mt->clk_auxadc); | |
1096 | ||
1097 | return ret; | |
1098 | } | |
1099 | ||
1100 | static int mtk_thermal_remove(struct platform_device *pdev) | |
1101 | { | |
1102 | struct mtk_thermal *mt = platform_get_drvdata(pdev); | |
1103 | ||
a92db1c8 SH |
1104 | clk_disable_unprepare(mt->clk_peri_therm); |
1105 | clk_disable_unprepare(mt->clk_auxadc); | |
1106 | ||
1107 | return 0; | |
1108 | } | |
1109 | ||
a92db1c8 SH |
1110 | static struct platform_driver mtk_thermal_driver = { |
1111 | .probe = mtk_thermal_probe, | |
1112 | .remove = mtk_thermal_remove, | |
1113 | .driver = { | |
f45ce7ee | 1114 | .name = "mtk-thermal", |
a92db1c8 SH |
1115 | .of_match_table = mtk_thermal_of_match, |
1116 | }, | |
1117 | }; | |
1118 | ||
1119 | module_platform_driver(mtk_thermal_driver); | |
1120 | ||
a4ffe6b5 | 1121 | MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>"); |
6cf7f002 | 1122 | MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>"); |
b7cf0053 | 1123 | MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>"); |
9ebfb4e0 | 1124 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); |
a92db1c8 SH |
1125 | MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); |
1126 | MODULE_DESCRIPTION("Mediatek thermal driver"); | |
1127 | MODULE_LICENSE("GPL v2"); |