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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
a92db1c8 SH |
2 | /* |
3 | * Copyright (c) 2015 MediaTek Inc. | |
4 | * Author: Hanyi Wu <hanyi.wu@mediatek.com> | |
5 | * Sascha Hauer <s.hauer@pengutronix.de> | |
b7cf0053 | 6 | * Dawei Chien <dawei.chien@mediatek.com> |
6cf7f002 | 7 | * Louis Yu <louis.yu@mediatek.com> |
a92db1c8 SH |
8 | */ |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/nvmem-consumer.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/of_address.h> | |
b7cf0053 | 18 | #include <linux/of_device.h> |
a92db1c8 SH |
19 | #include <linux/platform_device.h> |
20 | #include <linux/slab.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/thermal.h> | |
23 | #include <linux/reset.h> | |
24 | #include <linux/types.h> | |
a92db1c8 | 25 | |
24e21d9f FW |
26 | #include "thermal_hwmon.h" |
27 | ||
a92db1c8 | 28 | /* AUXADC Registers */ |
a92db1c8 SH |
29 | #define AUXADC_CON1_SET_V 0x008 |
30 | #define AUXADC_CON1_CLR_V 0x00c | |
31 | #define AUXADC_CON2_V 0x010 | |
32 | #define AUXADC_DATA(channel) (0x14 + (channel) * 4) | |
a92db1c8 SH |
33 | |
34 | #define APMIXED_SYS_TS_CON1 0x604 | |
35 | ||
36 | /* Thermal Controller Registers */ | |
37 | #define TEMP_MONCTL0 0x000 | |
38 | #define TEMP_MONCTL1 0x004 | |
39 | #define TEMP_MONCTL2 0x008 | |
40 | #define TEMP_MONIDET0 0x014 | |
41 | #define TEMP_MONIDET1 0x018 | |
42 | #define TEMP_MSRCTL0 0x038 | |
89945047 | 43 | #define TEMP_MSRCTL1 0x03c |
a92db1c8 SH |
44 | #define TEMP_AHBPOLL 0x040 |
45 | #define TEMP_AHBTO 0x044 | |
46 | #define TEMP_ADCPNP0 0x048 | |
47 | #define TEMP_ADCPNP1 0x04c | |
48 | #define TEMP_ADCPNP2 0x050 | |
49 | #define TEMP_ADCPNP3 0x0b4 | |
50 | ||
51 | #define TEMP_ADCMUX 0x054 | |
52 | #define TEMP_ADCEN 0x060 | |
53 | #define TEMP_PNPMUXADDR 0x064 | |
54 | #define TEMP_ADCMUXADDR 0x068 | |
55 | #define TEMP_ADCENADDR 0x074 | |
56 | #define TEMP_ADCVALIDADDR 0x078 | |
57 | #define TEMP_ADCVOLTADDR 0x07c | |
58 | #define TEMP_RDCTRL 0x080 | |
59 | #define TEMP_ADCVALIDMASK 0x084 | |
60 | #define TEMP_ADCVOLTAGESHIFT 0x088 | |
61 | #define TEMP_ADCWRITECTRL 0x08c | |
62 | #define TEMP_MSR0 0x090 | |
63 | #define TEMP_MSR1 0x094 | |
64 | #define TEMP_MSR2 0x098 | |
65 | #define TEMP_MSR3 0x0B8 | |
66 | ||
67 | #define TEMP_SPARE0 0x0f0 | |
68 | ||
a4ffe6b5 MK |
69 | #define TEMP_ADCPNP0_1 0x148 |
70 | #define TEMP_ADCPNP1_1 0x14c | |
71 | #define TEMP_ADCPNP2_1 0x150 | |
72 | #define TEMP_MSR0_1 0x190 | |
73 | #define TEMP_MSR1_1 0x194 | |
74 | #define TEMP_MSR2_1 0x198 | |
75 | #define TEMP_ADCPNP3_1 0x1b4 | |
76 | #define TEMP_MSR3_1 0x1B8 | |
77 | ||
a92db1c8 SH |
78 | #define PTPCORESEL 0x400 |
79 | ||
80 | #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) | |
81 | ||
eb4fc33e | 82 | #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16) |
a92db1c8 SH |
83 | #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) |
84 | ||
85 | #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) | |
86 | ||
87 | #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) | |
88 | #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) | |
89 | ||
90 | #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) | |
91 | #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) | |
92 | ||
b7cf0053 | 93 | /* MT8173 thermal sensors */ |
a92db1c8 SH |
94 | #define MT8173_TS1 0 |
95 | #define MT8173_TS2 1 | |
96 | #define MT8173_TS3 2 | |
97 | #define MT8173_TS4 3 | |
98 | #define MT8173_TSABB 4 | |
99 | ||
100 | /* AUXADC channel 11 is used for the temperature sensors */ | |
101 | #define MT8173_TEMP_AUXADC_CHANNEL 11 | |
102 | ||
103 | /* The total number of temperature sensors in the MT8173 */ | |
104 | #define MT8173_NUM_SENSORS 5 | |
105 | ||
106 | /* The number of banks in the MT8173 */ | |
107 | #define MT8173_NUM_ZONES 4 | |
108 | ||
109 | /* The number of sensing points per bank */ | |
110 | #define MT8173_NUM_SENSORS_PER_ZONE 4 | |
111 | ||
bd940394 MK |
112 | /* The number of controller in the MT8173 */ |
113 | #define MT8173_NUM_CONTROLLER 1 | |
114 | ||
f8451476 MK |
115 | /* The calibration coefficient of sensor */ |
116 | #define MT8173_CALIBRATION 165 | |
117 | ||
b7cf0053 | 118 | /* |
119 | * Layout of the fuses providing the calibration data | |
a4ffe6b5 MK |
120 | * These macros could be used for MT8183, MT8173, MT2701, and MT2712. |
121 | * MT8183 has 6 sensors and needs 6 VTS calibration data. | |
0a068993 LY |
122 | * MT8173 has 5 sensors and needs 5 VTS calibration data. |
123 | * MT2701 has 3 sensors and needs 3 VTS calibration data. | |
124 | * MT2712 has 4 sensors and needs 4 VTS calibration data. | |
b7cf0053 | 125 | */ |
54bf1e5a HY |
126 | #define CALIB_BUF0_VALID_V1 BIT(0) |
127 | #define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff) | |
128 | #define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff) | |
129 | #define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff) | |
130 | #define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff) | |
131 | #define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff) | |
132 | #define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff) | |
133 | #define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff) | |
134 | #define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f) | |
135 | #define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f) | |
136 | #define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1) | |
137 | #define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1) | |
1d081945 | 138 | |
89945047 HY |
139 | /* |
140 | * Layout of the fuses providing the calibration data | |
141 | * These macros could be used for MT7622. | |
142 | */ | |
143 | #define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff) | |
144 | #define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff) | |
145 | #define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f) | |
146 | #define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f) | |
147 | #define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff) | |
148 | #define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff) | |
149 | #define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff) | |
150 | #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) | |
151 | #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) | |
1d081945 MK |
152 | |
153 | enum { | |
154 | VTS1, | |
155 | VTS2, | |
156 | VTS3, | |
157 | VTS4, | |
a4ffe6b5 | 158 | VTS5, |
1d081945 MK |
159 | VTSABB, |
160 | MAX_NUM_VTS, | |
161 | }; | |
a92db1c8 | 162 | |
89945047 HY |
163 | enum mtk_thermal_version { |
164 | MTK_THERMAL_V1 = 1, | |
165 | MTK_THERMAL_V2, | |
166 | }; | |
167 | ||
b7cf0053 | 168 | /* MT2701 thermal sensors */ |
169 | #define MT2701_TS1 0 | |
170 | #define MT2701_TS2 1 | |
171 | #define MT2701_TSABB 2 | |
172 | ||
173 | /* AUXADC channel 11 is used for the temperature sensors */ | |
174 | #define MT2701_TEMP_AUXADC_CHANNEL 11 | |
175 | ||
176 | /* The total number of temperature sensors in the MT2701 */ | |
177 | #define MT2701_NUM_SENSORS 3 | |
178 | ||
b7cf0053 | 179 | /* The number of sensing points per bank */ |
180 | #define MT2701_NUM_SENSORS_PER_ZONE 3 | |
181 | ||
bd940394 MK |
182 | /* The number of controller in the MT2701 */ |
183 | #define MT2701_NUM_CONTROLLER 1 | |
184 | ||
f8451476 MK |
185 | /* The calibration coefficient of sensor */ |
186 | #define MT2701_CALIBRATION 165 | |
187 | ||
6cf7f002 LY |
188 | /* MT2712 thermal sensors */ |
189 | #define MT2712_TS1 0 | |
190 | #define MT2712_TS2 1 | |
191 | #define MT2712_TS3 2 | |
192 | #define MT2712_TS4 3 | |
193 | ||
194 | /* AUXADC channel 11 is used for the temperature sensors */ | |
195 | #define MT2712_TEMP_AUXADC_CHANNEL 11 | |
196 | ||
197 | /* The total number of temperature sensors in the MT2712 */ | |
198 | #define MT2712_NUM_SENSORS 4 | |
199 | ||
200 | /* The number of sensing points per bank */ | |
201 | #define MT2712_NUM_SENSORS_PER_ZONE 4 | |
202 | ||
bd940394 MK |
203 | /* The number of controller in the MT2712 */ |
204 | #define MT2712_NUM_CONTROLLER 1 | |
205 | ||
f8451476 MK |
206 | /* The calibration coefficient of sensor */ |
207 | #define MT2712_CALIBRATION 165 | |
208 | ||
3966be3c SW |
209 | #define MT7622_TEMP_AUXADC_CHANNEL 11 |
210 | #define MT7622_NUM_SENSORS 1 | |
211 | #define MT7622_NUM_ZONES 1 | |
212 | #define MT7622_NUM_SENSORS_PER_ZONE 1 | |
213 | #define MT7622_TS1 0 | |
bd940394 | 214 | #define MT7622_NUM_CONTROLLER 1 |
3966be3c | 215 | |
fb4d83f2 PHS |
216 | /* The maximum number of banks */ |
217 | #define MAX_NUM_ZONES 8 | |
218 | ||
f8451476 MK |
219 | /* The calibration coefficient of sensor */ |
220 | #define MT7622_CALIBRATION 165 | |
221 | ||
a4ffe6b5 MK |
222 | /* MT8183 thermal sensors */ |
223 | #define MT8183_TS1 0 | |
224 | #define MT8183_TS2 1 | |
225 | #define MT8183_TS3 2 | |
226 | #define MT8183_TS4 3 | |
227 | #define MT8183_TS5 4 | |
228 | #define MT8183_TSABB 5 | |
229 | ||
230 | /* AUXADC channel is used for the temperature sensors */ | |
231 | #define MT8183_TEMP_AUXADC_CHANNEL 11 | |
232 | ||
233 | /* The total number of temperature sensors in the MT8183 */ | |
234 | #define MT8183_NUM_SENSORS 6 | |
235 | ||
14533a5a MK |
236 | /* The number of banks in the MT8183 */ |
237 | #define MT8183_NUM_ZONES 1 | |
238 | ||
a4ffe6b5 MK |
239 | /* The number of sensing points per bank */ |
240 | #define MT8183_NUM_SENSORS_PER_ZONE 6 | |
241 | ||
242 | /* The number of controller in the MT8183 */ | |
243 | #define MT8183_NUM_CONTROLLER 2 | |
244 | ||
245 | /* The calibration coefficient of sensor */ | |
246 | #define MT8183_CALIBRATION 153 | |
247 | ||
a92db1c8 SH |
248 | struct mtk_thermal; |
249 | ||
b7cf0053 | 250 | struct thermal_bank_cfg { |
251 | unsigned int num_sensors; | |
252 | const int *sensors; | |
253 | }; | |
254 | ||
a92db1c8 SH |
255 | struct mtk_thermal_bank { |
256 | struct mtk_thermal *mt; | |
257 | int id; | |
258 | }; | |
259 | ||
b7cf0053 | 260 | struct mtk_thermal_data { |
261 | s32 num_banks; | |
262 | s32 num_sensors; | |
263 | s32 auxadc_channel; | |
1d081945 | 264 | const int *vts_index; |
b7cf0053 | 265 | const int *sensor_mux_values; |
266 | const int *msr; | |
267 | const int *adcpnp; | |
f8451476 | 268 | const int cali_val; |
bd940394 MK |
269 | const int num_controller; |
270 | const int *controller_offset; | |
cb82aaad | 271 | bool need_switch_bank; |
fb4d83f2 | 272 | struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; |
89945047 | 273 | enum mtk_thermal_version version; |
b7cf0053 | 274 | }; |
275 | ||
a92db1c8 SH |
276 | struct mtk_thermal { |
277 | struct device *dev; | |
278 | void __iomem *thermal_base; | |
279 | ||
280 | struct clk *clk_peri_therm; | |
281 | struct clk *clk_auxadc; | |
eb4fc33e | 282 | /* lock: for getting and putting banks */ |
a92db1c8 SH |
283 | struct mutex lock; |
284 | ||
285 | /* Calibration values */ | |
286 | s32 adc_ge; | |
89945047 | 287 | s32 adc_oe; |
a92db1c8 SH |
288 | s32 degc_cali; |
289 | s32 o_slope; | |
89945047 | 290 | s32 o_slope_sign; |
1d081945 | 291 | s32 vts[MAX_NUM_VTS]; |
a92db1c8 | 292 | |
b7cf0053 | 293 | const struct mtk_thermal_data *conf; |
fb4d83f2 | 294 | struct mtk_thermal_bank banks[MAX_NUM_ZONES]; |
a92db1c8 SH |
295 | }; |
296 | ||
a4ffe6b5 MK |
297 | /* MT8183 thermal sensor data */ |
298 | static const int mt8183_bank_data[MT8183_NUM_SENSORS] = { | |
299 | MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB | |
300 | }; | |
301 | ||
302 | static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = { | |
303 | TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1 | |
304 | }; | |
305 | ||
306 | static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = { | |
307 | TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1, | |
308 | TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1 | |
309 | }; | |
310 | ||
311 | static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 }; | |
312 | static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100}; | |
313 | ||
314 | static const int mt8183_vts_index[MT8183_NUM_SENSORS] = { | |
315 | VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB | |
316 | }; | |
317 | ||
b7cf0053 | 318 | /* MT8173 thermal sensor data */ |
992edf39 | 319 | static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = { |
b7cf0053 | 320 | { MT8173_TS2, MT8173_TS3 }, |
321 | { MT8173_TS2, MT8173_TS4 }, | |
322 | { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, | |
323 | { MT8173_TS2 }, | |
a92db1c8 SH |
324 | }; |
325 | ||
992edf39 | 326 | static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = { |
05d7839a | 327 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 |
b7cf0053 | 328 | }; |
a92db1c8 | 329 | |
992edf39 | 330 | static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = { |
b7cf0053 | 331 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 |
332 | }; | |
333 | ||
992edf39 | 334 | static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; |
bd940394 | 335 | static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, }; |
b7cf0053 | 336 | |
1d081945 MK |
337 | static const int mt8173_vts_index[MT8173_NUM_SENSORS] = { |
338 | VTS1, VTS2, VTS3, VTS4, VTSABB | |
339 | }; | |
340 | ||
b7cf0053 | 341 | /* MT2701 thermal sensor data */ |
992edf39 | 342 | static const int mt2701_bank_data[MT2701_NUM_SENSORS] = { |
b7cf0053 | 343 | MT2701_TS1, MT2701_TS2, MT2701_TSABB |
344 | }; | |
345 | ||
992edf39 | 346 | static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = { |
b7cf0053 | 347 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 |
348 | }; | |
349 | ||
992edf39 | 350 | static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = { |
b7cf0053 | 351 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 |
352 | }; | |
353 | ||
992edf39 | 354 | static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 }; |
bd940394 | 355 | static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, }; |
b7cf0053 | 356 | |
1d081945 MK |
357 | static const int mt2701_vts_index[MT2701_NUM_SENSORS] = { |
358 | VTS1, VTS2, VTS3 | |
359 | }; | |
360 | ||
6cf7f002 LY |
361 | /* MT2712 thermal sensor data */ |
362 | static const int mt2712_bank_data[MT2712_NUM_SENSORS] = { | |
363 | MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4 | |
364 | }; | |
365 | ||
366 | static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = { | |
367 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 | |
368 | }; | |
369 | ||
370 | static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = { | |
371 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 | |
372 | }; | |
373 | ||
374 | static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 }; | |
bd940394 | 375 | static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, }; |
6cf7f002 | 376 | |
1d081945 MK |
377 | static const int mt2712_vts_index[MT2712_NUM_SENSORS] = { |
378 | VTS1, VTS2, VTS3, VTS4 | |
379 | }; | |
380 | ||
3966be3c SW |
381 | /* MT7622 thermal sensor data */ |
382 | static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, }; | |
383 | static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; | |
384 | static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; | |
385 | static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, }; | |
1d081945 | 386 | static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; |
bd940394 | 387 | static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; |
3966be3c | 388 | |
3772bb42 | 389 | /* |
a92db1c8 SH |
390 | * The MT8173 thermal controller has four banks. Each bank can read up to |
391 | * four temperature sensors simultaneously. The MT8173 has a total of 5 | |
392 | * temperature sensors. We use each bank to measure a certain area of the | |
393 | * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple | |
394 | * areas, hence is used in different banks. | |
395 | * | |
396 | * The thermal core only gets the maximum temperature of all banks, so | |
397 | * the bank concept wouldn't be necessary here. However, the SVS (Smart | |
398 | * Voltage Scaling) unit makes its decisions based on the same bank | |
399 | * data, and this indeed needs the temperatures of the individual banks | |
400 | * for making better decisions. | |
401 | */ | |
b7cf0053 | 402 | static const struct mtk_thermal_data mt8173_thermal_data = { |
403 | .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL, | |
404 | .num_banks = MT8173_NUM_ZONES, | |
405 | .num_sensors = MT8173_NUM_SENSORS, | |
1d081945 | 406 | .vts_index = mt8173_vts_index, |
f8451476 | 407 | .cali_val = MT8173_CALIBRATION, |
bd940394 MK |
408 | .num_controller = MT8173_NUM_CONTROLLER, |
409 | .controller_offset = mt8173_tc_offset, | |
cb82aaad | 410 | .need_switch_bank = true, |
b7cf0053 | 411 | .bank_data = { |
412 | { | |
413 | .num_sensors = 2, | |
414 | .sensors = mt8173_bank_data[0], | |
415 | }, { | |
416 | .num_sensors = 2, | |
417 | .sensors = mt8173_bank_data[1], | |
418 | }, { | |
419 | .num_sensors = 3, | |
420 | .sensors = mt8173_bank_data[2], | |
421 | }, { | |
422 | .num_sensors = 1, | |
423 | .sensors = mt8173_bank_data[3], | |
424 | }, | |
a92db1c8 | 425 | }, |
b7cf0053 | 426 | .msr = mt8173_msr, |
427 | .adcpnp = mt8173_adcpnp, | |
428 | .sensor_mux_values = mt8173_mux_values, | |
89945047 | 429 | .version = MTK_THERMAL_V1, |
a92db1c8 SH |
430 | }; |
431 | ||
3772bb42 | 432 | /* |
b7cf0053 | 433 | * The MT2701 thermal controller has one bank, which can read up to |
434 | * three temperature sensors simultaneously. The MT2701 has a total of 3 | |
435 | * temperature sensors. | |
436 | * | |
437 | * The thermal core only gets the maximum temperature of this one bank, | |
438 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart | |
439 | * Voltage Scaling) unit makes its decisions based on the same bank | |
440 | * data. | |
441 | */ | |
442 | static const struct mtk_thermal_data mt2701_thermal_data = { | |
443 | .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL, | |
444 | .num_banks = 1, | |
445 | .num_sensors = MT2701_NUM_SENSORS, | |
1d081945 | 446 | .vts_index = mt2701_vts_index, |
f8451476 | 447 | .cali_val = MT2701_CALIBRATION, |
bd940394 MK |
448 | .num_controller = MT2701_NUM_CONTROLLER, |
449 | .controller_offset = mt2701_tc_offset, | |
cb82aaad | 450 | .need_switch_bank = true, |
b7cf0053 | 451 | .bank_data = { |
452 | { | |
453 | .num_sensors = 3, | |
454 | .sensors = mt2701_bank_data, | |
455 | }, | |
a92db1c8 | 456 | }, |
b7cf0053 | 457 | .msr = mt2701_msr, |
458 | .adcpnp = mt2701_adcpnp, | |
459 | .sensor_mux_values = mt2701_mux_values, | |
89945047 | 460 | .version = MTK_THERMAL_V1, |
a92db1c8 SH |
461 | }; |
462 | ||
3772bb42 | 463 | /* |
6cf7f002 LY |
464 | * The MT2712 thermal controller has one bank, which can read up to |
465 | * four temperature sensors simultaneously. The MT2712 has a total of 4 | |
466 | * temperature sensors. | |
467 | * | |
468 | * The thermal core only gets the maximum temperature of this one bank, | |
469 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart | |
470 | * Voltage Scaling) unit makes its decisions based on the same bank | |
471 | * data. | |
472 | */ | |
473 | static const struct mtk_thermal_data mt2712_thermal_data = { | |
474 | .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL, | |
475 | .num_banks = 1, | |
476 | .num_sensors = MT2712_NUM_SENSORS, | |
1d081945 | 477 | .vts_index = mt2712_vts_index, |
f8451476 | 478 | .cali_val = MT2712_CALIBRATION, |
bd940394 MK |
479 | .num_controller = MT2712_NUM_CONTROLLER, |
480 | .controller_offset = mt2712_tc_offset, | |
cb82aaad | 481 | .need_switch_bank = true, |
6cf7f002 LY |
482 | .bank_data = { |
483 | { | |
484 | .num_sensors = 4, | |
485 | .sensors = mt2712_bank_data, | |
486 | }, | |
487 | }, | |
488 | .msr = mt2712_msr, | |
489 | .adcpnp = mt2712_adcpnp, | |
490 | .sensor_mux_values = mt2712_mux_values, | |
89945047 | 491 | .version = MTK_THERMAL_V1, |
6cf7f002 LY |
492 | }; |
493 | ||
3966be3c SW |
494 | /* |
495 | * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data | |
496 | * access. | |
497 | */ | |
498 | static const struct mtk_thermal_data mt7622_thermal_data = { | |
499 | .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL, | |
500 | .num_banks = MT7622_NUM_ZONES, | |
501 | .num_sensors = MT7622_NUM_SENSORS, | |
1d081945 | 502 | .vts_index = mt7622_vts_index, |
f8451476 | 503 | .cali_val = MT7622_CALIBRATION, |
bd940394 MK |
504 | .num_controller = MT7622_NUM_CONTROLLER, |
505 | .controller_offset = mt7622_tc_offset, | |
cb82aaad | 506 | .need_switch_bank = true, |
3966be3c SW |
507 | .bank_data = { |
508 | { | |
509 | .num_sensors = 1, | |
510 | .sensors = mt7622_bank_data, | |
511 | }, | |
512 | }, | |
513 | .msr = mt7622_msr, | |
514 | .adcpnp = mt7622_adcpnp, | |
515 | .sensor_mux_values = mt7622_mux_values, | |
89945047 | 516 | .version = MTK_THERMAL_V2, |
3966be3c SW |
517 | }; |
518 | ||
3772bb42 | 519 | /* |
a4ffe6b5 MK |
520 | * The MT8183 thermal controller has one bank for the current SW framework. |
521 | * The MT8183 has a total of 6 temperature sensors. | |
522 | * There are two thermal controller to control the six sensor. | |
523 | * The first one bind 2 sensor, and the other bind 4 sensors. | |
524 | * The thermal core only gets the maximum temperature of all sensor, so | |
525 | * the bank concept wouldn't be necessary here. However, the SVS (Smart | |
526 | * Voltage Scaling) unit makes its decisions based on the same bank | |
527 | * data, and this indeed needs the temperatures of the individual banks | |
528 | * for making better decisions. | |
529 | */ | |
a4ffe6b5 MK |
530 | static const struct mtk_thermal_data mt8183_thermal_data = { |
531 | .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL, | |
14533a5a | 532 | .num_banks = MT8183_NUM_ZONES, |
a4ffe6b5 MK |
533 | .num_sensors = MT8183_NUM_SENSORS, |
534 | .vts_index = mt8183_vts_index, | |
535 | .cali_val = MT8183_CALIBRATION, | |
536 | .num_controller = MT8183_NUM_CONTROLLER, | |
537 | .controller_offset = mt8183_tc_offset, | |
538 | .need_switch_bank = false, | |
539 | .bank_data = { | |
540 | { | |
541 | .num_sensors = 6, | |
542 | .sensors = mt8183_bank_data, | |
543 | }, | |
544 | }, | |
545 | ||
546 | .msr = mt8183_msr, | |
547 | .adcpnp = mt8183_adcpnp, | |
548 | .sensor_mux_values = mt8183_mux_values, | |
89945047 | 549 | .version = MTK_THERMAL_V1, |
a4ffe6b5 MK |
550 | }; |
551 | ||
a92db1c8 SH |
552 | /** |
553 | * raw_to_mcelsius - convert a raw ADC value to mcelsius | |
3772bb42 AK |
554 | * @mt: The thermal controller |
555 | * @sensno: sensor number | |
a92db1c8 SH |
556 | * @raw: raw ADC value |
557 | * | |
558 | * This converts the raw ADC value to mcelsius using the SoC specific | |
559 | * calibration constants | |
560 | */ | |
54bf1e5a | 561 | static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw) |
a92db1c8 SH |
562 | { |
563 | s32 tmp; | |
564 | ||
565 | raw &= 0xfff; | |
566 | ||
567 | tmp = 203450520 << 3; | |
f8451476 | 568 | tmp /= mt->conf->cali_val + mt->o_slope; |
a92db1c8 SH |
569 | tmp /= 10000 + mt->adc_ge; |
570 | tmp *= raw - mt->vts[sensno] - 3350; | |
571 | tmp >>= 3; | |
572 | ||
573 | return mt->degc_cali * 500 - tmp; | |
574 | } | |
575 | ||
89945047 HY |
576 | static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw) |
577 | { | |
c310e546 CIK |
578 | s32 format_1; |
579 | s32 format_2; | |
580 | s32 g_oe; | |
581 | s32 g_gain; | |
582 | s32 g_x_roomt; | |
583 | s32 tmp; | |
89945047 HY |
584 | |
585 | if (raw == 0) | |
586 | return 0; | |
587 | ||
588 | raw &= 0xfff; | |
589 | g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12); | |
590 | g_oe = mt->adc_oe - 512; | |
591 | format_1 = mt->vts[VTS2] + 3105 - g_oe; | |
592 | format_2 = (mt->degc_cali * 10) >> 1; | |
593 | g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain; | |
594 | ||
595 | tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt; | |
596 | tmp = tmp * 10 * 100 / 11; | |
597 | ||
598 | if (mt->o_slope_sign == 0) | |
599 | tmp = tmp / (165 - mt->o_slope); | |
600 | else | |
601 | tmp = tmp / (165 + mt->o_slope); | |
602 | ||
603 | return (format_2 - tmp) * 100; | |
604 | } | |
605 | ||
a92db1c8 SH |
606 | /** |
607 | * mtk_thermal_get_bank - get bank | |
608 | * @bank: The bank | |
609 | * | |
610 | * The bank registers are banked, we have to select a bank in the | |
611 | * PTPCORESEL register to access it. | |
612 | */ | |
613 | static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) | |
614 | { | |
615 | struct mtk_thermal *mt = bank->mt; | |
616 | u32 val; | |
617 | ||
cb82aaad MK |
618 | if (mt->conf->need_switch_bank) { |
619 | mutex_lock(&mt->lock); | |
a92db1c8 | 620 | |
cb82aaad MK |
621 | val = readl(mt->thermal_base + PTPCORESEL); |
622 | val &= ~0xf; | |
623 | val |= bank->id; | |
624 | writel(val, mt->thermal_base + PTPCORESEL); | |
625 | } | |
a92db1c8 SH |
626 | } |
627 | ||
628 | /** | |
629 | * mtk_thermal_put_bank - release bank | |
630 | * @bank: The bank | |
631 | * | |
632 | * release a bank previously taken with mtk_thermal_get_bank, | |
633 | */ | |
634 | static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) | |
635 | { | |
636 | struct mtk_thermal *mt = bank->mt; | |
637 | ||
cb82aaad MK |
638 | if (mt->conf->need_switch_bank) |
639 | mutex_unlock(&mt->lock); | |
a92db1c8 SH |
640 | } |
641 | ||
642 | /** | |
643 | * mtk_thermal_bank_temperature - get the temperature of a bank | |
644 | * @bank: The bank | |
645 | * | |
646 | * The temperature of a bank is considered the maximum temperature of | |
647 | * the sensors associated to the bank. | |
648 | */ | |
649 | static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) | |
650 | { | |
651 | struct mtk_thermal *mt = bank->mt; | |
b7cf0053 | 652 | const struct mtk_thermal_data *conf = mt->conf; |
eb4fc33e | 653 | int i, temp = INT_MIN, max = INT_MIN; |
a92db1c8 SH |
654 | u32 raw; |
655 | ||
b7cf0053 | 656 | for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { |
a8f62f18 | 657 | raw = readl(mt->thermal_base + conf->msr[i]); |
a92db1c8 | 658 | |
89945047 HY |
659 | if (mt->conf->version == MTK_THERMAL_V1) { |
660 | temp = raw_to_mcelsius_v1( | |
661 | mt, conf->bank_data[bank->id].sensors[i], raw); | |
662 | } else { | |
663 | temp = raw_to_mcelsius_v2( | |
664 | mt, conf->bank_data[bank->id].sensors[i], raw); | |
665 | } | |
a92db1c8 SH |
666 | |
667 | /* | |
668 | * The first read of a sensor often contains very high bogus | |
669 | * temperature value. Filter these out so that the system does | |
670 | * not immediately shut down. | |
671 | */ | |
672 | if (temp > 200000) | |
673 | temp = 0; | |
674 | ||
675 | if (temp > max) | |
676 | max = temp; | |
677 | } | |
678 | ||
679 | return max; | |
680 | } | |
681 | ||
682 | static int mtk_read_temp(void *data, int *temperature) | |
683 | { | |
684 | struct mtk_thermal *mt = data; | |
685 | int i; | |
686 | int tempmax = INT_MIN; | |
687 | ||
b7cf0053 | 688 | for (i = 0; i < mt->conf->num_banks; i++) { |
a92db1c8 SH |
689 | struct mtk_thermal_bank *bank = &mt->banks[i]; |
690 | ||
691 | mtk_thermal_get_bank(bank); | |
692 | ||
693 | tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); | |
694 | ||
695 | mtk_thermal_put_bank(bank); | |
696 | } | |
697 | ||
698 | *temperature = tempmax; | |
699 | ||
700 | return 0; | |
701 | } | |
702 | ||
703 | static const struct thermal_zone_of_device_ops mtk_thermal_ops = { | |
704 | .get_temp = mtk_read_temp, | |
705 | }; | |
706 | ||
707 | static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, | |
bd940394 MK |
708 | u32 apmixed_phys_base, u32 auxadc_phys_base, |
709 | int ctrl_id) | |
a92db1c8 SH |
710 | { |
711 | struct mtk_thermal_bank *bank = &mt->banks[num]; | |
b7cf0053 | 712 | const struct mtk_thermal_data *conf = mt->conf; |
a92db1c8 SH |
713 | int i; |
714 | ||
bd940394 MK |
715 | int offset = mt->conf->controller_offset[ctrl_id]; |
716 | void __iomem *controller_base = mt->thermal_base + offset; | |
717 | ||
a92db1c8 SH |
718 | bank->id = num; |
719 | bank->mt = mt; | |
720 | ||
721 | mtk_thermal_get_bank(bank); | |
722 | ||
723 | /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ | |
bd940394 | 724 | writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1); |
a92db1c8 SH |
725 | |
726 | /* | |
727 | * filt interval is 1 * 46.540us = 46.54us, | |
728 | * sen interval is 429 * 46.540us = 19.96ms | |
729 | */ | |
730 | writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | | |
731 | TEMP_MONCTL2_SENSOR_INTERVAL(429), | |
bd940394 | 732 | controller_base + TEMP_MONCTL2); |
a92db1c8 SH |
733 | |
734 | /* poll is set to 10u */ | |
735 | writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), | |
bd940394 | 736 | controller_base + TEMP_AHBPOLL); |
a92db1c8 SH |
737 | |
738 | /* temperature sampling control, 1 sample */ | |
bd940394 | 739 | writel(0x0, controller_base + TEMP_MSRCTL0); |
a92db1c8 SH |
740 | |
741 | /* exceed this polling time, IRQ would be inserted */ | |
bd940394 | 742 | writel(0xffffffff, controller_base + TEMP_AHBTO); |
a92db1c8 SH |
743 | |
744 | /* number of interrupts per event, 1 is enough */ | |
bd940394 MK |
745 | writel(0x0, controller_base + TEMP_MONIDET0); |
746 | writel(0x0, controller_base + TEMP_MONIDET1); | |
a92db1c8 SH |
747 | |
748 | /* | |
749 | * The MT8173 thermal controller does not have its own ADC. Instead it | |
750 | * uses AHB bus accesses to control the AUXADC. To do this the thermal | |
751 | * controller has to be programmed with the physical addresses of the | |
752 | * AUXADC registers and with the various bit positions in the AUXADC. | |
753 | * Also the thermal controller controls a mux in the APMIXEDSYS register | |
754 | * space. | |
755 | */ | |
756 | ||
757 | /* | |
758 | * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) | |
759 | * automatically by hw | |
760 | */ | |
bd940394 | 761 | writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX); |
a92db1c8 SH |
762 | |
763 | /* AHB address for auxadc mux selection */ | |
764 | writel(auxadc_phys_base + AUXADC_CON1_CLR_V, | |
bd940394 | 765 | controller_base + TEMP_ADCMUXADDR); |
a92db1c8 | 766 | |
89945047 HY |
767 | if (mt->conf->version == MTK_THERMAL_V1) { |
768 | /* AHB address for pnp sensor mux selection */ | |
769 | writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, | |
770 | controller_base + TEMP_PNPMUXADDR); | |
771 | } | |
a92db1c8 SH |
772 | |
773 | /* AHB value for auxadc enable */ | |
bd940394 | 774 | writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN); |
a92db1c8 SH |
775 | |
776 | /* AHB address for auxadc enable (channel 0 immediate mode selected) */ | |
777 | writel(auxadc_phys_base + AUXADC_CON1_SET_V, | |
bd940394 | 778 | controller_base + TEMP_ADCENADDR); |
a92db1c8 SH |
779 | |
780 | /* AHB address for auxadc valid bit */ | |
b7cf0053 | 781 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
bd940394 | 782 | controller_base + TEMP_ADCVALIDADDR); |
a92db1c8 SH |
783 | |
784 | /* AHB address for auxadc voltage output */ | |
b7cf0053 | 785 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
bd940394 | 786 | controller_base + TEMP_ADCVOLTADDR); |
a92db1c8 SH |
787 | |
788 | /* read valid & voltage are at the same register */ | |
bd940394 | 789 | writel(0x0, controller_base + TEMP_RDCTRL); |
a92db1c8 SH |
790 | |
791 | /* indicate where the valid bit is */ | |
792 | writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), | |
bd940394 | 793 | controller_base + TEMP_ADCVALIDMASK); |
a92db1c8 SH |
794 | |
795 | /* no shift */ | |
bd940394 | 796 | writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT); |
a92db1c8 SH |
797 | |
798 | /* enable auxadc mux write transaction */ | |
799 | writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, | |
bd940394 | 800 | controller_base + TEMP_ADCWRITECTRL); |
a92db1c8 | 801 | |
b7cf0053 | 802 | for (i = 0; i < conf->bank_data[num].num_sensors; i++) |
803 | writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]], | |
a8f62f18 | 804 | mt->thermal_base + conf->adcpnp[i]); |
a92db1c8 | 805 | |
b7cf0053 | 806 | writel((1 << conf->bank_data[num].num_sensors) - 1, |
bd940394 | 807 | controller_base + TEMP_MONCTL0); |
a92db1c8 | 808 | |
eb4fc33e EV |
809 | writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | |
810 | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, | |
bd940394 | 811 | controller_base + TEMP_ADCWRITECTRL); |
a92db1c8 SH |
812 | |
813 | mtk_thermal_put_bank(bank); | |
814 | } | |
815 | ||
816 | static u64 of_get_phys_base(struct device_node *np) | |
817 | { | |
818 | u64 size64; | |
819 | const __be32 *regaddr_p; | |
820 | ||
821 | regaddr_p = of_get_address(np, 0, &size64, NULL); | |
822 | if (!regaddr_p) | |
823 | return OF_BAD_ADDR; | |
824 | ||
825 | return of_translate_address(np, regaddr_p); | |
826 | } | |
827 | ||
54bf1e5a HY |
828 | static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf) |
829 | { | |
830 | int i; | |
831 | ||
832 | if (!(buf[0] & CALIB_BUF0_VALID_V1)) | |
833 | return -EINVAL; | |
834 | ||
835 | mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]); | |
836 | ||
837 | for (i = 0; i < mt->conf->num_sensors; i++) { | |
838 | switch (mt->conf->vts_index[i]) { | |
839 | case VTS1: | |
840 | mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]); | |
841 | break; | |
842 | case VTS2: | |
843 | mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]); | |
844 | break; | |
845 | case VTS3: | |
846 | mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]); | |
847 | break; | |
848 | case VTS4: | |
849 | mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]); | |
850 | break; | |
851 | case VTS5: | |
852 | mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]); | |
853 | break; | |
854 | case VTSABB: | |
855 | mt->vts[VTSABB] = | |
856 | CALIB_BUF2_VTS_TSABB_V1(buf[2]); | |
857 | break; | |
858 | default: | |
859 | break; | |
860 | } | |
861 | } | |
862 | ||
863 | mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]); | |
864 | if (CALIB_BUF1_ID_V1(buf[1]) & | |
865 | CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0])) | |
866 | mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]); | |
867 | else | |
868 | mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]); | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
89945047 HY |
873 | static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf) |
874 | { | |
875 | if (!CALIB_BUF1_VALID_V2(buf[1])) | |
876 | return -EINVAL; | |
877 | ||
878 | mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]); | |
879 | mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]); | |
880 | mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]); | |
881 | mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]); | |
882 | mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]); | |
883 | mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]); | |
884 | mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]); | |
885 | mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]); | |
886 | ||
887 | return 0; | |
888 | } | |
889 | ||
eb4fc33e EV |
890 | static int mtk_thermal_get_calibration_data(struct device *dev, |
891 | struct mtk_thermal *mt) | |
a92db1c8 SH |
892 | { |
893 | struct nvmem_cell *cell; | |
894 | u32 *buf; | |
895 | size_t len; | |
896 | int i, ret = 0; | |
897 | ||
898 | /* Start with default values */ | |
899 | mt->adc_ge = 512; | |
b7cf0053 | 900 | for (i = 0; i < mt->conf->num_sensors; i++) |
a92db1c8 SH |
901 | mt->vts[i] = 260; |
902 | mt->degc_cali = 40; | |
903 | mt->o_slope = 0; | |
904 | ||
905 | cell = nvmem_cell_get(dev, "calibration-data"); | |
906 | if (IS_ERR(cell)) { | |
907 | if (PTR_ERR(cell) == -EPROBE_DEFER) | |
908 | return PTR_ERR(cell); | |
909 | return 0; | |
910 | } | |
911 | ||
912 | buf = (u32 *)nvmem_cell_read(cell, &len); | |
913 | ||
914 | nvmem_cell_put(cell); | |
915 | ||
916 | if (IS_ERR(buf)) | |
917 | return PTR_ERR(buf); | |
918 | ||
919 | if (len < 3 * sizeof(u32)) { | |
920 | dev_warn(dev, "invalid calibration data\n"); | |
921 | ret = -EINVAL; | |
922 | goto out; | |
923 | } | |
924 | ||
89945047 HY |
925 | if (mt->conf->version == MTK_THERMAL_V1) |
926 | ret = mtk_thermal_extract_efuse_v1(mt, buf); | |
927 | else | |
928 | ret = mtk_thermal_extract_efuse_v2(mt, buf); | |
1d081945 | 929 | |
89945047 | 930 | if (ret) { |
a92db1c8 | 931 | dev_info(dev, "Device not calibrated, using default calibration values\n"); |
89945047 | 932 | ret = 0; |
a92db1c8 SH |
933 | } |
934 | ||
935 | out: | |
936 | kfree(buf); | |
937 | ||
938 | return ret; | |
939 | } | |
940 | ||
b7cf0053 | 941 | static const struct of_device_id mtk_thermal_of_match[] = { |
942 | { | |
943 | .compatible = "mediatek,mt8173-thermal", | |
944 | .data = (void *)&mt8173_thermal_data, | |
945 | }, | |
946 | { | |
947 | .compatible = "mediatek,mt2701-thermal", | |
948 | .data = (void *)&mt2701_thermal_data, | |
6cf7f002 LY |
949 | }, |
950 | { | |
951 | .compatible = "mediatek,mt2712-thermal", | |
952 | .data = (void *)&mt2712_thermal_data, | |
3966be3c SW |
953 | }, |
954 | { | |
955 | .compatible = "mediatek,mt7622-thermal", | |
956 | .data = (void *)&mt7622_thermal_data, | |
a4ffe6b5 MK |
957 | }, |
958 | { | |
959 | .compatible = "mediatek,mt8183-thermal", | |
960 | .data = (void *)&mt8183_thermal_data, | |
b7cf0053 | 961 | }, { |
962 | }, | |
963 | }; | |
964 | MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); | |
965 | ||
89945047 HY |
966 | static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base) |
967 | { | |
968 | int tmp; | |
969 | ||
970 | tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1); | |
971 | tmp &= ~(0x37); | |
972 | tmp |= 0x1; | |
973 | writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1); | |
974 | udelay(200); | |
975 | } | |
976 | ||
977 | static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt, | |
978 | void __iomem *auxadc_base) | |
979 | { | |
980 | int tmp; | |
981 | ||
982 | writel(0x800, auxadc_base + AUXADC_CON1_SET_V); | |
983 | writel(0x1, mt->thermal_base + TEMP_MONCTL0); | |
984 | tmp = readl(mt->thermal_base + TEMP_MSRCTL1); | |
985 | writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1); | |
986 | } | |
987 | ||
a92db1c8 SH |
988 | static int mtk_thermal_probe(struct platform_device *pdev) |
989 | { | |
bd940394 | 990 | int ret, i, ctrl_id; |
a92db1c8 SH |
991 | struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; |
992 | struct mtk_thermal *mt; | |
993 | struct resource *res; | |
994 | u64 auxadc_phys_base, apmixed_phys_base; | |
1f6b0889 | 995 | struct thermal_zone_device *tzdev; |
89945047 | 996 | void __iomem *apmixed_base, *auxadc_base; |
a92db1c8 SH |
997 | |
998 | mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); | |
999 | if (!mt) | |
1000 | return -ENOMEM; | |
1001 | ||
9efc58df | 1002 | mt->conf = of_device_get_match_data(&pdev->dev); |
b7cf0053 | 1003 | |
a92db1c8 SH |
1004 | mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); |
1005 | if (IS_ERR(mt->clk_peri_therm)) | |
1006 | return PTR_ERR(mt->clk_peri_therm); | |
1007 | ||
1008 | mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); | |
1009 | if (IS_ERR(mt->clk_auxadc)) | |
1010 | return PTR_ERR(mt->clk_auxadc); | |
1011 | ||
1012 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1013 | mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); | |
1014 | if (IS_ERR(mt->thermal_base)) | |
1015 | return PTR_ERR(mt->thermal_base); | |
1016 | ||
1017 | ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); | |
1018 | if (ret) | |
1019 | return ret; | |
1020 | ||
1021 | mutex_init(&mt->lock); | |
1022 | ||
1023 | mt->dev = &pdev->dev; | |
1024 | ||
1025 | auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); | |
1026 | if (!auxadc) { | |
1027 | dev_err(&pdev->dev, "missing auxadc node\n"); | |
1028 | return -ENODEV; | |
1029 | } | |
1030 | ||
89945047 | 1031 | auxadc_base = of_iomap(auxadc, 0); |
a92db1c8 SH |
1032 | auxadc_phys_base = of_get_phys_base(auxadc); |
1033 | ||
1034 | of_node_put(auxadc); | |
1035 | ||
1036 | if (auxadc_phys_base == OF_BAD_ADDR) { | |
1037 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); | |
1038 | return -EINVAL; | |
1039 | } | |
1040 | ||
1041 | apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); | |
1042 | if (!apmixedsys) { | |
1043 | dev_err(&pdev->dev, "missing apmixedsys node\n"); | |
1044 | return -ENODEV; | |
1045 | } | |
1046 | ||
89945047 | 1047 | apmixed_base = of_iomap(apmixedsys, 0); |
a92db1c8 SH |
1048 | apmixed_phys_base = of_get_phys_base(apmixedsys); |
1049 | ||
1050 | of_node_put(apmixedsys); | |
1051 | ||
1052 | if (apmixed_phys_base == OF_BAD_ADDR) { | |
1053 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); | |
1054 | return -EINVAL; | |
1055 | } | |
1056 | ||
703456ba | 1057 | ret = device_reset_optional(&pdev->dev); |
6760f3f7 LY |
1058 | if (ret) |
1059 | return ret; | |
1060 | ||
a92db1c8 SH |
1061 | ret = clk_prepare_enable(mt->clk_auxadc); |
1062 | if (ret) { | |
1063 | dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); | |
1064 | return ret; | |
1065 | } | |
1066 | ||
a92db1c8 SH |
1067 | ret = clk_prepare_enable(mt->clk_peri_therm); |
1068 | if (ret) { | |
1069 | dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); | |
1070 | goto err_disable_clk_auxadc; | |
1071 | } | |
1072 | ||
89945047 HY |
1073 | if (mt->conf->version == MTK_THERMAL_V2) { |
1074 | mtk_thermal_turn_on_buffer(apmixed_base); | |
1075 | mtk_thermal_release_periodic_ts(mt, auxadc_base); | |
1076 | } | |
1077 | ||
bd940394 MK |
1078 | for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) |
1079 | for (i = 0; i < mt->conf->num_banks; i++) | |
1080 | mtk_thermal_init_bank(mt, i, apmixed_phys_base, | |
1081 | auxadc_phys_base, ctrl_id); | |
a92db1c8 SH |
1082 | |
1083 | platform_set_drvdata(pdev, mt); | |
1084 | ||
1f6b0889 AL |
1085 | tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt, |
1086 | &mtk_thermal_ops); | |
1087 | if (IS_ERR(tzdev)) { | |
1088 | ret = PTR_ERR(tzdev); | |
1089 | goto err_disable_clk_peri_therm; | |
1090 | } | |
a92db1c8 | 1091 | |
24e21d9f FW |
1092 | ret = devm_thermal_add_hwmon_sysfs(tzdev); |
1093 | if (ret) | |
1094 | dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs"); | |
1095 | ||
a92db1c8 SH |
1096 | return 0; |
1097 | ||
1f6b0889 AL |
1098 | err_disable_clk_peri_therm: |
1099 | clk_disable_unprepare(mt->clk_peri_therm); | |
a92db1c8 SH |
1100 | err_disable_clk_auxadc: |
1101 | clk_disable_unprepare(mt->clk_auxadc); | |
1102 | ||
1103 | return ret; | |
1104 | } | |
1105 | ||
1106 | static int mtk_thermal_remove(struct platform_device *pdev) | |
1107 | { | |
1108 | struct mtk_thermal *mt = platform_get_drvdata(pdev); | |
1109 | ||
a92db1c8 SH |
1110 | clk_disable_unprepare(mt->clk_peri_therm); |
1111 | clk_disable_unprepare(mt->clk_auxadc); | |
1112 | ||
1113 | return 0; | |
1114 | } | |
1115 | ||
a92db1c8 SH |
1116 | static struct platform_driver mtk_thermal_driver = { |
1117 | .probe = mtk_thermal_probe, | |
1118 | .remove = mtk_thermal_remove, | |
1119 | .driver = { | |
f45ce7ee | 1120 | .name = "mtk-thermal", |
a92db1c8 SH |
1121 | .of_match_table = mtk_thermal_of_match, |
1122 | }, | |
1123 | }; | |
1124 | ||
1125 | module_platform_driver(mtk_thermal_driver); | |
1126 | ||
a4ffe6b5 | 1127 | MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>"); |
6cf7f002 | 1128 | MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>"); |
b7cf0053 | 1129 | MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>"); |
9ebfb4e0 | 1130 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); |
a92db1c8 SH |
1131 | MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); |
1132 | MODULE_DESCRIPTION("Mediatek thermal driver"); | |
1133 | MODULE_LICENSE("GPL v2"); |