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a92db1c8 SH |
1 | /* |
2 | * Copyright (c) 2015 MediaTek Inc. | |
3 | * Author: Hanyi Wu <hanyi.wu@mediatek.com> | |
4 | * Sascha Hauer <s.hauer@pengutronix.de> | |
b7cf0053 | 5 | * Dawei Chien <dawei.chien@mediatek.com> |
a92db1c8 SH |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/clk.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/nvmem-consumer.h> | |
23 | #include <linux/of.h> | |
24 | #include <linux/of_address.h> | |
b7cf0053 | 25 | #include <linux/of_device.h> |
a92db1c8 SH |
26 | #include <linux/platform_device.h> |
27 | #include <linux/slab.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/thermal.h> | |
30 | #include <linux/reset.h> | |
31 | #include <linux/types.h> | |
a92db1c8 SH |
32 | |
33 | /* AUXADC Registers */ | |
34 | #define AUXADC_CON0_V 0x000 | |
35 | #define AUXADC_CON1_V 0x004 | |
36 | #define AUXADC_CON1_SET_V 0x008 | |
37 | #define AUXADC_CON1_CLR_V 0x00c | |
38 | #define AUXADC_CON2_V 0x010 | |
39 | #define AUXADC_DATA(channel) (0x14 + (channel) * 4) | |
40 | #define AUXADC_MISC_V 0x094 | |
41 | ||
42 | #define AUXADC_CON1_CHANNEL(x) BIT(x) | |
43 | ||
44 | #define APMIXED_SYS_TS_CON1 0x604 | |
45 | ||
46 | /* Thermal Controller Registers */ | |
47 | #define TEMP_MONCTL0 0x000 | |
48 | #define TEMP_MONCTL1 0x004 | |
49 | #define TEMP_MONCTL2 0x008 | |
50 | #define TEMP_MONIDET0 0x014 | |
51 | #define TEMP_MONIDET1 0x018 | |
52 | #define TEMP_MSRCTL0 0x038 | |
53 | #define TEMP_AHBPOLL 0x040 | |
54 | #define TEMP_AHBTO 0x044 | |
55 | #define TEMP_ADCPNP0 0x048 | |
56 | #define TEMP_ADCPNP1 0x04c | |
57 | #define TEMP_ADCPNP2 0x050 | |
58 | #define TEMP_ADCPNP3 0x0b4 | |
59 | ||
60 | #define TEMP_ADCMUX 0x054 | |
61 | #define TEMP_ADCEN 0x060 | |
62 | #define TEMP_PNPMUXADDR 0x064 | |
63 | #define TEMP_ADCMUXADDR 0x068 | |
64 | #define TEMP_ADCENADDR 0x074 | |
65 | #define TEMP_ADCVALIDADDR 0x078 | |
66 | #define TEMP_ADCVOLTADDR 0x07c | |
67 | #define TEMP_RDCTRL 0x080 | |
68 | #define TEMP_ADCVALIDMASK 0x084 | |
69 | #define TEMP_ADCVOLTAGESHIFT 0x088 | |
70 | #define TEMP_ADCWRITECTRL 0x08c | |
71 | #define TEMP_MSR0 0x090 | |
72 | #define TEMP_MSR1 0x094 | |
73 | #define TEMP_MSR2 0x098 | |
74 | #define TEMP_MSR3 0x0B8 | |
75 | ||
76 | #define TEMP_SPARE0 0x0f0 | |
77 | ||
78 | #define PTPCORESEL 0x400 | |
79 | ||
80 | #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) | |
81 | ||
eb4fc33e | 82 | #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16) |
a92db1c8 SH |
83 | #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) |
84 | ||
85 | #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) | |
86 | ||
87 | #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) | |
88 | #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) | |
89 | ||
90 | #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) | |
91 | #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) | |
92 | ||
b7cf0053 | 93 | /* MT8173 thermal sensors */ |
a92db1c8 SH |
94 | #define MT8173_TS1 0 |
95 | #define MT8173_TS2 1 | |
96 | #define MT8173_TS3 2 | |
97 | #define MT8173_TS4 3 | |
98 | #define MT8173_TSABB 4 | |
99 | ||
100 | /* AUXADC channel 11 is used for the temperature sensors */ | |
101 | #define MT8173_TEMP_AUXADC_CHANNEL 11 | |
102 | ||
103 | /* The total number of temperature sensors in the MT8173 */ | |
104 | #define MT8173_NUM_SENSORS 5 | |
105 | ||
106 | /* The number of banks in the MT8173 */ | |
107 | #define MT8173_NUM_ZONES 4 | |
108 | ||
109 | /* The number of sensing points per bank */ | |
110 | #define MT8173_NUM_SENSORS_PER_ZONE 4 | |
111 | ||
b7cf0053 | 112 | /* |
113 | * Layout of the fuses providing the calibration data | |
114 | * These macros could be used for both MT8173 and MT2701. | |
115 | * MT8173 has five sensors and need five VTS calibration data, | |
116 | * and MT2701 has three sensors and need three VTS calibration data. | |
117 | */ | |
eb4fc33e EV |
118 | #define MT8173_CALIB_BUF0_VALID BIT(0) |
119 | #define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff) | |
120 | #define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff) | |
121 | #define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8) & 0x1ff) | |
122 | #define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0) & 0x1ff) | |
123 | #define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23) & 0x1ff) | |
124 | #define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14) & 0x1ff) | |
125 | #define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f) | |
126 | #define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f) | |
a92db1c8 | 127 | |
b7cf0053 | 128 | /* MT2701 thermal sensors */ |
129 | #define MT2701_TS1 0 | |
130 | #define MT2701_TS2 1 | |
131 | #define MT2701_TSABB 2 | |
132 | ||
133 | /* AUXADC channel 11 is used for the temperature sensors */ | |
134 | #define MT2701_TEMP_AUXADC_CHANNEL 11 | |
135 | ||
136 | /* The total number of temperature sensors in the MT2701 */ | |
137 | #define MT2701_NUM_SENSORS 3 | |
138 | ||
a92db1c8 SH |
139 | #define THERMAL_NAME "mtk-thermal" |
140 | ||
b7cf0053 | 141 | /* The number of sensing points per bank */ |
142 | #define MT2701_NUM_SENSORS_PER_ZONE 3 | |
143 | ||
a92db1c8 SH |
144 | struct mtk_thermal; |
145 | ||
b7cf0053 | 146 | struct thermal_bank_cfg { |
147 | unsigned int num_sensors; | |
148 | const int *sensors; | |
149 | }; | |
150 | ||
a92db1c8 SH |
151 | struct mtk_thermal_bank { |
152 | struct mtk_thermal *mt; | |
153 | int id; | |
154 | }; | |
155 | ||
b7cf0053 | 156 | struct mtk_thermal_data { |
157 | s32 num_banks; | |
158 | s32 num_sensors; | |
159 | s32 auxadc_channel; | |
160 | const int *sensor_mux_values; | |
161 | const int *msr; | |
162 | const int *adcpnp; | |
163 | struct thermal_bank_cfg bank_data[]; | |
164 | }; | |
165 | ||
a92db1c8 SH |
166 | struct mtk_thermal { |
167 | struct device *dev; | |
168 | void __iomem *thermal_base; | |
169 | ||
170 | struct clk *clk_peri_therm; | |
171 | struct clk *clk_auxadc; | |
eb4fc33e | 172 | /* lock: for getting and putting banks */ |
a92db1c8 SH |
173 | struct mutex lock; |
174 | ||
175 | /* Calibration values */ | |
176 | s32 adc_ge; | |
177 | s32 degc_cali; | |
178 | s32 o_slope; | |
179 | s32 vts[MT8173_NUM_SENSORS]; | |
180 | ||
b7cf0053 | 181 | const struct mtk_thermal_data *conf; |
182 | struct mtk_thermal_bank banks[]; | |
a92db1c8 SH |
183 | }; |
184 | ||
b7cf0053 | 185 | /* MT8173 thermal sensor data */ |
186 | const int mt8173_bank_data[MT8173_NUM_ZONES][3] = { | |
187 | { MT8173_TS2, MT8173_TS3 }, | |
188 | { MT8173_TS2, MT8173_TS4 }, | |
189 | { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, | |
190 | { MT8173_TS2 }, | |
a92db1c8 SH |
191 | }; |
192 | ||
b7cf0053 | 193 | const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = { |
194 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR2 | |
195 | }; | |
a92db1c8 | 196 | |
b7cf0053 | 197 | const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = { |
198 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 | |
199 | }; | |
200 | ||
201 | const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; | |
202 | ||
203 | /* MT2701 thermal sensor data */ | |
204 | const int mt2701_bank_data[MT2701_NUM_SENSORS] = { | |
205 | MT2701_TS1, MT2701_TS2, MT2701_TSABB | |
206 | }; | |
207 | ||
208 | const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = { | |
209 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 | |
210 | }; | |
211 | ||
212 | const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = { | |
213 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 | |
214 | }; | |
215 | ||
216 | const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 }; | |
217 | ||
218 | /** | |
a92db1c8 SH |
219 | * The MT8173 thermal controller has four banks. Each bank can read up to |
220 | * four temperature sensors simultaneously. The MT8173 has a total of 5 | |
221 | * temperature sensors. We use each bank to measure a certain area of the | |
222 | * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple | |
223 | * areas, hence is used in different banks. | |
224 | * | |
225 | * The thermal core only gets the maximum temperature of all banks, so | |
226 | * the bank concept wouldn't be necessary here. However, the SVS (Smart | |
227 | * Voltage Scaling) unit makes its decisions based on the same bank | |
228 | * data, and this indeed needs the temperatures of the individual banks | |
229 | * for making better decisions. | |
230 | */ | |
b7cf0053 | 231 | static const struct mtk_thermal_data mt8173_thermal_data = { |
232 | .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL, | |
233 | .num_banks = MT8173_NUM_ZONES, | |
234 | .num_sensors = MT8173_NUM_SENSORS, | |
235 | .bank_data = { | |
236 | { | |
237 | .num_sensors = 2, | |
238 | .sensors = mt8173_bank_data[0], | |
239 | }, { | |
240 | .num_sensors = 2, | |
241 | .sensors = mt8173_bank_data[1], | |
242 | }, { | |
243 | .num_sensors = 3, | |
244 | .sensors = mt8173_bank_data[2], | |
245 | }, { | |
246 | .num_sensors = 1, | |
247 | .sensors = mt8173_bank_data[3], | |
248 | }, | |
a92db1c8 | 249 | }, |
b7cf0053 | 250 | .msr = mt8173_msr, |
251 | .adcpnp = mt8173_adcpnp, | |
252 | .sensor_mux_values = mt8173_mux_values, | |
a92db1c8 SH |
253 | }; |
254 | ||
b7cf0053 | 255 | /** |
256 | * The MT2701 thermal controller has one bank, which can read up to | |
257 | * three temperature sensors simultaneously. The MT2701 has a total of 3 | |
258 | * temperature sensors. | |
259 | * | |
260 | * The thermal core only gets the maximum temperature of this one bank, | |
261 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart | |
262 | * Voltage Scaling) unit makes its decisions based on the same bank | |
263 | * data. | |
264 | */ | |
265 | static const struct mtk_thermal_data mt2701_thermal_data = { | |
266 | .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL, | |
267 | .num_banks = 1, | |
268 | .num_sensors = MT2701_NUM_SENSORS, | |
269 | .bank_data = { | |
270 | { | |
271 | .num_sensors = 3, | |
272 | .sensors = mt2701_bank_data, | |
273 | }, | |
a92db1c8 | 274 | }, |
b7cf0053 | 275 | .msr = mt2701_msr, |
276 | .adcpnp = mt2701_adcpnp, | |
277 | .sensor_mux_values = mt2701_mux_values, | |
a92db1c8 SH |
278 | }; |
279 | ||
280 | /** | |
281 | * raw_to_mcelsius - convert a raw ADC value to mcelsius | |
282 | * @mt: The thermal controller | |
283 | * @raw: raw ADC value | |
284 | * | |
285 | * This converts the raw ADC value to mcelsius using the SoC specific | |
286 | * calibration constants | |
287 | */ | |
288 | static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) | |
289 | { | |
290 | s32 tmp; | |
291 | ||
292 | raw &= 0xfff; | |
293 | ||
294 | tmp = 203450520 << 3; | |
295 | tmp /= 165 + mt->o_slope; | |
296 | tmp /= 10000 + mt->adc_ge; | |
297 | tmp *= raw - mt->vts[sensno] - 3350; | |
298 | tmp >>= 3; | |
299 | ||
300 | return mt->degc_cali * 500 - tmp; | |
301 | } | |
302 | ||
303 | /** | |
304 | * mtk_thermal_get_bank - get bank | |
305 | * @bank: The bank | |
306 | * | |
307 | * The bank registers are banked, we have to select a bank in the | |
308 | * PTPCORESEL register to access it. | |
309 | */ | |
310 | static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) | |
311 | { | |
312 | struct mtk_thermal *mt = bank->mt; | |
313 | u32 val; | |
314 | ||
315 | mutex_lock(&mt->lock); | |
316 | ||
317 | val = readl(mt->thermal_base + PTPCORESEL); | |
318 | val &= ~0xf; | |
319 | val |= bank->id; | |
320 | writel(val, mt->thermal_base + PTPCORESEL); | |
321 | } | |
322 | ||
323 | /** | |
324 | * mtk_thermal_put_bank - release bank | |
325 | * @bank: The bank | |
326 | * | |
327 | * release a bank previously taken with mtk_thermal_get_bank, | |
328 | */ | |
329 | static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) | |
330 | { | |
331 | struct mtk_thermal *mt = bank->mt; | |
332 | ||
333 | mutex_unlock(&mt->lock); | |
334 | } | |
335 | ||
336 | /** | |
337 | * mtk_thermal_bank_temperature - get the temperature of a bank | |
338 | * @bank: The bank | |
339 | * | |
340 | * The temperature of a bank is considered the maximum temperature of | |
341 | * the sensors associated to the bank. | |
342 | */ | |
343 | static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) | |
344 | { | |
345 | struct mtk_thermal *mt = bank->mt; | |
b7cf0053 | 346 | const struct mtk_thermal_data *conf = mt->conf; |
eb4fc33e | 347 | int i, temp = INT_MIN, max = INT_MIN; |
a92db1c8 SH |
348 | u32 raw; |
349 | ||
b7cf0053 | 350 | for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { |
351 | raw = readl(mt->thermal_base + conf->msr[i]); | |
a92db1c8 | 352 | |
b7cf0053 | 353 | temp = raw_to_mcelsius(mt, |
354 | conf->bank_data[bank->id].sensors[i], | |
355 | raw); | |
a92db1c8 SH |
356 | |
357 | /* | |
358 | * The first read of a sensor often contains very high bogus | |
359 | * temperature value. Filter these out so that the system does | |
360 | * not immediately shut down. | |
361 | */ | |
362 | if (temp > 200000) | |
363 | temp = 0; | |
364 | ||
365 | if (temp > max) | |
366 | max = temp; | |
367 | } | |
368 | ||
369 | return max; | |
370 | } | |
371 | ||
372 | static int mtk_read_temp(void *data, int *temperature) | |
373 | { | |
374 | struct mtk_thermal *mt = data; | |
375 | int i; | |
376 | int tempmax = INT_MIN; | |
377 | ||
b7cf0053 | 378 | for (i = 0; i < mt->conf->num_banks; i++) { |
a92db1c8 SH |
379 | struct mtk_thermal_bank *bank = &mt->banks[i]; |
380 | ||
381 | mtk_thermal_get_bank(bank); | |
382 | ||
383 | tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); | |
384 | ||
385 | mtk_thermal_put_bank(bank); | |
386 | } | |
387 | ||
388 | *temperature = tempmax; | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
393 | static const struct thermal_zone_of_device_ops mtk_thermal_ops = { | |
394 | .get_temp = mtk_read_temp, | |
395 | }; | |
396 | ||
397 | static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, | |
eb4fc33e | 398 | u32 apmixed_phys_base, u32 auxadc_phys_base) |
a92db1c8 SH |
399 | { |
400 | struct mtk_thermal_bank *bank = &mt->banks[num]; | |
b7cf0053 | 401 | const struct mtk_thermal_data *conf = mt->conf; |
a92db1c8 SH |
402 | int i; |
403 | ||
404 | bank->id = num; | |
405 | bank->mt = mt; | |
406 | ||
407 | mtk_thermal_get_bank(bank); | |
408 | ||
409 | /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ | |
410 | writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); | |
411 | ||
412 | /* | |
413 | * filt interval is 1 * 46.540us = 46.54us, | |
414 | * sen interval is 429 * 46.540us = 19.96ms | |
415 | */ | |
416 | writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | | |
417 | TEMP_MONCTL2_SENSOR_INTERVAL(429), | |
418 | mt->thermal_base + TEMP_MONCTL2); | |
419 | ||
420 | /* poll is set to 10u */ | |
421 | writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), | |
eb4fc33e | 422 | mt->thermal_base + TEMP_AHBPOLL); |
a92db1c8 SH |
423 | |
424 | /* temperature sampling control, 1 sample */ | |
425 | writel(0x0, mt->thermal_base + TEMP_MSRCTL0); | |
426 | ||
427 | /* exceed this polling time, IRQ would be inserted */ | |
428 | writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); | |
429 | ||
430 | /* number of interrupts per event, 1 is enough */ | |
431 | writel(0x0, mt->thermal_base + TEMP_MONIDET0); | |
432 | writel(0x0, mt->thermal_base + TEMP_MONIDET1); | |
433 | ||
434 | /* | |
435 | * The MT8173 thermal controller does not have its own ADC. Instead it | |
436 | * uses AHB bus accesses to control the AUXADC. To do this the thermal | |
437 | * controller has to be programmed with the physical addresses of the | |
438 | * AUXADC registers and with the various bit positions in the AUXADC. | |
439 | * Also the thermal controller controls a mux in the APMIXEDSYS register | |
440 | * space. | |
441 | */ | |
442 | ||
443 | /* | |
444 | * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) | |
445 | * automatically by hw | |
446 | */ | |
b7cf0053 | 447 | writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCMUX); |
a92db1c8 SH |
448 | |
449 | /* AHB address for auxadc mux selection */ | |
450 | writel(auxadc_phys_base + AUXADC_CON1_CLR_V, | |
eb4fc33e | 451 | mt->thermal_base + TEMP_ADCMUXADDR); |
a92db1c8 SH |
452 | |
453 | /* AHB address for pnp sensor mux selection */ | |
454 | writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, | |
eb4fc33e | 455 | mt->thermal_base + TEMP_PNPMUXADDR); |
a92db1c8 SH |
456 | |
457 | /* AHB value for auxadc enable */ | |
b7cf0053 | 458 | writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCEN); |
a92db1c8 SH |
459 | |
460 | /* AHB address for auxadc enable (channel 0 immediate mode selected) */ | |
461 | writel(auxadc_phys_base + AUXADC_CON1_SET_V, | |
eb4fc33e | 462 | mt->thermal_base + TEMP_ADCENADDR); |
a92db1c8 SH |
463 | |
464 | /* AHB address for auxadc valid bit */ | |
b7cf0053 | 465 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
eb4fc33e | 466 | mt->thermal_base + TEMP_ADCVALIDADDR); |
a92db1c8 SH |
467 | |
468 | /* AHB address for auxadc voltage output */ | |
b7cf0053 | 469 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
eb4fc33e | 470 | mt->thermal_base + TEMP_ADCVOLTADDR); |
a92db1c8 SH |
471 | |
472 | /* read valid & voltage are at the same register */ | |
473 | writel(0x0, mt->thermal_base + TEMP_RDCTRL); | |
474 | ||
475 | /* indicate where the valid bit is */ | |
476 | writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), | |
eb4fc33e | 477 | mt->thermal_base + TEMP_ADCVALIDMASK); |
a92db1c8 SH |
478 | |
479 | /* no shift */ | |
480 | writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); | |
481 | ||
482 | /* enable auxadc mux write transaction */ | |
483 | writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, | |
eb4fc33e | 484 | mt->thermal_base + TEMP_ADCWRITECTRL); |
a92db1c8 | 485 | |
b7cf0053 | 486 | for (i = 0; i < conf->bank_data[num].num_sensors; i++) |
487 | writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]], | |
488 | mt->thermal_base + conf->adcpnp[i]); | |
a92db1c8 | 489 | |
b7cf0053 | 490 | writel((1 << conf->bank_data[num].num_sensors) - 1, |
491 | mt->thermal_base + TEMP_MONCTL0); | |
a92db1c8 | 492 | |
eb4fc33e EV |
493 | writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | |
494 | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, | |
495 | mt->thermal_base + TEMP_ADCWRITECTRL); | |
a92db1c8 SH |
496 | |
497 | mtk_thermal_put_bank(bank); | |
498 | } | |
499 | ||
500 | static u64 of_get_phys_base(struct device_node *np) | |
501 | { | |
502 | u64 size64; | |
503 | const __be32 *regaddr_p; | |
504 | ||
505 | regaddr_p = of_get_address(np, 0, &size64, NULL); | |
506 | if (!regaddr_p) | |
507 | return OF_BAD_ADDR; | |
508 | ||
509 | return of_translate_address(np, regaddr_p); | |
510 | } | |
511 | ||
eb4fc33e EV |
512 | static int mtk_thermal_get_calibration_data(struct device *dev, |
513 | struct mtk_thermal *mt) | |
a92db1c8 SH |
514 | { |
515 | struct nvmem_cell *cell; | |
516 | u32 *buf; | |
517 | size_t len; | |
518 | int i, ret = 0; | |
519 | ||
520 | /* Start with default values */ | |
521 | mt->adc_ge = 512; | |
b7cf0053 | 522 | for (i = 0; i < mt->conf->num_sensors; i++) |
a92db1c8 SH |
523 | mt->vts[i] = 260; |
524 | mt->degc_cali = 40; | |
525 | mt->o_slope = 0; | |
526 | ||
527 | cell = nvmem_cell_get(dev, "calibration-data"); | |
528 | if (IS_ERR(cell)) { | |
529 | if (PTR_ERR(cell) == -EPROBE_DEFER) | |
530 | return PTR_ERR(cell); | |
531 | return 0; | |
532 | } | |
533 | ||
534 | buf = (u32 *)nvmem_cell_read(cell, &len); | |
535 | ||
536 | nvmem_cell_put(cell); | |
537 | ||
538 | if (IS_ERR(buf)) | |
539 | return PTR_ERR(buf); | |
540 | ||
541 | if (len < 3 * sizeof(u32)) { | |
542 | dev_warn(dev, "invalid calibration data\n"); | |
543 | ret = -EINVAL; | |
544 | goto out; | |
545 | } | |
546 | ||
547 | if (buf[0] & MT8173_CALIB_BUF0_VALID) { | |
548 | mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); | |
549 | mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); | |
550 | mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); | |
551 | mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); | |
552 | mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); | |
553 | mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); | |
554 | mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); | |
555 | mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); | |
556 | } else { | |
557 | dev_info(dev, "Device not calibrated, using default calibration values\n"); | |
558 | } | |
559 | ||
560 | out: | |
561 | kfree(buf); | |
562 | ||
563 | return ret; | |
564 | } | |
565 | ||
b7cf0053 | 566 | static const struct of_device_id mtk_thermal_of_match[] = { |
567 | { | |
568 | .compatible = "mediatek,mt8173-thermal", | |
569 | .data = (void *)&mt8173_thermal_data, | |
570 | }, | |
571 | { | |
572 | .compatible = "mediatek,mt2701-thermal", | |
573 | .data = (void *)&mt2701_thermal_data, | |
574 | }, { | |
575 | }, | |
576 | }; | |
577 | MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); | |
578 | ||
a92db1c8 SH |
579 | static int mtk_thermal_probe(struct platform_device *pdev) |
580 | { | |
581 | int ret, i; | |
582 | struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; | |
583 | struct mtk_thermal *mt; | |
584 | struct resource *res; | |
b7cf0053 | 585 | const struct of_device_id *of_id; |
a92db1c8 | 586 | u64 auxadc_phys_base, apmixed_phys_base; |
1f6b0889 | 587 | struct thermal_zone_device *tzdev; |
a92db1c8 SH |
588 | |
589 | mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); | |
590 | if (!mt) | |
591 | return -ENOMEM; | |
592 | ||
b7cf0053 | 593 | of_id = of_match_device(mtk_thermal_of_match, &pdev->dev); |
594 | if (of_id) | |
595 | mt->conf = (const struct mtk_thermal_data *)of_id->data; | |
596 | ||
a92db1c8 SH |
597 | mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); |
598 | if (IS_ERR(mt->clk_peri_therm)) | |
599 | return PTR_ERR(mt->clk_peri_therm); | |
600 | ||
601 | mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); | |
602 | if (IS_ERR(mt->clk_auxadc)) | |
603 | return PTR_ERR(mt->clk_auxadc); | |
604 | ||
605 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
606 | mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); | |
607 | if (IS_ERR(mt->thermal_base)) | |
608 | return PTR_ERR(mt->thermal_base); | |
609 | ||
610 | ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); | |
611 | if (ret) | |
612 | return ret; | |
613 | ||
614 | mutex_init(&mt->lock); | |
615 | ||
616 | mt->dev = &pdev->dev; | |
617 | ||
618 | auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); | |
619 | if (!auxadc) { | |
620 | dev_err(&pdev->dev, "missing auxadc node\n"); | |
621 | return -ENODEV; | |
622 | } | |
623 | ||
624 | auxadc_phys_base = of_get_phys_base(auxadc); | |
625 | ||
626 | of_node_put(auxadc); | |
627 | ||
628 | if (auxadc_phys_base == OF_BAD_ADDR) { | |
629 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); | |
630 | return -EINVAL; | |
631 | } | |
632 | ||
633 | apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); | |
634 | if (!apmixedsys) { | |
635 | dev_err(&pdev->dev, "missing apmixedsys node\n"); | |
636 | return -ENODEV; | |
637 | } | |
638 | ||
639 | apmixed_phys_base = of_get_phys_base(apmixedsys); | |
640 | ||
641 | of_node_put(apmixedsys); | |
642 | ||
643 | if (apmixed_phys_base == OF_BAD_ADDR) { | |
644 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); | |
645 | return -EINVAL; | |
646 | } | |
647 | ||
648 | ret = clk_prepare_enable(mt->clk_auxadc); | |
649 | if (ret) { | |
650 | dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); | |
651 | return ret; | |
652 | } | |
653 | ||
654 | ret = device_reset(&pdev->dev); | |
655 | if (ret) | |
656 | goto err_disable_clk_auxadc; | |
657 | ||
658 | ret = clk_prepare_enable(mt->clk_peri_therm); | |
659 | if (ret) { | |
660 | dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); | |
661 | goto err_disable_clk_auxadc; | |
662 | } | |
663 | ||
b7cf0053 | 664 | for (i = 0; i < mt->conf->num_banks; i++) |
eb4fc33e EV |
665 | mtk_thermal_init_bank(mt, i, apmixed_phys_base, |
666 | auxadc_phys_base); | |
a92db1c8 SH |
667 | |
668 | platform_set_drvdata(pdev, mt); | |
669 | ||
1f6b0889 AL |
670 | tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt, |
671 | &mtk_thermal_ops); | |
672 | if (IS_ERR(tzdev)) { | |
673 | ret = PTR_ERR(tzdev); | |
674 | goto err_disable_clk_peri_therm; | |
675 | } | |
a92db1c8 SH |
676 | |
677 | return 0; | |
678 | ||
1f6b0889 AL |
679 | err_disable_clk_peri_therm: |
680 | clk_disable_unprepare(mt->clk_peri_therm); | |
a92db1c8 SH |
681 | err_disable_clk_auxadc: |
682 | clk_disable_unprepare(mt->clk_auxadc); | |
683 | ||
684 | return ret; | |
685 | } | |
686 | ||
687 | static int mtk_thermal_remove(struct platform_device *pdev) | |
688 | { | |
689 | struct mtk_thermal *mt = platform_get_drvdata(pdev); | |
690 | ||
a92db1c8 SH |
691 | clk_disable_unprepare(mt->clk_peri_therm); |
692 | clk_disable_unprepare(mt->clk_auxadc); | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
a92db1c8 SH |
697 | static struct platform_driver mtk_thermal_driver = { |
698 | .probe = mtk_thermal_probe, | |
699 | .remove = mtk_thermal_remove, | |
700 | .driver = { | |
701 | .name = THERMAL_NAME, | |
702 | .of_match_table = mtk_thermal_of_match, | |
703 | }, | |
704 | }; | |
705 | ||
706 | module_platform_driver(mtk_thermal_driver); | |
707 | ||
b7cf0053 | 708 | MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>"); |
9ebfb4e0 | 709 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); |
a92db1c8 SH |
710 | MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); |
711 | MODULE_DESCRIPTION("Mediatek thermal driver"); | |
712 | MODULE_LICENSE("GPL v2"); |