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Merge tag 'soc-for-linus-3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...
[linux-2.6-block.git] / drivers / thermal / exynos_thermal.c
CommitLineData
9d97e5c8 1/*
c48cbba6 2 * exynos_thermal.c - Samsung EXYNOS TMU (Thermal Management Unit)
9d97e5c8
DK		 3 *
4 * Copyright (C) 2011 Samsung Electronics
5 * Donggeun Kim <dg77.kim@samsung.com>
c48cbba6 6 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
9d97e5c8
DK		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/err.h>
26#include <linux/kernel.h>
27#include <linux/slab.h>
28#include <linux/platform_device.h>
29#include <linux/interrupt.h>
30#include <linux/clk.h>
31#include <linux/workqueue.h>
32#include <linux/sysfs.h>
33#include <linux/kobject.h>
34#include <linux/io.h>
35#include <linux/mutex.h>
c48cbba6 36#include <linux/platform_data/exynos_thermal.h>
7e0b55e6
ADK		 37#include <linux/thermal.h>
38#include <linux/cpufreq.h>
39#include <linux/cpu_cooling.h>
f22d9c03
ADK		 40#include <linux/of.h>
41
f22d9c03
ADK		 42/* Exynos generic registers */
43#define EXYNOS_TMU_REG_TRIMINFO 0x0
44#define EXYNOS_TMU_REG_CONTROL 0x20
45#define EXYNOS_TMU_REG_STATUS 0x28
46#define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
47#define EXYNOS_TMU_REG_INTEN 0x70
48#define EXYNOS_TMU_REG_INTSTAT 0x74
49#define EXYNOS_TMU_REG_INTCLEAR 0x78
50
51#define EXYNOS_TMU_TRIM_TEMP_MASK 0xff
52#define EXYNOS_TMU_GAIN_SHIFT 8
53#define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
54#define EXYNOS_TMU_CORE_ON 3
55#define EXYNOS_TMU_CORE_OFF 2
56#define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50
57
58/* Exynos4210 specific registers */
59#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
60#define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
61#define EXYNOS4210_TMU_REG_TRIG_LEVEL1 0x54
62#define EXYNOS4210_TMU_REG_TRIG_LEVEL2 0x58
63#define EXYNOS4210_TMU_REG_TRIG_LEVEL3 0x5C
64#define EXYNOS4210_TMU_REG_PAST_TEMP0 0x60
65#define EXYNOS4210_TMU_REG_PAST_TEMP1 0x64
66#define EXYNOS4210_TMU_REG_PAST_TEMP2 0x68
67#define EXYNOS4210_TMU_REG_PAST_TEMP3 0x6C
68
69#define EXYNOS4210_TMU_TRIG_LEVEL0_MASK 0x1
70#define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10
71#define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100
72#define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000
73#define EXYNOS4210_TMU_INTCLEAR_VAL 0x1111
74
75/* Exynos5250 and Exynos4412 specific registers */
76#define EXYNOS_TMU_TRIMINFO_CON 0x14
77#define EXYNOS_THD_TEMP_RISE 0x50
78#define EXYNOS_THD_TEMP_FALL 0x54
79#define EXYNOS_EMUL_CON 0x80
80
81#define EXYNOS_TRIMINFO_RELOAD 0x1
82#define EXYNOS_TMU_CLEAR_RISE_INT 0x111
3ad9524a 83#define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12)
f22d9c03
ADK		 84#define EXYNOS_MUX_ADDR_VALUE 6
85#define EXYNOS_MUX_ADDR_SHIFT 20
86#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
87
88#define EFUSE_MIN_VALUE 40
89#define EFUSE_MAX_VALUE 100
90
91/* In-kernel thermal framework related macros & definations */
92#define SENSOR_NAME_LEN 16
93#define MAX_TRIP_COUNT 8
94#define MAX_COOLING_DEVICE 4
4f0a6847 95#define MAX_THRESHOLD_LEVS 4
f22d9c03
ADK		 96
97#define ACTIVE_INTERVAL 500
98#define IDLE_INTERVAL 10000
7e0b55e6 99#define MCELSIUS 1000
f22d9c03 100
bbf63be4
JL		 101#ifdef CONFIG_EXYNOS_THERMAL_EMUL
102#define EXYNOS_EMUL_TIME 0x57F0
103#define EXYNOS_EMUL_TIME_SHIFT 16
104#define EXYNOS_EMUL_DATA_SHIFT 8
105#define EXYNOS_EMUL_DATA_MASK 0xFF
106#define EXYNOS_EMUL_ENABLE 0x1
107#endif /* CONFIG_EXYNOS_THERMAL_EMUL */
108
f22d9c03
ADK		 109/* CPU Zone information */
110#define PANIC_ZONE 4
111#define WARN_ZONE 3
112#define MONITOR_ZONE 2
113#define SAFE_ZONE 1
114
115#define GET_ZONE(trip) (trip + 2)
116#define GET_TRIP(zone) (zone - 2)
117
7e0b55e6
ADK		 118#define EXYNOS_ZONE_COUNT 3
119
f22d9c03
ADK		 120struct exynos_tmu_data {
121 struct exynos_tmu_platform_data *pdata;
9d97e5c8
DK		 122 struct resource *mem;
123 void __iomem *base;
124 int irq;
f22d9c03 125 enum soc_type soc;
9d97e5c8
DK		 126 struct work_struct irq_work;
127 struct mutex lock;
128 struct clk *clk;
129 u8 temp_error1, temp_error2;
130};
131
7e0b55e6
ADK		 132struct thermal_trip_point_conf {
133 int trip_val[MAX_TRIP_COUNT];
134 int trip_count;
4f0a6847 135 u8 trigger_falling;
7e0b55e6
ADK		 136};
137
138struct thermal_cooling_conf {
139 struct freq_clip_table freq_data[MAX_TRIP_COUNT];
140 int freq_clip_count;
141};
142
143struct thermal_sensor_conf {
144 char name[SENSOR_NAME_LEN];
145 int (*read_temperature)(void *data);
146 struct thermal_trip_point_conf trip_data;
147 struct thermal_cooling_conf cooling_data;
148 void *private_data;
149};
150
151struct exynos_thermal_zone {
152 enum thermal_device_mode mode;
153 struct thermal_zone_device *therm_dev;
154 struct thermal_cooling_device *cool_dev[MAX_COOLING_DEVICE];
155 unsigned int cool_dev_size;
156 struct platform_device *exynos4_dev;
157 struct thermal_sensor_conf *sensor_conf;
158 bool bind;
159};
160
161static struct exynos_thermal_zone *th_zone;
162static void exynos_unregister_thermal(void);
163static int exynos_register_thermal(struct thermal_sensor_conf *sensor_conf);
164
165/* Get mode callback functions for thermal zone */
166static int exynos_get_mode(struct thermal_zone_device *thermal,
167 enum thermal_device_mode *mode)
168{
169 if (th_zone)
170 *mode = th_zone->mode;
171 return 0;
172}
173
174/* Set mode callback functions for thermal zone */
175static int exynos_set_mode(struct thermal_zone_device *thermal,
176 enum thermal_device_mode mode)
177{
178 if (!th_zone->therm_dev) {
179 pr_notice("thermal zone not registered\n");
180 return 0;
181 }
182
183 mutex_lock(&th_zone->therm_dev->lock);
184
4f0a6847
JL		 185 if (mode == THERMAL_DEVICE_ENABLED &&
186 !th_zone->sensor_conf->trip_data.trigger_falling)
7e0b55e6
ADK		 187 th_zone->therm_dev->polling_delay = IDLE_INTERVAL;
188 else
189 th_zone->therm_dev->polling_delay = 0;
190
191 mutex_unlock(&th_zone->therm_dev->lock);
192
193 th_zone->mode = mode;
194 thermal_zone_device_update(th_zone->therm_dev);
195 pr_info("thermal polling set for duration=%d msec\n",
196 th_zone->therm_dev->polling_delay);
197 return 0;
198}
199
200
201/* Get trip type callback functions for thermal zone */
202static int exynos_get_trip_type(struct thermal_zone_device *thermal, int trip,
203 enum thermal_trip_type *type)
204{
205 switch (GET_ZONE(trip)) {
206 case MONITOR_ZONE:
207 case WARN_ZONE:
208 *type = THERMAL_TRIP_ACTIVE;
209 break;
210 case PANIC_ZONE:
211 *type = THERMAL_TRIP_CRITICAL;
212 break;
213 default:
214 return -EINVAL;
215 }
216 return 0;
217}
218
219/* Get trip temperature callback functions for thermal zone */
220static int exynos_get_trip_temp(struct thermal_zone_device *thermal, int trip,
221 unsigned long *temp)
222{
223 if (trip < GET_TRIP(MONITOR_ZONE) || trip > GET_TRIP(PANIC_ZONE))
224 return -EINVAL;
225
226 *temp = th_zone->sensor_conf->trip_data.trip_val[trip];
227 /* convert the temperature into millicelsius */
228 *temp = *temp * MCELSIUS;
229
230 return 0;
231}
232
233/* Get critical temperature callback functions for thermal zone */
234static int exynos_get_crit_temp(struct thermal_zone_device *thermal,
235 unsigned long *temp)
236{
237 int ret;
238 /* Panic zone */
239 ret = exynos_get_trip_temp(thermal, GET_TRIP(PANIC_ZONE), temp);
240 return ret;
241}
242
243static int exynos_get_frequency_level(unsigned int cpu, unsigned int freq)
244{
245 int i = 0, ret = -EINVAL;
246 struct cpufreq_frequency_table *table = NULL;
247#ifdef CONFIG_CPU_FREQ
248 table = cpufreq_frequency_get_table(cpu);
249#endif
250 if (!table)
251 return ret;
252
253 while (table[i].frequency != CPUFREQ_TABLE_END) {
254 if (table[i].frequency == CPUFREQ_ENTRY_INVALID)
255 continue;
256 if (table[i].frequency == freq)
257 return i;
258 i++;
259 }
260 return ret;
261}
262
263/* Bind callback functions for thermal zone */
264static int exynos_bind(struct thermal_zone_device *thermal,
265 struct thermal_cooling_device *cdev)
266{
267 int ret = 0, i, tab_size, level;
268 struct freq_clip_table *tab_ptr, *clip_data;
269 struct thermal_sensor_conf *data = th_zone->sensor_conf;
270
271 tab_ptr = (struct freq_clip_table *)data->cooling_data.freq_data;
272 tab_size = data->cooling_data.freq_clip_count;
273
274 if (tab_ptr == NULL || tab_size == 0)
275 return -EINVAL;
276
277 /* find the cooling device registered*/
278 for (i = 0; i < th_zone->cool_dev_size; i++)
279 if (cdev == th_zone->cool_dev[i])
280 break;
281
282 /* No matching cooling device */
283 if (i == th_zone->cool_dev_size)
284 return 0;
285
286 /* Bind the thermal zone to the cpufreq cooling device */
287 for (i = 0; i < tab_size; i++) {
288 clip_data = (struct freq_clip_table *)&(tab_ptr[i]);
289 level = exynos_get_frequency_level(0, clip_data->freq_clip_max);
290 if (level < 0)
291 return 0;
292 switch (GET_ZONE(i)) {
293 case MONITOR_ZONE:
294 case WARN_ZONE:
295 if (thermal_zone_bind_cooling_device(thermal, i, cdev,
ce760ed3 296 level, 0)) {
7e0b55e6
ADK		 297 pr_err("error binding cdev inst %d\n", i);
298 ret = -EINVAL;
299 }
300 th_zone->bind = true;
301 break;
302 default:
303 ret = -EINVAL;
304 }
305 }
306
307 return ret;
308}
309
310/* Unbind callback functions for thermal zone */
311static int exynos_unbind(struct thermal_zone_device *thermal,
312 struct thermal_cooling_device *cdev)
313{
314 int ret = 0, i, tab_size;
315 struct thermal_sensor_conf *data = th_zone->sensor_conf;
316
317 if (th_zone->bind == false)
318 return 0;
319
320 tab_size = data->cooling_data.freq_clip_count;
321
322 if (tab_size == 0)
323 return -EINVAL;
324
325 /* find the cooling device registered*/
326 for (i = 0; i < th_zone->cool_dev_size; i++)
327 if (cdev == th_zone->cool_dev[i])
328 break;
329
330 /* No matching cooling device */
331 if (i == th_zone->cool_dev_size)
332 return 0;
333
334 /* Bind the thermal zone to the cpufreq cooling device */
335 for (i = 0; i < tab_size; i++) {
336 switch (GET_ZONE(i)) {
337 case MONITOR_ZONE:
338 case WARN_ZONE:
339 if (thermal_zone_unbind_cooling_device(thermal, i,
340 cdev)) {
341 pr_err("error unbinding cdev inst=%d\n", i);
342 ret = -EINVAL;
343 }
344 th_zone->bind = false;
345 break;
346 default:
347 ret = -EINVAL;
348 }
349 }
350 return ret;
351}
352
353/* Get temperature callback functions for thermal zone */
354static int exynos_get_temp(struct thermal_zone_device *thermal,
355 unsigned long *temp)
356{
357 void *data;
358
359 if (!th_zone->sensor_conf) {
360 pr_info("Temperature sensor not initialised\n");
361 return -EINVAL;
362 }
363 data = th_zone->sensor_conf->private_data;
364 *temp = th_zone->sensor_conf->read_temperature(data);
365 /* convert the temperature into millicelsius */
366 *temp = *temp * MCELSIUS;
367 return 0;
368}
369
370/* Get the temperature trend */
371static int exynos_get_trend(struct thermal_zone_device *thermal,
372 int trip, enum thermal_trend *trend)
373{
3ad9524a
ADK		 374 int ret;
375 unsigned long trip_temp;
376
377 ret = exynos_get_trip_temp(thermal, trip, &trip_temp);
378 if (ret < 0)
379 return ret;
380
381 if (thermal->temperature >= trip_temp)
ce760ed3 382 *trend = THERMAL_TREND_RAISE_FULL;
7e0b55e6 383 else
ce760ed3 384 *trend = THERMAL_TREND_DROP_FULL;
7e0b55e6
ADK		 385
386 return 0;
387}
388/* Operation callback functions for thermal zone */
389static struct thermal_zone_device_ops const exynos_dev_ops = {
390 .bind = exynos_bind,
391 .unbind = exynos_unbind,
392 .get_temp = exynos_get_temp,
393 .get_trend = exynos_get_trend,
394 .get_mode = exynos_get_mode,
395 .set_mode = exynos_set_mode,
396 .get_trip_type = exynos_get_trip_type,
397 .get_trip_temp = exynos_get_trip_temp,
398 .get_crit_temp = exynos_get_crit_temp,
399};
400
401/*
402 * This function may be called from interrupt based temperature sensor
403 * when threshold is changed.
404 */
405static void exynos_report_trigger(void)
406{
407 unsigned int i;
408 char data[10];
409 char *envp[] = { data, NULL };
410
411 if (!th_zone || !th_zone->therm_dev)
412 return;
413 if (th_zone->bind == false) {
414 for (i = 0; i < th_zone->cool_dev_size; i++) {
415 if (!th_zone->cool_dev[i])
416 continue;
417 exynos_bind(th_zone->therm_dev,
418 th_zone->cool_dev[i]);
419 }
420 }
421
422 thermal_zone_device_update(th_zone->therm_dev);
423
424 mutex_lock(&th_zone->therm_dev->lock);
425 /* Find the level for which trip happened */
426 for (i = 0; i < th_zone->sensor_conf->trip_data.trip_count; i++) {
427 if (th_zone->therm_dev->last_temperature <
428 th_zone->sensor_conf->trip_data.trip_val[i] * MCELSIUS)
429 break;
430 }
431
4f0a6847
JL		 432 if (th_zone->mode == THERMAL_DEVICE_ENABLED &&
433 !th_zone->sensor_conf->trip_data.trigger_falling) {
7e0b55e6
ADK		 434 if (i > 0)
435 th_zone->therm_dev->polling_delay = ACTIVE_INTERVAL;
436 else
437 th_zone->therm_dev->polling_delay = IDLE_INTERVAL;
438 }
439
440 snprintf(data, sizeof(data), "%u", i);
441 kobject_uevent_env(&th_zone->therm_dev->device.kobj, KOBJ_CHANGE, envp);
442 mutex_unlock(&th_zone->therm_dev->lock);
443}
444
445/* Register with the in-kernel thermal management */
446static int exynos_register_thermal(struct thermal_sensor_conf *sensor_conf)
447{
448 int ret;
449 struct cpumask mask_val;
450
451 if (!sensor_conf || !sensor_conf->read_temperature) {
452 pr_err("Temperature sensor not initialised\n");
453 return -EINVAL;
454 }
455
456 th_zone = kzalloc(sizeof(struct exynos_thermal_zone), GFP_KERNEL);
457 if (!th_zone)
458 return -ENOMEM;
459
460 th_zone->sensor_conf = sensor_conf;
461 cpumask_set_cpu(0, &mask_val);
462 th_zone->cool_dev[0] = cpufreq_cooling_register(&mask_val);
463 if (IS_ERR(th_zone->cool_dev[0])) {
464 pr_err("Failed to register cpufreq cooling device\n");
465 ret = -EINVAL;
466 goto err_unregister;
467 }
468 th_zone->cool_dev_size++;
469
470 th_zone->therm_dev = thermal_zone_device_register(sensor_conf->name,
50125a9b 471 EXYNOS_ZONE_COUNT, 0, NULL, &exynos_dev_ops, NULL, 0,
4f0a6847
JL		 472 sensor_conf->trip_data.trigger_falling ?
473 0 : IDLE_INTERVAL);
7e0b55e6
ADK		 474
475 if (IS_ERR(th_zone->therm_dev)) {
476 pr_err("Failed to register thermal zone device\n");
043e4652 477 ret = PTR_ERR(th_zone->therm_dev);
7e0b55e6
ADK		 478 goto err_unregister;
479 }
480 th_zone->mode = THERMAL_DEVICE_ENABLED;
481
482 pr_info("Exynos: Kernel Thermal management registered\n");
483
484 return 0;
485
486err_unregister:
487 exynos_unregister_thermal();
488 return ret;
489}
490
491/* Un-Register with the in-kernel thermal management */
492static void exynos_unregister_thermal(void)
493{
494 int i;
495
c072fed9
SK		 496 if (!th_zone)
497 return;
498
499 if (th_zone->therm_dev)
7e0b55e6
ADK		 500 thermal_zone_device_unregister(th_zone->therm_dev);
501
502 for (i = 0; i < th_zone->cool_dev_size; i++) {
c072fed9 503 if (th_zone->cool_dev[i])
7e0b55e6
ADK		 504 cpufreq_cooling_unregister(th_zone->cool_dev[i]);
505 }
506
507 kfree(th_zone);
508 pr_info("Exynos: Kernel Thermal management unregistered\n");
509}
510
9d97e5c8
DK		 511/*
512 * TMU treats temperature as a mapped temperature code.
513 * The temperature is converted differently depending on the calibration type.
514 */
f22d9c03 515static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
9d97e5c8 516{
f22d9c03 517 struct exynos_tmu_platform_data *pdata = data->pdata;
9d97e5c8
DK		 518 int temp_code;
519
f22d9c03
ADK		 520 if (data->soc == SOC_ARCH_EXYNOS4210)
521 /* temp should range between 25 and 125 */
522 if (temp < 25 || temp > 125) {
523 temp_code = -EINVAL;
524 goto out;
525 }
9d97e5c8
DK		 526
527 switch (pdata->cal_type) {
528 case TYPE_TWO_POINT_TRIMMING:
529 temp_code = (temp - 25) *
530 (data->temp_error2 - data->temp_error1) /
531 (85 - 25) + data->temp_error1;
532 break;
533 case TYPE_ONE_POINT_TRIMMING:
534 temp_code = temp + data->temp_error1 - 25;
535 break;
536 default:
f22d9c03 537 temp_code = temp + EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
9d97e5c8
DK		 538 break;
539 }
540out:
541 return temp_code;
542}
543
544/*
545 * Calculate a temperature value from a temperature code.
546 * The unit of the temperature is degree Celsius.
547 */
f22d9c03 548static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
9d97e5c8 549{
f22d9c03 550 struct exynos_tmu_platform_data *pdata = data->pdata;
9d97e5c8
DK		 551 int temp;
552
f22d9c03
ADK		 553 if (data->soc == SOC_ARCH_EXYNOS4210)
554 /* temp_code should range between 75 and 175 */
555 if (temp_code < 75 || temp_code > 175) {
556 temp = -ENODATA;
557 goto out;
558 }
9d97e5c8
DK		 559
560 switch (pdata->cal_type) {
561 case TYPE_TWO_POINT_TRIMMING:
562 temp = (temp_code - data->temp_error1) * (85 - 25) /
563 (data->temp_error2 - data->temp_error1) + 25;
564 break;
565 case TYPE_ONE_POINT_TRIMMING:
566 temp = temp_code - data->temp_error1 + 25;
567 break;
568 default:
f22d9c03 569 temp = temp_code - EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
9d97e5c8
DK		 570 break;
571 }
572out:
573 return temp;
574}
575
f22d9c03 576static int exynos_tmu_initialize(struct platform_device *pdev)
9d97e5c8 577{
f22d9c03
ADK		 578 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
579 struct exynos_tmu_platform_data *pdata = data->pdata;
4f0a6847
JL		 580 unsigned int status, trim_info;
581 unsigned int rising_threshold = 0, falling_threshold = 0;
582 int ret = 0, threshold_code, i, trigger_levs = 0;
9d97e5c8
DK		 583
584 mutex_lock(&data->lock);
585 clk_enable(data->clk);
586
f22d9c03 587 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
9d97e5c8
DK		 588 if (!status) {
589 ret = -EBUSY;
590 goto out;
591 }
592
f22d9c03
ADK		 593 if (data->soc == SOC_ARCH_EXYNOS) {
594 __raw_writel(EXYNOS_TRIMINFO_RELOAD,
595 data->base + EXYNOS_TMU_TRIMINFO_CON);
596 }
9d97e5c8 597 /* Save trimming info in order to perform calibration */
f22d9c03
ADK		 598 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
599 data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
600 data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);
601
602 if ((EFUSE_MIN_VALUE > data->temp_error1) ||
603 (data->temp_error1 > EFUSE_MAX_VALUE) ||
604 (data->temp_error2 != 0))
605 data->temp_error1 = pdata->efuse_value;
606
4f0a6847
JL		 607 /* Count trigger levels to be enabled */
608 for (i = 0; i < MAX_THRESHOLD_LEVS; i++)
609 if (pdata->trigger_levels[i])
610 trigger_levs++;
611
f22d9c03
ADK		 612 if (data->soc == SOC_ARCH_EXYNOS4210) {
613 /* Write temperature code for threshold */
614 threshold_code = temp_to_code(data, pdata->threshold);
615 if (threshold_code < 0) {
616 ret = threshold_code;
617 goto out;
618 }
619 writeb(threshold_code,
620 data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
4f0a6847
JL		 621 for (i = 0; i < trigger_levs; i++)
622 writeb(pdata->trigger_levels[i],
623 data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
f22d9c03
ADK		 624
625 writel(EXYNOS4210_TMU_INTCLEAR_VAL,
626 data->base + EXYNOS_TMU_REG_INTCLEAR);
627 } else if (data->soc == SOC_ARCH_EXYNOS) {
4f0a6847
JL		 628 /* Write temperature code for rising and falling threshold */
629 for (i = 0; i < trigger_levs; i++) {
630 threshold_code = temp_to_code(data,
631 pdata->trigger_levels[i]);
632 if (threshold_code < 0) {
633 ret = threshold_code;
634 goto out;
635 }
636 rising_threshold |= threshold_code << 8 * i;
637 if (pdata->threshold_falling) {
638 threshold_code = temp_to_code(data,
639 pdata->trigger_levels[i] -
640 pdata->threshold_falling);
641 if (threshold_code > 0)
642 falling_threshold |=
643 threshold_code << 8 * i;
644 }
f22d9c03 645 }
f22d9c03
ADK		 646
647 writel(rising_threshold,
648 data->base + EXYNOS_THD_TEMP_RISE);
4f0a6847
JL		 649 writel(falling_threshold,
650 data->base + EXYNOS_THD_TEMP_FALL);
f22d9c03 651
4f0a6847 652 writel(EXYNOS_TMU_CLEAR_RISE_INT | EXYNOS_TMU_CLEAR_FALL_INT,
f22d9c03 653 data->base + EXYNOS_TMU_REG_INTCLEAR);
9d97e5c8 654 }
9d97e5c8
DK		 655out:
656 clk_disable(data->clk);
657 mutex_unlock(&data->lock);
658
659 return ret;
660}
661
f22d9c03 662static void exynos_tmu_control(struct platform_device *pdev, bool on)
9d97e5c8 663{
f22d9c03
ADK		 664 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
665 struct exynos_tmu_platform_data *pdata = data->pdata;
9d97e5c8
DK		 666 unsigned int con, interrupt_en;
667
668 mutex_lock(&data->lock);
669 clk_enable(data->clk);
670
f22d9c03
ADK		 671 con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
672 pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
673
674 if (data->soc == SOC_ARCH_EXYNOS) {
675 con |= pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT;
676 con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
677 }
678
9d97e5c8 679 if (on) {
f22d9c03 680 con |= EXYNOS_TMU_CORE_ON;
9d97e5c8
DK		 681 interrupt_en = pdata->trigger_level3_en << 12 |
682 pdata->trigger_level2_en << 8 |
683 pdata->trigger_level1_en << 4 |
684 pdata->trigger_level0_en;
4f0a6847
JL		 685 if (pdata->threshold_falling)
686 interrupt_en |= interrupt_en << 16;
9d97e5c8 687 } else {
f22d9c03 688 con |= EXYNOS_TMU_CORE_OFF;
9d97e5c8
DK		 689 interrupt_en = 0; /* Disable all interrupts */
690 }
f22d9c03
ADK		 691 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
692 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
9d97e5c8
DK		 693
694 clk_disable(data->clk);
695 mutex_unlock(&data->lock);
696}
697
f22d9c03 698static int exynos_tmu_read(struct exynos_tmu_data *data)
9d97e5c8
DK		 699{
700 u8 temp_code;
701 int temp;
702
703 mutex_lock(&data->lock);
704 clk_enable(data->clk);
705
f22d9c03 706 temp_code = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
9d97e5c8
DK		 707 temp = code_to_temp(data, temp_code);
708
709 clk_disable(data->clk);
710 mutex_unlock(&data->lock);
711
712 return temp;
713}
714
f22d9c03 715static void exynos_tmu_work(struct work_struct *work)
9d97e5c8 716{
f22d9c03
ADK		 717 struct exynos_tmu_data *data = container_of(work,
718 struct exynos_tmu_data, irq_work);
9d97e5c8 719
3ad9524a 720 exynos_report_trigger();
9d97e5c8
DK		 721 mutex_lock(&data->lock);
722 clk_enable(data->clk);
f22d9c03 723 if (data->soc == SOC_ARCH_EXYNOS)
4f0a6847
JL		 724 writel(EXYNOS_TMU_CLEAR_RISE_INT |
725 EXYNOS_TMU_CLEAR_FALL_INT,
f22d9c03
ADK		 726 data->base + EXYNOS_TMU_REG_INTCLEAR);
727 else
728 writel(EXYNOS4210_TMU_INTCLEAR_VAL,
729 data->base + EXYNOS_TMU_REG_INTCLEAR);
9d97e5c8
DK		 730 clk_disable(data->clk);
731 mutex_unlock(&data->lock);
3ad9524a 732
f22d9c03 733 enable_irq(data->irq);
9d97e5c8
DK		 734}
735
f22d9c03 736static irqreturn_t exynos_tmu_irq(int irq, void *id)
9d97e5c8 737{
f22d9c03 738 struct exynos_tmu_data *data = id;
9d97e5c8
DK		 739
740 disable_irq_nosync(irq);
741 schedule_work(&data->irq_work);
742
743 return IRQ_HANDLED;
744}
7e0b55e6
ADK		 745static struct thermal_sensor_conf exynos_sensor_conf = {
746 .name = "exynos-therm",
747 .read_temperature = (int (*)(void *))exynos_tmu_read,
17be868e
ADK		 748};
749
750#if defined(CONFIG_CPU_EXYNOS4210)
751static struct exynos_tmu_platform_data const exynos4210_default_tmu_data = {
752 .threshold = 80,
753 .trigger_levels[0] = 5,
754 .trigger_levels[1] = 20,
755 .trigger_levels[2] = 30,
756 .trigger_level0_en = 1,
757 .trigger_level1_en = 1,
758 .trigger_level2_en = 1,
759 .trigger_level3_en = 0,
760 .gain = 15,
761 .reference_voltage = 7,
762 .cal_type = TYPE_ONE_POINT_TRIMMING,
763 .freq_tab[0] = {
764 .freq_clip_max = 800 * 1000,
765 .temp_level = 85,
766 },
767 .freq_tab[1] = {
768 .freq_clip_max = 200 * 1000,
769 .temp_level = 100,
770 },
771 .freq_tab_count = 2,
772 .type = SOC_ARCH_EXYNOS4210,
773};
774#define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data)
775#else
776#define EXYNOS4210_TMU_DRV_DATA (NULL)
777#endif
778
779#if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412)
780static struct exynos_tmu_platform_data const exynos_default_tmu_data = {
4f0a6847 781 .threshold_falling = 10,
17be868e
ADK		 782 .trigger_levels[0] = 85,
783 .trigger_levels[1] = 103,
784 .trigger_levels[2] = 110,
785 .trigger_level0_en = 1,
786 .trigger_level1_en = 1,
787 .trigger_level2_en = 1,
788 .trigger_level3_en = 0,
789 .gain = 8,
790 .reference_voltage = 16,
791 .noise_cancel_mode = 4,
792 .cal_type = TYPE_ONE_POINT_TRIMMING,
793 .efuse_value = 55,
794 .freq_tab[0] = {
795 .freq_clip_max = 800 * 1000,
796 .temp_level = 85,
797 },
798 .freq_tab[1] = {
799 .freq_clip_max = 200 * 1000,
800 .temp_level = 103,
801 },
802 .freq_tab_count = 2,
803 .type = SOC_ARCH_EXYNOS,
804};
805#define EXYNOS_TMU_DRV_DATA (&exynos_default_tmu_data)
806#else
807#define EXYNOS_TMU_DRV_DATA (NULL)
808#endif
809
810#ifdef CONFIG_OF
811static const struct of_device_id exynos_tmu_match[] = {
812 {
813 .compatible = "samsung,exynos4210-tmu",
814 .data = (void *)EXYNOS4210_TMU_DRV_DATA,
815 },
816 {
817 .compatible = "samsung,exynos5250-tmu",
818 .data = (void *)EXYNOS_TMU_DRV_DATA,
819 },
820 {},
821};
822MODULE_DEVICE_TABLE(of, exynos_tmu_match);
17be868e
ADK		 823#endif
824
825static struct platform_device_id exynos_tmu_driver_ids[] = {
826 {
827 .name = "exynos4210-tmu",
828 .driver_data = (kernel_ulong_t)EXYNOS4210_TMU_DRV_DATA,
829 },
830 {
831 .name = "exynos5250-tmu",
832 .driver_data = (kernel_ulong_t)EXYNOS_TMU_DRV_DATA,
833 },
834 { },
835};
3ae53b1e 836MODULE_DEVICE_TABLE(platform, exynos_tmu_driver_ids);
17be868e
ADK		 837
838static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
839 struct platform_device *pdev)
840{
841#ifdef CONFIG_OF
842 if (pdev->dev.of_node) {
843 const struct of_device_id *match;
844 match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
845 if (!match)
846 return NULL;
847 return (struct exynos_tmu_platform_data *) match->data;
848 }
849#endif
850 return (struct exynos_tmu_platform_data *)
851 platform_get_device_id(pdev)->driver_data;
7e0b55e6 852}
bbf63be4
JL		 853
854#ifdef CONFIG_EXYNOS_THERMAL_EMUL
855static ssize_t exynos_tmu_emulation_show(struct device *dev,
856 struct device_attribute *attr,
857 char *buf)
858{
859 struct platform_device *pdev = container_of(dev,
860 struct platform_device, dev);
861 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
862 unsigned int reg;
863 u8 temp_code;
864 int temp = 0;
865
866 if (data->soc == SOC_ARCH_EXYNOS4210)
867 goto out;
868
869 mutex_lock(&data->lock);
870 clk_enable(data->clk);
871 reg = readl(data->base + EXYNOS_EMUL_CON);
872 clk_disable(data->clk);
873 mutex_unlock(&data->lock);
874
875 if (reg & EXYNOS_EMUL_ENABLE) {
876 reg >>= EXYNOS_EMUL_DATA_SHIFT;
877 temp_code = reg & EXYNOS_EMUL_DATA_MASK;
878 temp = code_to_temp(data, temp_code);
879 }
880out:
881 return sprintf(buf, "%d\n", temp * MCELSIUS);
882}
883
884static ssize_t exynos_tmu_emulation_store(struct device *dev,
885 struct device_attribute *attr,
886 const char *buf, size_t count)
887{
888 struct platform_device *pdev = container_of(dev,
889 struct platform_device, dev);
890 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
891 unsigned int reg;
892 int temp;
893
894 if (data->soc == SOC_ARCH_EXYNOS4210)
895 goto out;
896
897 if (!sscanf(buf, "%d\n", &temp) || temp < 0)
898 return -EINVAL;
899
900 mutex_lock(&data->lock);
901 clk_enable(data->clk);
902
903 reg = readl(data->base + EXYNOS_EMUL_CON);
904
905 if (temp) {
906 /* Both CELSIUS and MCELSIUS type are available for input */
907 if (temp > MCELSIUS)
908 temp /= MCELSIUS;
909
910 reg = (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT) |
911 (temp_to_code(data, (temp / MCELSIUS))
912 << EXYNOS_EMUL_DATA_SHIFT) | EXYNOS_EMUL_ENABLE;
913 } else {
914 reg &= ~EXYNOS_EMUL_ENABLE;
915 }
916
917 writel(reg, data->base + EXYNOS_EMUL_CON);
918
919 clk_disable(data->clk);
920 mutex_unlock(&data->lock);
921
922out:
923 return count;
924}
925
926static DEVICE_ATTR(emulation, 0644, exynos_tmu_emulation_show,
927 exynos_tmu_emulation_store);
928static int create_emulation_sysfs(struct device *dev)
929{
930 return device_create_file(dev, &dev_attr_emulation);
931}
932static void remove_emulation_sysfs(struct device *dev)
933{
934 device_remove_file(dev, &dev_attr_emulation);
935}
936#else
937static inline int create_emulation_sysfs(struct device *dev) { return 0; }
938static inline void remove_emulation_sysfs(struct device *dev) {}
939#endif
940
4eab7a9e 941static int exynos_tmu_probe(struct platform_device *pdev)
9d97e5c8 942{
f22d9c03
ADK		 943 struct exynos_tmu_data *data;
944 struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data;
7e0b55e6 945 int ret, i;
9d97e5c8 946
17be868e
ADK		 947 if (!pdata)
948 pdata = exynos_get_driver_data(pdev);
949
9d97e5c8
DK		 950 if (!pdata) {
951 dev_err(&pdev->dev, "No platform init data supplied.\n");
952 return -ENODEV;
953 }
79e093c3
ADK		 954 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
955 GFP_KERNEL);
9d97e5c8
DK		 956 if (!data) {
957 dev_err(&pdev->dev, "Failed to allocate driver structure\n");
958 return -ENOMEM;
959 }
960
961 data->irq = platform_get_irq(pdev, 0);
962 if (data->irq < 0) {
9d97e5c8 963 dev_err(&pdev->dev, "Failed to get platform irq\n");
79e093c3 964 return data->irq;
9d97e5c8
DK		 965 }
966
f22d9c03 967 INIT_WORK(&data->irq_work, exynos_tmu_work);
9d97e5c8
DK		 968
969 data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
970 if (!data->mem) {
9d97e5c8 971 dev_err(&pdev->dev, "Failed to get platform resource\n");
79e093c3 972 return -ENOENT;
9d97e5c8
DK		 973 }
974
ca36b1ba
TR		 975 data->base = devm_ioremap_resource(&pdev->dev, data->mem);
976 if (IS_ERR(data->base))
977 return PTR_ERR(data->base);
9d97e5c8 978
79e093c3 979 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
f22d9c03 980 IRQF_TRIGGER_RISING, "exynos-tmu", data);
9d97e5c8
DK		 981 if (ret) {
982 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
79e093c3 983 return ret;
9d97e5c8
DK		 984 }
985
986 data->clk = clk_get(NULL, "tmu_apbif");
987 if (IS_ERR(data->clk)) {
9d97e5c8 988 dev_err(&pdev->dev, "Failed to get clock\n");
79e093c3 989 return PTR_ERR(data->clk);
9d97e5c8
DK		 990 }
991
f22d9c03
ADK		 992 if (pdata->type == SOC_ARCH_EXYNOS ||
993 pdata->type == SOC_ARCH_EXYNOS4210)
994 data->soc = pdata->type;
995 else {
996 ret = -EINVAL;
997 dev_err(&pdev->dev, "Platform not supported\n");
998 goto err_clk;
999 }
1000
9d97e5c8
DK		 1001 data->pdata = pdata;
1002 platform_set_drvdata(pdev, data);
1003 mutex_init(&data->lock);
1004
f22d9c03 1005 ret = exynos_tmu_initialize(pdev);
9d97e5c8
DK		 1006 if (ret) {
1007 dev_err(&pdev->dev, "Failed to initialize TMU\n");
1008 goto err_clk;
1009 }
1010
f22d9c03 1011 exynos_tmu_control(pdev, true);
9d97e5c8 1012
7e0b55e6
ADK		 1013 /* Register the sensor with thermal management interface */
1014 (&exynos_sensor_conf)->private_data = data;
1015 exynos_sensor_conf.trip_data.trip_count = pdata->trigger_level0_en +
1016 pdata->trigger_level1_en + pdata->trigger_level2_en +
1017 pdata->trigger_level3_en;
1018
1019 for (i = 0; i < exynos_sensor_conf.trip_data.trip_count; i++)
1020 exynos_sensor_conf.trip_data.trip_val[i] =
1021 pdata->threshold + pdata->trigger_levels[i];
1022
4f0a6847
JL		 1023 exynos_sensor_conf.trip_data.trigger_falling = pdata->threshold_falling;
1024
7e0b55e6
ADK		 1025 exynos_sensor_conf.cooling_data.freq_clip_count =
1026 pdata->freq_tab_count;
1027 for (i = 0; i < pdata->freq_tab_count; i++) {
1028 exynos_sensor_conf.cooling_data.freq_data[i].freq_clip_max =
1029 pdata->freq_tab[i].freq_clip_max;
1030 exynos_sensor_conf.cooling_data.freq_data[i].temp_level =
1031 pdata->freq_tab[i].temp_level;
1032 }
1033
1034 ret = exynos_register_thermal(&exynos_sensor_conf);
1035 if (ret) {
1036 dev_err(&pdev->dev, "Failed to register thermal interface\n");
1037 goto err_clk;
1038 }
bbf63be4
JL		 1039
1040 ret = create_emulation_sysfs(&pdev->dev);
1041 if (ret)
1042 dev_err(&pdev->dev, "Failed to create emulation mode sysfs node\n");
1043
9d97e5c8 1044 return 0;
9d97e5c8
DK		 1045err_clk:
1046 platform_set_drvdata(pdev, NULL);
1047 clk_put(data->clk);
9d97e5c8
DK		 1048 return ret;
1049}
1050
4eab7a9e 1051static int exynos_tmu_remove(struct platform_device *pdev)
9d97e5c8 1052{
f22d9c03 1053 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
9d97e5c8 1054
bbf63be4
JL		 1055 remove_emulation_sysfs(&pdev->dev);
1056
f22d9c03 1057 exynos_tmu_control(pdev, false);
9d97e5c8 1058
7e0b55e6
ADK		 1059 exynos_unregister_thermal();
1060
9d97e5c8
DK		 1061 clk_put(data->clk);
1062
9d97e5c8
DK		 1063 platform_set_drvdata(pdev, NULL);
1064
9d97e5c8
DK		 1065 return 0;
1066}
1067
08cd6753 1068#ifdef CONFIG_PM_SLEEP
f22d9c03 1069static int exynos_tmu_suspend(struct device *dev)
9d97e5c8 1070{
f22d9c03 1071 exynos_tmu_control(to_platform_device(dev), false);
9d97e5c8
DK		 1072
1073 return 0;
1074}
1075
f22d9c03 1076static int exynos_tmu_resume(struct device *dev)
9d97e5c8 1077{
08cd6753
RW		 1078 struct platform_device *pdev = to_platform_device(dev);
1079
f22d9c03
ADK		 1080 exynos_tmu_initialize(pdev);
1081 exynos_tmu_control(pdev, true);
9d97e5c8
DK		 1082
1083 return 0;
1084}
08cd6753 1085
f22d9c03
ADK		 1086static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
1087 exynos_tmu_suspend, exynos_tmu_resume);
1088#define EXYNOS_TMU_PM (&exynos_tmu_pm)
9d97e5c8 1089#else
f22d9c03 1090#define EXYNOS_TMU_PM NULL
9d97e5c8
DK		 1091#endif
1092
f22d9c03 1093static struct platform_driver exynos_tmu_driver = {
9d97e5c8 1094 .driver = {
f22d9c03 1095 .name = "exynos-tmu",
9d97e5c8 1096 .owner = THIS_MODULE,
f22d9c03 1097 .pm = EXYNOS_TMU_PM,
caa5cbd5 1098 .of_match_table = of_match_ptr(exynos_tmu_match),
9d97e5c8 1099 },
f22d9c03 1100 .probe = exynos_tmu_probe,
4eab7a9e 1101 .remove = exynos_tmu_remove,
17be868e 1102 .id_table = exynos_tmu_driver_ids,
9d97e5c8
DK		 1103};
1104
f22d9c03 1105module_platform_driver(exynos_tmu_driver);
9d97e5c8 1106
f22d9c03 1107MODULE_DESCRIPTION("EXYNOS TMU Driver");
9d97e5c8
DK		 1108MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
1109MODULE_LICENSE("GPL");
f22d9c03 1110MODULE_ALIAS("platform:exynos-tmu");
Linux 6.x block layer and io_uring tree(s)