[linux-2.6-block.git] / drivers / staging / xillybus / xillybus.h

/*
 * linux/drivers/misc/xillybus.h
 *
 * Copyright 2011 Xillybus Ltd, http://xillybus.com
 *
 * Header file for the Xillybus FPGA/host framework.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the smems of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 */

#ifndef __XILLYBUS_H
#define __XILLYBUS_H

#include <linux/list.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/cdev.h>
#include <linux/spinlock.h>
#include <linux/mutex.h>
#include <linux/workqueue.h>

struct xilly_endpoint_hardware;

struct xilly_page {
	struct list_head node;
	unsigned long addr;
	unsigned int order;
};

struct xilly_dma {
	struct list_head node;
	struct pci_dev *pdev;
	struct device *dev;
	dma_addr_t dma_addr;
	size_t size;
	int direction;
};

struct xilly_buffer {
	void *addr;
	dma_addr_t dma_addr;
	int end_offset; /* Counting elements, not bytes */
};

struct xilly_cleanup {
	struct list_head to_kfree;
	struct list_head to_pagefree;
	struct list_head to_unmap;
};

struct xilly_idt_handle {
	unsigned char *chandesc;
	unsigned char *idt;
	int entries;
};

/*
 * Read-write confusion: wr_* and rd_* notation sticks to FPGA view, so
 * wr_* buffers are those consumed by read(), since the FPGA writes to them
 * and vice versa.
 */

struct xilly_channel {
	struct xilly_endpoint *endpoint;
	int chan_num;
	int log2_element_size;
	int seekable;

	struct xilly_buffer **wr_buffers; /* FPGA writes, driver reads! */
	int num_wr_buffers;
	unsigned int wr_buf_size; /* In bytes */
	int wr_fpga_buf_idx;
	int wr_host_buf_idx;
	int wr_host_buf_pos;
	int wr_empty;
	int wr_ready; /* Significant only when wr_empty == 1 */
	int wr_sleepy;
	int wr_eof;
	int wr_hangup;
	spinlock_t wr_spinlock;
	struct mutex wr_mutex;
	wait_queue_head_t wr_wait;
	wait_queue_head_t wr_ready_wait;
	int wr_ref_count;
	int wr_synchronous;
	int wr_allow_partial;
	int wr_exclusive_open;
	int wr_supports_nonempty;

	struct xilly_buffer **rd_buffers; /* FPGA reads, driver writes! */
	int num_rd_buffers;
	unsigned int rd_buf_size; /* In bytes */
	int rd_fpga_buf_idx;
	int rd_host_buf_pos;
	int rd_host_buf_idx;
	int rd_full;
	spinlock_t rd_spinlock;
	struct mutex rd_mutex;
	wait_queue_head_t rd_wait;
	int rd_ref_count;
	int rd_allow_partial;
	int rd_synchronous;
	int rd_exclusive_open;
	struct delayed_work rd_workitem;
	unsigned char rd_leftovers[4];
};

struct xilly_endpoint {
	/*
	 * One of pdev and dev is always NULL, and the other is a valid
	 * pointer, depending on the type of device
	 */
	struct pci_dev *pdev;
	struct device *dev;
	struct xilly_endpoint_hardware *ephw;

	struct list_head ep_list;
	int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */
	__iomem u32 *registers;
	int fatal_error;

	struct mutex register_mutex;
	wait_queue_head_t ep_wait;

	/* List of memory allocations, to make release easy */
	struct xilly_cleanup cleanup;

	/* Channels and message handling */
	struct cdev cdev;

	int major;
	int lowest_minor; /* Highest minor = lowest_minor + num_channels - 1 */

	int num_channels; /* EXCLUDING message buffer */
	struct xilly_channel **channels;
	int msg_counter;
	int failed_messages;
	int idtlen;

	u32 *msgbuf_addr;
	dma_addr_t msgbuf_dma_addr;
	unsigned int msg_buf_size;
};

struct xilly_endpoint_hardware {
	struct module *owner;
	void (*hw_sync_sgl_for_cpu)(struct xilly_endpoint *,
				    dma_addr_t,
				    size_t,
				    int);
	void (*hw_sync_sgl_for_device)(struct xilly_endpoint *,
				       dma_addr_t,
				       size_t,
				       int);
	dma_addr_t (*map_single)(struct xilly_cleanup *,
				 struct xilly_endpoint *,
				 void *,
				 size_t,
				 int);
	void (*unmap_single)(struct xilly_dma *entry);
};

irqreturn_t xillybus_isr(int irq, void *data);

void xillybus_do_cleanup(struct xilly_cleanup *mem,
			 struct xilly_endpoint *endpoint);

struct xilly_endpoint *xillybus_init_endpoint(struct pci_dev *pdev,
					      struct device *dev,
					      struct xilly_endpoint_hardware
					      *ephw);

int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint);

void xillybus_endpoint_remove(struct xilly_endpoint *endpoint);

#endif /* __XILLYBUS_H */
Commit	Line	Data
48bae050 EB	1	/*
	2	* linux/drivers/misc/xillybus.h
	3	*
	4	* Copyright 2011 Xillybus Ltd, http://xillybus.com
	5	*
	6	* Header file for the Xillybus FPGA/host framework.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the smems of the GNU General Public License as published by
	10	* the Free Software Foundation; version 2 of the License.
	11	*/
	12
	13	#ifndef __XILLYBUS_H
	14	#define __XILLYBUS_H
	15
	16	#include <linux/list.h>
	17	#include <linux/device.h>
	18	#include <linux/dma-mapping.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/sched.h>
	21	#include <linux/cdev.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/mutex.h>
48bae050 EB	24	#include <linux/workqueue.h>
48bae050 EB	25
48bae050 EB	26	struct xilly_endpoint_hardware;
	27
	28	struct xilly_page {
	29	struct list_head node;
	30	unsigned long addr;
	31	unsigned int order;
	32	};
	33
	34	struct xilly_dma {
	35	struct list_head node;
	36	struct pci_dev *pdev;
	37	struct device *dev;
	38	dma_addr_t dma_addr;
	39	size_t size;
	40	int direction;
	41	};
	42
	43	struct xilly_buffer {
	44	void *addr;
	45	dma_addr_t dma_addr;
	46	int end_offset; /* Counting elements, not bytes */
	47	};
	48
	49	struct xilly_cleanup {
	50	struct list_head to_kfree;
	51	struct list_head to_pagefree;
	52	struct list_head to_unmap;
	53	};
	54
	55	struct xilly_idt_handle {
	56	unsigned char *chandesc;
	57	unsigned char *idt;
	58	int entries;
	59	};
	60
	61	/*
	62	* Read-write confusion: wr_* and rd_* notation sticks to FPGA view, so
	63	* wr_* buffers are those consumed by read(), since the FPGA writes to them
	64	* and vice versa.
	65	*/
	66
	67	struct xilly_channel {
	68	struct xilly_endpoint *endpoint;
	69	int chan_num;
	70	int log2_element_size;
	71	int seekable;
	72
	73	struct xilly_buffer *wr_buffers; / FPGA writes, driver reads! */
	74	int num_wr_buffers;
	75	unsigned int wr_buf_size; /* In bytes */
	76	int wr_fpga_buf_idx;
	77	int wr_host_buf_idx;
	78	int wr_host_buf_pos;
	79	int wr_empty;
	80	int wr_ready; /* Significant only when wr_empty == 1 */
	81	int wr_sleepy;
	82	int wr_eof;
	83	int wr_hangup;
	84	spinlock_t wr_spinlock;
	85	struct mutex wr_mutex;
	86	wait_queue_head_t wr_wait;
	87	wait_queue_head_t wr_ready_wait;
	88	int wr_ref_count;
	89	int wr_synchronous;
90	int wr_allow_partial;
91	int wr_exclusive_open;
92	int wr_supports_nonempty;
93
94	struct xilly_buffer *rd_buffers; / FPGA reads, driver writes! */
95	int num_rd_buffers;
96	unsigned int rd_buf_size; /* In bytes */
97	int rd_fpga_buf_idx;
98	int rd_host_buf_pos;
99	int rd_host_buf_idx;
100	int rd_full;
101	spinlock_t rd_spinlock;
102	struct mutex rd_mutex;
103	wait_queue_head_t rd_wait;
104	int rd_ref_count;
105	int rd_allow_partial;
106	int rd_synchronous;
107	int rd_exclusive_open;
108	struct delayed_work rd_workitem;
109	unsigned char rd_leftovers[4];
110	};
111
112	struct xilly_endpoint {
113	/*
114	* One of pdev and dev is always NULL, and the other is a valid
115	* pointer, depending on the type of device
116	*/
117	struct pci_dev *pdev;
118	struct device *dev;
48bae050 EB	119	struct xilly_endpoint_hardware *ephw;
	120
	121	struct list_head ep_list;
	122	int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */
7ee9ded2	123	__iomem u32 *registers;
48bae050 EB	124	int fatal_error;
	125
	126	struct mutex register_mutex;
	127	wait_queue_head_t ep_wait;
	128
	129	/* List of memory allocations, to make release easy */
	130	struct xilly_cleanup cleanup;
	131
	132	/* Channels and message handling */
	133	struct cdev cdev;
	134
	135	int major;
	136	int lowest_minor; /* Highest minor = lowest_minor + num_channels - 1 */
	137
	138	int num_channels; /* EXCLUDING message buffer */
	139	struct xilly_channel **channels;
	140	int msg_counter;
	141	int failed_messages;
	142	int idtlen;
	143
	144	u32 *msgbuf_addr;
	145	dma_addr_t msgbuf_dma_addr;
	146	unsigned int msg_buf_size;
	147	};
	148
	149	struct xilly_endpoint_hardware {
	150	struct module *owner;
7ee9ded2	151	void (hw_sync_sgl_for_cpu)(struct xilly_endpoint ,
48bae050 EB	152	dma_addr_t,
	153	size_t,
	154	int);
7ee9ded2	155	void (hw_sync_sgl_for_device)(struct xilly_endpoint ,
48bae050 EB	156	dma_addr_t,
	157	size_t,
	158	int);
	159	dma_addr_t (map_single)(struct xilly_cleanup ,
	160	struct xilly_endpoint *,
	161	void *,
	162	size_t,
	163	int);
	164	void (unmap_single)(struct xilly_dma entry);
	165	};
	166
	167	irqreturn_t xillybus_isr(int irq, void *data);
	168
	169	void xillybus_do_cleanup(struct xilly_cleanup *mem,
	170	struct xilly_endpoint *endpoint);
	171
	172	struct xilly_endpoint xillybus_init_endpoint(struct pci_dev pdev,
	173	struct device *dev,
	174	struct xilly_endpoint_hardware
	175	*ephw);
	176
	177	int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint);
	178
	179	void xillybus_endpoint_remove(struct xilly_endpoint *endpoint);
	180
	181	#endif /* __XILLYBUS_H */