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Merge remote-tracking branches 'asoc/fix/dpcm', 'asoc/fix/imx', 'asoc/fix/msm8916...
[linux-2.6-block.git] / drivers / staging / xgifb / vb_init.c
CommitLineData
949eb0ae 1#include <linux/delay.h>
02a81dd9 2#include <linux/vmalloc.h>
6048d761 3
d7636e0b 4#include "XGIfb.h"
d7636e0b 5#include "vb_def.h"
d7636e0b 6#include "vb_util.h"
7#include "vb_setmode.h"
e054102b 8#include "vb_init.h"
d6461e49
PH		 9static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
10 { 16, 0x45},
11 { 8, 0x35},
12 { 4, 0x31},
13 { 2, 0x21} };
14
15static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
16 { 128, 0x5D},
17 { 64, 0x59},
18 { 64, 0x4D},
19 { 32, 0x55},
20 { 32, 0x49},
21 { 32, 0x3D},
22 { 16, 0x51},
23 { 16, 0x45},
24 { 16, 0x39},
25 { 8, 0x41},
26 { 8, 0x35},
27 { 4, 0x31} };
d7636e0b 28
02a81dd9
AK		 29#define XGIFB_ROM_SIZE 65536
30
bf32fcb9
KT		 31static unsigned char
32XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
33 struct vb_device_info *pVBInfo)
d7636e0b 34{
b9ebf5e5 35 unsigned char data, temp;
d7636e0b 36
b9ebf5e5 37 if (HwDeviceExtension->jChipType < XG20) {
6d12dae4
PH		 38 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
39 if (data == 0)
40 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
41 0x02) >> 1;
42 return data;
b9ebf5e5 43 } else if (HwDeviceExtension->jChipType == XG27) {
58839b01 44 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
bf32fcb9 45 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
6490311f 46 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
b9ebf5e5
AK		 47 data = 0; /* DDR */
48 else
49 data = 1; /* DDRII */
50 return data;
51 } else if (HwDeviceExtension->jChipType == XG21) {
bf32fcb9
KT		 52 /* Independent GPIO control */
53 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
d8acac94 54 usleep_range(800, 1800);
b9bf6e4e 55 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
bf32fcb9 56 /* GPIOF 0:DVI 1:DVO */
fb70b191 57 data = xgifb_reg_get(pVBInfo->P3d4, 0x48);
bb1243a6
WF		 58 /*
59 * HOTPLUG_SUPPORT
60 * for current XG20 & XG21, GPIOH is floating, driver will
288f152c
JR		 61 * fix DDR temporarily
62 */
fb70b191
PH		 63 /* DVI read GPIOH */
64 data &= 0x01; /* 1=DDRII, 0=DDR */
b9ebf5e5 65 /* ~HOTPLUG_SUPPORT */
b9bf6e4e 66 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
b9ebf5e5 67 return data;
9c8c8315
TG		 68 }
69 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
d7636e0b 70
9c8c8315
TG		 71 if (data == 1)
72 data++;
d7636e0b 73
9c8c8315 74 return data;
b9ebf5e5 75}
d7636e0b 76
bf32fcb9
KT		 77static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
78 struct vb_device_info *pVBInfo)
b9ebf5e5 79{
8104e329
AK		 80 xgifb_reg_set(P3c4, 0x18, 0x01);
81 xgifb_reg_set(P3c4, 0x19, 0x20);
82 xgifb_reg_set(P3c4, 0x16, 0x00);
83 xgifb_reg_set(P3c4, 0x16, 0x80);
d7636e0b 84
d8acac94 85 usleep_range(3, 1003);
6d12dae4
PH		 86 xgifb_reg_set(P3c4, 0x18, 0x00);
87 xgifb_reg_set(P3c4, 0x19, 0x20);
88 xgifb_reg_set(P3c4, 0x16, 0x00);
89 xgifb_reg_set(P3c4, 0x16, 0x80);
d7636e0b 90
d8acac94 91 usleep_range(60, 1060);
597d96b6 92 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
8104e329 93 xgifb_reg_set(P3c4, 0x19, 0x01);
0904f7f3
AK		 94 xgifb_reg_set(P3c4, 0x16, 0x03);
95 xgifb_reg_set(P3c4, 0x16, 0x83);
d8acac94 96 usleep_range(1, 1001);
8104e329 97 xgifb_reg_set(P3c4, 0x1B, 0x03);
d8acac94 98 usleep_range(500, 1500);
597d96b6 99 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
8104e329 100 xgifb_reg_set(P3c4, 0x19, 0x00);
0904f7f3
AK		 101 xgifb_reg_set(P3c4, 0x16, 0x03);
102 xgifb_reg_set(P3c4, 0x16, 0x83);
8104e329 103 xgifb_reg_set(P3c4, 0x1B, 0x00);
b9ebf5e5 104}
d7636e0b 105
b053af16 106static void XGINew_SetMemoryClock(struct vb_device_info *pVBInfo)
b9ebf5e5 107{
bf32fcb9
KT		 108 xgifb_reg_set(pVBInfo->P3c4,
109 0x28,
2af1a29d 110 pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
bf32fcb9
KT		 111 xgifb_reg_set(pVBInfo->P3c4,
112 0x29,
2af1a29d 113 pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
bf32fcb9
KT		 114 xgifb_reg_set(pVBInfo->P3c4,
115 0x2A,
2af1a29d 116 pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
bf32fcb9
KT		 117
118 xgifb_reg_set(pVBInfo->P3c4,
119 0x2E,
9b047458 120 XGI340_ECLKData[pVBInfo->ram_type].SR2E);
bf32fcb9
KT		 121 xgifb_reg_set(pVBInfo->P3c4,
122 0x2F,
9b047458 123 XGI340_ECLKData[pVBInfo->ram_type].SR2F);
bf32fcb9
KT		 124 xgifb_reg_set(pVBInfo->P3c4,
125 0x30,
9b047458 126 XGI340_ECLKData[pVBInfo->ram_type].SR30);
b9ebf5e5 127}
d7636e0b 128
b9ebf5e5
AK		 129static void XGINew_DDRII_Bootup_XG27(
130 struct xgi_hw_device_info *HwDeviceExtension,
131 unsigned long P3c4, struct vb_device_info *pVBInfo)
132{
133 unsigned long P3d4 = P3c4 + 0x10;
694683f6 134
2af1a29d 135 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
b053af16 136 XGINew_SetMemoryClock(pVBInfo);
d7636e0b 137
b9ebf5e5 138 /* Set Double Frequency */
6d12dae4 139 xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
d7636e0b 140
d8acac94 141 usleep_range(200, 1200);
d7636e0b 142
8104e329
AK		 143 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
144 xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
145 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
d8acac94 146 usleep_range(15, 1015);
8104e329 147 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
d8acac94 148 usleep_range(15, 1015);
d7636e0b 149
8104e329
AK		 150 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
151 xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
152 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
d8acac94 153 usleep_range(15, 1015);
8104e329 154 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
d8acac94 155 usleep_range(15, 1015);
d7636e0b 156
8104e329
AK		 157 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
158 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
159 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
d8acac94 160 usleep_range(30, 1030);
8104e329 161 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
d8acac94 162 usleep_range(15, 1015);
d7636e0b 163
8104e329
AK		 164 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
165 xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
166 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
d8acac94 167 usleep_range(30, 1030);
8104e329
AK		 168 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
169 xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
d7636e0b 170
8104e329 171 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
d8acac94 172 usleep_range(60, 1060);
8104e329 173 xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
d7636e0b 174
8104e329
AK		 175 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
176 xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
177 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
d7636e0b 178
d8acac94 179 usleep_range(30, 1030);
8104e329 180 xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
d8acac94 181 usleep_range(15, 1015);
d7636e0b 182
8104e329
AK		 183 xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
184 xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
185 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
d8acac94 186 usleep_range(30, 1030);
8104e329 187 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
d8acac94 188 usleep_range(15, 1015);
d7636e0b 189
8104e329
AK		 190 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
191 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
192 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
d8acac94 193 usleep_range(30, 1030);
8104e329 194 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
d8acac94 195 usleep_range(15, 1015);
d7636e0b 196
bf32fcb9
KT		 197 /* Set SR1B refresh control 000:close; 010:open */
198 xgifb_reg_set(P3c4, 0x1B, 0x04);
d8acac94 199 usleep_range(200, 1200);
b9ebf5e5 200}
d7636e0b 201
b9ebf5e5 202static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
945e17ce
WF		 203 unsigned long P3c4,
204 struct vb_device_info *pVBInfo)
b9ebf5e5
AK		 205{
206 unsigned long P3d4 = P3c4 + 0x10;
d7636e0b 207
2af1a29d 208 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
b053af16 209 XGINew_SetMemoryClock(pVBInfo);
d7636e0b 210
8104e329 211 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
d7636e0b 212
d8acac94 213 usleep_range(200, 1200);
8104e329
AK		 214 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
215 xgifb_reg_set(P3c4, 0x19, 0x80);
216 xgifb_reg_set(P3c4, 0x16, 0x05);
217 xgifb_reg_set(P3c4, 0x16, 0x85);
218
219 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
220 xgifb_reg_set(P3c4, 0x19, 0xC0);
221 xgifb_reg_set(P3c4, 0x16, 0x05);
222 xgifb_reg_set(P3c4, 0x16, 0x85);
223
224 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
225 xgifb_reg_set(P3c4, 0x19, 0x40);
226 xgifb_reg_set(P3c4, 0x16, 0x05);
227 xgifb_reg_set(P3c4, 0x16, 0x85);
228
8104e329
AK		 229 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
230 xgifb_reg_set(P3c4, 0x19, 0x02);
231 xgifb_reg_set(P3c4, 0x16, 0x05);
232 xgifb_reg_set(P3c4, 0x16, 0x85);
a24d60f4 233
d8acac94 234 usleep_range(15, 1015);
8104e329 235 xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
d8acac94 236 usleep_range(30, 1030);
8104e329 237 xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
d8acac94 238 usleep_range(100, 1100);
a24d60f4 239
8104e329
AK		 240 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
241 xgifb_reg_set(P3c4, 0x19, 0x00);
242 xgifb_reg_set(P3c4, 0x16, 0x05);
243 xgifb_reg_set(P3c4, 0x16, 0x85);
a24d60f4 244
d8acac94 245 usleep_range(200, 1200);
b9ebf5e5 246}
a24d60f4 247
bf32fcb9
KT		 248static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
249 struct vb_device_info *pVBInfo)
b9ebf5e5 250{
8104e329
AK		 251 xgifb_reg_set(P3c4, 0x18, 0x01);
252 xgifb_reg_set(P3c4, 0x19, 0x40);
253 xgifb_reg_set(P3c4, 0x16, 0x00);
254 xgifb_reg_set(P3c4, 0x16, 0x80);
d8acac94 255 usleep_range(60, 1060);
a24d60f4 256
8104e329
AK		 257 xgifb_reg_set(P3c4, 0x18, 0x00);
258 xgifb_reg_set(P3c4, 0x19, 0x40);
259 xgifb_reg_set(P3c4, 0x16, 0x00);
260 xgifb_reg_set(P3c4, 0x16, 0x80);
d8acac94 261 usleep_range(60, 1060);
597d96b6 262 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
8104e329
AK		 263 xgifb_reg_set(P3c4, 0x19, 0x01);
264 xgifb_reg_set(P3c4, 0x16, 0x03);
265 xgifb_reg_set(P3c4, 0x16, 0x83);
d8acac94 266 usleep_range(1, 1001);
8104e329 267 xgifb_reg_set(P3c4, 0x1B, 0x03);
d8acac94 268 usleep_range(500, 1500);
597d96b6 269 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
8104e329
AK		 270 xgifb_reg_set(P3c4, 0x19, 0x00);
271 xgifb_reg_set(P3c4, 0x16, 0x03);
272 xgifb_reg_set(P3c4, 0x16, 0x83);
273 xgifb_reg_set(P3c4, 0x1B, 0x00);
b9ebf5e5 274}
a24d60f4 275
b9ebf5e5
AK		 276static void XGINew_DDR1x_DefaultRegister(
277 struct xgi_hw_device_info *HwDeviceExtension,
278 unsigned long Port, struct vb_device_info *pVBInfo)
279{
280 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
a24d60f4 281
b9ebf5e5 282 if (HwDeviceExtension->jChipType >= XG20) {
b053af16 283 XGINew_SetMemoryClock(pVBInfo);
bf32fcb9
KT		 284 xgifb_reg_set(P3d4,
285 0x82,
2af1a29d 286 pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
bf32fcb9
KT		 287 xgifb_reg_set(P3d4,
288 0x85,
2af1a29d 289 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
bf32fcb9
KT		 290 xgifb_reg_set(P3d4,
291 0x86,
2af1a29d 292 pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
a24d60f4 293
8104e329
AK		 294 xgifb_reg_set(P3d4, 0x98, 0x01);
295 xgifb_reg_set(P3d4, 0x9A, 0x02);
a24d60f4 296
b9ebf5e5
AK		 297 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
298 } else {
b053af16 299 XGINew_SetMemoryClock(pVBInfo);
a24d60f4 300
b9ebf5e5 301 switch (HwDeviceExtension->jChipType) {
b9ebf5e5 302 case XG42:
bf32fcb9
KT		 303 /* CR82 */
304 xgifb_reg_set(P3d4,
305 0x82,
2af1a29d 306 pVBInfo->CR40[11][pVBInfo->ram_type]);
bf32fcb9
KT		 307 /* CR85 */
308 xgifb_reg_set(P3d4,
309 0x85,
2af1a29d 310 pVBInfo->CR40[12][pVBInfo->ram_type]);
bf32fcb9
KT		 311 /* CR86 */
312 xgifb_reg_set(P3d4,
313 0x86,
2af1a29d 314 pVBInfo->CR40[13][pVBInfo->ram_type]);
b9ebf5e5
AK		 315 break;
316 default:
8104e329
AK		 317 xgifb_reg_set(P3d4, 0x82, 0x88);
318 xgifb_reg_set(P3d4, 0x86, 0x00);
bf32fcb9
KT		 319 /* Insert read command for delay */
320 xgifb_reg_get(P3d4, 0x86);
8104e329 321 xgifb_reg_set(P3d4, 0x86, 0x88);
58839b01 322 xgifb_reg_get(P3d4, 0x86);
bf32fcb9
KT		 323 xgifb_reg_set(P3d4,
324 0x86,
2af1a29d 325 pVBInfo->CR40[13][pVBInfo->ram_type]);
8104e329
AK		 326 xgifb_reg_set(P3d4, 0x82, 0x77);
327 xgifb_reg_set(P3d4, 0x85, 0x00);
bf32fcb9
KT		 328
329 /* Insert read command for delay */
330 xgifb_reg_get(P3d4, 0x85);
8104e329 331 xgifb_reg_set(P3d4, 0x85, 0x88);
bf32fcb9
KT		 332
333 /* Insert read command for delay */
334 xgifb_reg_get(P3d4, 0x85);
335 /* CR85 */
336 xgifb_reg_set(P3d4,
337 0x85,
2af1a29d 338 pVBInfo->CR40[12][pVBInfo->ram_type]);
bf32fcb9
KT		 339 /* CR82 */
340 xgifb_reg_set(P3d4,
341 0x82,
2af1a29d 342 pVBInfo->CR40[11][pVBInfo->ram_type]);
b9ebf5e5 343 break;
a24d60f4 344 }
a24d60f4 345
8104e329
AK		 346 xgifb_reg_set(P3d4, 0x97, 0x00);
347 xgifb_reg_set(P3d4, 0x98, 0x01);
348 xgifb_reg_set(P3d4, 0x9A, 0x02);
b9ebf5e5
AK		 349 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
350 }
351}
a24d60f4 352
b9ebf5e5
AK		 353static void XGINew_DDR2_DefaultRegister(
354 struct xgi_hw_device_info *HwDeviceExtension,
355 unsigned long Port, struct vb_device_info *pVBInfo)
356{
357 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
bb1243a6
WF		 358 /*
359 * keep following setting sequence, each setting in
56e18f8c
CB		 360 * the same reg insert idle
361 */
8104e329
AK		 362 xgifb_reg_set(P3d4, 0x82, 0x77);
363 xgifb_reg_set(P3d4, 0x86, 0x00);
58839b01 364 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
8104e329 365 xgifb_reg_set(P3d4, 0x86, 0x88);
58839b01 366 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
bf32fcb9 367 /* CR86 */
2af1a29d 368 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
8104e329
AK		 369 xgifb_reg_set(P3d4, 0x82, 0x77);
370 xgifb_reg_set(P3d4, 0x85, 0x00);
58839b01 371 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
8104e329 372 xgifb_reg_set(P3d4, 0x85, 0x88);
58839b01 373 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
2af1a29d
AK		 374 xgifb_reg_set(P3d4,
375 0x85,
376 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
b9ebf5e5 377 if (HwDeviceExtension->jChipType == XG27)
bf32fcb9 378 /* CR82 */
2af1a29d 379 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
b9ebf5e5 380 else
8104e329 381 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
a24d60f4 382
8104e329
AK		 383 xgifb_reg_set(P3d4, 0x98, 0x01);
384 xgifb_reg_set(P3d4, 0x9A, 0x02);
b9ebf5e5
AK		 385 if (HwDeviceExtension->jChipType == XG27)
386 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
387 else
388 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
389}
a24d60f4 390
0141bb2e 391static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
945e17ce 392 u8 shift_factor, u8 mask1, u8 mask2)
0141bb2e
PH		 393{
394 u8 j;
694683f6 395
0141bb2e
PH		 396 for (j = 0; j < 4; j++) {
397 temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
398 xgifb_reg_set(P3d4, reg, temp2);
399 xgifb_reg_get(P3d4, reg);
400 temp2 &= mask1;
401 temp2 += mask2;
402 }
403}
404
b9ebf5e5
AK		 405static void XGINew_SetDRAMDefaultRegister340(
406 struct xgi_hw_device_info *HwDeviceExtension,
407 unsigned long Port, struct vb_device_info *pVBInfo)
408{
fc008aff 409 unsigned char temp, temp1, temp2, temp3, j, k;
a24d60f4 410
b9ebf5e5 411 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
a24d60f4 412
2af1a29d
AK		 413 xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
414 xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
415 xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
416 xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
a24d60f4 417
1504ecbe 418 /* CR6B DQS fine tune delay */
6a7fd2db 419 temp = 0xaa;
1504ecbe 420 XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
a24d60f4 421
1504ecbe
PH		 422 /* CR6E DQM fine tune delay */
423 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
a24d60f4 424
b9ebf5e5
AK		 425 temp3 = 0;
426 for (k = 0; k < 4; k++) {
bf32fcb9
KT		 427 /* CR6E_D[1:0] select channel */
428 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
1504ecbe 429 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
b9ebf5e5
AK		 430 temp3 += 0x01;
431 }
a24d60f4 432
2af1a29d
AK		 433 xgifb_reg_set(P3d4,
434 0x80,
435 pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
436 xgifb_reg_set(P3d4,
437 0x81,
438 pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
a24d60f4 439
b9ebf5e5 440 temp2 = 0x80;
bf32fcb9 441 /* CR89 terminator type select */
0141bb2e 442 XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
a24d60f4 443
7e29d632 444 temp = 0;
b9ebf5e5
AK		 445 temp1 = temp & 0x03;
446 temp2 |= temp1;
8104e329 447 xgifb_reg_set(P3d4, 0x89, temp2);
a24d60f4 448
2af1a29d 449 temp = pVBInfo->CR40[3][pVBInfo->ram_type];
b9ebf5e5
AK		 450 temp1 = temp & 0x0F;
451 temp2 = (temp >> 4) & 0x07;
452 temp3 = temp & 0x80;
8104e329
AK		 453 xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
454 xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
b9bf6e4e 455 xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
2af1a29d
AK		 456 xgifb_reg_set(P3d4,
457 0x41,
458 pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
a24d60f4 459
b9ebf5e5 460 if (HwDeviceExtension->jChipType == XG27)
6d12dae4 461 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
a24d60f4 462
bf32fcb9 463 for (j = 0; j <= 6; j++) /* CR90 - CR96 */
8104e329 464 xgifb_reg_set(P3d4, (0x90 + j),
945e17ce 465 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
a24d60f4 466
bf32fcb9 467 for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
8104e329 468 xgifb_reg_set(P3d4, (0xC3 + j),
945e17ce 469 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
a24d60f4 470
bf32fcb9 471 for (j = 0; j < 2; j++) /* CR8A - CR8B */
8104e329 472 xgifb_reg_set(P3d4, (0x8A + j),
945e17ce 473 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
a24d60f4 474
18408da0 475 if (HwDeviceExtension->jChipType == XG42)
8104e329 476 xgifb_reg_set(P3d4, 0x8C, 0x87);
a24d60f4 477
2af1a29d
AK		 478 xgifb_reg_set(P3d4,
479 0x59,
480 pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
a24d60f4 481
8104e329
AK		 482 xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
483 xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
6d12dae4 484 xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
2af1a29d 485 if (pVBInfo->ram_type) {
8104e329 486 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
b9ebf5e5 487 if (HwDeviceExtension->jChipType == XG27)
8104e329 488 xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
a24d60f4 489
b9ebf5e5 490 } else {
8104e329 491 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
b9ebf5e5 492 }
8104e329 493 xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
a24d60f4 494
b9ebf5e5
AK		 495 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
496 if (temp == 0) {
497 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
498 } else {
8104e329 499 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
b9ebf5e5
AK		 500 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
501 }
d7ab4a4f 502 xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */
b9ebf5e5 503}
a24d60f4 504
d6461e49
PH		 505static unsigned short XGINew_SetDRAMSize20Reg(
506 unsigned short dram_size,
b9ebf5e5 507 struct vb_device_info *pVBInfo)
d7636e0b 508{
b9ebf5e5
AK		 509 unsigned short data = 0, memsize = 0;
510 int RankSize;
511 unsigned char ChannelNo;
d7636e0b 512
d6461e49 513 RankSize = dram_size * pVBInfo->ram_bus / 8;
58839b01 514 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
b9ebf5e5 515 data &= 0x80;
d7636e0b 516
b9ebf5e5
AK		 517 if (data == 0x80)
518 RankSize *= 2;
a24d60f4 519
b9ebf5e5 520 data = 0;
a24d60f4 521
ee055a48 522 if (pVBInfo->ram_channel == 3)
b9ebf5e5
AK		 523 ChannelNo = 4;
524 else
ee055a48 525 ChannelNo = pVBInfo->ram_channel;
a24d60f4 526
b9ebf5e5
AK		 527 if (ChannelNo * RankSize <= 256) {
528 while ((RankSize >>= 1) > 0)
529 data += 0x10;
a24d60f4 530
b9ebf5e5 531 memsize = data >> 4;
a24d60f4 532
949eb0ae 533 /* Fix DRAM Sizing Error */
bf32fcb9
KT		 534 xgifb_reg_set(pVBInfo->P3c4,
535 0x14,
536 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
537 (data & 0xF0));
d8acac94 538 usleep_range(15, 1015);
b9ebf5e5
AK		 539 }
540 return memsize;
541}
a24d60f4 542
b9ebf5e5 543static int XGINew_ReadWriteRest(unsigned short StopAddr,
945e17ce
WF		 544 unsigned short StartAddr,
545 struct vb_device_info *pVBInfo)
b9ebf5e5
AK		 546{
547 int i;
548 unsigned long Position = 0;
c44fa627 549 void __iomem *fbaddr = pVBInfo->FBAddr;
a24d60f4 550
c44fa627 551 writel(Position, fbaddr + Position);
a24d60f4 552
b9ebf5e5
AK		 553 for (i = StartAddr; i <= StopAddr; i++) {
554 Position = 1 << i;
c44fa627 555 writel(Position, fbaddr + Position);
b9ebf5e5 556 }
a24d60f4 557
d3d62d1d
CB		 558 /* Fix #1759 Memory Size error in Multi-Adapter. */
559 usleep_range(500, 1500);
a24d60f4 560
b9ebf5e5
AK		 561 Position = 0;
562
c44fa627 563 if (readl(fbaddr + Position) != Position)
b9ebf5e5 564 return 0;
d7636e0b 565
b9ebf5e5
AK		 566 for (i = StartAddr; i <= StopAddr; i++) {
567 Position = 1 << i;
c44fa627 568 if (readl(fbaddr + Position) != Position)
b9ebf5e5
AK		 569 return 0;
570 }
571 return 1;
d7636e0b 572}
a24d60f4 573
b9ebf5e5 574static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
d7636e0b 575{
b9ebf5e5 576 unsigned char data;
a24d60f4 577
58839b01 578 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
a24d60f4 579
b9ebf5e5 580 if ((data & 0x10) == 0) {
58839b01 581 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
1f8bb58e 582 return (data & 0x02) >> 1;
b9ebf5e5 583 }
9c8c8315 584 return data & 0x01;
b9ebf5e5 585}
a24d60f4 586
b9ebf5e5 587static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
945e17ce 588 struct vb_device_info *pVBInfo)
b9ebf5e5
AK		 589{
590 unsigned char data;
a24d60f4 591
b9ebf5e5
AK		 592 switch (HwDeviceExtension->jChipType) {
593 case XG20:
594 case XG21:
58839b01 595 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
b9ebf5e5 596 data = data & 0x01;
ee055a48 597 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
a24d60f4 598
b9ebf5e5 599 if (data == 0) { /* Single_32_16 */
a24d60f4 600
b9ebf5e5
AK		 601 if ((HwDeviceExtension->ulVideoMemorySize - 1)
602 > 0x1000000) {
2f0f395e 603 pVBInfo->ram_bus = 32; /* 32 bits */
bf32fcb9
KT		 604 /* 22bit + 2 rank + 32bit */
605 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
8104e329 606 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
d8acac94 607 usleep_range(15, 1015);
a24d60f4 608
b9ebf5e5
AK		 609 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
610 return;
d7636e0b 611
bf32fcb9
KT		 612 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
613 0x800000) {
614 /* 22bit + 1 rank + 32bit */
615 xgifb_reg_set(pVBInfo->P3c4,
616 0x13,
617 0x31);
618 xgifb_reg_set(pVBInfo->P3c4,
619 0x14,
620 0x42);
d8acac94 621 usleep_range(15, 1015);
a24d60f4 622
bf32fcb9
KT		 623 if (XGINew_ReadWriteRest(23,
624 23,
625 pVBInfo) == 1)
b9ebf5e5
AK		 626 return;
627 }
628 }
a24d60f4 629
bf32fcb9
KT		 630 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
631 0x800000) {
2f0f395e 632 pVBInfo->ram_bus = 16; /* 16 bits */
bf32fcb9
KT		 633 /* 22bit + 2 rank + 16bit */
634 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
8104e329 635 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
d8acac94 636 usleep_range(15, 1015);
a24d60f4 637
b9ebf5e5
AK		 638 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
639 return;
9c8c8315
TG		 640 xgifb_reg_set(pVBInfo->P3c4,
641 0x13,
642 0x31);
d8acac94 643 usleep_range(15, 1015);
b9ebf5e5 644 }
a24d60f4 645
b9ebf5e5 646 } else { /* Dual_16_8 */
bf32fcb9
KT		 647 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
648 0x800000) {
2f0f395e 649 pVBInfo->ram_bus = 16; /* 16 bits */
bf32fcb9
KT		 650 /* (0x31:12x8x2) 22bit + 2 rank */
651 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
bb1243a6 652 /* 0x41:16Mx16 bit */
bf32fcb9 653 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
d8acac94 654 usleep_range(15, 1015);
a24d60f4 655
b9ebf5e5
AK		 656 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
657 return;
a24d60f4 658
bf32fcb9
KT		 659 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
660 0x400000) {
661 /* (0x31:12x8x2) 22bit + 1 rank */
662 xgifb_reg_set(pVBInfo->P3c4,
663 0x13,
664 0x31);
bb1243a6 665 /* 0x31:8Mx16 bit */
bf32fcb9
KT		 666 xgifb_reg_set(pVBInfo->P3c4,
667 0x14,
668 0x31);
d8acac94 669 usleep_range(15, 1015);
a24d60f4 670
bf32fcb9
KT		 671 if (XGINew_ReadWriteRest(22,
672 22,
673 pVBInfo) == 1)
b9ebf5e5
AK		 674 return;
675 }
676 }
a24d60f4 677
bf32fcb9
KT		 678 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
679 0x400000) {
2f0f395e 680 pVBInfo->ram_bus = 8; /* 8 bits */
bf32fcb9
KT		 681 /* (0x31:12x8x2) 22bit + 2 rank */
682 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
bb1243a6 683 /* 0x30:8Mx8 bit */
bf32fcb9 684 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
d8acac94 685 usleep_range(15, 1015);
d7636e0b 686
b9ebf5e5
AK		 687 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
688 return;
9c8c8315
TG		 689
690 /* (0x31:12x8x2) 22bit + 1 rank */
691 xgifb_reg_set(pVBInfo->P3c4,
692 0x13,
693 0x31);
d8acac94 694 usleep_range(15, 1015);
a24d60f4
PS		 695 }
696 }
b9ebf5e5 697 break;
a24d60f4 698
b9ebf5e5 699 case XG27:
2f0f395e 700 pVBInfo->ram_bus = 16; /* 16 bits */
ee055a48 701 pVBInfo->ram_channel = 1; /* Single channel */
bb1243a6 702 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit */
b9ebf5e5 703 break;
b9ebf5e5
AK		 704 case XG42:
705 /*
56e18f8c
CB		 706 * XG42 SR14 D[3] Reserve
707 * D[2] = 1, Dual Channel
708 * = 0, Single Channel
709 *
710 * It's Different from Other XG40 Series.
b9ebf5e5
AK		 711 */
712 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
2f0f395e 713 pVBInfo->ram_bus = 32; /* 32 bits */
ee055a48 714 pVBInfo->ram_channel = 2; /* 2 Channel */
8104e329
AK		 715 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
716 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
a24d60f4 717
b9ebf5e5
AK		 718 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
719 return;
a24d60f4 720
8104e329
AK		 721 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
722 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
b9ebf5e5
AK		 723 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
724 return;
a24d60f4 725
ee055a48 726 pVBInfo->ram_channel = 1; /* Single Channel */
8104e329
AK		 727 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
728 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
d7636e0b 729
b9ebf5e5
AK		 730 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
731 return;
9c8c8315
TG		 732 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
733 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
b9ebf5e5 734 } else { /* DDR */
2f0f395e 735 pVBInfo->ram_bus = 64; /* 64 bits */
ee055a48 736 pVBInfo->ram_channel = 1; /* 1 channels */
8104e329
AK		 737 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
738 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
d7636e0b 739
b9ebf5e5
AK		 740 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
741 return;
9c8c8315
TG		 742 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
743 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
b9ebf5e5 744 }
d7636e0b 745
b9ebf5e5 746 break;
d7636e0b 747
b9ebf5e5 748 default: /* XG40 */
d7636e0b 749
b9ebf5e5 750 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
2f0f395e 751 pVBInfo->ram_bus = 32; /* 32 bits */
ee055a48 752 pVBInfo->ram_channel = 3;
8104e329
AK		 753 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
754 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
d7636e0b 755
b9ebf5e5
AK		 756 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
757 return;
d7636e0b 758
ee055a48 759 pVBInfo->ram_channel = 2; /* 2 channels */
8104e329 760 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
a24d60f4 761
b9ebf5e5
AK		 762 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
763 return;
d7636e0b 764
8104e329
AK		 765 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
766 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
d7636e0b 767
b9ebf5e5 768 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
ee055a48 769 pVBInfo->ram_channel = 3; /* 4 channels */
b9ebf5e5 770 } else {
ee055a48 771 pVBInfo->ram_channel = 2; /* 2 channels */
8104e329 772 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
b9ebf5e5
AK		 773 }
774 } else { /* DDR */
2f0f395e 775 pVBInfo->ram_bus = 64; /* 64 bits */
ee055a48 776 pVBInfo->ram_channel = 2; /* 2 channels */
8104e329
AK		 777 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
778 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
d7636e0b 779
9c8c8315 780 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
b9ebf5e5 781 return;
9c8c8315
TG		 782 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
783 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
b9ebf5e5
AK		 784 }
785 break;
a24d60f4 786 }
d7636e0b 787}
788
b9ebf5e5 789static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
945e17ce 790 struct vb_device_info *pVBInfo)
d7636e0b 791{
672f5ee2
PH		 792 u8 i, size;
793 unsigned short memsize, start_addr;
d6461e49 794 const unsigned short (*dram_table)[2];
d7636e0b 795
8104e329
AK		 796 xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
797 xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
b9ebf5e5 798 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
d7636e0b 799
b9ebf5e5 800 if (HwDeviceExtension->jChipType >= XG20) {
672f5ee2
PH		 801 dram_table = XGINew_DDRDRAM_TYPE20;
802 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
803 start_addr = 5;
b9ebf5e5 804 } else {
672f5ee2
PH		 805 dram_table = XGINew_DDRDRAM_TYPE340;
806 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
807 start_addr = 9;
808 }
809
810 for (i = 0; i < size; i++) {
4e55d0b3 811 /* SetDRAMSizingType */
d6461e49 812 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
d8acac94 813 usleep_range(50, 1050); /* should delay 50 ns */
4e55d0b3 814
d6461e49 815 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
672f5ee2
PH		 816
817 if (memsize == 0)
818 continue;
819
820 memsize += (pVBInfo->ram_channel - 2) + 20;
821 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
c3a56f75 822 (unsigned long)(1 << memsize))
672f5ee2
PH		 823 continue;
824
825 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
826 return 1;
a24d60f4 827 }
b9ebf5e5 828 return 0;
a24d60f4 829}
d7636e0b 830
fab04b97 831static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
945e17ce
WF		 832 struct xgi_hw_device_info *HwDeviceExtension,
833 struct vb_device_info *pVBInfo)
d7636e0b 834{
b9ebf5e5 835 unsigned short data;
a24d60f4 836
b9ebf5e5 837 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
a24d60f4 838
fab04b97 839 XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
a24d60f4 840
58839b01 841 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
bf32fcb9 842 /* disable read cache */
c3a56f75 843 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF));
fab04b97 844 XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
a24d60f4 845
b9ebf5e5 846 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
58839b01 847 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
bf32fcb9 848 /* enable read cache */
c3a56f75 849 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20));
b9ebf5e5 850}
a24d60f4 851
08ce239c 852static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
02a81dd9
AK		 853{
854 void __iomem *rom_address;
82986dd9 855 u8 *rom_copy;
02a81dd9 856
08ce239c 857 rom_address = pci_map_rom(dev, rom_size);
076e2358 858 if (!rom_address)
02a81dd9
AK		 859 return NULL;
860
861 rom_copy = vzalloc(XGIFB_ROM_SIZE);
076e2358 862 if (!rom_copy)
02a81dd9
AK		 863 goto done;
864
08ce239c
AK		 865 *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
866 memcpy_fromio(rom_copy, rom_address, *rom_size);
02a81dd9
AK		 867
868done:
869 pci_unmap_rom(dev, rom_address);
870 return rom_copy;
871}
872
334ab072 873static bool xgifb_read_vbios(struct pci_dev *pdev)
b9ebf5e5 874{
02a81dd9 875 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
82986dd9 876 u8 *vbios;
b9ebf5e5 877 unsigned long i;
d1805b38 878 unsigned char j;
97f4532d 879 struct XGI21_LVDSCapStruct *lvds;
08ce239c 880 size_t vbios_size;
d1805b38 881 int entry;
a24d60f4 882
08ce239c 883 vbios = xgifb_copy_rom(pdev, &vbios_size);
076e2358 884 if (!vbios) {
be25aef0 885 dev_err(&pdev->dev, "Video BIOS not available\n");
c0d60da8 886 return false;
02a81dd9 887 }
08ce239c
AK		 888 if (vbios_size <= 0x65)
889 goto error;
25aa75f1
AK		 890 /*
891 * The user can ignore the LVDS bit in the BIOS and force the display
892 * type.
893 */
894 if (!(vbios[0x65] & 0x1) &&
895 (!xgifb_info->display2_force ||
896 xgifb_info->display2 != XGIFB_DISP_LCD)) {
02a81dd9 897 vfree(vbios);
c0d60da8 898 return false;
02a81dd9 899 }
08ce239c
AK		 900 if (vbios_size <= 0x317)
901 goto error;
4b21d990 902 i = vbios[0x316] | (vbios[0x317] << 8);
08ce239c
AK		 903 if (vbios_size <= i - 1)
904 goto error;
4b21d990 905 j = vbios[i - 1];
08ce239c
AK		 906 if (j == 0)
907 goto error;
bd761274
AK		 908 if (j == 0xff)
909 j = 1;
bb1243a6
WF		 910
911 /* Read the LVDS table index scratch register set by the BIOS. */
912
d1805b38
AK		 913 entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
914 if (entry >= j)
915 entry = 0;
916 i += entry * 25;
fab04b97 917 lvds = &xgifb_info->lvds_data;
d1805b38
AK		 918 if (vbios_size <= i + 24)
919 goto error;
920 lvds->LVDS_Capability = vbios[i] | (vbios[i + 1] << 8);
921 lvds->LVDSHT = vbios[i + 2] | (vbios[i + 3] << 8);
922 lvds->LVDSVT = vbios[i + 4] | (vbios[i + 5] << 8);
923 lvds->LVDSHDE = vbios[i + 6] | (vbios[i + 7] << 8);
924 lvds->LVDSVDE = vbios[i + 8] | (vbios[i + 9] << 8);
925 lvds->LVDSHFP = vbios[i + 10] | (vbios[i + 11] << 8);
926 lvds->LVDSVFP = vbios[i + 12] | (vbios[i + 13] << 8);
927 lvds->LVDSHSYNC = vbios[i + 14] | (vbios[i + 15] << 8);
928 lvds->LVDSVSYNC = vbios[i + 16] | (vbios[i + 17] << 8);
929 lvds->VCLKData1 = vbios[i + 18];
930 lvds->VCLKData2 = vbios[i + 19];
931 lvds->PSC_S1 = vbios[i + 20];
932 lvds->PSC_S2 = vbios[i + 21];
933 lvds->PSC_S3 = vbios[i + 22];
934 lvds->PSC_S4 = vbios[i + 23];
935 lvds->PSC_S5 = vbios[i + 24];
02a81dd9 936 vfree(vbios);
c0d60da8 937 return true;
08ce239c 938error:
be25aef0 939 dev_err(&pdev->dev, "Video BIOS corrupted\n");
08ce239c 940 vfree(vbios);
c0d60da8 941 return false;
b9ebf5e5 942}
a24d60f4 943
b053af16 944static void XGINew_ChkSenseStatus(struct vb_device_info *pVBInfo)
b9ebf5e5
AK		 945{
946 unsigned short tempbx = 0, temp, tempcx, CR3CData;
a24d60f4 947
58839b01 948 temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
a24d60f4 949
b9ebf5e5
AK		 950 if (temp & Monitor1Sense)
951 tempbx |= ActiveCRT1;
952 if (temp & LCDSense)
953 tempbx |= ActiveLCD;
954 if (temp & Monitor2Sense)
955 tempbx |= ActiveCRT2;
956 if (temp & TVSense) {
957 tempbx |= ActiveTV;
958 if (temp & AVIDEOSense)
959 tempbx |= (ActiveAVideo << 8);
960 if (temp & SVIDEOSense)
961 tempbx |= (ActiveSVideo << 8);
962 if (temp & SCARTSense)
963 tempbx |= (ActiveSCART << 8);
964 if (temp & HiTVSense)
965 tempbx |= (ActiveHiTV << 8);
966 if (temp & YPbPrSense)
967 tempbx |= (ActiveYPbPr << 8);
968 }
a24d60f4 969
58839b01
AK		 970 tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
971 tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
a24d60f4 972
b9ebf5e5 973 if (tempbx & tempcx) {
58839b01 974 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
3bcc2460 975 if (!(CR3CData & DisplayDeviceFromCMOS))
b9ebf5e5 976 tempcx = 0x1FF0;
b9ebf5e5
AK		 977 } else {
978 tempcx = 0x1FF0;
b9ebf5e5 979 }
a24d60f4 980
b9ebf5e5 981 tempbx &= tempcx;
8104e329
AK		 982 xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
983 xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
b9ebf5e5 984}
d7636e0b 985
b053af16 986static void XGINew_SetModeScratch(struct vb_device_info *pVBInfo)
b9ebf5e5
AK		 987{
988 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
d7636e0b 989
58839b01
AK		 990 temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
991 temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
992 temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
d7636e0b 993
b9ebf5e5
AK		 994 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
995 if (temp & ActiveCRT2)
996 tempcl = SetCRT2ToRAMDAC;
997 }
d7636e0b 998
b9ebf5e5
AK		 999 if (temp & ActiveLCD) {
1000 tempcl |= SetCRT2ToLCD;
1001 if (temp & DriverMode) {
1002 if (temp & ActiveTV) {
1003 tempch = SetToLCDA | EnableDualEdge;
1004 temp ^= SetCRT2ToLCD;
d7636e0b 1005
b9ebf5e5
AK		 1006 if ((temp >> 8) & ActiveAVideo)
1007 tempcl |= SetCRT2ToAVIDEO;
1008 if ((temp >> 8) & ActiveSVideo)
1009 tempcl |= SetCRT2ToSVIDEO;
1010 if ((temp >> 8) & ActiveSCART)
1011 tempcl |= SetCRT2ToSCART;
a24d60f4 1012
b9ebf5e5
AK		 1013 if (pVBInfo->IF_DEF_HiVision == 1) {
1014 if ((temp >> 8) & ActiveHiTV)
599801f9 1015 tempcl |= SetCRT2ToHiVision;
b9ebf5e5 1016 }
a24d60f4 1017
b9ebf5e5
AK		 1018 if (pVBInfo->IF_DEF_YPbPr == 1) {
1019 if ((temp >> 8) & ActiveYPbPr)
1020 tempch |= SetYPbPr;
1021 }
1022 }
1023 }
1024 } else {
1025 if ((temp >> 8) & ActiveAVideo)
1026 tempcl |= SetCRT2ToAVIDEO;
1027 if ((temp >> 8) & ActiveSVideo)
1028 tempcl |= SetCRT2ToSVIDEO;
1029 if ((temp >> 8) & ActiveSCART)
1030 tempcl |= SetCRT2ToSCART;
a24d60f4 1031
b9ebf5e5
AK		 1032 if (pVBInfo->IF_DEF_HiVision == 1) {
1033 if ((temp >> 8) & ActiveHiTV)
599801f9 1034 tempcl |= SetCRT2ToHiVision;
b9ebf5e5 1035 }
a24d60f4 1036
b9ebf5e5
AK		 1037 if (pVBInfo->IF_DEF_YPbPr == 1) {
1038 if ((temp >> 8) & ActiveYPbPr)
1039 tempch |= SetYPbPr;
1040 }
1041 }
d7636e0b 1042
b9ebf5e5 1043 tempcl |= SetSimuScanMode;
49a906a9
WF		 1044 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) ||
1045 (temp & ActiveTV) ||
1046 (temp & ActiveCRT2)))
6896b94e 1047 tempcl ^= (SetSimuScanMode | SwitchCRT2);
b9ebf5e5 1048 if ((temp & ActiveLCD) && (temp & ActiveTV))
6896b94e 1049 tempcl ^= (SetSimuScanMode | SwitchCRT2);
8104e329 1050 xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
d7636e0b 1051
58839b01 1052 CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
b9ebf5e5
AK		 1053 CR31Data &= ~(SetNotSimuMode >> 8);
1054 if (!(temp & ActiveCRT1))
1055 CR31Data |= (SetNotSimuMode >> 8);
1056 CR31Data &= ~(DisableCRT2Display >> 8);
1057 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1058 CR31Data |= (DisableCRT2Display >> 8);
8104e329 1059 xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
d7636e0b 1060
58839b01 1061 CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
b9ebf5e5
AK		 1062 CR38Data &= ~SetYPbPr;
1063 CR38Data |= tempch;
8104e329 1064 xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
b9ebf5e5 1065}
a24d60f4 1066
40544b04
AK		 1067static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1068 *HwDeviceExtension,
1069 struct vb_device_info *pVBInfo)
1070{
bcd1f165
PH		 1071 unsigned short temp = HwDeviceExtension->ulCRT2LCDType;
1072
1073 switch (HwDeviceExtension->ulCRT2LCDType) {
1074 case LCD_640x480:
1075 case LCD_1024x600:
1076 case LCD_1152x864:
1077 case LCD_1280x960:
1078 case LCD_1152x768:
1079 case LCD_1920x1440:
1080 case LCD_2048x1536:
1081 temp = 0; /* overwrite used ulCRT2LCDType */
1082 break;
1083 case LCD_UNKNOWN: /* unknown lcd, do nothing */
40544b04 1084 return 0;
40544b04 1085 }
bcd1f165
PH		 1086 xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1087 return 1;
40544b04
AK		 1088}
1089
c0d60da8 1090static void XGINew_GetXG21Sense(struct pci_dev *pdev,
945e17ce 1091 struct vb_device_info *pVBInfo)
b9ebf5e5 1092{
c0d60da8 1093 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
b9ebf5e5 1094 unsigned char Temp;
a24d60f4 1095
334ab072 1096 if (xgifb_read_vbios(pdev)) { /* For XG21 LVDS */
b9bf6e4e 1097 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
bf32fcb9
KT		 1098 /* LVDS on chip */
1099 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
b9ebf5e5 1100 } else {
bb1243a6 1101 /* Enable GPIOA/B read */
bf32fcb9 1102 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
58839b01 1103 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
b9ebf5e5 1104 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
c0d60da8 1105 XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo);
b9bf6e4e 1106 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
bf32fcb9
KT		 1107 /* Enable read GPIOF */
1108 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
9195ba09
PH		 1109 if (xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04)
1110 Temp = 0xA0; /* Only DVO on chip */
a24d60f4 1111 else
9195ba09
PH		 1112 Temp = 0x80; /* TMDS on chip */
1113 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, Temp);
bf32fcb9
KT		 1114 /* Disable read GPIOF */
1115 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
a24d60f4 1116 }
b9ebf5e5 1117 }
b9ebf5e5 1118}
a24d60f4 1119
b053af16 1120static void XGINew_GetXG27Sense(struct vb_device_info *pVBInfo)
b9ebf5e5
AK		 1121{
1122 unsigned char Temp, bCR4A;
a24d60f4 1123
58839b01 1124 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
bb1243a6 1125 /* Enable GPIOA/B/C read */
bf32fcb9 1126 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
58839b01 1127 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
8104e329 1128 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
a24d60f4 1129
b9ebf5e5 1130 if (Temp <= 0x02) {
bf32fcb9
KT		 1131 /* LVDS setting */
1132 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
8104e329 1133 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
b9ebf5e5 1134 } else {
bf32fcb9
KT		 1135 /* TMDS/DVO setting */
1136 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
b9ebf5e5 1137 }
b9bf6e4e 1138 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
b9ebf5e5 1139}
a24d60f4 1140
b9ebf5e5
AK		 1141static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1142{
1143 unsigned char CR38, CR4A, temp;
a24d60f4 1144
58839b01 1145 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
bf32fcb9
KT		 1146 /* enable GPIOE read */
1147 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
58839b01 1148 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
b9ebf5e5
AK		 1149 temp = 0;
1150 if ((CR38 & 0xE0) > 0x80) {
58839b01 1151 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
b9ebf5e5
AK		 1152 temp &= 0x08;
1153 temp >>= 3;
1154 }
a24d60f4 1155
8104e329 1156 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
a24d60f4 1157
b9ebf5e5
AK		 1158 return temp;
1159}
a24d60f4 1160
b9ebf5e5
AK		 1161static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1162{
1163 unsigned char CR4A, temp;
a24d60f4 1164
58839b01 1165 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
bf32fcb9
KT		 1166 /* enable GPIOA/B/C read */
1167 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
58839b01 1168 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
986eb9fa 1169 if (temp > 2)
2f123cbc 1170 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
a24d60f4 1171
8104e329 1172 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
a24d60f4 1173
b9ebf5e5
AK		 1174 return temp;
1175}
a24d60f4 1176
c976c781
AK		 1177static bool xgifb_bridge_is_on(struct vb_device_info *vb_info)
1178{
1179 u8 flag;
1180
1181 flag = xgifb_reg_get(vb_info->Part4Port, 0x00);
1182 return flag == 1 || flag == 2;
1183}
1184
6048d761 1185unsigned char XGIInitNew(struct pci_dev *pdev)
b9ebf5e5 1186{
ab886ff8 1187 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
6048d761 1188 struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
b9ebf5e5
AK		 1189 struct vb_device_info VBINF;
1190 struct vb_device_info *pVBInfo = &VBINF;
1191 unsigned char i, temp = 0, temp1;
a24d60f4 1192
b9ebf5e5 1193 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
a24d60f4 1194
076e2358 1195 if (!pVBInfo->FBAddr) {
19185703 1196 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
b9ebf5e5
AK		 1197 return 0;
1198 }
a24d60f4 1199
56810a92 1200 XGIRegInit(pVBInfo, xgifb_info->vga_base);
d7636e0b 1201
b8e1cc5c
AK		 1202 outb(0x67, pVBInfo->P3c2);
1203
b9ebf5e5
AK		 1204 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1205
949eb0ae 1206 /* Openkey */
8104e329 1207 xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
b9ebf5e5
AK		 1208
1209 /* GetXG21Sense (GPIO) */
1210 if (HwDeviceExtension->jChipType == XG21)
c0d60da8 1211 XGINew_GetXG21Sense(pdev, pVBInfo);
b9ebf5e5
AK		 1212
1213 if (HwDeviceExtension->jChipType == XG27)
b053af16 1214 XGINew_GetXG27Sense(pVBInfo);
b9ebf5e5 1215
949eb0ae 1216 /* Reset Extended register */
b9ebf5e5
AK		 1217
1218 for (i = 0x06; i < 0x20; i++)
8104e329 1219 xgifb_reg_set(pVBInfo->P3c4, i, 0);
b9ebf5e5
AK		 1220
1221 for (i = 0x21; i <= 0x27; i++)
8104e329 1222 xgifb_reg_set(pVBInfo->P3c4, i, 0);
b9ebf5e5 1223
06587335 1224 for (i = 0x31; i <= 0x3B; i++)
8104e329 1225 xgifb_reg_set(pVBInfo->P3c4, i, 0);
d7636e0b 1226
949eb0ae 1227 /* Auto over driver for XG42 */
bf32fcb9 1228 if (HwDeviceExtension->jChipType == XG42)
8104e329 1229 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
d7636e0b 1230
b9ebf5e5 1231 for (i = 0x79; i <= 0x7C; i++)
949eb0ae 1232 xgifb_reg_set(pVBInfo->P3d4, i, 0);
d7636e0b 1233
b9ebf5e5 1234 if (HwDeviceExtension->jChipType >= XG20)
6d12dae4 1235 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
a24d60f4 1236
949eb0ae 1237 /* SetDefExt1Regs begin */
6d12dae4 1238 xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
b9ebf5e5 1239 if (HwDeviceExtension->jChipType == XG27) {
6d12dae4
PH		 1240 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1241 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
a24d60f4 1242 }
8104e329 1243 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
6d12dae4 1244 xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
949eb0ae 1245 /* Frame buffer can read/write SR20 */
bf32fcb9 1246 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
949eb0ae 1247 /* H/W request for slow corner chip */
bf32fcb9 1248 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
949eb0ae 1249 if (HwDeviceExtension->jChipType == XG27)
6d12dae4 1250 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
a24d60f4 1251
949eb0ae 1252 if (HwDeviceExtension->jChipType < XG20) {
6048d761
AK		 1253 u32 Temp;
1254
06587335
AK		 1255 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1256 for (i = 0x47; i <= 0x4C; i++)
bf32fcb9
KT		 1257 xgifb_reg_set(pVBInfo->P3d4,
1258 i,
ea12b4e0 1259 XGI340_AGPReg[i - 0x47]);
06587335
AK		 1260
1261 for (i = 0x70; i <= 0x71; i++)
bf32fcb9
KT		 1262 xgifb_reg_set(pVBInfo->P3d4,
1263 i,
ea12b4e0 1264 XGI340_AGPReg[6 + i - 0x70]);
06587335
AK		 1265
1266 for (i = 0x74; i <= 0x77; i++)
bf32fcb9
KT		 1267 xgifb_reg_set(pVBInfo->P3d4,
1268 i,
ea12b4e0 1269 XGI340_AGPReg[8 + i - 0x74]);
06587335 1270
6048d761 1271 pci_read_config_dword(pdev, 0x50, &Temp);
06587335
AK		 1272 Temp >>= 20;
1273 Temp &= 0xF;
1274
1275 if (Temp == 1)
8104e329 1276 xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
b9ebf5e5 1277 } /* != XG20 */
a24d60f4 1278
b9ebf5e5 1279 /* Set PCI */
6d12dae4
PH		 1280 xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1281 xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
38c09652 1282 xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
a24d60f4 1283
949eb0ae 1284 if (HwDeviceExtension->jChipType < XG20) {
b9ebf5e5 1285 /* Set VB */
b053af16 1286 XGI_UnLockCRT2(pVBInfo);
949eb0ae 1287 /* disable VideoCapture */
bf32fcb9 1288 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
8104e329 1289 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
bf32fcb9 1290 /* chk if BCLK>=100MHz */
9388ad9c 1291 temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
a24d60f4 1292
bf32fcb9 1293 xgifb_reg_set(pVBInfo->Part1Port,
6d12dae4 1294 0x02, XGI330_CRT2Data_1_2);
a24d60f4 1295
8104e329 1296 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
b9ebf5e5 1297 } /* != XG20 */
a24d60f4 1298
8104e329 1299 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
b9ebf5e5 1300
bf32fcb9
KT		 1301 if ((HwDeviceExtension->jChipType == XG42) &&
1302 XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1303 /* Not DDR */
1304 xgifb_reg_set(pVBInfo->P3c4,
1305 0x31,
6d12dae4 1306 (XGI330_SR31 & 0x3F) | 0x40);
bf32fcb9
KT		 1307 xgifb_reg_set(pVBInfo->P3c4,
1308 0x32,
6d12dae4 1309 (XGI330_SR32 & 0xFC) | 0x01);
a24d60f4 1310 } else {
6d12dae4
PH		 1311 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1312 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
b9ebf5e5 1313 }
6d12dae4 1314 xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
a24d60f4 1315
949eb0ae 1316 if (HwDeviceExtension->jChipType < XG20) {
c976c781 1317 if (xgifb_bridge_is_on(pVBInfo)) {
6bc54277
AK		 1318 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1319 xgifb_reg_set(pVBInfo->Part4Port,
1320 0x0D, XGI330_CRT2Data_4_D);
1321 xgifb_reg_set(pVBInfo->Part4Port,
1322 0x0E, XGI330_CRT2Data_4_E);
1323 xgifb_reg_set(pVBInfo->Part4Port,
1324 0x10, XGI330_CRT2Data_4_10);
1325 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
b053af16 1326 XGI_LockCRT2(pVBInfo);
a24d60f4 1327 }
b9ebf5e5 1328 } /* != XG20 */
a24d60f4 1329
b9ebf5e5 1330 XGI_SenseCRT1(pVBInfo);
d7636e0b 1331
b9ebf5e5 1332 if (HwDeviceExtension->jChipType == XG21) {
bf32fcb9
KT		 1333 xgifb_reg_and_or(pVBInfo->P3d4,
1334 0x32,
1335 ~Monitor1Sense,
1336 Monitor1Sense); /* Z9 default has CRT */
b9ebf5e5 1337 temp = GetXG21FPBits(pVBInfo);
ec9e5d3e 1338 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
a24d60f4 1339 }
b9ebf5e5 1340 if (HwDeviceExtension->jChipType == XG27) {
bf32fcb9
KT		 1341 xgifb_reg_and_or(pVBInfo->P3d4,
1342 0x32,
1343 ~Monitor1Sense,
1344 Monitor1Sense); /* Z9 default has CRT */
b9ebf5e5 1345 temp = GetXG27FPBits(pVBInfo);
ec9e5d3e 1346 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
b9ebf5e5 1347 }
d7636e0b 1348
2af1a29d 1349 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
d7636e0b 1350
bf32fcb9
KT		 1351 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1352 pVBInfo->P3d4,
1353 pVBInfo);
a24d60f4 1354
fab04b97 1355 XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
d7636e0b 1356
38c09652
AK		 1357 xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1358 xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
d7636e0b 1359
b053af16
AK		 1360 XGINew_ChkSenseStatus(pVBInfo);
1361 XGINew_SetModeScratch(pVBInfo);
a24d60f4 1362
8104e329 1363 xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
d7636e0b 1364
b9ebf5e5
AK		 1365 return 1;
1366} /* end of init */
Linux 6.x block layer and io_uring tree(s)