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66101de1 PM |
1 | #include "os_common.h" |
2 | ||
3 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
4 | // Original Phy.h | |
5 | //***************************************************************************** | |
6 | ||
7 | /***************************************************************************** | |
8 | ; For MAXIM2825/6/7 Ver. 331 or more | |
9 | ; Edited by Tiger, Sep-17-2003 | |
10 | ; revised by Ben, Sep-18-2003 | |
11 | ||
12 | 0x00 0x000a2 | |
13 | 0x01 0x21cc0 | |
14 | ;0x02 0x13802 | |
15 | 0x02 0x1383a | |
16 | ||
17 | ;channe1 01 ; 0x03 0x30142 ; 0x04 0x0b333; | |
18 | ;channe1 02 ;0x03 0x32141 ;0x04 0x08444; | |
19 | ;channe1 03 ;0x03 0x32143 ;0x04 0x0aeee; | |
20 | ;channe1 04 ;0x03 0x32142 ;0x04 0x0b333; | |
21 | ;channe1 05 ;0x03 0x31141 ;0x04 0x08444; | |
22 | ;channe1 06 ; | |
23 | 0x03 0x31143; | |
24 | 0x04 0x0aeee; | |
25 | ;channe1 07 ;0x03 0x31142 ;0x04 0x0b333; | |
26 | ;channe1 08 ;0x03 0x33141 ;0x04 0x08444; | |
27 | ;channe1 09 ;0x03 0x33143 ;0x04 0x0aeee; | |
28 | ;channe1 10 ;0x03 0x33142 ;0x04 0x0b333; | |
29 | ;channe1 11 ;0x03 0x30941 ;0x04 0x08444; | |
30 | ;channe1 12 ;0x03 0x30943 ;0x04 0x0aeee; | |
31 | ;channe1 13 ;0x03 0x30942 ;0x04 0x0b333; | |
32 | ||
33 | 0x05 0x28986 | |
34 | 0x06 0x18008 | |
35 | 0x07 0x38400 | |
36 | 0x08 0x05100; 100 Hz DC | |
37 | ;0x08 0x05900; 30 KHz DC | |
38 | 0x09 0x24f08 | |
39 | 0x0a 0x17e00, 0x17ea0 | |
40 | 0x0b 0x37d80 | |
41 | 0x0c 0x0c900 // 0x0ca00 (lager power 9db than 0x0c000), 0x0c000 | |
42 | *****************************************************************************/ | |
43 | // MAX2825 (pure b/g) | |
44 | u32 max2825_rf_data[] = | |
45 | { | |
46 | (0x00<<18)|0x000a2, | |
47 | (0x01<<18)|0x21cc0, | |
48 | (0x02<<18)|0x13806, | |
49 | (0x03<<18)|0x30142, | |
50 | (0x04<<18)|0x0b333, | |
51 | (0x05<<18)|0x289A6, | |
52 | (0x06<<18)|0x18008, | |
53 | (0x07<<18)|0x38000, | |
54 | (0x08<<18)|0x05100, | |
55 | (0x09<<18)|0x24f08, | |
56 | (0x0A<<18)|0x14000, | |
57 | (0x0B<<18)|0x37d80, | |
58 | (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100 | |
59 | }; | |
60 | ||
61 | u32 max2825_channel_data_24[][3] = | |
62 | { | |
63 | {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01 | |
64 | {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02 | |
65 | {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03 | |
66 | {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04 | |
67 | {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05 | |
68 | {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06 | |
69 | {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07 | |
70 | {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08 | |
71 | {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09 | |
72 | {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10 | |
73 | {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11 | |
74 | {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12 | |
75 | {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13 | |
76 | {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify | |
77 | }; | |
78 | ||
79 | u32 max2825_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100}; | |
80 | ||
81 | /****************************************************************************/ | |
82 | // MAX2827 (a/b/g) | |
83 | u32 max2827_rf_data[] = | |
84 | { | |
85 | (0x00<<18)|0x000a2, | |
86 | (0x01<<18)|0x21cc0, | |
87 | (0x02<<18)|0x13806, | |
88 | (0x03<<18)|0x30142, | |
89 | (0x04<<18)|0x0b333, | |
90 | (0x05<<18)|0x289A6, | |
91 | (0x06<<18)|0x18008, | |
92 | (0x07<<18)|0x38000, | |
93 | (0x08<<18)|0x05100, | |
94 | (0x09<<18)|0x24f08, | |
95 | (0x0A<<18)|0x14000, | |
96 | (0x0B<<18)|0x37d80, | |
97 | (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100 | |
98 | }; | |
99 | ||
100 | u32 max2827_channel_data_24[][3] = | |
101 | { | |
102 | {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01 | |
103 | {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02 | |
104 | {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03 | |
105 | {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04 | |
106 | {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05 | |
107 | {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06 | |
108 | {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07 | |
109 | {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08 | |
110 | {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09 | |
111 | {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10 | |
112 | {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11 | |
113 | {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12 | |
114 | {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13 | |
115 | {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify | |
116 | }; | |
117 | ||
118 | u32 max2827_channel_data_50[][3] = | |
119 | { | |
120 | {(0x03<<18)|0x33cc3, (0x04<<18)|0x08ccc, (0x05<<18)|0x2A9A6}, // channel 36 | |
121 | {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x2A9A6}, // channel 40 | |
122 | {(0x03<<18)|0x302c2, (0x04<<18)|0x0b333, (0x05<<18)|0x2A9A6}, // channel 44 | |
123 | {(0x03<<18)|0x322c1, (0x04<<18)|0x09999, (0x05<<18)|0x2A9A6}, // channel 48 | |
124 | {(0x03<<18)|0x312c1, (0x04<<18)|0x0a666, (0x05<<18)|0x2A9A6}, // channel 52 | |
125 | {(0x03<<18)|0x332c3, (0x04<<18)|0x08ccc, (0x05<<18)|0x2A9A6}, // channel 56 | |
126 | {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x2A9A6}, // channel 60 | |
127 | {(0x03<<18)|0x30ac2, (0x04<<18)|0x0b333, (0x05<<18)|0x2A9A6} // channel 64 | |
128 | }; | |
129 | ||
130 | u32 max2827_power_data_24[] = {(0x0C<<18)|0x0C000, (0x0C<<18)|0x0D600, (0x0C<<18)|0x0C100}; | |
131 | u32 max2827_power_data_50[] = {(0x0C<<18)|0x0C400, (0x0C<<18)|0x0D500, (0x0C<<18)|0x0C300}; | |
132 | ||
133 | /****************************************************************************/ | |
134 | // MAX2828 (a/b/g) | |
135 | u32 max2828_rf_data[] = | |
136 | { | |
137 | (0x00<<18)|0x000a2, | |
138 | (0x01<<18)|0x21cc0, | |
139 | (0x02<<18)|0x13806, | |
140 | (0x03<<18)|0x30142, | |
141 | (0x04<<18)|0x0b333, | |
142 | (0x05<<18)|0x289A6, | |
143 | (0x06<<18)|0x18008, | |
144 | (0x07<<18)|0x38000, | |
145 | (0x08<<18)|0x05100, | |
146 | (0x09<<18)|0x24f08, | |
147 | (0x0A<<18)|0x14000, | |
148 | (0x0B<<18)|0x37d80, | |
149 | (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100 | |
150 | }; | |
151 | ||
152 | u32 max2828_channel_data_24[][3] = | |
153 | { | |
154 | {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01 | |
155 | {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02 | |
156 | {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03 | |
157 | {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04 | |
158 | {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05 | |
159 | {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06 | |
160 | {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07 | |
161 | {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08 | |
162 | {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09 | |
163 | {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10 | |
164 | {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11 | |
165 | {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12 | |
166 | {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13 | |
167 | {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify | |
168 | }; | |
169 | ||
170 | u32 max2828_channel_data_50[][3] = | |
171 | { | |
172 | {(0x03<<18)|0x33cc3, (0x04<<18)|0x08ccc, (0x05<<18)|0x289A6}, // channel 36 | |
173 | {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x289A6}, // channel 40 | |
174 | {(0x03<<18)|0x302c2, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channel 44 | |
175 | {(0x03<<18)|0x322c1, (0x04<<18)|0x09999, (0x05<<18)|0x289A6}, // channel 48 | |
176 | {(0x03<<18)|0x312c1, (0x04<<18)|0x0a666, (0x05<<18)|0x289A6}, // channel 52 | |
177 | {(0x03<<18)|0x332c3, (0x04<<18)|0x08ccc, (0x05<<18)|0x289A6}, // channel 56 | |
178 | {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x289A6}, // channel 60 | |
179 | {(0x03<<18)|0x30ac2, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6} // channel 64 | |
180 | }; | |
181 | ||
182 | u32 max2828_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100}; | |
183 | u32 max2828_power_data_50[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100}; | |
184 | ||
185 | /****************************************************************************/ | |
186 | // LA20040728 kevin | |
187 | // MAX2829 (a/b/g) | |
188 | u32 max2829_rf_data[] = | |
189 | { | |
190 | (0x00<<18)|0x000a2, | |
191 | (0x01<<18)|0x23520, | |
192 | (0x02<<18)|0x13802, | |
193 | (0x03<<18)|0x30142, | |
194 | (0x04<<18)|0x0b333, | |
195 | (0x05<<18)|0x28906, | |
196 | (0x06<<18)|0x18008, | |
197 | (0x07<<18)|0x3B500, | |
198 | (0x08<<18)|0x05100, | |
199 | (0x09<<18)|0x24f08, | |
200 | (0x0A<<18)|0x14000, | |
201 | (0x0B<<18)|0x37d80, | |
202 | (0x0C<<18)|0x0F300 //TXVGA=51, (MAX-6 dB) | |
203 | }; | |
204 | ||
205 | u32 max2829_channel_data_24[][3] = | |
206 | { | |
207 | {(3<<18)|0x30142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 01 (2412MHz) | |
208 | {(3<<18)|0x32141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 02 (2417MHz) | |
209 | {(3<<18)|0x32143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 03 (2422MHz) | |
210 | {(3<<18)|0x32142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 04 (2427MHz) | |
211 | {(3<<18)|0x31141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 05 (2432MHz) | |
212 | {(3<<18)|0x31143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 06 (2437MHz) | |
213 | {(3<<18)|0x31142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 07 (2442MHz) | |
214 | {(3<<18)|0x33141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 08 (2447MHz) | |
215 | {(3<<18)|0x33143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 09 (2452MHz) | |
216 | {(3<<18)|0x33142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 10 (2457MHz) | |
217 | {(3<<18)|0x30941, (4<<18)|0x08444, (5<<18)|0x289C6}, // 11 (2462MHz) | |
218 | {(3<<18)|0x30943, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 12 (2467MHz) | |
219 | {(3<<18)|0x30942, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 13 (2472MHz) | |
220 | {(3<<18)|0x32941, (4<<18)|0x09999, (5<<18)|0x289C6}, // 14 (2484MHz) hh-modify | |
221 | }; | |
222 | ||
223 | u32 max2829_channel_data_50[][4] = | |
224 | { | |
225 | {36, (3<<18)|0x33cc3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 36 (5.180GHz) | |
226 | {40, (3<<18)|0x302c0, (4<<18)|0x08000, (5<<18)|0x2A946}, // 40 (5.200GHz) | |
227 | {44, (3<<18)|0x302c2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 44 (5.220GHz) | |
228 | {48, (3<<18)|0x322c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 48 (5.240GHz) | |
229 | {52, (3<<18)|0x312c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 52 (5.260GHz) | |
230 | {56, (3<<18)|0x332c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 56 (5.280GHz) | |
231 | {60, (3<<18)|0x30ac0, (4<<18)|0x08000, (5<<18)|0x2A946}, // 60 (5.300GHz) | |
232 | {64, (3<<18)|0x30ac2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 64 (5.320GHz) | |
233 | ||
234 | {100, (3<<18)|0x30ec0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 100 (5.500GHz) | |
235 | {104, (3<<18)|0x30ec2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 104 (5.520GHz) | |
236 | {108, (3<<18)|0x32ec1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 108 (5.540GHz) | |
237 | {112, (3<<18)|0x31ec1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 112 (5.560GHz) | |
238 | {116, (3<<18)|0x33ec3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 116 (5.580GHz) | |
239 | {120, (3<<18)|0x301c0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 120 (5.600GHz) | |
240 | {124, (3<<18)|0x301c2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 124 (5.620GHz) | |
241 | {128, (3<<18)|0x321c1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 128 (5.640GHz) | |
242 | {132, (3<<18)|0x311c1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 132 (5.660GHz) | |
243 | {136, (3<<18)|0x331c3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 136 (5.680GHz) | |
244 | {140, (3<<18)|0x309c0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 140 (5.700GHz) | |
245 | ||
246 | {149, (3<<18)|0x329c2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 149 (5.745GHz) | |
247 | {153, (3<<18)|0x319c1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 153 (5.765GHz) | |
248 | {157, (3<<18)|0x339c1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 157 (5.785GHz) | |
249 | {161, (3<<18)|0x305c3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 161 (5.805GHz) | |
250 | ||
251 | // Japan | |
252 | { 184, (3<<18)|0x308c2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 184 (4.920GHz) | |
253 | { 188, (3<<18)|0x328c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 188 (4.940GHz) | |
254 | { 192, (3<<18)|0x318c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 192 (4.960GHz) | |
255 | { 196, (3<<18)|0x338c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 196 (4.980GHz) | |
256 | { 8, (3<<18)|0x324c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 8 (5.040GHz) | |
257 | { 12, (3<<18)|0x314c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 12 (5.060GHz) | |
258 | { 16, (3<<18)|0x334c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 16 (5.080GHz) | |
259 | { 34, (3<<18)|0x31cc2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 34 (5.170GHz) | |
260 | { 38, (3<<18)|0x33cc1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 38 (5.190GHz) | |
261 | { 42, (3<<18)|0x302c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 42 (5.210GHz) | |
262 | { 46, (3<<18)|0x322c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 46 (5.230GHz) | |
263 | }; | |
264 | ||
265 | /***************************************************************************** | |
266 | ; For MAXIM2825/6/7 Ver. 317 or less | |
267 | ; Edited by Tiger, Sep-17-2003 for 2.4Ghz channels | |
268 | ; Updated by Tiger, Sep-22-2003 for 5.0Ghz channels | |
269 | ; Corrected by Tiger, Sep-23-2003, for 0x03 and 0x04 of 5.0Ghz channels | |
270 | ||
271 | 0x00 0x00080 | |
272 | 0x01 0x214c0 | |
273 | 0x02 0x13802 | |
274 | ||
275 | ;2.4GHz Channels | |
276 | ;channe1 01 (2.412GHz); 0x03 0x30143 ;0x04 0x0accc | |
277 | ;channe1 02 (2.417GHz); 0x03 0x32140 ;0x04 0x09111 | |
278 | ;channe1 03 (2.422GHz); 0x03 0x32142 ;0x04 0x0bbbb | |
279 | ;channe1 04 (2.427GHz); 0x03 0x32143 ;0x04 0x0accc | |
280 | ;channe1 05 (2.432GHz); 0x03 0x31140 ;0x04 0x09111 | |
281 | ;channe1 06 (2.437GHz); 0x03 0x31142 ;0x04 0x0bbbb | |
282 | ;channe1 07 (2.442GHz); 0x03 0x31143 ;0x04 0x0accc | |
283 | ;channe1 08 (2.447GHz); 0x03 0x33140 ;0x04 0x09111 | |
284 | ;channe1 09 (2.452GHz); 0x03 0x33142 ;0x04 0x0bbbb | |
285 | ;channe1 10 (2.457GHz); 0x03 0x33143 ;0x04 0x0accc | |
286 | ;channe1 11 (2.462GHz); 0x03 0x30940 ;0x04 0x09111 | |
287 | ;channe1 12 (2.467GHz); 0x03 0x30942 ;0x04 0x0bbbb | |
288 | ;channe1 13 (2.472GHz); 0x03 0x30943 ;0x04 0x0accc | |
289 | ||
290 | ;5.0Ghz Channels | |
291 | ;channel 36 (5.180GHz); 0x03 0x33cc0 ;0x04 0x0b333 | |
292 | ;channel 40 (5.200GHz); 0x03 0x302c0 ;0x04 0x08000 | |
293 | ;channel 44 (5.220GHz); 0x03 0x302c2 ;0x04 0x0b333 | |
294 | ;channel 48 (5.240GHz); 0x03 0x322c1 ;0x04 0x09999 | |
295 | ;channel 52 (5.260GHz); 0x03 0x312c1 ;0x04 0x0a666 | |
296 | ;channel 56 (5.280GHz); 0x03 0x332c3 ;0x04 0x08ccc | |
297 | ;channel 60 (5.300GHz); 0x03 0x30ac0 ;0x04 0x08000 | |
298 | ;channel 64 (5.320GHz); 0x03 0x30ac2 ;0x04 0x08333 | |
299 | ||
300 | ;2.4GHz band ;0x05 0x28986; | |
301 | ;5.0GHz band | |
302 | 0x05 0x2a986 | |
303 | ||
304 | 0x06 0x18008 | |
305 | 0x07 0x38400 | |
306 | 0x08 0x05108 | |
307 | 0x09 0x27ff8 | |
308 | 0x0a 0x14000 | |
309 | 0x0b 0x37f99 | |
310 | 0x0c 0x0c000 | |
311 | *****************************************************************************/ | |
312 | u32 maxim_317_rf_data[] = | |
313 | { | |
314 | (0x00<<18)|0x000a2, | |
315 | (0x01<<18)|0x214c0, | |
316 | (0x02<<18)|0x13802, | |
317 | (0x03<<18)|0x30143, | |
318 | (0x04<<18)|0x0accc, | |
319 | (0x05<<18)|0x28986, | |
320 | (0x06<<18)|0x18008, | |
321 | (0x07<<18)|0x38400, | |
322 | (0x08<<18)|0x05108, | |
323 | (0x09<<18)|0x27ff8, | |
324 | (0x0A<<18)|0x14000, | |
325 | (0x0B<<18)|0x37f99, | |
326 | (0x0C<<18)|0x0c000 | |
327 | }; | |
328 | ||
329 | u32 maxim_317_channel_data_24[][3] = | |
330 | { | |
331 | {(0x03<<18)|0x30143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 01 | |
332 | {(0x03<<18)|0x32140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 02 | |
333 | {(0x03<<18)|0x32142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 03 | |
334 | {(0x03<<18)|0x32143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 04 | |
335 | {(0x03<<18)|0x31140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 05 | |
336 | {(0x03<<18)|0x31142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 06 | |
337 | {(0x03<<18)|0x31143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 07 | |
338 | {(0x03<<18)|0x33140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 08 | |
339 | {(0x03<<18)|0x33142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 09 | |
340 | {(0x03<<18)|0x33143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 10 | |
341 | {(0x03<<18)|0x30940, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 11 | |
342 | {(0x03<<18)|0x30942, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 12 | |
343 | {(0x03<<18)|0x30943, (0x04<<18)|0x0accc, (0x05<<18)|0x28986} // channe1 13 | |
344 | }; | |
345 | ||
346 | u32 maxim_317_channel_data_50[][3] = | |
347 | { | |
348 | {(0x03<<18)|0x33cc0, (0x04<<18)|0x0b333, (0x05<<18)|0x2a986}, // channel 36 | |
349 | {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x2a986}, // channel 40 | |
350 | {(0x03<<18)|0x302c3, (0x04<<18)|0x0accc, (0x05<<18)|0x2a986}, // channel 44 | |
351 | {(0x03<<18)|0x322c1, (0x04<<18)|0x09666, (0x05<<18)|0x2a986}, // channel 48 | |
352 | {(0x03<<18)|0x312c2, (0x04<<18)|0x09999, (0x05<<18)|0x2a986}, // channel 52 | |
353 | {(0x03<<18)|0x332c0, (0x04<<18)|0x0b333, (0x05<<18)|0x2a99e}, // channel 56 | |
354 | {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x2a99e}, // channel 60 | |
355 | {(0x03<<18)|0x30ac3, (0x04<<18)|0x0accc, (0x05<<18)|0x2a99e} // channel 64 | |
356 | }; | |
357 | ||
358 | u32 maxim_317_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100}; | |
359 | u32 maxim_317_power_data_50[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100}; | |
360 | ||
361 | /***************************************************************************** | |
362 | ;;AL2230 MP (Mass Production Version) | |
363 | ;;RF Registers Setting for Airoha AL2230 silicon after June 1st, 2004 | |
364 | ;;Updated by Tiger Huang (June 1st, 2004) | |
365 | ;;20-bit length and LSB first | |
366 | ||
367 | ;;Ch01 (2412MHz) ;0x00 0x09EFC ;0x01 0x8CCCC; | |
368 | ;;Ch02 (2417MHz) ;0x00 0x09EFC ;0x01 0x8CCCD; | |
369 | ;;Ch03 (2422MHz) ;0x00 0x09E7C ;0x01 0x8CCCC; | |
370 | ;;Ch04 (2427MHz) ;0x00 0x09E7C ;0x01 0x8CCCD; | |
371 | ;;Ch05 (2432MHz) ;0x00 0x05EFC ;0x01 0x8CCCC; | |
372 | ;;Ch06 (2437MHz) ;0x00 0x05EFC ;0x01 0x8CCCD; | |
373 | ;;Ch07 (2442MHz) ;0x00 0x05E7C ;0x01 0x8CCCC; | |
374 | ;;Ch08 (2447MHz) ;0x00 0x05E7C ;0x01 0x8CCCD; | |
375 | ;;Ch09 (2452MHz) ;0x00 0x0DEFC ;0x01 0x8CCCC; | |
376 | ;;Ch10 (2457MHz) ;0x00 0x0DEFC ;0x01 0x8CCCD; | |
377 | ;;Ch11 (2462MHz) ;0x00 0x0DE7C ;0x01 0x8CCCC; | |
378 | ;;Ch12 (2467MHz) ;0x00 0x0DE7C ;0x01 0x8CCCD; | |
379 | ;;Ch13 (2472MHz) ;0x00 0x03EFC ;0x01 0x8CCCC; | |
380 | ;;Ch14 (2484Mhz) ;0x00 0x03E7C ;0x01 0x86666; | |
381 | ||
382 | 0x02 0x401D8; RXDCOC BW 100Hz for RXHP low | |
383 | ;;0x02 0x481DC; RXDCOC BW 30Khz for RXHP low | |
384 | ||
385 | 0x03 0xCFFF0 | |
386 | 0x04 0x23800 | |
387 | 0x05 0xA3B72 | |
388 | 0x06 0x6DA01 | |
389 | 0x07 0xE1688 | |
390 | 0x08 0x11600 | |
391 | 0x09 0x99E02 | |
392 | 0x0A 0x5DDB0 | |
393 | 0x0B 0xD9900 | |
394 | 0x0C 0x3FFBD | |
395 | 0x0D 0xB0000 | |
396 | 0x0F 0xF00A0 | |
397 | ||
398 | ;RF Calibration for Airoha AL2230 | |
399 | ;Edit by Ben Chang (01/30/04) | |
400 | ;Updated by Tiger Huang (03/03/04) | |
401 | 0x0f 0xf00a0 ; Initial Setting | |
402 | 0x0f 0xf00b0 ; Activate TX DCC | |
403 | 0x0f 0xf02a0 ; Activate Phase Calibration | |
404 | 0x0f 0xf00e0 ; Activate Filter RC Calibration | |
405 | 0x0f 0xf00a0 ; Restore Initial Setting | |
406 | *****************************************************************************/ | |
407 | ||
408 | u32 al2230_rf_data[] = | |
409 | { | |
410 | (0x00<<20)|0x09EFC, | |
411 | (0x01<<20)|0x8CCCC, | |
412 | (0x02<<20)|0x40058,// 20060627 Anson 0x401D8, | |
413 | (0x03<<20)|0xCFFF0, | |
414 | (0x04<<20)|0x24100,// 20060627 Anson 0x23800, | |
415 | (0x05<<20)|0xA3B2F,// 20060627 Anson 0xA3B72 | |
416 | (0x06<<20)|0x6DA01, | |
417 | (0x07<<20)|0xE3628,// 20060627 Anson 0xE1688, | |
418 | (0x08<<20)|0x11600, | |
419 | (0x09<<20)|0x9DC02,// 20060627 Anosn 0x97602,//0x99E02, //0x9AE02 | |
420 | (0x0A<<20)|0x5ddb0, // 941206 For QCOM interference 0x588b0,//0x5DDB0, 940601 adj 0x5aa30 for bluetooth | |
421 | (0x0B<<20)|0xD9900, | |
422 | (0x0C<<20)|0x3FFBD, | |
423 | (0x0D<<20)|0xB0000, | |
424 | (0x0F<<20)|0xF01A0 // 20060627 Anson 0xF00A0 | |
425 | }; | |
426 | ||
427 | u32 al2230s_rf_data[] = | |
428 | { | |
429 | (0x00<<20)|0x09EFC, | |
430 | (0x01<<20)|0x8CCCC, | |
431 | (0x02<<20)|0x40058,// 20060419 0x401D8, | |
432 | (0x03<<20)|0xCFFF0, | |
433 | (0x04<<20)|0x24100,// 20060419 0x23800, | |
434 | (0x05<<20)|0xA3B2F,// 20060419 0xA3B72, | |
435 | (0x06<<20)|0x6DA01, | |
436 | (0x07<<20)|0xE3628,// 20060419 0xE1688, | |
437 | (0x08<<20)|0x11600, | |
438 | (0x09<<20)|0x9DC02,// 20060419 0x97602,//0x99E02, //0x9AE02 | |
439 | (0x0A<<20)|0x5DDB0,// 941206 For QCOM interference 0x588b0,//0x5DDB0, 940601 adj 0x5aa30 for bluetooth | |
440 | (0x0B<<20)|0xD9900, | |
441 | (0x0C<<20)|0x3FFBD, | |
442 | (0x0D<<20)|0xB0000, | |
443 | (0x0F<<20)|0xF01A0 // 20060419 0xF00A0 | |
444 | }; | |
445 | ||
446 | u32 al2230_channel_data_24[][2] = | |
447 | { | |
448 | {(0x00<<20)|0x09EFC, (0x01<<20)|0x8CCCC}, // channe1 01 | |
449 | {(0x00<<20)|0x09EFC, (0x01<<20)|0x8CCCD}, // channe1 02 | |
450 | {(0x00<<20)|0x09E7C, (0x01<<20)|0x8CCCC}, // channe1 03 | |
451 | {(0x00<<20)|0x09E7C, (0x01<<20)|0x8CCCD}, // channe1 04 | |
452 | {(0x00<<20)|0x05EFC, (0x01<<20)|0x8CCCC}, // channe1 05 | |
453 | {(0x00<<20)|0x05EFC, (0x01<<20)|0x8CCCD}, // channe1 06 | |
454 | {(0x00<<20)|0x05E7C, (0x01<<20)|0x8CCCC}, // channe1 07 | |
455 | {(0x00<<20)|0x05E7C, (0x01<<20)|0x8CCCD}, // channe1 08 | |
456 | {(0x00<<20)|0x0DEFC, (0x01<<20)|0x8CCCC}, // channe1 09 | |
457 | {(0x00<<20)|0x0DEFC, (0x01<<20)|0x8CCCD}, // channe1 10 | |
458 | {(0x00<<20)|0x0DE7C, (0x01<<20)|0x8CCCC}, // channe1 11 | |
459 | {(0x00<<20)|0x0DE7C, (0x01<<20)|0x8CCCD}, // channe1 12 | |
460 | {(0x00<<20)|0x03EFC, (0x01<<20)|0x8CCCC}, // channe1 13 | |
461 | {(0x00<<20)|0x03E7C, (0x01<<20)|0x86666} // channe1 14 | |
462 | }; | |
463 | ||
464 | // Current setting. u32 airoha_power_data_24[] = {(0x09<<20)|0x90202, (0x09<<20)|0x96602, (0x09<<20)|0x97602}; | |
465 | #define AIROHA_TXVGA_LOW_INDEX 31 // Index for 0x90202 | |
466 | #define AIROHA_TXVGA_MIDDLE_INDEX 12 // Index for 0x96602 | |
467 | #define AIROHA_TXVGA_HIGH_INDEX 8 // Index for 0x97602 1.0.24.0 1.0.28.0 | |
468 | /* | |
469 | u32 airoha_power_data_24[] = | |
470 | { | |
471 | 0x9FE02, // Max - 0 dB | |
472 | 0x9BE02, // Max - 1 dB | |
473 | 0x9DE02, // Max - 2 dB | |
474 | 0x99E02, // Max - 3 dB | |
475 | 0x9EE02, // Max - 4 dB | |
476 | 0x9AE02, // Max - 5 dB | |
477 | 0x9CE02, // Max - 6 dB | |
478 | 0x98E02, // Max - 7 dB | |
479 | 0x97602, // Max - 8 dB | |
480 | 0x93602, // Max - 9 dB | |
481 | 0x95602, // Max - 10 dB | |
482 | 0x91602, // Max - 11 dB | |
483 | 0x96602, // Max - 12 dB | |
484 | 0x92602, // Max - 13 dB | |
485 | 0x94602, // Max - 14 dB | |
486 | 0x90602, // Max - 15 dB | |
487 | 0x97A02, // Max - 16 dB | |
488 | 0x93A02, // Max - 17 dB | |
489 | 0x95A02, // Max - 18 dB | |
490 | 0x91A02, // Max - 19 dB | |
491 | 0x96A02, // Max - 20 dB | |
492 | 0x92A02, // Max - 21 dB | |
493 | 0x94A02, // Max - 22 dB | |
494 | 0x90A02, // Max - 23 dB | |
495 | 0x97202, // Max - 24 dB | |
496 | 0x93202, // Max - 25 dB | |
497 | 0x95202, // Max - 26 dB | |
498 | 0x91202, // Max - 27 dB | |
499 | 0x96202, // Max - 28 dB | |
500 | 0x92202, // Max - 29 dB | |
501 | 0x94202, // Max - 30 dB | |
502 | 0x90202 // Max - 31 dB | |
503 | }; | |
504 | */ | |
505 | ||
506 | // 20040927 1.1.69.1000 ybjiang | |
507 | // from John | |
508 | u32 al2230_txvga_data[][2] = | |
509 | { | |
510 | //value , index | |
511 | {0x090202, 0}, | |
512 | {0x094202, 2}, | |
513 | {0x092202, 4}, | |
514 | {0x096202, 6}, | |
515 | {0x091202, 8}, | |
516 | {0x095202, 10}, | |
517 | {0x093202, 12}, | |
518 | {0x097202, 14}, | |
519 | {0x090A02, 16}, | |
520 | {0x094A02, 18}, | |
521 | {0x092A02, 20}, | |
522 | {0x096A02, 22}, | |
523 | {0x091A02, 24}, | |
524 | {0x095A02, 26}, | |
525 | {0x093A02, 28}, | |
526 | {0x097A02, 30}, | |
527 | {0x090602, 32}, | |
528 | {0x094602, 34}, | |
529 | {0x092602, 36}, | |
530 | {0x096602, 38}, | |
531 | {0x091602, 40}, | |
532 | {0x095602, 42}, | |
533 | {0x093602, 44}, | |
534 | {0x097602, 46}, | |
535 | {0x090E02, 48}, | |
536 | {0x098E02, 49}, | |
537 | {0x094E02, 50}, | |
538 | {0x09CE02, 51}, | |
539 | {0x092E02, 52}, | |
540 | {0x09AE02, 53}, | |
541 | {0x096E02, 54}, | |
542 | {0x09EE02, 55}, | |
543 | {0x091E02, 56}, | |
544 | {0x099E02, 57}, | |
545 | {0x095E02, 58}, | |
546 | {0x09DE02, 59}, | |
547 | {0x093E02, 60}, | |
548 | {0x09BE02, 61}, | |
549 | {0x097E02, 62}, | |
550 | {0x09FE02, 63} | |
551 | }; | |
552 | ||
553 | //-------------------------------- | |
554 | // For Airoha AL7230, 2.4Ghz band | |
555 | // Edit by Tiger, (March, 9, 2005) | |
556 | // 24bit, MSB first | |
557 | ||
558 | //channel independent registers: | |
559 | u32 al7230_rf_data_24[] = | |
560 | { | |
561 | (0x00<<24)|0x003790, | |
562 | (0x01<<24)|0x133331, | |
563 | (0x02<<24)|0x841FF2, | |
564 | (0x03<<24)|0x3FDFA3, | |
565 | (0x04<<24)|0x7FD784, | |
566 | (0x05<<24)|0x802B55, | |
567 | (0x06<<24)|0x56AF36, | |
568 | (0x07<<24)|0xCE0207, | |
569 | (0x08<<24)|0x6EBC08, | |
570 | (0x09<<24)|0x221BB9, | |
571 | (0x0A<<24)|0xE0000A, | |
572 | (0x0B<<24)|0x08071B, | |
573 | (0x0C<<24)|0x000A3C, | |
574 | (0x0D<<24)|0xFFFFFD, | |
575 | (0x0E<<24)|0x00000E, | |
576 | (0x0F<<24)|0x1ABA8F | |
577 | }; | |
578 | ||
579 | u32 al7230_channel_data_24[][2] = | |
580 | { | |
581 | {(0x00<<24)|0x003790, (0x01<<24)|0x133331}, // channe1 01 | |
582 | {(0x00<<24)|0x003790, (0x01<<24)|0x1B3331}, // channe1 02 | |
583 | {(0x00<<24)|0x003790, (0x01<<24)|0x033331}, // channe1 03 | |
584 | {(0x00<<24)|0x003790, (0x01<<24)|0x0B3331}, // channe1 04 | |
585 | {(0x00<<24)|0x0037A0, (0x01<<24)|0x133331}, // channe1 05 | |
586 | {(0x00<<24)|0x0037A0, (0x01<<24)|0x1B3331}, // channe1 06 | |
587 | {(0x00<<24)|0x0037A0, (0x01<<24)|0x033331}, // channe1 07 | |
588 | {(0x00<<24)|0x0037A0, (0x01<<24)|0x0B3331}, // channe1 08 | |
589 | {(0x00<<24)|0x0037B0, (0x01<<24)|0x133331}, // channe1 09 | |
590 | {(0x00<<24)|0x0037B0, (0x01<<24)|0x1B3331}, // channe1 10 | |
591 | {(0x00<<24)|0x0037B0, (0x01<<24)|0x033331}, // channe1 11 | |
592 | {(0x00<<24)|0x0037B0, (0x01<<24)|0x0B3331}, // channe1 12 | |
593 | {(0x00<<24)|0x0037C0, (0x01<<24)|0x133331}, // channe1 13 | |
594 | {(0x00<<24)|0x0037C0, (0x01<<24)|0x066661} // channel 14 | |
595 | }; | |
596 | ||
597 | //channel independent registers: | |
598 | u32 al7230_rf_data_50[] = | |
599 | { | |
600 | (0x00<<24)|0x0FF520, | |
601 | (0x01<<24)|0x000001, | |
602 | (0x02<<24)|0x451FE2, | |
603 | (0x03<<24)|0x5FDFA3, | |
604 | (0x04<<24)|0x6FD784, | |
605 | (0x05<<24)|0x853F55, | |
606 | (0x06<<24)|0x56AF36, | |
607 | (0x07<<24)|0xCE0207, | |
608 | (0x08<<24)|0x6EBC08, | |
609 | (0x09<<24)|0x221BB9, | |
610 | (0x0A<<24)|0xE0600A, | |
611 | (0x0B<<24)|0x08044B, | |
612 | (0x0C<<24)|0x00143C, | |
613 | (0x0D<<24)|0xFFFFFD, | |
614 | (0x0E<<24)|0x00000E, | |
615 | (0x0F<<24)|0x12BACF //5Ghz default state | |
616 | }; | |
617 | ||
618 | u32 al7230_channel_data_5[][4] = | |
619 | { | |
620 | //channel dependent registers: 0x00, 0x01 and 0x04 | |
621 | //11J =========== | |
622 | {184, (0x00<<24)|0x0FF520, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 184 | |
623 | {188, (0x00<<24)|0x0FF520, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 188 | |
624 | {192, (0x00<<24)|0x0FF530, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 192 | |
625 | {196, (0x00<<24)|0x0FF530, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 196 | |
626 | {8, (0x00<<24)|0x0FF540, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 008 | |
627 | {12, (0x00<<24)|0x0FF540, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 012 | |
628 | {16, (0x00<<24)|0x0FF550, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 016 | |
629 | {34, (0x00<<24)|0x0FF560, (0x01<<24)|0x055551, (0x04<<24)|0x77F784}, // channel 034 | |
630 | {38, (0x00<<24)|0x0FF570, (0x01<<24)|0x100001, (0x04<<24)|0x77F784}, // channel 038 | |
631 | {42, (0x00<<24)|0x0FF570, (0x01<<24)|0x1AAAA1, (0x04<<24)|0x77F784}, // channel 042 | |
632 | {46, (0x00<<24)|0x0FF570, (0x01<<24)|0x055551, (0x04<<24)|0x77F784}, // channel 046 | |
633 | //11 A/H ========= | |
634 | {36, (0x00<<24)|0x0FF560, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 036 | |
635 | {40, (0x00<<24)|0x0FF570, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 040 | |
636 | {44, (0x00<<24)|0x0FF570, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 044 | |
637 | {48, (0x00<<24)|0x0FF570, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 048 | |
638 | {52, (0x00<<24)|0x0FF580, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 052 | |
639 | {56, (0x00<<24)|0x0FF580, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 056 | |
640 | {60, (0x00<<24)|0x0FF580, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 060 | |
641 | {64, (0x00<<24)|0x0FF590, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 064 | |
642 | {100, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 100 | |
643 | {104, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 104 | |
644 | {108, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 108 | |
645 | {112, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 112 | |
646 | {116, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 116 | |
647 | {120, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 120 | |
648 | {124, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 124 | |
649 | {128, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 128 | |
650 | {132, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 132 | |
651 | {136, (0x00<<24)|0x0FF5F0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 136 | |
652 | {140, (0x00<<24)|0x0FF5F0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 140 | |
653 | {149, (0x00<<24)|0x0FF600, (0x01<<24)|0x180001, (0x04<<24)|0x77F784}, // channel 149 | |
654 | {153, (0x00<<24)|0x0FF600, (0x01<<24)|0x02AAA1, (0x04<<24)|0x77F784}, // channel 153 | |
655 | {157, (0x00<<24)|0x0FF600, (0x01<<24)|0x0D5551, (0x04<<24)|0x77F784}, // channel 157 | |
656 | {161, (0x00<<24)|0x0FF610, (0x01<<24)|0x180001, (0x04<<24)|0x77F784}, // channel 161 | |
657 | {165, (0x00<<24)|0x0FF610, (0x01<<24)|0x02AAA1, (0x04<<24)|0x77F784} // channel 165 | |
658 | }; | |
659 | ||
660 | //; RF Calibration <=== Register 0x0F | |
661 | //0x0F 0x1ABA8F; start from 2.4Ghz default state | |
662 | //0x0F 0x9ABA8F; TXDC compensation | |
663 | //0x0F 0x3ABA8F; RXFIL adjustment | |
664 | //0x0F 0x1ABA8F; restore 2.4Ghz default state | |
665 | ||
666 | //;TXVGA Mapping Table <=== Register 0x0B | |
667 | u32 al7230_txvga_data[][2] = | |
668 | { | |
669 | {0x08040B, 0}, //TXVGA=0; | |
670 | {0x08041B, 1}, //TXVGA=1; | |
671 | {0x08042B, 2}, //TXVGA=2; | |
672 | {0x08043B, 3}, //TXVGA=3; | |
673 | {0x08044B, 4}, //TXVGA=4; | |
674 | {0x08045B, 5}, //TXVGA=5; | |
675 | {0x08046B, 6}, //TXVGA=6; | |
676 | {0x08047B, 7}, //TXVGA=7; | |
677 | {0x08048B, 8}, //TXVGA=8; | |
678 | {0x08049B, 9}, //TXVGA=9; | |
679 | {0x0804AB, 10}, //TXVGA=10; | |
680 | {0x0804BB, 11}, //TXVGA=11; | |
681 | {0x0804CB, 12}, //TXVGA=12; | |
682 | {0x0804DB, 13}, //TXVGA=13; | |
683 | {0x0804EB, 14}, //TXVGA=14; | |
684 | {0x0804FB, 15}, //TXVGA=15; | |
685 | {0x08050B, 16}, //TXVGA=16; | |
686 | {0x08051B, 17}, //TXVGA=17; | |
687 | {0x08052B, 18}, //TXVGA=18; | |
688 | {0x08053B, 19}, //TXVGA=19; | |
689 | {0x08054B, 20}, //TXVGA=20; | |
690 | {0x08055B, 21}, //TXVGA=21; | |
691 | {0x08056B, 22}, //TXVGA=22; | |
692 | {0x08057B, 23}, //TXVGA=23; | |
693 | {0x08058B, 24}, //TXVGA=24; | |
694 | {0x08059B, 25}, //TXVGA=25; | |
695 | {0x0805AB, 26}, //TXVGA=26; | |
696 | {0x0805BB, 27}, //TXVGA=27; | |
697 | {0x0805CB, 28}, //TXVGA=28; | |
698 | {0x0805DB, 29}, //TXVGA=29; | |
699 | {0x0805EB, 30}, //TXVGA=30; | |
700 | {0x0805FB, 31}, //TXVGA=31; | |
701 | {0x08060B, 32}, //TXVGA=32; | |
702 | {0x08061B, 33}, //TXVGA=33; | |
703 | {0x08062B, 34}, //TXVGA=34; | |
704 | {0x08063B, 35}, //TXVGA=35; | |
705 | {0x08064B, 36}, //TXVGA=36; | |
706 | {0x08065B, 37}, //TXVGA=37; | |
707 | {0x08066B, 38}, //TXVGA=38; | |
708 | {0x08067B, 39}, //TXVGA=39; | |
709 | {0x08068B, 40}, //TXVGA=40; | |
710 | {0x08069B, 41}, //TXVGA=41; | |
711 | {0x0806AB, 42}, //TXVGA=42; | |
712 | {0x0806BB, 43}, //TXVGA=43; | |
713 | {0x0806CB, 44}, //TXVGA=44; | |
714 | {0x0806DB, 45}, //TXVGA=45; | |
715 | {0x0806EB, 46}, //TXVGA=46; | |
716 | {0x0806FB, 47}, //TXVGA=47; | |
717 | {0x08070B, 48}, //TXVGA=48; | |
718 | {0x08071B, 49}, //TXVGA=49; | |
719 | {0x08072B, 50}, //TXVGA=50; | |
720 | {0x08073B, 51}, //TXVGA=51; | |
721 | {0x08074B, 52}, //TXVGA=52; | |
722 | {0x08075B, 53}, //TXVGA=53; | |
723 | {0x08076B, 54}, //TXVGA=54; | |
724 | {0x08077B, 55}, //TXVGA=55; | |
725 | {0x08078B, 56}, //TXVGA=56; | |
726 | {0x08079B, 57}, //TXVGA=57; | |
727 | {0x0807AB, 58}, //TXVGA=58; | |
728 | {0x0807BB, 59}, //TXVGA=59; | |
729 | {0x0807CB, 60}, //TXVGA=60; | |
730 | {0x0807DB, 61}, //TXVGA=61; | |
731 | {0x0807EB, 62}, //TXVGA=62; | |
732 | {0x0807FB, 63}, //TXVGA=63; | |
733 | }; | |
734 | //-------------------------------- | |
735 | ||
736 | ||
737 | //; W89RF242 RFIC SPI programming initial data | |
738 | //; Winbond WLAN 11g RFIC BB-SPI register -- version FA5976A rev 1.3b | |
739 | //; Update Date: Ocotber 3, 2005 by PP10 Hsiang-Te Ho | |
740 | //; | |
741 | //; Version 1.3b revision items: (Oct. 1, 2005 by HTHo) for FA5976A | |
742 | u32 w89rf242_rf_data[] = | |
743 | { | |
744 | (0x00<<24)|0xF86100, // 20060721 0xF86100, //; 3E184; MODA (0x00) -- Normal mode ; calibration off | |
745 | (0x01<<24)|0xEFFFC2, //; 3BFFF; MODB (0x01) -- turn off RSSI, and other circuits are turned on | |
746 | (0x02<<24)|0x102504, //; 04094; FSET (0x02) -- default 20MHz crystal ; Icmp=1.5mA | |
747 | (0x03<<24)|0x026286, //; 0098A; FCHN (0x03) -- default CH7, 2442MHz | |
748 | (0x04<<24)|0x000208, // 20060612.1.a 0x0002C8, // 20050818 // 20050816 0x000388 | |
749 | //; 02008; FCAL (0x04) -- XTAL Freq Trim=001000 (socket board#1); FA5976AYG_v1.3C | |
750 | (0x05<<24)|0x24C60A, // 20060612.1.a 0x24C58A, // 941003 0x24C48A, // 20050818.2 0x24848A, // 20050818 // 20050816 0x24C48A | |
751 | //; 09316; GANA (0x05) -- TX VGA default (TXVGA=0x18(12)) & TXGPK=110 ; FA5976A_1.3D | |
752 | (0x06<<24)|0x3432CC, // 941003 0x26C34C, // 20050818 0x06B40C | |
753 | //; 0D0CB; GANB (0x06) -- RXDC(DC offset) on; LNA=11; RXVGA=001011(11) ; RXFLSW=11(010001); RXGPK=00; RXGCF=00; -50dBm input | |
754 | (0x07<<24)|0x0C68CE, // 20050818.2 0x0C66CE, // 20050818 // 20050816 0x0C68CE | |
755 | //; 031A3; FILT (0x07) -- TX/RX filter with auto-tuning; TFLBW=011; RFLBW=100 | |
756 | (0x08<<24)|0x100010, //; 04000; TCAL (0x08) -- //for LO | |
757 | (0x09<<24)|0x004012, // 20060612.1.a 0x6E4012, // 0x004012, | |
758 | //; 1B900; RCALA (0x09) -- FASTS=11; HPDE=01 (100nsec); SEHP=1 (select B0 pin=RXHP); RXHP=1 (Turn on RXHP function)(FA5976A_1.3C) | |
759 | (0x0A<<24)|0x704014, //; 1C100; RCALB (0x0A) | |
760 | (0x0B<<24)|0x18BDD6, // 941003 0x1805D6, // 20050818.2 0x1801D6, // 20050818 // 20050816 0x1805D6 | |
761 | //; 062F7; IQCAL (0x0B) -- Turn on LO phase tuner=0111 & RX-LO phase = 0111; FA5976A_1.3B (2005/09/29) | |
762 | (0x0C<<24)|0x575558, // 20050818.2 0x555558, // 20050818 // 20050816 0x575558 | |
763 | //; 15D55 ; IBSA (0x0C) -- IFPre =11 ; TC5376A_v1.3A for corner | |
764 | (0x0D<<24)|0x55545A, // 20060612.1.a 0x55555A, | |
765 | //; 15555 ; IBSB (0x0D) | |
766 | (0x0E<<24)|0x5557DC, // 20060612.1.a 0x55555C, // 941003 0x5557DC, | |
767 | //; 1555F ; IBSC (0x0E) -- IRLNA & IRLNB (PTAT & Const current)=01/01; FA5976B_1.3F (2005/11/25) | |
768 | (0x10<<24)|0x000C20, // 941003 0x000020, // 20050818 | |
769 | //; 00030 ; TMODA (0x10) -- LNA_gain_step=0011 ; LNA=15/16dB | |
770 | (0x11<<24)|0x0C0022, // 941003 0x030022 // 20050818.2 0x030022 // 20050818 // 20050816 0x0C0022 | |
771 | //; 03000 ; TMODB (0x11) -- Turn ON RX-Q path Test Switch; To improve IQ path group delay (FA5976A_1.3C) | |
772 | (0x12<<24)|0x000024 // 20060612.1.a 0x001824 // 941003 add | |
773 | //; TMODC (0x12) -- Turn OFF Tempearure sensor | |
774 | }; | |
775 | ||
776 | u32 w89rf242_channel_data_24[][2] = | |
777 | { | |
778 | {(0x03<<24)|0x025B06, (0x04<<24)|0x080408}, // channe1 01 | |
779 | {(0x03<<24)|0x025C46, (0x04<<24)|0x080408}, // channe1 02 | |
780 | {(0x03<<24)|0x025D86, (0x04<<24)|0x080408}, // channe1 03 | |
781 | {(0x03<<24)|0x025EC6, (0x04<<24)|0x080408}, // channe1 04 | |
782 | {(0x03<<24)|0x026006, (0x04<<24)|0x080408}, // channe1 05 | |
783 | {(0x03<<24)|0x026146, (0x04<<24)|0x080408}, // channe1 06 | |
784 | {(0x03<<24)|0x026286, (0x04<<24)|0x080408}, // channe1 07 | |
785 | {(0x03<<24)|0x0263C6, (0x04<<24)|0x080408}, // channe1 08 | |
786 | {(0x03<<24)|0x026506, (0x04<<24)|0x080408}, // channe1 09 | |
787 | {(0x03<<24)|0x026646, (0x04<<24)|0x080408}, // channe1 10 | |
788 | {(0x03<<24)|0x026786, (0x04<<24)|0x080408}, // channe1 11 | |
789 | {(0x03<<24)|0x0268C6, (0x04<<24)|0x080408}, // channe1 12 | |
790 | {(0x03<<24)|0x026A06, (0x04<<24)|0x080408}, // channe1 13 | |
791 | {(0x03<<24)|0x026D06, (0x04<<24)|0x080408} // channe1 14 | |
792 | }; | |
793 | ||
794 | u32 w89rf242_power_data_24[] = {(0x05<<24)|0x24C48A, (0x05<<24)|0x24C48A, (0x05<<24)|0x24C48A}; | |
795 | ||
796 | // 20060315.6 Enlarge for new scale | |
797 | // 20060316.6 20060619.2.a add mapping array | |
798 | u32 w89rf242_txvga_old_mapping[][2] = | |
799 | { | |
800 | {0, 0} , // New <-> Old | |
801 | {1, 1} , | |
802 | {2, 2} , | |
803 | {3, 3} , | |
804 | {4, 4} , | |
805 | {6, 5} , | |
806 | {8, 6 }, | |
807 | {10, 7 }, | |
808 | {12, 8 }, | |
809 | {14, 9 }, | |
810 | {16, 10}, | |
811 | {18, 11}, | |
812 | {20, 12}, | |
813 | {22, 13}, | |
814 | {24, 14}, | |
815 | {26, 15}, | |
816 | {28, 16}, | |
817 | {30, 17}, | |
818 | {32, 18}, | |
819 | {34, 19}, | |
820 | ||
821 | ||
822 | }; | |
823 | ||
824 | // 20060619.3 modify from Bruce's mail | |
825 | u32 w89rf242_txvga_data[][5] = | |
826 | { | |
827 | //low gain mode | |
828 | { (0x05<<24)|0x24C00A, 0, 0x00292315, 0x0800FEFF, 0x52523131 },// ; min gain | |
829 | { (0x05<<24)|0x24C80A, 1, 0x00292315, 0x0800FEFF, 0x52523131 }, | |
830 | { (0x05<<24)|0x24C04A, 2, 0x00292315, 0x0800FEFF, 0x52523131 },// (default) +14dBm (ANT) | |
831 | { (0x05<<24)|0x24C84A, 3, 0x00292315, 0x0800FEFF, 0x52523131 }, | |
832 | ||
833 | //TXVGA=0x10 | |
834 | { (0x05<<24)|0x24C40A, 4, 0x00292315, 0x0800FEFF, 0x60603838 }, | |
835 | { (0x05<<24)|0x24C40A, 5, 0x00262114, 0x0700FEFF, 0x65653B3B }, | |
836 | ||
837 | //TXVGA=0x11 | |
838 | { (0x05<<24)|0x24C44A, 6, 0x00241F13, 0x0700FFFF, 0x58583333 }, | |
839 | { (0x05<<24)|0x24C44A, 7, 0x00292315, 0x0800FEFF, 0x5E5E3737 }, | |
840 | ||
841 | //TXVGA=0x12 | |
842 | { (0x05<<24)|0x24C48A, 8, 0x00262114, 0x0700FEFF, 0x53533030 }, | |
843 | { (0x05<<24)|0x24C48A, 9, 0x00241F13, 0x0700FFFF, 0x59593434 }, | |
844 | ||
845 | //TXVGA=0x13 | |
846 | { (0x05<<24)|0x24C4CA, 10, 0x00292315, 0x0800FEFF, 0x52523030 }, | |
847 | { (0x05<<24)|0x24C4CA, 11, 0x00262114, 0x0700FEFF, 0x56563232 }, | |
848 | ||
849 | //TXVGA=0x14 | |
850 | { (0x05<<24)|0x24C50A, 12, 0x00292315, 0x0800FEFF, 0x54543131 }, | |
851 | { (0x05<<24)|0x24C50A, 13, 0x00262114, 0x0700FEFF, 0x58583434 }, | |
852 | ||
853 | //TXVGA=0x15 | |
854 | { (0x05<<24)|0x24C54A, 14, 0x00292315, 0x0800FEFF, 0x54543131 }, | |
855 | { (0x05<<24)|0x24C54A, 15, 0x00262114, 0x0700FEFF, 0x59593434 }, | |
856 | ||
857 | //TXVGA=0x16 | |
858 | { (0x05<<24)|0x24C58A, 16, 0x00292315, 0x0800FEFF, 0x55553131 }, | |
859 | { (0x05<<24)|0x24C58A, 17, 0x00292315, 0x0800FEFF, 0x5B5B3535 }, | |
860 | ||
861 | //TXVGA=0x17 | |
862 | { (0x05<<24)|0x24C5CA, 18, 0x00262114, 0x0700FEFF, 0x51512F2F }, | |
863 | { (0x05<<24)|0x24C5CA, 19, 0x00241F13, 0x0700FFFF, 0x55553131 }, | |
864 | ||
865 | //TXVGA=0x18 | |
866 | { (0x05<<24)|0x24C60A, 20, 0x00292315, 0x0800FEFF, 0x4F4F2E2E }, | |
867 | { (0x05<<24)|0x24C60A, 21, 0x00262114, 0x0700FEFF, 0x53533030 }, | |
868 | ||
869 | //TXVGA=0x19 | |
870 | { (0x05<<24)|0x24C64A, 22, 0x00292315, 0x0800FEFF, 0x4E4E2D2D }, | |
871 | { (0x05<<24)|0x24C64A, 23, 0x00262114, 0x0700FEFF, 0x53533030 }, | |
872 | ||
873 | //TXVGA=0x1A | |
874 | { (0x05<<24)|0x24C68A, 24, 0x00292315, 0x0800FEFF, 0x50502E2E }, | |
875 | { (0x05<<24)|0x24C68A, 25, 0x00262114, 0x0700FEFF, 0x55553131 }, | |
876 | ||
877 | //TXVGA=0x1B | |
878 | { (0x05<<24)|0x24C6CA, 26, 0x00262114, 0x0700FEFF, 0x53533030 }, | |
879 | { (0x05<<24)|0x24C6CA, 27, 0x00292315, 0x0800FEFF, 0x5A5A3434 }, | |
880 | ||
881 | //TXVGA=0x1C | |
882 | { (0x05<<24)|0x24C70A, 28, 0x00292315, 0x0800FEFF, 0x55553131 }, | |
883 | { (0x05<<24)|0x24C70A, 29, 0x00292315, 0x0800FEFF, 0x5D5D3636 }, | |
884 | ||
885 | //TXVGA=0x1D | |
886 | { (0x05<<24)|0x24C74A, 30, 0x00292315, 0x0800FEFF, 0x5F5F3737 }, | |
887 | { (0x05<<24)|0x24C74A, 31, 0x00262114, 0x0700FEFF, 0x65653B3B }, | |
888 | ||
889 | //TXVGA=0x1E | |
890 | { (0x05<<24)|0x24C78A, 32, 0x00292315, 0x0800FEFF, 0x66663B3B }, | |
891 | { (0x05<<24)|0x24C78A, 33, 0x00262114, 0x0700FEFF, 0x70704141 }, | |
892 | ||
893 | //TXVGA=0x1F | |
894 | { (0x05<<24)|0x24C7CA, 34, 0x00292315, 0x0800FEFF, 0x72724242 } | |
895 | }; | |
896 | ||
897 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
898 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
899 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
900 | ||
901 | ||
902 | ||
903 | //============================================================================================================= | |
904 | // Uxx_ReadEthernetAddress -- | |
905 | // | |
906 | // Routine Description: | |
907 | // Reads in the Ethernet address from the IC. | |
908 | // | |
909 | // Arguments: | |
910 | // pHwData - The pHwData structure | |
911 | // | |
912 | // Return Value: | |
913 | // | |
914 | // The address is stored in EthernetIDAddr. | |
915 | //============================================================================================================= | |
916 | void | |
917 | Uxx_ReadEthernetAddress( phw_data_t pHwData ) | |
918 | { | |
919 | u32 ltmp; | |
920 | ||
921 | // Reading Ethernet address from EEPROM and set into hardware due to MAC address maybe change. | |
922 | // Only unplug and plug again can make hardware read EEPROM again. 20060727 | |
923 | Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08000000 ); // Start EEPROM access + Read + address(0x0d) | |
924 | Wb35Reg_ReadSync( pHwData, 0x03b4, <mp ); | |
925 | *(PUSHORT)pHwData->PermanentMacAddress = cpu_to_le16((u16)ltmp); //20060926 anson's endian | |
926 | Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08010000 ); // Start EEPROM access + Read + address(0x0d) | |
927 | Wb35Reg_ReadSync( pHwData, 0x03b4, <mp ); | |
928 | *(PUSHORT)(pHwData->PermanentMacAddress + 2) = cpu_to_le16((u16)ltmp); //20060926 anson's endian | |
929 | Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08020000 ); // Start EEPROM access + Read + address(0x0d) | |
930 | Wb35Reg_ReadSync( pHwData, 0x03b4, <mp ); | |
931 | *(PUSHORT)(pHwData->PermanentMacAddress + 4) = cpu_to_le16((u16)ltmp); //20060926 anson's endian | |
932 | *(PUSHORT)(pHwData->PermanentMacAddress + 6) = 0; | |
933 | Wb35Reg_WriteSync( pHwData, 0x03e8, cpu_to_le32(*(PULONG)pHwData->PermanentMacAddress) ); //20060926 anson's endian | |
934 | Wb35Reg_WriteSync( pHwData, 0x03ec, cpu_to_le32(*(PULONG)(pHwData->PermanentMacAddress+4)) ); //20060926 anson's endian | |
935 | } | |
936 | ||
937 | ||
938 | //=============================================================================================================== | |
939 | // CardGetMulticastBit -- | |
940 | // Description: | |
941 | // For a given multicast address, returns the byte and bit in the card multicast registers that it hashes to. | |
942 | // Calls CardComputeCrc() to determine the CRC value. | |
943 | // Arguments: | |
944 | // Address - the address | |
945 | // Byte - the byte that it hashes to | |
946 | // Value - will have a 1 in the relevant bit | |
947 | // Return Value: | |
948 | // None. | |
949 | //============================================================================================================== | |
950 | void CardGetMulticastBit( u8 Address[ETH_LENGTH_OF_ADDRESS], | |
951 | u8 *Byte, u8 *Value ) | |
952 | { | |
953 | u32 Crc; | |
954 | u32 BitNumber; | |
955 | ||
956 | // First compute the CRC. | |
957 | Crc = CardComputeCrc(Address, ETH_LENGTH_OF_ADDRESS); | |
958 | ||
959 | // The computed CRC is bit0~31 from left to right | |
960 | //At first we should do right shift 25bits, and read 7bits by using '&', 2^7=128 | |
961 | BitNumber = (u32) ((Crc >> 26) & 0x3f); | |
962 | ||
963 | *Byte = (u8) (BitNumber >> 3);// 900514 original (BitNumber / 8) | |
964 | *Value = (u8) ((u8)1 << (BitNumber % 8)); | |
965 | } | |
966 | ||
967 | void Uxx_power_on_procedure( phw_data_t pHwData ) | |
968 | { | |
969 | u32 ltmp, loop; | |
970 | ||
971 | if( pHwData->phy_type <= RF_MAXIM_V1 ) | |
972 | Wb35Reg_WriteSync( pHwData, 0x03d4, 0xffffff38 ); | |
973 | else | |
974 | { | |
975 | Wb35Reg_WriteSync( pHwData, 0x03f4, 0xFF5807FF );// 20060721 For NEW IC 0xFF5807FF | |
976 | ||
977 | // 20060511.1 Fix the following 4 steps for Rx of RF 2230 initial fail | |
978 | Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only | |
979 | OS_SLEEP(10000); // Modify 20051221.1.b | |
980 | Wb35Reg_WriteSync( pHwData, 0x03d4, 0xb8 );// REG_ON RF_RSTN on, and | |
981 | OS_SLEEP(10000); // Modify 20051221.1.b | |
982 | ||
983 | ltmp = 0x4968; | |
984 | if( (pHwData->phy_type == RF_WB_242) || | |
985 | (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add | |
986 | ltmp = 0x4468; | |
987 | Wb35Reg_WriteSync( pHwData, 0x03d0, ltmp ); | |
988 | ||
989 | Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0 | |
990 | ||
991 | OS_SLEEP(20000); // Modify 20051221.1.b | |
992 | Wb35Reg_ReadSync( pHwData, 0x03d0, <mp ); | |
993 | loop = 500; // Wait for 5 second 20061101 | |
994 | while( !(ltmp & 0x20) && loop-- ) | |
995 | { | |
996 | OS_SLEEP(10000); // Modify 20051221.1.b | |
997 | if( !Wb35Reg_ReadSync( pHwData, 0x03d0, <mp ) ) | |
998 | break; | |
999 | } | |
1000 | ||
1001 | Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN | |
1002 | } | |
1003 | ||
1004 | Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first | |
1005 | OS_SLEEP(10000); // Add this 20051221.1.b | |
1006 | ||
1007 | // Set burst write delay | |
1008 | Wb35Reg_WriteSync( pHwData, 0x03f8, 0x7ff ); | |
1009 | } | |
1010 | ||
1011 | void Set_ChanIndep_RfData_al7230_24( phw_data_t pHwData, u32 *pltmp ,char number) | |
1012 | { | |
1013 | u8 i; | |
1014 | ||
1015 | for( i=0; i<number; i++ ) | |
1016 | { | |
1017 | pHwData->phy_para[i] = al7230_rf_data_24[i]; | |
1018 | pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_24[i]&0xffffff); | |
1019 | } | |
1020 | } | |
1021 | ||
1022 | void Set_ChanIndep_RfData_al7230_50( phw_data_t pHwData, u32 *pltmp, char number) | |
1023 | { | |
1024 | u8 i; | |
1025 | ||
1026 | for( i=0; i<number; i++ ) | |
1027 | { | |
1028 | pHwData->phy_para[i] = al7230_rf_data_50[i]; | |
1029 | pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_50[i]&0xffffff); | |
1030 | } | |
1031 | } | |
1032 | ||
1033 | ||
1034 | //============================================================================================================= | |
1035 | // RFSynthesizer_initial -- | |
1036 | //============================================================================================================= | |
1037 | void | |
1038 | RFSynthesizer_initial(phw_data_t pHwData) | |
1039 | { | |
1040 | u32 altmp[32]; | |
1041 | PULONG pltmp = altmp; | |
1042 | u32 ltmp; | |
1043 | u8 number=0x00; // The number of register vale | |
1044 | u8 i; | |
1045 | ||
1046 | // | |
1047 | // bit[31] SPI Enable. | |
1048 | // 1=perform synthesizer program operation. This bit will | |
1049 | // cleared automatically after the operation is completed. | |
1050 | // bit[30] SPI R/W Control | |
1051 | // 0=write, 1=read | |
1052 | // bit[29:24] SPI Data Format Length | |
1053 | // bit[17:4 ] RF Data bits. | |
1054 | // bit[3 :0 ] RF address. | |
1055 | switch( pHwData->phy_type ) | |
1056 | { | |
1057 | case RF_MAXIM_2825: | |
1058 | case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) | |
1059 | number = sizeof(max2825_rf_data)/sizeof(max2825_rf_data[0]); | |
1060 | for( i=0; i<number; i++ ) | |
1061 | { | |
1062 | pHwData->phy_para[i] = max2825_rf_data[i];// Backup Rf parameter | |
1063 | pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_rf_data[i], 18); | |
1064 | } | |
1065 | break; | |
1066 | ||
1067 | case RF_MAXIM_2827: | |
1068 | number = sizeof(max2827_rf_data)/sizeof(max2827_rf_data[0]); | |
1069 | for( i=0; i<number; i++ ) | |
1070 | { | |
1071 | pHwData->phy_para[i] = max2827_rf_data[i]; | |
1072 | pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_rf_data[i], 18); | |
1073 | } | |
1074 | break; | |
1075 | ||
1076 | case RF_MAXIM_2828: | |
1077 | number = sizeof(max2828_rf_data)/sizeof(max2828_rf_data[0]); | |
1078 | for( i=0; i<number; i++ ) | |
1079 | { | |
1080 | pHwData->phy_para[i] = max2828_rf_data[i]; | |
1081 | pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_rf_data[i], 18); | |
1082 | } | |
1083 | break; | |
1084 | ||
1085 | case RF_MAXIM_2829: | |
1086 | number = sizeof(max2829_rf_data)/sizeof(max2829_rf_data[0]); | |
1087 | for( i=0; i<number; i++ ) | |
1088 | { | |
1089 | pHwData->phy_para[i] = max2829_rf_data[i]; | |
1090 | pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_rf_data[i], 18); | |
1091 | } | |
1092 | break; | |
1093 | ||
1094 | case RF_AIROHA_2230: | |
1095 | number = sizeof(al2230_rf_data)/sizeof(al2230_rf_data[0]); | |
1096 | for( i=0; i<number; i++ ) | |
1097 | { | |
1098 | pHwData->phy_para[i] = al2230_rf_data[i]; | |
1099 | pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[i], 20); | |
1100 | } | |
1101 | break; | |
1102 | ||
1103 | case RF_AIROHA_2230S: | |
1104 | number = sizeof(al2230s_rf_data)/sizeof(al2230s_rf_data[0]); | |
1105 | for( i=0; i<number; i++ ) | |
1106 | { | |
1107 | pHwData->phy_para[i] = al2230s_rf_data[i]; | |
1108 | pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230s_rf_data[i], 20); | |
1109 | } | |
1110 | break; | |
1111 | ||
1112 | case RF_AIROHA_7230: | |
1113 | ||
1114 | //Start to fill RF parameters, PLL_ON should be pulled low. | |
1115 | Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 ); | |
1116 | #ifdef _PE_STATE_DUMP_ | |
1117 | WBDEBUG(("* PLL_ON low\n")); | |
1118 | #endif | |
1119 | ||
1120 | number = sizeof(al7230_rf_data_24)/sizeof(al7230_rf_data_24[0]); | |
1121 | Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number); | |
1122 | break; | |
1123 | ||
1124 | case RF_WB_242: | |
1125 | case RF_WB_242_1: // 20060619.5 Add | |
1126 | number = sizeof(w89rf242_rf_data)/sizeof(w89rf242_rf_data[0]); | |
1127 | for( i=0; i<number; i++ ) | |
1128 | { | |
1129 | ltmp = w89rf242_rf_data[i]; | |
1130 | if( i == 4 ) // Update the VCO trim from EEPROM | |
1131 | { | |
1132 | ltmp &= ~0xff0; // Mask bit4 ~bit11 | |
1133 | ltmp |= pHwData->VCO_trim<<4; | |
1134 | } | |
1135 | ||
1136 | pHwData->phy_para[i] = ltmp; | |
1137 | pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( ltmp, 24); | |
1138 | } | |
1139 | break; | |
1140 | } | |
1141 | ||
1142 | pHwData->phy_number = number; | |
1143 | ||
1144 | // The 16 is the maximum capability of hardware. Here use 12 | |
1145 | if( number > 12 ) { | |
1146 | //Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 12, NO_INCREMENT ); | |
1147 | for( i=0; i<12; i++ ) // For Al2230 | |
1148 | Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] ); | |
1149 | ||
1150 | pltmp += 12; | |
1151 | number -= 12; | |
1152 | } | |
1153 | ||
1154 | // Write to register. number must less and equal than 16 | |
1155 | for( i=0; i<number; i++ ) | |
1156 | Wb35Reg_WriteSync( pHwData, 0x864, pltmp[i] ); | |
1157 | ||
1158 | // 20060630.1 Calibration only 1 time | |
1159 | if( pHwData->CalOneTime ) | |
1160 | return; | |
1161 | pHwData->CalOneTime = 1; | |
1162 | ||
1163 | switch( pHwData->phy_type ) | |
1164 | { | |
1165 | case RF_AIROHA_2230: | |
1166 | ||
1167 | // 20060511.1 --- Modifying the follow step for Rx issue----------------- | |
1168 | ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x07<<20)|0xE168E, 20); | |
1169 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1170 | OS_SLEEP(10000); | |
1171 | ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[7], 20); | |
1172 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1173 | OS_SLEEP(10000); | |
1174 | ||
1175 | case RF_AIROHA_2230S: // 20060420 Add this | |
1176 | ||
1177 | // 20060511.1 --- Modifying the follow step for Rx issue----------------- | |
1178 | Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only | |
1179 | OS_SLEEP(10000); // Modify 20051221.1.b | |
1180 | ||
1181 | Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0 | |
1182 | OS_SLEEP(10000); // Modify 20051221.1.b | |
1183 | ||
1184 | Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN | |
1185 | Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first | |
1186 | OS_SLEEP(10000); // Add this 20051221.1.b | |
1187 | //------------------------------------------------------------------------ | |
1188 | ||
1189 | // The follow code doesn't use the burst-write mode | |
1190 | //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Raise Initial Setting | |
1191 | ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20); | |
1192 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1193 | ||
1194 | ltmp = pHwData->Wb35Reg.BB5C & 0xfffff000; | |
1195 | Wb35Reg_WriteSync( pHwData, 0x105c, ltmp ); | |
1196 | pHwData->Wb35Reg.BB50 |= 0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060315.1 modify | |
1197 | Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50); | |
1198 | OS_SLEEP(5000); | |
1199 | ||
1200 | //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01B0); //Activate Filter Cal. | |
1201 | ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01B0, 20); | |
1202 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1203 | OS_SLEEP(5000); | |
1204 | ||
1205 | //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01e0); //Activate TX DCC | |
1206 | ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01E0, 20); | |
1207 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1208 | OS_SLEEP(5000); | |
1209 | ||
1210 | //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Resotre Initial Setting | |
1211 | ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20); | |
1212 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1213 | ||
1214 | // //Force TXI(Q)P(N) to normal control | |
1215 | Wb35Reg_WriteSync( pHwData, 0x105c, pHwData->Wb35Reg.BB5C ); | |
1216 | pHwData->Wb35Reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START); | |
1217 | Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50); | |
1218 | break; | |
1219 | ||
1220 | case RF_AIROHA_7230: | |
1221 | ||
1222 | //RF parameters have filled completely, PLL_ON should be | |
1223 | //pulled high | |
1224 | Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 ); | |
1225 | #ifdef _PE_STATE_DUMP_ | |
1226 | WBDEBUG(("* PLL_ON high\n")); | |
1227 | #endif | |
1228 | ||
1229 | //2.4GHz | |
1230 | //ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F; | |
1231 | //Wb35Reg_WriteSync pHwData, 0x0864, ltmp ); | |
1232 | //OS_SLEEP(1000); // Sleep 1 ms | |
1233 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F; | |
1234 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1235 | OS_SLEEP(5000); | |
1236 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F; | |
1237 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1238 | OS_SLEEP(5000); | |
1239 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F; | |
1240 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1241 | OS_SLEEP(5000); | |
1242 | ||
1243 | //5GHz | |
1244 | Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 ); | |
1245 | #ifdef _PE_STATE_DUMP_ | |
1246 | WBDEBUG(("* PLL_ON low\n")); | |
1247 | #endif | |
1248 | ||
1249 | number = sizeof(al7230_rf_data_50)/sizeof(al7230_rf_data_50[0]); | |
1250 | Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number); | |
1251 | // Write to register. number must less and equal than 16 | |
1252 | for( i=0; i<number; i++ ) | |
1253 | Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] ); | |
1254 | OS_SLEEP(5000); | |
1255 | ||
1256 | Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 ); | |
1257 | #ifdef _PE_STATE_DUMP_ | |
1258 | WBDEBUG(("* PLL_ON high\n")); | |
1259 | #endif | |
1260 | ||
1261 | //ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF; | |
1262 | //Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1263 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F; | |
1264 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1265 | OS_SLEEP(5000); | |
1266 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F; | |
1267 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1268 | OS_SLEEP(5000); | |
1269 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF; | |
1270 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1271 | OS_SLEEP(5000); | |
1272 | ||
1273 | //Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 ); | |
1274 | //WBDEBUG(("* PLL_ON high\n")); | |
1275 | break; | |
1276 | ||
1277 | case RF_WB_242: | |
1278 | case RF_WB_242_1: // 20060619.5 Add | |
1279 | ||
1280 | // | |
1281 | // ; Version 1.3B revision items: for FA5976A , October 3, 2005 by HTHo | |
1282 | // | |
1283 | ltmp = pHwData->Wb35Reg.BB5C & 0xfffff000; | |
1284 | Wb35Reg_WriteSync( pHwData, 0x105c, ltmp ); | |
1285 | Wb35Reg_WriteSync( pHwData, 0x1058, 0 ); | |
1286 | pHwData->Wb35Reg.BB50 |= 0x3;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060630 | |
1287 | Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50); | |
1288 | ||
1289 | //----- Calibration (1). VCO frequency calibration | |
1290 | //Calibration (1a.0). Synthesizer reset (HTHo corrected 2005/05/10) | |
1291 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00101E, 24); | |
1292 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1293 | OS_SLEEP( 5000 ); // Sleep 5ms | |
1294 | //Calibration (1a). VCO frequency calibration mode ; waiting 2msec VCO calibration time | |
1295 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFE69c0, 24); | |
1296 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1297 | OS_SLEEP( 2000 ); // Sleep 2ms | |
1298 | ||
1299 | //----- Calibration (2). TX baseband Gm-C filter auto-tuning | |
1300 | //Calibration (2a). turn off ENCAL signal | |
1301 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24); | |
1302 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1303 | //Calibration (2b.0). TX filter auto-tuning BW: TFLBW=101 (TC5376A default) | |
1304 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x07<<24) | 0x0C68CE, 24); | |
1305 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1306 | //Calibration (2b). send TX reset signal (HTHo corrected May 10, 2005) | |
1307 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00201E, 24); | |
1308 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1309 | //Calibration (2c). turn-on TX Gm-C filter auto-tuning | |
1310 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFCEBC0, 24); | |
1311 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1312 | OS_SLEEP( 150 ); // Sleep 150 us | |
1313 | //turn off ENCAL signal | |
1314 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24); | |
1315 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1316 | ||
1317 | //----- Calibration (3). RX baseband Gm-C filter auto-tuning | |
1318 | //Calibration (3a). turn off ENCAL signal | |
1319 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); | |
1320 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1321 | //Calibration (3b.0). RX filter auto-tuning BW: RFLBW=100 (TC5376A+corner default; July 26, 2005) | |
1322 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x07<<24) | 0x0C68CE, 24); | |
1323 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1324 | //Calibration (3b). send RX reset signal (HTHo corrected May 10, 2005) | |
1325 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00401E, 24); | |
1326 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1327 | //Calibration (3c). turn-on RX Gm-C filter auto-tuning | |
1328 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFEEDC0, 24); | |
1329 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1330 | OS_SLEEP( 150 ); // Sleep 150 us | |
1331 | //Calibration (3e). turn off ENCAL signal | |
1332 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); | |
1333 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1334 | ||
1335 | //----- Calibration (4). TX LO leakage calibration | |
1336 | //Calibration (4a). TX LO leakage calibration | |
1337 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFD6BC0, 24); | |
1338 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1339 | OS_SLEEP( 150 ); // Sleep 150 us | |
1340 | ||
1341 | //----- Calibration (5). RX DC offset calibration | |
1342 | //Calibration (5a). turn off ENCAL signal and set to RX SW DC caliration mode | |
1343 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); | |
1344 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1345 | //Calibration (5b). turn off AGC servo-loop & RSSI | |
1346 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x01<<24) | 0xEBFFC2, 24); | |
1347 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1348 | ||
1349 | //; for LNA=11 -------- | |
1350 | //Calibration (5c-h). RX DC offset current bias ON; & LNA=11; RXVGA=111111 | |
1351 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x343FCC, 24); | |
1352 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1353 | //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time | |
1354 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24); | |
1355 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1356 | OS_SLEEP(2000); // Sleep 2ms | |
1357 | //Calibration (5f). turn off ENCAL signal | |
1358 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); | |
1359 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1360 | ||
1361 | //; for LNA=10 -------- | |
1362 | //Calibration (5c-m). RX DC offset current bias ON; & LNA=10; RXVGA=111111 | |
1363 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x342FCC, 24); | |
1364 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1365 | //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time | |
1366 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24); | |
1367 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1368 | OS_SLEEP(2000); // Sleep 2ms | |
1369 | //Calibration (5f). turn off ENCAL signal | |
1370 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); | |
1371 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1372 | ||
1373 | //; for LNA=01 -------- | |
1374 | //Calibration (5c-m). RX DC offset current bias ON; & LNA=01; RXVGA=111111 | |
1375 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x341FCC, 24); | |
1376 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1377 | //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time | |
1378 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24); | |
1379 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1380 | OS_SLEEP(2000); // Sleep 2ms | |
1381 | //Calibration (5f). turn off ENCAL signal | |
1382 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); | |
1383 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1384 | ||
1385 | //; for LNA=00 -------- | |
1386 | //Calibration (5c-l). RX DC offset current bias ON; & LNA=00; RXVGA=111111 | |
1387 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x340FCC, 24); | |
1388 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1389 | //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time | |
1390 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24); | |
1391 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1392 | OS_SLEEP(2000); // Sleep 2ms | |
1393 | //Calibration (5f). turn off ENCAL signal | |
1394 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); | |
1395 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1396 | //Calibration (5g). turn on AGC servo-loop | |
1397 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x01<<24) | 0xEFFFC2, 24); | |
1398 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1399 | ||
1400 | //; ----- Calibration (7). Switch RF chip to normal mode | |
1401 | //0x00 0xF86100 ; 3E184 ; Switch RF chip to normal mode | |
1402 | // OS_SLEEP(10000); // @@ 20060721 | |
1403 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF86100, 24); | |
1404 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1405 | OS_SLEEP(5000); // Sleep 5 ms | |
1406 | ||
1407 | // //write back | |
1408 | // Wb35Reg_WriteSync( pHwData, 0x105c, pHwData->Wb35Reg.BB5C ); | |
1409 | // pHwData->Wb35Reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START); // 20060315.1 fix | |
1410 | // Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50); | |
1411 | // OS_SLEEP(1000); // Sleep 1 ms | |
1412 | break; | |
1413 | } | |
1414 | } | |
1415 | ||
1416 | void BBProcessor_AL7230_2400( phw_data_t pHwData) | |
1417 | { | |
1418 | PWB35REG pWb35Reg = &pHwData->Wb35Reg; | |
1419 | u32 pltmp[12]; | |
1420 | ||
1421 | pltmp[0] = 0x16A8337A; // 0x16a5215f; // 0x1000 AGC_Ctrl1 | |
1422 | pltmp[1] = 0x9AFF9AA6; // 0x9aff9ca6; // 0x1004 AGC_Ctrl2 | |
1423 | pltmp[2] = 0x55D00A04; // 0x55d00a04; // 0x1008 AGC_Ctrl3 | |
1424 | pltmp[3] = 0xFFF72031; // 0xFfFf2138; // 0x100c AGC_Ctrl4 | |
1425 | pWb35Reg->BB0C = 0xFFF72031; | |
1426 | pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7 | |
1427 | pltmp[5] = 0x00CAA333; // 0x00eaa333; // 0x1014 AGC_Ctrl6 | |
1428 | pltmp[6] = 0xF2211111; // 0x11111111; // 0x1018 AGC_Ctrl7 | |
1429 | pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 | |
1430 | pltmp[8] = 0x06443440; // 0x1020 AGC_Ctrl9 | |
1431 | pltmp[9] = 0xA8002A79; // 0xa9002A79; // 0x1024 AGC_Ctrl10 | |
1432 | pltmp[10] = 0x40000528; // 20050927 0x40000228 | |
1433 | pltmp[11] = 0x232D7F30; // 0x23457f30;// 0x102c A_ACQ_Ctrl | |
1434 | pWb35Reg->BB2C = 0x232D7F30; | |
1435 | Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); | |
1436 | ||
1437 | pltmp[0] = 0x00002c54; // 0x1030 B_ACQ_Ctrl | |
1438 | pWb35Reg->BB30 = 0x00002c54; | |
1439 | pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl | |
1440 | pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl | |
1441 | pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter | |
1442 | pWb35Reg->BB3C = 0x00000000; | |
1443 | pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter | |
1444 | pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter | |
1445 | pltmp[6] = 0x00332C1B; // 0x00453B24; // 0x1048 11b TX RC filter | |
1446 | pltmp[7] = 0x0A00FEFF; // 0x0E00FEFF; // 0x104c 11b TX RC filter | |
1447 | pltmp[8] = 0x2B106208; // 0x1050 MODE_Ctrl | |
1448 | pWb35Reg->BB50 = 0x2B106208; | |
1449 | pltmp[9] = 0; // 0x1054 | |
1450 | pWb35Reg->BB54 = 0x00000000; | |
1451 | pltmp[10] = 0x52524242; // 0x64645252; // 0x1058 IQ_Alpha | |
1452 | pWb35Reg->BB58 = 0x52524242; | |
1453 | pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel | |
1454 | Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); | |
1455 | ||
1456 | } | |
1457 | ||
1458 | void BBProcessor_AL7230_5000( phw_data_t pHwData) | |
1459 | { | |
1460 | PWB35REG pWb35Reg = &pHwData->Wb35Reg; | |
1461 | u32 pltmp[12]; | |
1462 | ||
1463 | pltmp[0] = 0x16AA6678; // 0x1000 AGC_Ctrl1 | |
1464 | pltmp[1] = 0x9AFFA0B2; // 0x1004 AGC_Ctrl2 | |
1465 | pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3 | |
1466 | pltmp[3] = 0xEFFF233E; // 0x100c AGC_Ctrl4 | |
1467 | pWb35Reg->BB0C = 0xEFFF233E; | |
1468 | pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7 | |
1469 | pltmp[5] = 0x00CAA333; // 0x1014 AGC_Ctrl6 | |
1470 | pltmp[6] = 0xF2432111; // 0x1018 AGC_Ctrl7 | |
1471 | pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 | |
1472 | pltmp[8] = 0x05C43440; // 0x1020 AGC_Ctrl9 | |
1473 | pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 | |
1474 | pltmp[10] = 0x40000528; // 20050927 0x40000228 | |
1475 | pltmp[11] = 0x232FDF30;// 0x102c A_ACQ_Ctrl | |
1476 | pWb35Reg->BB2C = 0x232FDF30; | |
1477 | Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); | |
1478 | ||
1479 | pltmp[0] = 0x80002C7C; // 0x1030 B_ACQ_Ctrl | |
1480 | pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl | |
1481 | pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl | |
1482 | pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter | |
1483 | pWb35Reg->BB3C = 0x00000000; | |
1484 | pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter | |
1485 | pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter | |
1486 | pltmp[6] = 0x00332C1B; // 0x1048 11b TX RC filter | |
1487 | pltmp[7] = 0x0A00FEFF; // 0x104c 11b TX RC filter | |
1488 | pltmp[8] = 0x2B107208; // 0x1050 MODE_Ctrl | |
1489 | pWb35Reg->BB50 = 0x2B107208; | |
1490 | pltmp[9] = 0; // 0x1054 | |
1491 | pWb35Reg->BB54 = 0x00000000; | |
1492 | pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha | |
1493 | pWb35Reg->BB58 = 0x52524242; | |
1494 | pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel | |
1495 | Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); | |
1496 | ||
1497 | } | |
1498 | ||
1499 | //============================================================================================================= | |
1500 | // BBProcessorPowerupInit -- | |
1501 | // | |
1502 | // Description: | |
1503 | // Initialize the Baseband processor. | |
1504 | // | |
1505 | // Arguments: | |
1506 | // pHwData - Handle of the USB Device. | |
1507 | // | |
1508 | // Return values: | |
1509 | // None. | |
1510 | //============================================================================================================= | |
1511 | void | |
1512 | BBProcessor_initial( phw_data_t pHwData ) | |
1513 | { | |
1514 | PWB35REG pWb35Reg = &pHwData->Wb35Reg; | |
1515 | u32 i, pltmp[12]; | |
1516 | ||
1517 | switch( pHwData->phy_type ) | |
1518 | { | |
1519 | case RF_MAXIM_V1: // Initializng the Winbond 2nd BB(with Phy board (v1) + Maxim 331) | |
1520 | ||
1521 | pltmp[0] = 0x16F47E77; // 0x1000 AGC_Ctrl1 | |
1522 | pltmp[1] = 0x9AFFAEA4; // 0x1004 AGC_Ctrl2 | |
1523 | pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3 | |
1524 | pltmp[3] = 0xEFFF1A34; // 0x100c AGC_Ctrl4 | |
1525 | pWb35Reg->BB0C = 0xEFFF1A34; | |
1526 | pltmp[4] = 0x0FABE0B7; // 0x1010 AGC_Ctrl5 | |
1527 | pltmp[5] = 0x00CAA332; // 0x1014 AGC_Ctrl6 | |
1528 | pltmp[6] = 0xF6632111; // 0x1018 AGC_Ctrl7 | |
1529 | pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 | |
1530 | pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9 | |
1531 | pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 | |
1532 | pltmp[10] = (pHwData->phy_type==3) ? 0x40000a28 : 0x40000228; // 0x1028 MAXIM_331(b31=0) + WBRF_V1(b11=1) : MAXIM_331(b31=0) + WBRF_V2(b11=0) | |
1533 | pltmp[11] = 0x232FDF30; // 0x102c A_ACQ_Ctrl | |
1534 | pWb35Reg->BB2C = 0x232FDF30; //Modify for 33's 1.0.95.xxx version, antenna 1 | |
1535 | Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); | |
1536 | ||
1537 | pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl | |
1538 | pWb35Reg->BB30 = 0x00002C54; | |
1539 | pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl | |
1540 | pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl | |
1541 | pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter | |
1542 | pWb35Reg->BB3C = 0x00000000; | |
1543 | pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter | |
1544 | pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter | |
1545 | pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter | |
1546 | pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter | |
1547 | pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl | |
1548 | pWb35Reg->BB50 = 0x27106208; | |
1549 | pltmp[9] = 0; // 0x1054 | |
1550 | pWb35Reg->BB54 = 0x00000000; | |
1551 | pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha | |
1552 | pWb35Reg->BB58 = 0x64646464; | |
1553 | pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel | |
1554 | Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); | |
1555 | ||
1556 | Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); | |
1557 | break; | |
1558 | ||
1559 | //------------------------------------------------------------------ | |
1560 | //[20040722 WK] | |
1561 | //Only for baseband version 2 | |
1562 | // case RF_MAXIM_317: | |
1563 | case RF_MAXIM_2825: | |
1564 | case RF_MAXIM_2827: | |
1565 | case RF_MAXIM_2828: | |
1566 | ||
1567 | pltmp[0] = 0x16b47e77; // 0x1000 AGC_Ctrl1 | |
1568 | pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2 | |
1569 | pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3 | |
1570 | pltmp[3] = 0xefff1a34; // 0x100c AGC_Ctrl4 | |
1571 | pWb35Reg->BB0C = 0xefff1a34; | |
1572 | pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5 | |
1573 | pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6 | |
1574 | pltmp[6] = 0xf6632111; // 0x1018 AGC_Ctrl7 | |
1575 | pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 | |
1576 | pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9 | |
1577 | pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 | |
1578 | pltmp[10] = 0x40000528; // 0x40000128; Modify for 33's 1.0.95 | |
1579 | pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl | |
1580 | pWb35Reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1 | |
1581 | Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); | |
1582 | ||
1583 | pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl | |
1584 | pWb35Reg->BB30 = 0x00002C54; | |
1585 | pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl | |
1586 | pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl | |
1587 | pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter | |
1588 | pWb35Reg->BB3C = 0x00000000; | |
1589 | pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter | |
1590 | pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter | |
1591 | pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter | |
1592 | pltmp[7] = 0x0D00FDFF; // 0x104c 11b TX RC filter | |
1593 | pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl | |
1594 | pWb35Reg->BB50 = 0x27106208; | |
1595 | pltmp[9] = 0; // 0x1054 | |
1596 | pWb35Reg->BB54 = 0x00000000; | |
1597 | pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha | |
1598 | pWb35Reg->BB58 = 0x64646464; | |
1599 | pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel | |
1600 | Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); | |
1601 | ||
1602 | Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); | |
1603 | break; | |
1604 | ||
1605 | case RF_MAXIM_2829: | |
1606 | ||
1607 | pltmp[0] = 0x16b47e77; // 0x1000 AGC_Ctrl1 | |
1608 | pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2 | |
1609 | pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3 | |
1610 | pltmp[3] = 0xf4ff1632; // 0xefff1a34; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95 | |
1611 | pWb35Reg->BB0C = 0xf4ff1632; // 0xefff1a34; Modify for 33's 1.0.95 | |
1612 | pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5 | |
1613 | pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6 | |
1614 | pltmp[6] = 0xf8632112; // 0xf6632111; // 0x1018 AGC_Ctrl7 Modify for 33's 1.0.95 | |
1615 | pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 | |
1616 | pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9 | |
1617 | pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 | |
1618 | pltmp[10] = 0x40000528; // 0x40000128; modify for 33's 1.0.95 | |
1619 | pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl | |
1620 | pWb35Reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1 | |
1621 | Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); | |
1622 | ||
1623 | pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl | |
1624 | pWb35Reg->BB30 = 0x00002C54; | |
1625 | pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl | |
1626 | pltmp[2] = 0x5b2c8769; // 0x5B6C8769; // 0x1038 B_TXRX_Ctrl Modify for 33's 1.0.95 | |
1627 | pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter | |
1628 | pWb35Reg->BB3C = 0x00000000; | |
1629 | pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter | |
1630 | pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter | |
1631 | pltmp[6] = 0x002c2617; // 0x00453B24; // 0x1048 11b TX RC filter Modify for 33's 1.0.95 | |
1632 | pltmp[7] = 0x0800feff; // 0x0D00FDFF; // 0x104c 11b TX RC filter Modify for 33's 1.0.95 | |
1633 | pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl | |
1634 | pWb35Reg->BB50 = 0x27106208; | |
1635 | pltmp[9] = 0; // 0x1054 | |
1636 | pWb35Reg->BB54 = 0x00000000; | |
1637 | pltmp[10] = 0x64644a4a; // 0x64646464; // 0x1058 IQ_Alpha Modify for 33's 1.0.95 | |
1638 | pWb35Reg->BB58 = 0x64646464; | |
1639 | pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel | |
1640 | Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); | |
1641 | ||
1642 | Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); | |
1643 | break; | |
1644 | ||
1645 | case RF_AIROHA_2230: | |
1646 | ||
1647 | pltmp[0] = 0X16764A77; // 0x1000 AGC_Ctrl1 //0x16765A77 | |
1648 | pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2 | |
1649 | pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3 | |
1650 | pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version | |
1651 | pWb35Reg->BB0C = 0xFFFd203c; | |
1652 | pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version | |
1653 | pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version | |
1654 | pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version | |
1655 | pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 | |
1656 | pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9 | |
1657 | pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 | |
1658 | pltmp[10] = 0X40000528; //0x40000228 | |
1659 | pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730 | |
1660 | pWb35Reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1 | |
1661 | Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); | |
1662 | ||
1663 | pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl | |
1664 | pWb35Reg->BB30 = 0x00002C54; | |
1665 | pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl | |
1666 | pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769 | |
1667 | pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter | |
1668 | pWb35Reg->BB3C = 0x00000000; | |
1669 | pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter | |
1670 | pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter | |
1671 | pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2 | |
1672 | pWb35Reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2 | |
1673 | pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2 | |
1674 | pWb35Reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1 20060613.2 | |
1675 | pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl | |
1676 | pWb35Reg->BB50 = 0x27106200; | |
1677 | pltmp[9] = 0; // 0x1054 | |
1678 | pWb35Reg->BB54 = 0x00000000; | |
1679 | pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha | |
1680 | pWb35Reg->BB58 = 0x52524242; | |
1681 | pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel | |
1682 | Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); | |
1683 | ||
1684 | Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); | |
1685 | break; | |
1686 | ||
1687 | case RF_AIROHA_2230S: // 20060420 Add this | |
1688 | ||
1689 | pltmp[0] = 0X16764A77; // 0x1000 AGC_Ctrl1 //0x16765A77 | |
1690 | pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2 | |
1691 | pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3 | |
1692 | pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version | |
1693 | pWb35Reg->BB0C = 0xFFFd203c; | |
1694 | pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version | |
1695 | pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version | |
1696 | pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version | |
1697 | pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 | |
1698 | pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9 | |
1699 | pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 | |
1700 | pltmp[10] = 0X40000528; //0x40000228 | |
1701 | pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730 | |
1702 | pWb35Reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1 | |
1703 | Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); | |
1704 | ||
1705 | pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl | |
1706 | pWb35Reg->BB30 = 0x00002C54; | |
1707 | pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl | |
1708 | pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769 | |
1709 | pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter | |
1710 | pWb35Reg->BB3C = 0x00000000; | |
1711 | pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter | |
1712 | pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter | |
1713 | pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2 | |
1714 | pWb35Reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2 | |
1715 | pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2 | |
1716 | pWb35Reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1 | |
1717 | pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl | |
1718 | pWb35Reg->BB50 = 0x27106200; | |
1719 | pltmp[9] = 0; // 0x1054 | |
1720 | pWb35Reg->BB54 = 0x00000000; | |
1721 | pltmp[10] = 0x52523232; // 20060419 0x52524242; // 0x1058 IQ_Alpha | |
1722 | pWb35Reg->BB58 = 0x52523232; // 20060419 0x52524242; | |
1723 | pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel | |
1724 | Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); | |
1725 | ||
1726 | Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); | |
1727 | break; | |
1728 | ||
1729 | case RF_AIROHA_7230: | |
1730 | /* | |
1731 | pltmp[0] = 0x16a84a77; // 0x1000 AGC_Ctrl1 | |
1732 | pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2 | |
1733 | pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3 | |
1734 | pltmp[3] = 0xFFFb203a; // 0x100c AGC_Ctrl4 | |
1735 | pWb35Reg->BB0c = 0xFFFb203a; | |
1736 | pltmp[4] = 0x0FBFDCB7; // 0x1010 AGC_Ctrl5 | |
1737 | pltmp[5] = 0x00caa333; // 0x1014 AGC_Ctrl6 | |
1738 | pltmp[6] = 0xf6632112; // 0x1018 AGC_Ctrl7 | |
1739 | pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 | |
1740 | pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9 | |
1741 | pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 | |
1742 | pltmp[10] = 0x40000228; | |
1743 | pltmp[11] = 0x232A9F30;// 0x102c A_ACQ_Ctrl | |
1744 | pWb35Reg->BB2c = 0x232A9F30; | |
1745 | Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); | |
1746 | ||
1747 | pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl | |
1748 | pWb35Reg->BB30 = 0x00002C54; | |
1749 | pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl | |
1750 | pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl | |
1751 | pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter | |
1752 | pWb35Reg->BB3c = 0x00000000; | |
1753 | pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter | |
1754 | pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter | |
1755 | pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter | |
1756 | pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter | |
1757 | pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl | |
1758 | pWb35Reg->BB50 = 0x27106200; | |
1759 | pltmp[9] = 0; // 0x1054 | |
1760 | pWb35Reg->BB54 = 0x00000000; | |
1761 | pltmp[10] = 0x64645252; // 0x1058 IQ_Alpha | |
1762 | pWb35Reg->BB58 = 0x64645252; | |
1763 | pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel | |
1764 | Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); | |
1765 | */ | |
1766 | BBProcessor_AL7230_2400( pHwData ); | |
1767 | ||
1768 | Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); | |
1769 | break; | |
1770 | ||
1771 | case RF_WB_242: | |
1772 | case RF_WB_242_1: // 20060619.5 Add | |
1773 | ||
1774 | pltmp[0] = 0x16A8525D; // 0x1000 AGC_Ctrl1 | |
1775 | pltmp[1] = 0x9AFF9ABA; // 0x1004 AGC_Ctrl2 | |
1776 | pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3 | |
1777 | pltmp[3] = 0xEEE91C32; // 0x100c AGC_Ctrl4 | |
1778 | pWb35Reg->BB0C = 0xEEE91C32; | |
1779 | pltmp[4] = 0x0FACDCC5; // 0x1010 AGC_Ctrl5 | |
1780 | pltmp[5] = 0x000AA344; // 0x1014 AGC_Ctrl6 | |
1781 | pltmp[6] = 0x22222221; // 0x1018 AGC_Ctrl7 | |
1782 | pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 | |
1783 | pltmp[8] = 0x04CC3440; // 20051018 0x03CB3440; // 0x1020 AGC_Ctrl9 20051014 0x03C33440 | |
1784 | pltmp[9] = 0xA9002A79; // 0x1024 AGC_Ctrl10 | |
1785 | pltmp[10] = 0x40000528; // 0x1028 | |
1786 | pltmp[11] = 0x23457F30; // 0x102c A_ACQ_Ctrl | |
1787 | pWb35Reg->BB2C = 0x23457F30; | |
1788 | Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); | |
1789 | ||
1790 | pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl | |
1791 | pWb35Reg->BB30 = 0x00002C54; | |
1792 | pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl | |
1793 | pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl | |
1794 | pltmp[3] = pHwData->BB3c_cal; // 0x103c 11a TX LS filter | |
1795 | pWb35Reg->BB3C = pHwData->BB3c_cal; | |
1796 | pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter | |
1797 | pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter | |
1798 | pltmp[6] = BB48_DEFAULT_WB242_11G; // 0x1048 11b TX RC filter 20060613.2 | |
1799 | pWb35Reg->BB48 = BB48_DEFAULT_WB242_11G; // 20060613.1 20060613.2 | |
1800 | pltmp[7] = BB4C_DEFAULT_WB242_11G; // 0x104c 11b TX RC filter 20060613.2 | |
1801 | pWb35Reg->BB4C = BB4C_DEFAULT_WB242_11G; // 20060613.1 20060613.2 | |
1802 | pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl | |
1803 | pWb35Reg->BB50 = 0x27106208; | |
1804 | pltmp[9] = pHwData->BB54_cal; // 0x1054 | |
1805 | pWb35Reg->BB54 = pHwData->BB54_cal; | |
1806 | pltmp[10] = 0x52523131; // 0x1058 IQ_Alpha | |
1807 | pWb35Reg->BB58 = 0x52523131; | |
1808 | pltmp[11] = 0xAA0AC000; // 20060825 0xAA2AC000; // 0x105c DC_Cancel | |
1809 | Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); | |
1810 | ||
1811 | Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); | |
1812 | break; | |
1813 | } | |
1814 | ||
1815 | // Fill the LNA table | |
1816 | pWb35Reg->LNAValue[0] = (u8)(pWb35Reg->BB0C & 0xff); | |
1817 | pWb35Reg->LNAValue[1] = 0; | |
1818 | pWb35Reg->LNAValue[2] = (u8)((pWb35Reg->BB0C & 0xff00)>>8); | |
1819 | pWb35Reg->LNAValue[3] = 0; | |
1820 | ||
1821 | // Fill SQ3 table | |
1822 | for( i=0; i<MAX_SQ3_FILTER_SIZE; i++ ) | |
1823 | pWb35Reg->SQ3_filter[i] = 0x2f; // half of Bit 0 ~ 6 | |
1824 | } | |
1825 | ||
1826 | void set_tx_power_per_channel_max2829( phw_data_t pHwData, ChanInfo Channel) | |
1827 | { | |
1828 | RFSynthesizer_SetPowerIndex( pHwData, 100 ); // 20060620.1 Modify | |
1829 | } | |
1830 | ||
1831 | void set_tx_power_per_channel_al2230( phw_data_t pHwData, ChanInfo Channel ) | |
1832 | { | |
1833 | u8 index = 100; | |
1834 | ||
1835 | if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) // 20060620.1 Add | |
1836 | index = pHwData->TxVgaFor24[Channel.ChanNo - 1]; | |
1837 | ||
1838 | RFSynthesizer_SetPowerIndex( pHwData, index ); | |
1839 | } | |
1840 | ||
1841 | void set_tx_power_per_channel_al7230( phw_data_t pHwData, ChanInfo Channel) | |
1842 | { | |
1843 | u8 i, index = 100; | |
1844 | ||
1845 | switch ( Channel.band ) | |
1846 | { | |
1847 | case BAND_TYPE_DSSS: | |
1848 | case BAND_TYPE_OFDM_24: | |
1849 | { | |
1850 | if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) | |
1851 | index = pHwData->TxVgaFor24[Channel.ChanNo - 1]; | |
1852 | } | |
1853 | break; | |
1854 | case BAND_TYPE_OFDM_5: | |
1855 | { | |
1856 | for (i =0; i<35; i++) | |
1857 | { | |
1858 | if (Channel.ChanNo == pHwData->TxVgaFor50[i].ChanNo) | |
1859 | { | |
1860 | if (pHwData->TxVgaFor50[i].TxVgaValue != 0xff) | |
1861 | index = pHwData->TxVgaFor50[i].TxVgaValue; | |
1862 | break; | |
1863 | } | |
1864 | } | |
1865 | } | |
1866 | break; | |
1867 | } | |
1868 | RFSynthesizer_SetPowerIndex( pHwData, index ); | |
1869 | } | |
1870 | ||
1871 | void set_tx_power_per_channel_wb242( phw_data_t pHwData, ChanInfo Channel) | |
1872 | { | |
1873 | u8 index = 100; | |
1874 | ||
1875 | switch ( Channel.band ) | |
1876 | { | |
1877 | case BAND_TYPE_DSSS: | |
1878 | case BAND_TYPE_OFDM_24: | |
1879 | { | |
1880 | if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) | |
1881 | index = pHwData->TxVgaFor24[Channel.ChanNo - 1]; | |
1882 | } | |
1883 | break; | |
1884 | case BAND_TYPE_OFDM_5: | |
1885 | break; | |
1886 | } | |
1887 | RFSynthesizer_SetPowerIndex( pHwData, index ); | |
1888 | } | |
1889 | ||
1890 | //============================================================================================================= | |
1891 | // RFSynthesizer_SwitchingChannel -- | |
1892 | // | |
1893 | // Description: | |
1894 | // Swithch the RF channel. | |
1895 | // | |
1896 | // Arguments: | |
1897 | // pHwData - Handle of the USB Device. | |
1898 | // Channel - The channel no. | |
1899 | // | |
1900 | // Return values: | |
1901 | // None. | |
1902 | //============================================================================================================= | |
1903 | void | |
1904 | RFSynthesizer_SwitchingChannel( phw_data_t pHwData, ChanInfo Channel ) | |
1905 | { | |
1906 | PWB35REG pWb35Reg = &pHwData->Wb35Reg; | |
1907 | u32 pltmp[16]; // The 16 is the maximum capability of hardware | |
1908 | u32 count, ltmp; | |
1909 | u8 i, j, number; | |
1910 | u8 ChnlTmp; | |
1911 | ||
1912 | switch( pHwData->phy_type ) | |
1913 | { | |
1914 | case RF_MAXIM_2825: | |
1915 | case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) | |
1916 | ||
1917 | if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13 | |
1918 | { | |
1919 | for( i=0; i<3; i++ ) | |
1920 | pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_channel_data_24[Channel.ChanNo-1][i], 18); | |
1921 | Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); | |
1922 | } | |
1923 | RFSynthesizer_SetPowerIndex( pHwData, 100 ); | |
1924 | break; | |
1925 | ||
1926 | case RF_MAXIM_2827: | |
1927 | ||
1928 | if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13 | |
1929 | { | |
1930 | for( i=0; i<3; i++ ) | |
1931 | pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_channel_data_24[Channel.ChanNo-1][i], 18); | |
1932 | Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); | |
1933 | } | |
1934 | else if( Channel.band == BAND_TYPE_OFDM_5 ) // channel 36 ~ 64 | |
1935 | { | |
1936 | ChnlTmp = (Channel.ChanNo - 36) / 4; | |
1937 | for( i=0; i<3; i++ ) | |
1938 | pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_channel_data_50[ChnlTmp][i], 18); | |
1939 | Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); | |
1940 | } | |
1941 | RFSynthesizer_SetPowerIndex( pHwData, 100 ); | |
1942 | break; | |
1943 | ||
1944 | case RF_MAXIM_2828: | |
1945 | ||
1946 | if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13 | |
1947 | { | |
1948 | for( i=0; i<3; i++ ) | |
1949 | pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_channel_data_24[Channel.ChanNo-1][i], 18); | |
1950 | Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); | |
1951 | } | |
1952 | else if( Channel.band == BAND_TYPE_OFDM_5 ) // channel 36 ~ 64 | |
1953 | { | |
1954 | ChnlTmp = (Channel.ChanNo - 36) / 4; | |
1955 | for ( i = 0; i < 3; i++) | |
1956 | pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_channel_data_50[ChnlTmp][i], 18); | |
1957 | Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); | |
1958 | } | |
1959 | RFSynthesizer_SetPowerIndex( pHwData, 100 ); | |
1960 | break; | |
1961 | ||
1962 | case RF_MAXIM_2829: | |
1963 | ||
1964 | if( Channel.band <= BAND_TYPE_OFDM_24) | |
1965 | { | |
1966 | for( i=0; i<3; i++ ) | |
1967 | pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_channel_data_24[Channel.ChanNo-1][i], 18); | |
1968 | Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); | |
1969 | } | |
1970 | else if( Channel.band == BAND_TYPE_OFDM_5 ) | |
1971 | { | |
1972 | count = sizeof(max2829_channel_data_50) / sizeof(max2829_channel_data_50[0]); | |
1973 | ||
1974 | for( i=0; i<count; i++ ) | |
1975 | { | |
1976 | if( max2829_channel_data_50[i][0] == Channel.ChanNo ) | |
1977 | { | |
1978 | for( j=0; j<3; j++ ) | |
1979 | pltmp[j] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_channel_data_50[i][j+1], 18); | |
1980 | Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); | |
1981 | ||
1982 | if( (max2829_channel_data_50[i][3] & 0x3FFFF) == 0x2A946 ) | |
1983 | { | |
1984 | ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( (5<<18)|0x2A906, 18); | |
1985 | Wb35Reg_Write( pHwData, 0x0864, ltmp ); | |
1986 | } | |
1987 | else // 0x2A9C6 | |
1988 | { | |
1989 | ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( (5<<18)|0x2A986, 18); | |
1990 | Wb35Reg_Write( pHwData, 0x0864, ltmp ); | |
1991 | } | |
1992 | } | |
1993 | } | |
1994 | } | |
1995 | set_tx_power_per_channel_max2829( pHwData, Channel ); | |
1996 | break; | |
1997 | ||
1998 | case RF_AIROHA_2230: | |
1999 | case RF_AIROHA_2230S: // 20060420 Add this | |
2000 | ||
2001 | if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14 | |
2002 | { | |
2003 | for( i=0; i<2; i++ ) | |
2004 | pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_channel_data_24[Channel.ChanNo-1][i], 20); | |
2005 | Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 2, NO_INCREMENT ); | |
2006 | } | |
2007 | set_tx_power_per_channel_al2230( pHwData, Channel ); | |
2008 | break; | |
2009 | ||
2010 | case RF_AIROHA_7230: | |
2011 | ||
2012 | //Start to fill RF parameters, PLL_ON should be pulled low. | |
2013 | //Wb35Reg_Write( pHwData, 0x03dc, 0x00000000 ); | |
2014 | //WBDEBUG(("* PLL_ON low\n")); | |
2015 | ||
2016 | //Channel independent registers | |
2017 | if( Channel.band != pHwData->band) | |
2018 | { | |
2019 | if (Channel.band <= BAND_TYPE_OFDM_24) | |
2020 | { | |
2021 | //Update BB register | |
2022 | BBProcessor_AL7230_2400(pHwData); | |
2023 | ||
2024 | number = sizeof(al7230_rf_data_24)/sizeof(al7230_rf_data_24[0]); | |
2025 | Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number); | |
2026 | } | |
2027 | else | |
2028 | { | |
2029 | //Update BB register | |
2030 | BBProcessor_AL7230_5000(pHwData); | |
2031 | ||
2032 | number = sizeof(al7230_rf_data_50)/sizeof(al7230_rf_data_50[0]); | |
2033 | Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number); | |
2034 | } | |
2035 | ||
2036 | // Write to register. number must less and equal than 16 | |
2037 | Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, number, NO_INCREMENT ); | |
2038 | #ifdef _PE_STATE_DUMP_ | |
2039 | WBDEBUG(("Band changed\n")); | |
2040 | #endif | |
2041 | } | |
2042 | ||
2043 | if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14 | |
2044 | { | |
2045 | for( i=0; i<2; i++ ) | |
2046 | pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_24[Channel.ChanNo-1][i]&0xffffff); | |
2047 | Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 2, NO_INCREMENT ); | |
2048 | } | |
2049 | else if( Channel.band == BAND_TYPE_OFDM_5 ) | |
2050 | { | |
2051 | //Update Reg12 | |
2052 | if ((Channel.ChanNo > 64) && (Channel.ChanNo <= 165)) | |
2053 | { | |
2054 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00143c; | |
2055 | Wb35Reg_Write( pHwData, 0x0864, ltmp ); | |
2056 | } | |
2057 | else //reg12 = 0x00147c at Channel 4920 ~ 5320 | |
2058 | { | |
2059 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00147c; | |
2060 | Wb35Reg_Write( pHwData, 0x0864, ltmp ); | |
2061 | } | |
2062 | ||
2063 | count = sizeof(al7230_channel_data_5) / sizeof(al7230_channel_data_5[0]); | |
2064 | ||
2065 | for (i=0; i<count; i++) | |
2066 | { | |
2067 | if (al7230_channel_data_5[i][0] == Channel.ChanNo) | |
2068 | { | |
2069 | for( j=0; j<3; j++ ) | |
2070 | pltmp[j] = (1 << 31) | (0 << 30) | (24 << 24) | ( al7230_channel_data_5[i][j+1]&0xffffff); | |
2071 | Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); | |
2072 | } | |
2073 | } | |
2074 | } | |
2075 | set_tx_power_per_channel_al7230(pHwData, Channel); | |
2076 | break; | |
2077 | ||
2078 | case RF_WB_242: | |
2079 | case RF_WB_242_1: // 20060619.5 Add | |
2080 | ||
2081 | if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14 | |
2082 | { | |
2083 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( w89rf242_channel_data_24[Channel.ChanNo-1][0], 24); | |
2084 | Wb35Reg_Write( pHwData, 0x864, ltmp ); | |
2085 | } | |
2086 | set_tx_power_per_channel_wb242(pHwData, Channel); | |
2087 | break; | |
2088 | } | |
2089 | ||
2090 | if( Channel.band <= BAND_TYPE_OFDM_24 ) | |
2091 | { | |
2092 | // BB: select 2.4 GHz, bit[12-11]=00 | |
2093 | pWb35Reg->BB50 &= ~(BIT(11)|BIT(12)); | |
2094 | Wb35Reg_Write( pHwData, 0x1050, pWb35Reg->BB50 ); // MODE_Ctrl | |
2095 | // MAC: select 2.4 GHz, bit[5]=0 | |
2096 | pWb35Reg->M78_ERPInformation &= ~BIT(5); | |
2097 | Wb35Reg_Write( pHwData, 0x0878, pWb35Reg->M78_ERPInformation ); | |
2098 | // enable 11b Baseband | |
2099 | pWb35Reg->BB30 &= ~BIT(31); | |
2100 | Wb35Reg_Write( pHwData, 0x1030, pWb35Reg->BB30 ); | |
2101 | } | |
2102 | else if( (Channel.band == BAND_TYPE_OFDM_5) ) | |
2103 | { | |
2104 | // BB: select 5 GHz | |
2105 | pWb35Reg->BB50 &= ~(BIT(11)|BIT(12)); | |
2106 | if (Channel.ChanNo <=64 ) | |
2107 | pWb35Reg->BB50 |= BIT(12); // 10-5.25GHz | |
2108 | else if ((Channel.ChanNo >= 100) && (Channel.ChanNo <= 124)) | |
2109 | pWb35Reg->BB50 |= BIT(11); // 01-5.48GHz | |
2110 | else if ((Channel.ChanNo >=128) && (Channel.ChanNo <= 161)) | |
2111 | pWb35Reg->BB50 |= (BIT(12)|BIT(11)); // 11-5.775GHz | |
2112 | else //Chan 184 ~ 196 will use bit[12-11] = 10 in version sh-src-1.2.25 | |
2113 | pWb35Reg->BB50 |= BIT(12); | |
2114 | Wb35Reg_Write( pHwData, 0x1050, pWb35Reg->BB50 ); // MODE_Ctrl | |
2115 | ||
2116 | //(1) M78 should alway use 2.4G setting when using RF_AIROHA_7230 | |
2117 | //(2) BB30 has been updated previously. | |
2118 | if (pHwData->phy_type != RF_AIROHA_7230) | |
2119 | { | |
2120 | // MAC: select 5 GHz, bit[5]=1 | |
2121 | pWb35Reg->M78_ERPInformation |= BIT(5); | |
2122 | Wb35Reg_Write( pHwData, 0x0878, pWb35Reg->M78_ERPInformation ); | |
2123 | ||
2124 | // disable 11b Baseband | |
2125 | pWb35Reg->BB30 |= BIT(31); | |
2126 | Wb35Reg_Write( pHwData, 0x1030, pWb35Reg->BB30 ); | |
2127 | } | |
2128 | } | |
2129 | } | |
2130 | ||
2131 | //Set the tx power directly from DUT GUI, not from the EEPROM. Return the current setting | |
2132 | u8 RFSynthesizer_SetPowerIndex( phw_data_t pHwData, u8 PowerIndex ) | |
2133 | { | |
2134 | u32 Band = pHwData->band; | |
2135 | u8 index=0; | |
2136 | ||
2137 | if( pHwData->power_index == PowerIndex ) // 20060620.1 Add | |
2138 | return PowerIndex; | |
2139 | ||
2140 | if (RF_MAXIM_2825 == pHwData->phy_type) | |
2141 | { | |
2142 | // Channel 1 - 13 | |
2143 | index = RFSynthesizer_SetMaxim2825Power( pHwData, PowerIndex ); | |
2144 | } | |
2145 | else if (RF_MAXIM_2827 == pHwData->phy_type) | |
2146 | { | |
2147 | if( Band <= BAND_TYPE_OFDM_24 ) // Channel 1 - 13 | |
2148 | index = RFSynthesizer_SetMaxim2827_24Power( pHwData, PowerIndex ); | |
2149 | else// if( Band == BAND_TYPE_OFDM_5 ) // Channel 36 - 64 | |
2150 | index = RFSynthesizer_SetMaxim2827_50Power( pHwData, PowerIndex ); | |
2151 | } | |
2152 | else if (RF_MAXIM_2828 == pHwData->phy_type) | |
2153 | { | |
2154 | if( Band <= BAND_TYPE_OFDM_24 ) // Channel 1 - 13 | |
2155 | index = RFSynthesizer_SetMaxim2828_24Power( pHwData, PowerIndex ); | |
2156 | else// if( Band == BAND_TYPE_OFDM_5 ) // Channel 36 - 64 | |
2157 | index = RFSynthesizer_SetMaxim2828_50Power( pHwData, PowerIndex ); | |
2158 | } | |
2159 | else if( RF_AIROHA_2230 == pHwData->phy_type ) | |
2160 | { | |
2161 | //Power index: 0 ~ 63 // Channel 1 - 14 | |
2162 | index = RFSynthesizer_SetAiroha2230Power( pHwData, PowerIndex ); | |
2163 | index = (u8)al2230_txvga_data[index][1]; | |
2164 | } | |
2165 | else if( RF_AIROHA_2230S == pHwData->phy_type ) // 20060420 Add this | |
2166 | { | |
2167 | //Power index: 0 ~ 63 // Channel 1 - 14 | |
2168 | index = RFSynthesizer_SetAiroha2230Power( pHwData, PowerIndex ); | |
2169 | index = (u8)al2230_txvga_data[index][1]; | |
2170 | } | |
2171 | else if( RF_AIROHA_7230 == pHwData->phy_type ) | |
2172 | { | |
2173 | //Power index: 0 ~ 63 | |
2174 | index = RFSynthesizer_SetAiroha7230Power( pHwData, PowerIndex ); | |
2175 | index = (u8)al7230_txvga_data[index][1]; | |
2176 | } | |
2177 | else if( (RF_WB_242 == pHwData->phy_type) || | |
2178 | (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add | |
2179 | { | |
2180 | //Power index: 0 ~ 19 for original. New range is 0 ~ 33 | |
2181 | index = RFSynthesizer_SetWinbond242Power( pHwData, PowerIndex ); | |
2182 | index = (u8)w89rf242_txvga_data[index][1]; | |
2183 | } | |
2184 | ||
2185 | pHwData->power_index = index; // Backup current | |
2186 | return index; | |
2187 | } | |
2188 | ||
2189 | //-- Sub function | |
2190 | u8 RFSynthesizer_SetMaxim2828_24Power( phw_data_t pHwData, u8 index ) | |
2191 | { | |
2192 | u32 PowerData; | |
2193 | if( index > 1 ) index = 1; | |
2194 | PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_power_data_24[index], 18); | |
2195 | Wb35Reg_Write( pHwData, 0x0864, PowerData ); | |
2196 | return index; | |
2197 | } | |
2198 | //-- | |
2199 | u8 RFSynthesizer_SetMaxim2828_50Power( phw_data_t pHwData, u8 index ) | |
2200 | { | |
2201 | u32 PowerData; | |
2202 | if( index > 1 ) index = 1; | |
2203 | PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_power_data_50[index], 18); | |
2204 | Wb35Reg_Write( pHwData, 0x0864, PowerData ); | |
2205 | return index; | |
2206 | } | |
2207 | //-- | |
2208 | u8 RFSynthesizer_SetMaxim2827_24Power( phw_data_t pHwData, u8 index ) | |
2209 | { | |
2210 | u32 PowerData; | |
2211 | if( index > 1 ) index = 1; | |
2212 | PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_power_data_24[index], 18); | |
2213 | Wb35Reg_Write( pHwData, 0x0864, PowerData ); | |
2214 | return index; | |
2215 | } | |
2216 | //-- | |
2217 | u8 RFSynthesizer_SetMaxim2827_50Power( phw_data_t pHwData, u8 index ) | |
2218 | { | |
2219 | u32 PowerData; | |
2220 | if( index > 1 ) index = 1; | |
2221 | PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_power_data_50[index], 18); | |
2222 | Wb35Reg_Write( pHwData, 0x0864, PowerData ); | |
2223 | return index; | |
2224 | } | |
2225 | //-- | |
2226 | u8 RFSynthesizer_SetMaxim2825Power( phw_data_t pHwData, u8 index ) | |
2227 | { | |
2228 | u32 PowerData; | |
2229 | if( index > 1 ) index = 1; | |
2230 | PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_power_data_24[index], 18); | |
2231 | Wb35Reg_Write( pHwData, 0x0864, PowerData ); | |
2232 | return index; | |
2233 | } | |
2234 | //-- | |
2235 | u8 RFSynthesizer_SetAiroha2230Power( phw_data_t pHwData, u8 index ) | |
2236 | { | |
2237 | u32 PowerData; | |
2238 | u8 i,count; | |
2239 | ||
2240 | count = sizeof(al2230_txvga_data) / sizeof(al2230_txvga_data[0]); | |
2241 | for (i=0; i<count; i++) | |
2242 | { | |
2243 | if (al2230_txvga_data[i][1] >= index) | |
2244 | break; | |
2245 | } | |
2246 | if (i == count) | |
2247 | i--; | |
2248 | ||
2249 | PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_txvga_data[i][0], 20); | |
2250 | Wb35Reg_Write( pHwData, 0x0864, PowerData ); | |
2251 | return i; | |
2252 | } | |
2253 | //-- | |
2254 | u8 RFSynthesizer_SetAiroha7230Power( phw_data_t pHwData, u8 index ) | |
2255 | { | |
2256 | u32 PowerData; | |
2257 | u8 i,count; | |
2258 | ||
2259 | //PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( airoha_power_data_24[index], 20); | |
2260 | count = sizeof(al7230_txvga_data) / sizeof(al7230_txvga_data[0]); | |
2261 | for (i=0; i<count; i++) | |
2262 | { | |
2263 | if (al7230_txvga_data[i][1] >= index) | |
2264 | break; | |
2265 | } | |
2266 | if (i == count) | |
2267 | i--; | |
2268 | PowerData = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_txvga_data[i][0]&0xffffff); | |
2269 | Wb35Reg_Write( pHwData, 0x0864, PowerData ); | |
2270 | return i; | |
2271 | } | |
2272 | ||
2273 | u8 RFSynthesizer_SetWinbond242Power( phw_data_t pHwData, u8 index ) | |
2274 | { | |
2275 | u32 PowerData; | |
2276 | u8 i,count; | |
2277 | ||
2278 | count = sizeof(w89rf242_txvga_data) / sizeof(w89rf242_txvga_data[0]); | |
2279 | for (i=0; i<count; i++) | |
2280 | { | |
2281 | if (w89rf242_txvga_data[i][1] >= index) | |
2282 | break; | |
2283 | } | |
2284 | if (i == count) | |
2285 | i--; | |
2286 | ||
2287 | // Set TxVga into RF | |
2288 | PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( w89rf242_txvga_data[i][0], 24); | |
2289 | Wb35Reg_Write( pHwData, 0x0864, PowerData ); | |
2290 | ||
2291 | // Update BB48 BB4C BB58 for high precision txvga | |
2292 | Wb35Reg_Write( pHwData, 0x1048, w89rf242_txvga_data[i][2] ); | |
2293 | Wb35Reg_Write( pHwData, 0x104c, w89rf242_txvga_data[i][3] ); | |
2294 | Wb35Reg_Write( pHwData, 0x1058, w89rf242_txvga_data[i][4] ); | |
2295 | ||
2296 | // Rf vga 0 ~ 3 for temperature compensate. It will affect the scan Bss. | |
2297 | // The i value equals to 8 or 7 usually. So It's not necessary to setup this RF register. | |
2298 | // if( i <= 3 ) | |
2299 | // PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( 0x000024, 24 ); | |
2300 | // else | |
2301 | // PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( 0x001824, 24 ); | |
2302 | // Wb35Reg_Write( pHwData, 0x0864, PowerData ); | |
2303 | return i; | |
2304 | } | |
2305 | ||
2306 | //=========================================================================================================== | |
2307 | // Dxx_initial -- | |
2308 | // Mxx_initial -- | |
2309 | // | |
2310 | // Routine Description: | |
2311 | // Initial the hardware setting and module variable | |
2312 | // | |
2313 | //=========================================================================================================== | |
2314 | void Dxx_initial( phw_data_t pHwData ) | |
2315 | { | |
2316 | PWB35REG pWb35Reg = &pHwData->Wb35Reg; | |
2317 | ||
2318 | // Old IC:Single mode only. | |
2319 | // New IC: operation decide by Software set bit[4]. 1:multiple 0: single | |
2320 | pWb35Reg->D00_DmaControl = 0xc0000004; //Txon, Rxon, multiple Rx for new 4k DMA | |
2321 | //Txon, Rxon, single Rx for old 8k ASIC | |
2322 | if( !HAL_USB_MODE_BURST( pHwData ) ) | |
2323 | pWb35Reg->D00_DmaControl = 0xc0000000;//Txon, Rxon, single Rx for new 4k DMA | |
2324 | ||
2325 | Wb35Reg_WriteSync( pHwData, 0x0400, pWb35Reg->D00_DmaControl ); | |
2326 | } | |
2327 | ||
2328 | void Mxx_initial( phw_data_t pHwData ) | |
2329 | { | |
2330 | PWB35REG pWb35Reg = &pHwData->Wb35Reg; | |
2331 | u32 tmp; | |
2332 | u32 pltmp[11]; | |
2333 | u16 i; | |
2334 | ||
2335 | ||
2336 | //====================================================== | |
2337 | // Initial Mxx register | |
2338 | //====================================================== | |
2339 | ||
2340 | // M00 bit set | |
2341 | #ifdef _IBSS_BEACON_SEQ_STICK_ | |
2342 | pWb35Reg->M00_MacControl = 0; // Solve beacon sequence number stop by software | |
2343 | #else | |
2344 | pWb35Reg->M00_MacControl = 0x80000000; // Solve beacon sequence number stop by hardware | |
2345 | #endif | |
2346 | ||
2347 | // M24 disable enter power save, BB RxOn and enable NAV attack | |
2348 | pWb35Reg->M24_MacControl = 0x08040042; | |
2349 | pltmp[0] = pWb35Reg->M24_MacControl; | |
2350 | ||
2351 | pltmp[1] = 0; // Skip M28, because no initialize value is required. | |
2352 | ||
2353 | // M2C CWmin and CWmax setting | |
2354 | pHwData->cwmin = DEFAULT_CWMIN; | |
2355 | pHwData->cwmax = DEFAULT_CWMAX; | |
2356 | pWb35Reg->M2C_MacControl = DEFAULT_CWMIN << 10; | |
2357 | pWb35Reg->M2C_MacControl |= DEFAULT_CWMAX; | |
2358 | pltmp[2] = pWb35Reg->M2C_MacControl; | |
2359 | ||
2360 | // M30 BSSID | |
2361 | pltmp[3] = *(PULONG)pHwData->bssid; | |
2362 | ||
2363 | // M34 | |
2364 | pHwData->AID = DEFAULT_AID; | |
2365 | tmp = *(PUSHORT)(pHwData->bssid+4); | |
2366 | tmp |= DEFAULT_AID << 16; | |
2367 | pltmp[4] = tmp; | |
2368 | ||
2369 | // M38 | |
2370 | pWb35Reg->M38_MacControl = (DEFAULT_RATE_RETRY_LIMIT<<8) | (DEFAULT_LONG_RETRY_LIMIT << 4) | DEFAULT_SHORT_RETRY_LIMIT; | |
2371 | pltmp[5] = pWb35Reg->M38_MacControl; | |
2372 | ||
2373 | // M3C | |
2374 | tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST ; | |
2375 | pWb35Reg->M3C_MacControl = tmp; | |
2376 | pltmp[6] = tmp; | |
2377 | ||
2378 | // M40 | |
2379 | pHwData->slot_time_select = DEFAULT_SLOT_TIME; | |
2380 | tmp = (DEFAULT_ATIMWD << 16) | DEFAULT_SLOT_TIME; | |
2381 | pWb35Reg->M40_MacControl = tmp; | |
2382 | pltmp[7] = tmp; | |
2383 | ||
2384 | // M44 | |
2385 | tmp = DEFAULT_MAX_TX_MSDU_LIFE_TIME << 10; // *1024 | |
2386 | pWb35Reg->M44_MacControl = tmp; | |
2387 | pltmp[8] = tmp; | |
2388 | ||
2389 | // M48 | |
2390 | pHwData->BeaconPeriod = DEFAULT_BEACON_INTERVAL; | |
2391 | pHwData->ProbeDelay = DEFAULT_PROBE_DELAY_TIME; | |
2392 | tmp = (DEFAULT_BEACON_INTERVAL << 16) | DEFAULT_PROBE_DELAY_TIME; | |
2393 | pWb35Reg->M48_MacControl = tmp; | |
2394 | pltmp[9] = tmp; | |
2395 | ||
2396 | //M4C | |
2397 | pWb35Reg->M4C_MacStatus = (DEFAULT_PROTOCOL_VERSION << 30) | (DEFAULT_MAC_POWER_STATE << 28) | (DEFAULT_DTIM_ALERT_TIME << 24); | |
2398 | pltmp[10] = pWb35Reg->M4C_MacStatus; | |
2399 | ||
2400 | // Burst write | |
2401 | //Wb35Reg_BurstWrite( pHwData, 0x0824, pltmp, 11, AUTO_INCREMENT ); | |
2402 | for( i=0; i<11; i++ ) | |
2403 | Wb35Reg_WriteSync( pHwData, 0x0824 + i*4, pltmp[i] ); | |
2404 | ||
2405 | // M60 | |
2406 | Wb35Reg_WriteSync( pHwData, 0x0860, 0x12481248 ); | |
2407 | pWb35Reg->M60_MacControl = 0x12481248; | |
2408 | ||
2409 | // M68 | |
2410 | Wb35Reg_WriteSync( pHwData, 0x0868, 0x00050900 ); // 20051018 0x000F0F00 ); // 940930 0x00131300 | |
2411 | pWb35Reg->M68_MacControl = 0x00050900; | |
2412 | ||
2413 | // M98 | |
2414 | Wb35Reg_WriteSync( pHwData, 0x0898, 0xffff8888 ); | |
2415 | pWb35Reg->M98_MacControl = 0xffff8888; | |
2416 | } | |
2417 | ||
2418 | ||
2419 | void Uxx_power_off_procedure( phw_data_t pHwData ) | |
2420 | { | |
2421 | // SW, PMU reset and turn off clock | |
2422 | Wb35Reg_WriteSync( pHwData, 0x03b0, 3 ); | |
2423 | Wb35Reg_WriteSync( pHwData, 0x03f0, 0xf9 ); | |
2424 | } | |
2425 | ||
2426 | //Decide the TxVga of every channel | |
2427 | void GetTxVgaFromEEPROM( phw_data_t pHwData ) | |
2428 | { | |
2429 | u32 i, j, ltmp; | |
2430 | u16 Value[MAX_TXVGA_EEPROM]; | |
2431 | PUCHAR pctmp; | |
2432 | u8 ctmp=0; | |
2433 | ||
2434 | // Get the entire TxVga setting in EEPROM | |
2435 | for( i=0; i<MAX_TXVGA_EEPROM; i++ ) | |
2436 | { | |
2437 | Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08100000 + 0x00010000*i ); | |
2438 | Wb35Reg_ReadSync( pHwData, 0x03b4, <mp ); | |
2439 | Value[i] = (u16)( ltmp & 0xffff ); // Get 16 bit available | |
2440 | Value[i] = cpu_to_le16( Value[i] ); // [7:0]2412 [7:0]2417 .... | |
2441 | } | |
2442 | ||
2443 | // Adjust the filed which fills with reserved value. | |
2444 | pctmp = (PUCHAR)Value; | |
2445 | for( i=0; i<(MAX_TXVGA_EEPROM*2); i++ ) | |
2446 | { | |
2447 | if( pctmp[i] != 0xff ) | |
2448 | ctmp = pctmp[i]; | |
2449 | else | |
2450 | pctmp[i] = ctmp; | |
2451 | } | |
2452 | ||
2453 | // Adjust WB_242 to WB_242_1 TxVga scale | |
2454 | if( pHwData->phy_type == RF_WB_242 ) | |
2455 | { | |
2456 | for( i=0; i<4; i++ ) // Only 2412 2437 2462 2484 case must be modified | |
2457 | { | |
2458 | for( j=0; j<(sizeof(w89rf242_txvga_old_mapping)/sizeof(w89rf242_txvga_old_mapping[0])); j++ ) | |
2459 | { | |
2460 | if( pctmp[i] < (u8)w89rf242_txvga_old_mapping[j][1] ) | |
2461 | { | |
2462 | pctmp[i] = (u8)w89rf242_txvga_old_mapping[j][0]; | |
2463 | break; | |
2464 | } | |
2465 | } | |
2466 | ||
2467 | if( j == (sizeof(w89rf242_txvga_old_mapping)/sizeof(w89rf242_txvga_old_mapping[0])) ) | |
2468 | pctmp[i] = (u8)w89rf242_txvga_old_mapping[j-1][0]; | |
2469 | } | |
2470 | } | |
2471 | ||
2472 | // 20060621 Add | |
2473 | memcpy( pHwData->TxVgaSettingInEEPROM, pctmp, MAX_TXVGA_EEPROM*2 ); //MAX_TXVGA_EEPROM is u16 count | |
2474 | EEPROMTxVgaAdjust( pHwData ); | |
2475 | } | |
2476 | ||
2477 | // This function will affect the TxVga parameter in HAL. If hal_set_current_channel | |
2478 | // or RFSynthesizer_SetPowerIndex be called, new TxVga will take effect. | |
2479 | // TxVgaSettingInEEPROM of sHwData is an u8 array point to EEPROM contain for IS89C35 | |
2480 | // This function will use default TxVgaSettingInEEPROM data to calculate new TxVga. | |
2481 | void EEPROMTxVgaAdjust( phw_data_t pHwData ) // 20060619.5 Add | |
2482 | { | |
2483 | PUCHAR pTxVga = pHwData->TxVgaSettingInEEPROM; | |
2484 | s16 i, stmp; | |
2485 | ||
2486 | //-- 2.4G -- 20060704.2 Request from Tiger | |
2487 | //channel 1 ~ 5 | |
2488 | stmp = pTxVga[1] - pTxVga[0]; | |
2489 | for( i=0; i<5; i++ ) | |
2490 | pHwData->TxVgaFor24[i] = pTxVga[0] + stmp*i/4; | |
2491 | //channel 6 ~ 10 | |
2492 | stmp = pTxVga[2] - pTxVga[1]; | |
2493 | for( i=5; i<10; i++ ) | |
2494 | pHwData->TxVgaFor24[i] = pTxVga[1] + stmp*(i-5)/4; | |
2495 | //channel 11 ~ 13 | |
2496 | stmp = pTxVga[3] - pTxVga[2]; | |
2497 | for( i=10; i<13; i++ ) | |
2498 | pHwData->TxVgaFor24[i] = pTxVga[2] + stmp*(i-10)/2; | |
2499 | //channel 14 | |
2500 | pHwData->TxVgaFor24[13] = pTxVga[3]; | |
2501 | ||
2502 | //-- 5G -- | |
2503 | if( pHwData->phy_type == RF_AIROHA_7230 ) | |
2504 | { | |
2505 | //channel 184 | |
2506 | pHwData->TxVgaFor50[0].ChanNo = 184; | |
2507 | pHwData->TxVgaFor50[0].TxVgaValue = pTxVga[4]; | |
2508 | //channel 196 | |
2509 | pHwData->TxVgaFor50[3].ChanNo = 196; | |
2510 | pHwData->TxVgaFor50[3].TxVgaValue = pTxVga[5]; | |
2511 | //interpolate | |
2512 | pHwData->TxVgaFor50[1].ChanNo = 188; | |
2513 | pHwData->TxVgaFor50[2].ChanNo = 192; | |
2514 | stmp = pTxVga[5] - pTxVga[4]; | |
2515 | pHwData->TxVgaFor50[2].TxVgaValue = pTxVga[5] - stmp/3; | |
2516 | pHwData->TxVgaFor50[1].TxVgaValue = pTxVga[5] - stmp*2/3; | |
2517 | ||
2518 | //channel 16 | |
2519 | pHwData->TxVgaFor50[6].ChanNo = 16; | |
2520 | pHwData->TxVgaFor50[6].TxVgaValue = pTxVga[6]; | |
2521 | pHwData->TxVgaFor50[4].ChanNo = 8; | |
2522 | pHwData->TxVgaFor50[4].TxVgaValue = pTxVga[6]; | |
2523 | pHwData->TxVgaFor50[5].ChanNo = 12; | |
2524 | pHwData->TxVgaFor50[5].TxVgaValue = pTxVga[6]; | |
2525 | ||
2526 | //channel 36 | |
2527 | pHwData->TxVgaFor50[8].ChanNo = 36; | |
2528 | pHwData->TxVgaFor50[8].TxVgaValue = pTxVga[7]; | |
2529 | pHwData->TxVgaFor50[7].ChanNo = 34; | |
2530 | pHwData->TxVgaFor50[7].TxVgaValue = pTxVga[7]; | |
2531 | pHwData->TxVgaFor50[9].ChanNo = 38; | |
2532 | pHwData->TxVgaFor50[9].TxVgaValue = pTxVga[7]; | |
2533 | ||
2534 | //channel 40 | |
2535 | pHwData->TxVgaFor50[10].ChanNo = 40; | |
2536 | pHwData->TxVgaFor50[10].TxVgaValue = pTxVga[8]; | |
2537 | //channel 48 | |
2538 | pHwData->TxVgaFor50[14].ChanNo = 48; | |
2539 | pHwData->TxVgaFor50[14].TxVgaValue = pTxVga[9]; | |
2540 | //interpolate | |
2541 | pHwData->TxVgaFor50[11].ChanNo = 42; | |
2542 | pHwData->TxVgaFor50[12].ChanNo = 44; | |
2543 | pHwData->TxVgaFor50[13].ChanNo = 46; | |
2544 | stmp = pTxVga[9] - pTxVga[8]; | |
2545 | pHwData->TxVgaFor50[13].TxVgaValue = pTxVga[9] - stmp/4; | |
2546 | pHwData->TxVgaFor50[12].TxVgaValue = pTxVga[9] - stmp*2/4; | |
2547 | pHwData->TxVgaFor50[11].TxVgaValue = pTxVga[9] - stmp*3/4; | |
2548 | ||
2549 | //channel 52 | |
2550 | pHwData->TxVgaFor50[15].ChanNo = 52; | |
2551 | pHwData->TxVgaFor50[15].TxVgaValue = pTxVga[10]; | |
2552 | //channel 64 | |
2553 | pHwData->TxVgaFor50[18].ChanNo = 64; | |
2554 | pHwData->TxVgaFor50[18].TxVgaValue = pTxVga[11]; | |
2555 | //interpolate | |
2556 | pHwData->TxVgaFor50[16].ChanNo = 56; | |
2557 | pHwData->TxVgaFor50[17].ChanNo = 60; | |
2558 | stmp = pTxVga[11] - pTxVga[10]; | |
2559 | pHwData->TxVgaFor50[17].TxVgaValue = pTxVga[11] - stmp/3; | |
2560 | pHwData->TxVgaFor50[16].TxVgaValue = pTxVga[11] - stmp*2/3; | |
2561 | ||
2562 | //channel 100 | |
2563 | pHwData->TxVgaFor50[19].ChanNo = 100; | |
2564 | pHwData->TxVgaFor50[19].TxVgaValue = pTxVga[12]; | |
2565 | //channel 112 | |
2566 | pHwData->TxVgaFor50[22].ChanNo = 112; | |
2567 | pHwData->TxVgaFor50[22].TxVgaValue = pTxVga[13]; | |
2568 | //interpolate | |
2569 | pHwData->TxVgaFor50[20].ChanNo = 104; | |
2570 | pHwData->TxVgaFor50[21].ChanNo = 108; | |
2571 | stmp = pTxVga[13] - pTxVga[12]; | |
2572 | pHwData->TxVgaFor50[21].TxVgaValue = pTxVga[13] - stmp/3; | |
2573 | pHwData->TxVgaFor50[20].TxVgaValue = pTxVga[13] - stmp*2/3; | |
2574 | ||
2575 | //channel 128 | |
2576 | pHwData->TxVgaFor50[26].ChanNo = 128; | |
2577 | pHwData->TxVgaFor50[26].TxVgaValue = pTxVga[14]; | |
2578 | //interpolate | |
2579 | pHwData->TxVgaFor50[23].ChanNo = 116; | |
2580 | pHwData->TxVgaFor50[24].ChanNo = 120; | |
2581 | pHwData->TxVgaFor50[25].ChanNo = 124; | |
2582 | stmp = pTxVga[14] - pTxVga[13]; | |
2583 | pHwData->TxVgaFor50[25].TxVgaValue = pTxVga[14] - stmp/4; | |
2584 | pHwData->TxVgaFor50[24].TxVgaValue = pTxVga[14] - stmp*2/4; | |
2585 | pHwData->TxVgaFor50[23].TxVgaValue = pTxVga[14] - stmp*3/4; | |
2586 | ||
2587 | //channel 140 | |
2588 | pHwData->TxVgaFor50[29].ChanNo = 140; | |
2589 | pHwData->TxVgaFor50[29].TxVgaValue = pTxVga[15]; | |
2590 | //interpolate | |
2591 | pHwData->TxVgaFor50[27].ChanNo = 132; | |
2592 | pHwData->TxVgaFor50[28].ChanNo = 136; | |
2593 | stmp = pTxVga[15] - pTxVga[14]; | |
2594 | pHwData->TxVgaFor50[28].TxVgaValue = pTxVga[15] - stmp/3; | |
2595 | pHwData->TxVgaFor50[27].TxVgaValue = pTxVga[15] - stmp*2/3; | |
2596 | ||
2597 | //channel 149 | |
2598 | pHwData->TxVgaFor50[30].ChanNo = 149; | |
2599 | pHwData->TxVgaFor50[30].TxVgaValue = pTxVga[16]; | |
2600 | //channel 165 | |
2601 | pHwData->TxVgaFor50[34].ChanNo = 165; | |
2602 | pHwData->TxVgaFor50[34].TxVgaValue = pTxVga[17]; | |
2603 | //interpolate | |
2604 | pHwData->TxVgaFor50[31].ChanNo = 153; | |
2605 | pHwData->TxVgaFor50[32].ChanNo = 157; | |
2606 | pHwData->TxVgaFor50[33].ChanNo = 161; | |
2607 | stmp = pTxVga[17] - pTxVga[16]; | |
2608 | pHwData->TxVgaFor50[33].TxVgaValue = pTxVga[17] - stmp/4; | |
2609 | pHwData->TxVgaFor50[32].TxVgaValue = pTxVga[17] - stmp*2/4; | |
2610 | pHwData->TxVgaFor50[31].TxVgaValue = pTxVga[17] - stmp*3/4; | |
2611 | } | |
2612 | ||
2613 | #ifdef _PE_STATE_DUMP_ | |
2614 | WBDEBUG((" TxVgaFor24 : \n")); | |
2615 | DataDmp((u8 *)pHwData->TxVgaFor24, 14 ,0); | |
2616 | WBDEBUG((" TxVgaFor50 : \n")); | |
2617 | DataDmp((u8 *)pHwData->TxVgaFor50, 70 ,0); | |
2618 | #endif | |
2619 | } | |
2620 | ||
2621 | void BBProcessor_RateChanging( phw_data_t pHwData, u8 rate ) // 20060613.1 | |
2622 | { | |
2623 | PWB35REG pWb35Reg = &pHwData->Wb35Reg; | |
2624 | unsigned char Is11bRate; | |
2625 | ||
2626 | Is11bRate = (rate % 6) ? 1 : 0; | |
2627 | switch( pHwData->phy_type ) | |
2628 | { | |
2629 | case RF_AIROHA_2230: | |
2630 | case RF_AIROHA_2230S: // 20060420 Add this | |
2631 | if( Is11bRate ) | |
2632 | { | |
2633 | if( (pWb35Reg->BB48 != BB48_DEFAULT_AL2230_11B) && | |
2634 | (pWb35Reg->BB4C != BB4C_DEFAULT_AL2230_11B) ) | |
2635 | { | |
2636 | Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11B ); | |
2637 | Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11B ); | |
2638 | } | |
2639 | } | |
2640 | else | |
2641 | { | |
2642 | if( (pWb35Reg->BB48 != BB48_DEFAULT_AL2230_11G) && | |
2643 | (pWb35Reg->BB4C != BB4C_DEFAULT_AL2230_11G) ) | |
2644 | { | |
2645 | Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11G ); | |
2646 | Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11G ); | |
2647 | } | |
2648 | } | |
2649 | break; | |
2650 | ||
2651 | case RF_WB_242: // 20060623 The fix only for old TxVGA setting | |
2652 | if( Is11bRate ) | |
2653 | { | |
2654 | if( (pWb35Reg->BB48 != BB48_DEFAULT_WB242_11B) && | |
2655 | (pWb35Reg->BB4C != BB4C_DEFAULT_WB242_11B) ) | |
2656 | { | |
2657 | pWb35Reg->BB48 = BB48_DEFAULT_WB242_11B; | |
2658 | pWb35Reg->BB4C = BB4C_DEFAULT_WB242_11B; | |
2659 | Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11B ); | |
2660 | Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11B ); | |
2661 | } | |
2662 | } | |
2663 | else | |
2664 | { | |
2665 | if( (pWb35Reg->BB48 != BB48_DEFAULT_WB242_11G) && | |
2666 | (pWb35Reg->BB4C != BB4C_DEFAULT_WB242_11G) ) | |
2667 | { | |
2668 | pWb35Reg->BB48 = BB48_DEFAULT_WB242_11G; | |
2669 | pWb35Reg->BB4C = BB4C_DEFAULT_WB242_11G; | |
2670 | Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11G ); | |
2671 | Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11G ); | |
2672 | } | |
2673 | } | |
2674 | break; | |
2675 | } | |
2676 | } | |
2677 | ||
2678 | ||
2679 | ||
2680 | ||
2681 | ||
2682 | ||
2683 |