projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 5449c685 FB |
1 | /* |
| 2 | * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. | |
| 3 | * All rights reserved. | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License as published by | |
| 7 | * the Free Software Foundation; either version 2 of the License, or | |
| 8 | * (at your option) any later version. | |
| 9 | * | |
| 10 | * This program is distributed in the hope that it will be useful, | |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | * GNU General Public License for more details. | |
| 14 | * | |
| 15 | * You should have received a copy of the GNU General Public License along | |
| 16 | * with this program; if not, write to the Free Software Foundation, Inc., | |
| 17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 | * | |
| 19 | * | |
| 20 | * File: rf.c | |
| 21 | * | |
| 22 | * Purpose: rf function code | |
| 23 | * | |
| 24 | * Author: Jerry Chen | |
| 25 | * | |
| 26 | * Date: Feb. 19, 2004 | |
| 27 | * | |
| 28 | * Functions: | |
| 623b2b39 | 29 | * IFRFbWriteEmbedded - Embedded write RF register via MAC |
| 5449c685 FB |
30 | * |
| 31 | * Revision History: | |
| 0a5ea1e3 MP |
32 | * RobertYu 2005 |
| 33 | * chester 2008 | |
| 5449c685 FB |
34 | * |
| 35 | */ | |
| 612822f5 | 36 | |
| 5449c685 | 37 | #include "mac.h" |
| 5449c685 | 38 | #include "srom.h" |
| 5449c685 | 39 | #include "rf.h" |
| 5449c685 | 40 | #include "baseband.h" |
| 5449c685 | 41 | |
| 5449c685 FB |
42 | #define BY_AL2230_REG_LEN 23 //24bit |
| 43 | #define CB_AL2230_INIT_SEQ 15 | |
| 44 | #define SWITCH_CHANNEL_DELAY_AL2230 200 //us | |
| 45 | #define AL2230_PWR_IDX_LEN 64 | |
| 46 | ||
| 5449c685 FB |
47 | #define BY_AL7230_REG_LEN 23 //24bit |
| 48 | #define CB_AL7230_INIT_SEQ 16 | |
| 49 | #define SWITCH_CHANNEL_DELAY_AL7230 200 //us | |
| 50 | #define AL7230_PWR_IDX_LEN 64 | |
| 5449c685 | 51 | |
| 5da5804b | 52 | static const unsigned long dwAL2230InitTable[CB_AL2230_INIT_SEQ] = { |
| 3bd1996e JP |
53 | 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // |
| 54 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // | |
| 55 | 0x01A00200+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // | |
| 56 | 0x00FFF300+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // | |
| 57 | 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // | |
| 58 | 0x0F4DC500+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // | |
| 59 | 0x0805B600+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // | |
| 60 | 0x0146C700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // | |
| 61 | 0x00068800+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // | |
| 62 | 0x0403B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // | |
| 63 | 0x00DBBA00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // | |
| 64 | 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // | |
| 65 | 0x0BDFFC00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 66 | 0x00000D00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 67 | 0x00580F00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW | |
| 68 | }; | |
| 5449c685 | 69 | |
| 5da5804b | 70 | static const unsigned long dwAL2230ChannelTable0[CB_MAX_CHANNEL] = { |
| 3bd1996e JP |
71 | 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz |
| 72 | 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz | |
| 73 | 0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz | |
| 74 | 0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz | |
| 75 | 0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz | |
| 76 | 0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz | |
| 77 | 0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz | |
| 78 | 0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz | |
| 79 | 0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz | |
| 80 | 0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz | |
| 81 | 0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz | |
| 82 | 0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz | |
| 83 | 0x03F7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz | |
| 84 | 0x03E7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW // channel = 14, Tf = 2412M | |
| 85 | }; | |
| 5449c685 | 86 | |
| 5da5804b | 87 | static const unsigned long dwAL2230ChannelTable1[CB_MAX_CHANNEL] = { |
| 3bd1996e JP |
88 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz |
| 89 | 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz | |
| 90 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz | |
| 91 | 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz | |
| 92 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz | |
| 93 | 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz | |
| 94 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz | |
| 95 | 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz | |
| 96 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz | |
| 97 | 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz | |
| 98 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz | |
| 99 | 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz | |
| 100 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz | |
| 101 | 0x06666100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW // channel = 14, Tf = 2412M | |
| 102 | }; | |
| 5449c685 | 103 | |
| 5da5804b | 104 | static unsigned long dwAL2230PowerTable[AL2230_PWR_IDX_LEN] = { |
| 3bd1996e JP |
105 | 0x04040900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 106 | 0x04041900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 107 | 0x04042900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 108 | 0x04043900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 109 | 0x04044900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 110 | 0x04045900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 111 | 0x04046900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 112 | 0x04047900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 113 | 0x04048900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 114 | 0x04049900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 115 | 0x0404A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 116 | 0x0404B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 117 | 0x0404C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 118 | 0x0404D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 119 | 0x0404E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 120 | 0x0404F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 121 | 0x04050900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 122 | 0x04051900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 123 | 0x04052900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 124 | 0x04053900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 125 | 0x04054900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 126 | 0x04055900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 127 | 0x04056900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 128 | 0x04057900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 129 | 0x04058900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 130 | 0x04059900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 131 | 0x0405A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 132 | 0x0405B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 133 | 0x0405C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 134 | 0x0405D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 135 | 0x0405E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 136 | 0x0405F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 137 | 0x04060900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 138 | 0x04061900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 139 | 0x04062900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 140 | 0x04063900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 141 | 0x04064900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 142 | 0x04065900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 143 | 0x04066900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 144 | 0x04067900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 145 | 0x04068900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 146 | 0x04069900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 147 | 0x0406A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 148 | 0x0406B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 149 | 0x0406C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 150 | 0x0406D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 151 | 0x0406E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 152 | 0x0406F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 153 | 0x04070900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 154 | 0x04071900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 155 | 0x04072900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 156 | 0x04073900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 157 | 0x04074900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 158 | 0x04075900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 159 | 0x04076900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 160 | 0x04077900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 161 | 0x04078900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 162 | 0x04079900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 163 | 0x0407A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 164 | 0x0407B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 165 | 0x0407C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 166 | 0x0407D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 167 | 0x0407E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 168 | 0x0407F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW | |
| 169 | }; | |
| 5449c685 | 170 | |
| 5449c685 FB |
171 | // 40MHz reference frequency |
| 172 | // Need to Pull PLLON(PE3) low when writing channel registers through 3-wire. | |
| 5da5804b | 173 | static const unsigned long dwAL7230InitTable[CB_AL7230_INIT_SEQ] = { |
| 3bd1996e JP |
174 | 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a |
| 175 | 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a | |
| 176 | 0x841FF200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 451FE2 | |
| 177 | 0x3FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 5FDFA3 | |
| 178 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11b/g // Need modify for 11a | |
| 3bd1996e JP |
179 | // RoberYu:20050113, Rev0.47 Regsiter Setting Guide |
| 180 | 0x802B5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B55 | |
| 181 | 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 182 | 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 860207 | |
| 183 | 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 184 | 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 185 | 0xE0000A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: E0600A | |
| 186 | 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) | |
| 3bd1996e JP |
187 | // RoberYu:20050113, Rev0.47 Regsiter Setting Guide |
| 188 | 0x000A3C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C | |
| 189 | 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 190 | 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 191 | 0x1ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // Need modify for 11a: 12BACF | |
| 192 | }; | |
| 5449c685 | 193 | |
| 5da5804b | 194 | static const unsigned long dwAL7230InitTableAMode[CB_AL7230_INIT_SEQ] = { |
| 3bd1996e JP |
195 | 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g |
| 196 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g | |
| 197 | 0x451FE200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g | |
| 198 | 0x5FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g | |
| 199 | 0x67F78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11a // Need modify for 11b/g | |
| 200 | 0x853F5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g, RoberYu:20050113 | |
| 201 | 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 202 | 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g | |
| 203 | 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 204 | 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 205 | 0xE0600A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g | |
| 206 | 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) | |
| 207 | 0x00147C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g | |
| 208 | 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 209 | 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, | |
| 210 | 0x12BACF00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // Need modify for 11b/g | |
| 211 | }; | |
| 5449c685 | 212 | |
| 5da5804b | 213 | static const unsigned long dwAL7230ChannelTable0[CB_MAX_CHANNEL] = { |
| 3bd1996e JP |
214 | 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz |
| 215 | 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz | |
| 216 | 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz | |
| 217 | 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz | |
| 218 | 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz | |
| 219 | 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz | |
| 220 | 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz | |
| 221 | 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49 | |
| 222 | 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49 | |
| 223 | 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49 | |
| 224 | 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49 | |
| 225 | 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49 | |
| 226 | 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49 | |
| 227 | 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz | |
| 228 | ||
| 229 | // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) | |
| 230 | 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15) | |
| 231 | 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16) | |
| 232 | 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17) | |
| 233 | 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18) | |
| 234 | 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19) | |
| 235 | 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20) | |
| 236 | 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21) | |
| 237 | 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22) | |
| 238 | ||
| 239 | // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, | |
| 240 | // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) | |
| 241 | ||
| 242 | 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23) | |
| 243 | 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24) | |
| 244 | 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25) | |
| 245 | 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26) | |
| 246 | 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27) | |
| 247 | 0x0FF55000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28) | |
| 248 | 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29) | |
| 249 | 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30) | |
| 250 | 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49 | |
| 251 | 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32) | |
| 252 | 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33) | |
| 253 | 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34) | |
| 254 | 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35) | |
| 255 | 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36) | |
| 256 | 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37) | |
| 257 | 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38) | |
| 258 | 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39) | |
| 259 | 0x0FF59000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40) | |
| 260 | ||
| 261 | 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41) | |
| 262 | 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42) | |
| 263 | 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43) | |
| 264 | 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44) | |
| 265 | 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45) | |
| 266 | 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46) | |
| 267 | 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47) | |
| 268 | 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48) | |
| 269 | 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49) | |
| 270 | 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50) | |
| 271 | 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51) | |
| 272 | 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52) | |
| 273 | 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53) | |
| 274 | 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54) | |
| 275 | 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55) | |
| 276 | 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56) | |
| 277 | }; | |
| 5449c685 | 278 | |
| 5da5804b | 279 | static const unsigned long dwAL7230ChannelTable1[CB_MAX_CHANNEL] = { |
| 3bd1996e JP |
280 | 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz |
| 281 | 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz | |
| 282 | 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz | |
| 283 | 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz | |
| 284 | 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz | |
| 285 | 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz | |
| 286 | 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz | |
| 287 | 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz | |
| 288 | 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz | |
| 289 | 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz | |
| 290 | 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz | |
| 291 | 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz | |
| 292 | 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz | |
| 293 | 0x06666100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz | |
| 294 | ||
| 295 | // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) | |
| 296 | 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15) | |
| 297 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16) | |
| 298 | 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17) | |
| 299 | 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18) | |
| 300 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19) | |
| 301 | 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20) | |
| 302 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21) | |
| 303 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22) | |
| 304 | ||
| 305 | // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, | |
| 306 | // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) | |
| 307 | 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23) | |
| 308 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24) | |
| 309 | 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25) | |
| 310 | 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26) | |
| 311 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27) | |
| 312 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28) | |
| 313 | 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29) | |
| 314 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30) | |
| 315 | 0x10000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31) | |
| 316 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32) | |
| 317 | 0x1AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33) | |
| 318 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34) | |
| 319 | 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35) | |
| 320 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36) | |
| 321 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37) | |
| 322 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38) | |
| 323 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39) | |
| 324 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40) | |
| 325 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41) | |
| 326 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42) | |
| 327 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43) | |
| 328 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44) | |
| 329 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45) | |
| 330 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46) | |
| 331 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47) | |
| 332 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48) | |
| 333 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49) | |
| 334 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50) | |
| 335 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51) | |
| 336 | 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52) | |
| 337 | 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53) | |
| 338 | 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54) | |
| 339 | 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55) | |
| 340 | 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56) | |
| 341 | }; | |
| 5449c685 | 342 | |
| 5da5804b | 343 | static const unsigned long dwAL7230ChannelTable2[CB_MAX_CHANNEL] = { |
| 3bd1996e JP |
344 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz |
| 345 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz | |
| 346 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz | |
| 347 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz | |
| 348 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz | |
| 349 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz | |
| 350 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz | |
| 351 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz | |
| 352 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz | |
| 353 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz | |
| 354 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz | |
| 355 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz | |
| 356 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz | |
| 357 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz | |
| 358 | ||
| 359 | // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) | |
| 360 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15) | |
| 361 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16) | |
| 362 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17) | |
| 363 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18) | |
| 364 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19) | |
| 365 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20) | |
| 366 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21) | |
| 367 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22) | |
| 368 | ||
| 369 | // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, | |
| 370 | // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) | |
| 371 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23) | |
| 372 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24) | |
| 373 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25) | |
| 374 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26) | |
| 375 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27) | |
| 376 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28) | |
| 377 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29) | |
| 378 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30) | |
| 379 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31) | |
| 380 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32) | |
| 381 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33) | |
| 382 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34) | |
| 383 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35) | |
| 384 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36) | |
| 385 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37) | |
| 386 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38) | |
| 387 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39) | |
| 388 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40) | |
| 389 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41) | |
| 390 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42) | |
| 391 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43) | |
| 392 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44) | |
| 393 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45) | |
| 394 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46) | |
| 395 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47) | |
| 396 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48) | |
| 397 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49) | |
| 398 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50) | |
| 399 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51) | |
| 400 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52) | |
| 401 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53) | |
| 402 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54) | |
| 403 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55) | |
| 404 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56) | |
| 405 | }; | |
| 5449c685 | 406 | |
| 5449c685 FB |
407 | /* |
| 408 | * Description: AIROHA IFRF chip init function | |
| 409 | * | |
| 410 | * Parameters: | |
| 411 | * In: | |
| 412 | * dwIoBase - I/O base address | |
| 413 | * Out: | |
| 414 | * none | |
| 415 | * | |
| 5a5a2a6a | 416 | * Return Value: true if succeeded; false if failed. |
| 5449c685 FB |
417 | * |
| 418 | */ | |
| 78b3c1fd | 419 | static bool s_bAL7230Init(struct vnt_private *priv) |
| 5449c685 | 420 | { |
| 78b3c1fd | 421 | void __iomem *dwIoBase = priv->PortOffset; |
| 3bd1996e JP |
422 | int ii; |
| 423 | bool bResult; | |
| 5449c685 | 424 | |
| 3bd1996e | 425 | bResult = true; |
| 5449c685 | 426 | |
| 74ed42c7 | 427 | /* 3-wire control for normal mode */ |
| 3bd1996e | 428 | VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0); |
| 5449c685 | 429 | |
| 3bd1996e JP |
430 | MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | |
| 431 | SOFTPWRCTL_TXPEINV)); | |
| 78b3c1fd | 432 | BBvPowerSaveModeOFF(priv); /* RobertYu:20050106, have DC value for Calibration */ |
| 5449c685 | 433 | |
| 3bd1996e | 434 | for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) |
| b310a0cd | 435 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[ii]); |
| 5449c685 | 436 | |
| 74ed42c7 | 437 | /* PLL On */ |
| 3bd1996e | 438 | MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); |
| 5449c685 | 439 | |
| 74ed42c7 | 440 | /* Calibration */ |
| 3bd1996e | 441 | MACvTimer0MicroSDelay(dwIoBase, 150);//150us |
| b310a0cd MP |
442 | /* TXDCOC:active, RCK:disable */ |
| 443 | bResult &= IFRFbWriteEmbedded(priv, (0x9ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); | |
| 3bd1996e | 444 | MACvTimer0MicroSDelay(dwIoBase, 30);//30us |
| b310a0cd MP |
445 | /* TXDCOC:disable, RCK:active */ |
| 446 | bResult &= IFRFbWriteEmbedded(priv, (0x3ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); | |
| 3bd1996e | 447 | MACvTimer0MicroSDelay(dwIoBase, 30);//30us |
| b310a0cd MP |
448 | /* TXDCOC:disable, RCK:disable */ |
| 449 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[CB_AL7230_INIT_SEQ-1]); | |
| 5449c685 | 450 | |
| 3bd1996e JP |
451 | MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | |
| 452 | SOFTPWRCTL_SWPE2 | | |
| 453 | SOFTPWRCTL_SWPECTI | | |
| 454 | SOFTPWRCTL_TXPEINV)); | |
| 5449c685 | 455 | |
| 78b3c1fd | 456 | BBvPowerSaveModeON(priv); /* RobertYu:20050106 */ |
| 5449c685 | 457 | |
| 74ed42c7 MP |
458 | /* PE1: TX_ON, PE2: RX_ON, PE3: PLLON */ |
| 459 | /* 3-wire control for power saving mode */ | |
| 3bd1996e | 460 | VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000 |
| 5449c685 | 461 | |
| 3bd1996e | 462 | return bResult; |
| 5449c685 FB |
463 | } |
| 464 | ||
| 74ed42c7 MP |
465 | /* Need to Pull PLLON low when writing channel registers through |
| 466 | * 3-wire interface */ | |
| 817c985b | 467 | static bool s_bAL7230SelectChannel(struct vnt_private *priv, unsigned char byChannel) |
| 5449c685 | 468 | { |
| 817c985b | 469 | void __iomem *dwIoBase = priv->PortOffset; |
| 3bd1996e | 470 | bool bResult; |
| 5449c685 | 471 | |
| 3bd1996e | 472 | bResult = true; |
| 5449c685 | 473 | |
| 74ed42c7 | 474 | /* PLLON Off */ |
| 3bd1996e | 475 | MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); |
| 5449c685 | 476 | |
| b310a0cd MP |
477 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable0[byChannel - 1]); |
| 478 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable1[byChannel - 1]); | |
| 479 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable2[byChannel - 1]); | |
| 5449c685 | 480 | |
| 74ed42c7 | 481 | /* PLLOn On */ |
| 3bd1996e | 482 | MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); |
| 5449c685 | 483 | |
| 74ed42c7 | 484 | /* Set Channel[7] = 0 to tell H/W channel is changing now. */ |
| 3bd1996e JP |
485 | VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F)); |
| 486 | MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL7230); | |
| 74ed42c7 | 487 | /* Set Channel[7] = 1 to tell H/W channel change is done. */ |
| 3bd1996e | 488 | VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80)); |
| 5449c685 | 489 | |
| 3bd1996e | 490 | return bResult; |
| 5449c685 FB |
491 | } |
| 492 | ||
| 5449c685 | 493 | /* |
| 789d1aef | 494 | * Description: Write to IF/RF, by embedded programming |
| 5449c685 FB |
495 | * |
| 496 | * Parameters: | |
| 497 | * In: | |
| 498 | * dwIoBase - I/O base address | |
| 499 | * dwData - data to write | |
| 500 | * Out: | |
| 501 | * none | |
| 502 | * | |
| 5a5a2a6a | 503 | * Return Value: true if succeeded; false if failed. |
| 5449c685 FB |
504 | * |
| 505 | */ | |
| b310a0cd | 506 | bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData) |
| 5449c685 | 507 | { |
| b310a0cd | 508 | void __iomem *dwIoBase = priv->PortOffset; |
| 3bd1996e JP |
509 | unsigned short ww; |
| 510 | unsigned long dwValue; | |
| 5449c685 | 511 | |
| 3bd1996e | 512 | VNSvOutPortD(dwIoBase + MAC_REG_IFREGCTL, dwData); |
| 5449c685 | 513 | |
| 74ed42c7 | 514 | /* W_MAX_TIMEOUT is the timeout period */ |
| 3bd1996e JP |
515 | for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { |
| 516 | VNSvInPortD(dwIoBase + MAC_REG_IFREGCTL, &dwValue); | |
| 517 | if (dwValue & IFREGCTL_DONE) | |
| 518 | break; | |
| 519 | } | |
| 5449c685 | 520 | |
| 4e8a7e5f | 521 | if (ww == W_MAX_TIMEOUT) |
| 3bd1996e | 522 | return false; |
| 4e8a7e5f | 523 | |
| 3bd1996e | 524 | return true; |
| 5449c685 FB |
525 | } |
| 526 | ||
| 5449c685 FB |
527 | /* |
| 528 | * Description: AIROHA IFRF chip init function | |
| 529 | * | |
| 530 | * Parameters: | |
| 531 | * In: | |
| 532 | * dwIoBase - I/O base address | |
| 533 | * Out: | |
| 534 | * none | |
| 535 | * | |
| 5a5a2a6a | 536 | * Return Value: true if succeeded; false if failed. |
| 5449c685 FB |
537 | * |
| 538 | */ | |
| 817c985b | 539 | static bool RFbAL2230Init(struct vnt_private *priv) |
| 5449c685 | 540 | { |
| 817c985b | 541 | void __iomem *dwIoBase = priv->PortOffset; |
| 3bd1996e JP |
542 | int ii; |
| 543 | bool bResult; | |
| 5449c685 | 544 | |
| 3bd1996e | 545 | bResult = true; |
| 5449c685 | 546 | |
| 74ed42c7 | 547 | /* 3-wire control for normal mode */ |
| 3bd1996e | 548 | VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0); |
| 5449c685 | 549 | |
| 3bd1996e JP |
550 | MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | |
| 551 | SOFTPWRCTL_TXPEINV)); | |
| 74ed42c7 | 552 | /* PLL Off */ |
| 3bd1996e | 553 | MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); |
| 5449c685 | 554 | |
| 74ed42c7 | 555 | /* patch abnormal AL2230 frequency output */ |
| b310a0cd | 556 | IFRFbWriteEmbedded(priv, (0x07168700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); |
| 5449c685 | 557 | |
| 3bd1996e | 558 | for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++) |
| b310a0cd | 559 | bResult &= IFRFbWriteEmbedded(priv, dwAL2230InitTable[ii]); |
| 3bd1996e | 560 | MACvTimer0MicroSDelay(dwIoBase, 30); //delay 30 us |
| 5449c685 | 561 | |
| 74ed42c7 | 562 | /* PLL On */ |
| 3bd1996e | 563 | MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); |
| 5449c685 | 564 | |
| 3bd1996e | 565 | MACvTimer0MicroSDelay(dwIoBase, 150);//150us |
| b310a0cd | 566 | bResult &= IFRFbWriteEmbedded(priv, (0x00d80f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); |
| 3bd1996e | 567 | MACvTimer0MicroSDelay(dwIoBase, 30);//30us |
| b310a0cd | 568 | bResult &= IFRFbWriteEmbedded(priv, (0x00780f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); |
| 3bd1996e | 569 | MACvTimer0MicroSDelay(dwIoBase, 30);//30us |
| b310a0cd | 570 | bResult &= IFRFbWriteEmbedded(priv, dwAL2230InitTable[CB_AL2230_INIT_SEQ-1]); |
| 5449c685 | 571 | |
| 3bd1996e JP |
572 | MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | |
| 573 | SOFTPWRCTL_SWPE2 | | |
| 574 | SOFTPWRCTL_SWPECTI | | |
| 575 | SOFTPWRCTL_TXPEINV)); | |
| 5449c685 | 576 | |
| 74ed42c7 | 577 | /* 3-wire control for power saving mode */ |
| 3bd1996e | 578 | VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000 |
| 5449c685 | 579 | |
| 3bd1996e | 580 | return bResult; |
| 5449c685 FB |
581 | } |
| 582 | ||
| 817c985b | 583 | static bool RFbAL2230SelectChannel(struct vnt_private *priv, unsigned char byChannel) |
| 5449c685 | 584 | { |
| 817c985b | 585 | void __iomem *dwIoBase = priv->PortOffset; |
| 3bd1996e | 586 | bool bResult; |
| 5449c685 | 587 | |
| 3bd1996e | 588 | bResult = true; |
| 5449c685 | 589 | |
| b310a0cd MP |
590 | bResult &= IFRFbWriteEmbedded(priv, dwAL2230ChannelTable0[byChannel - 1]); |
| 591 | bResult &= IFRFbWriteEmbedded(priv, dwAL2230ChannelTable1[byChannel - 1]); | |
| 5449c685 | 592 | |
| 74ed42c7 | 593 | /* Set Channel[7] = 0 to tell H/W channel is changing now. */ |
| 3bd1996e JP |
594 | VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F)); |
| 595 | MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL2230); | |
| 74ed42c7 | 596 | /* Set Channel[7] = 1 to tell H/W channel change is done. */ |
| 3bd1996e | 597 | VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80)); |
| 5449c685 | 598 | |
| 3bd1996e | 599 | return bResult; |
| 5449c685 FB |
600 | } |
| 601 | ||
| 5449c685 FB |
602 | /* |
| 603 | * Description: RF init function | |
| 604 | * | |
| 605 | * Parameters: | |
| 606 | * In: | |
| 607 | * byBBType | |
| 608 | * byRFType | |
| 609 | * Out: | |
| 610 | * none | |
| 611 | * | |
| 5a5a2a6a | 612 | * Return Value: true if succeeded; false if failed. |
| 5449c685 FB |
613 | * |
| 614 | */ | |
| 3bd1996e | 615 | bool RFbInit( |
| ac3e134a | 616 | struct vnt_private *priv |
| 3bd1996e | 617 | ) |
| 5449c685 | 618 | { |
| 3bd1996e | 619 | bool bResult = true; |
| 6b711271 | 620 | |
| ac3e134a | 621 | switch (priv->byRFType) { |
| 3bd1996e JP |
622 | case RF_AIROHA: |
| 623 | case RF_AL2230S: | |
| ac3e134a MP |
624 | priv->byMaxPwrLevel = AL2230_PWR_IDX_LEN; |
| 625 | bResult = RFbAL2230Init(priv); | |
| 3bd1996e JP |
626 | break; |
| 627 | case RF_AIROHA7230: | |
| ac3e134a MP |
628 | priv->byMaxPwrLevel = AL7230_PWR_IDX_LEN; |
| 629 | bResult = s_bAL7230Init(priv); | |
| 3bd1996e JP |
630 | break; |
| 631 | case RF_NOTHING: | |
| 632 | bResult = true; | |
| 633 | break; | |
| 634 | default: | |
| 635 | bResult = false; | |
| 636 | break; | |
| 637 | } | |
| 638 | return bResult; | |
| 5449c685 FB |
639 | } |
| 640 | ||
| 5449c685 FB |
641 | /* |
| 642 | * Description: Select channel | |
| 643 | * | |
| 644 | * Parameters: | |
| 645 | * In: | |
| 646 | * byRFType | |
| 647 | * byChannel - Channel number | |
| 648 | * Out: | |
| 649 | * none | |
| 650 | * | |
| 5a5a2a6a | 651 | * Return Value: true if succeeded; false if failed. |
| 5449c685 FB |
652 | * |
| 653 | */ | |
| 63e8d787 MP |
654 | bool RFbSelectChannel(struct vnt_private *priv, unsigned char byRFType, |
| 655 | u16 byChannel) | |
| 5449c685 | 656 | { |
| 3bd1996e | 657 | bool bResult = true; |
| 6b711271 | 658 | |
| 3bd1996e | 659 | switch (byRFType) { |
| 3bd1996e JP |
660 | case RF_AIROHA: |
| 661 | case RF_AL2230S: | |
| 817c985b | 662 | bResult = RFbAL2230SelectChannel(priv, byChannel); |
| 3bd1996e JP |
663 | break; |
| 664 | //{{ RobertYu: 20050104 | |
| 665 | case RF_AIROHA7230: | |
| 817c985b | 666 | bResult = s_bAL7230SelectChannel(priv, byChannel); |
| 3bd1996e JP |
667 | break; |
| 668 | //}} RobertYu | |
| 669 | case RF_NOTHING: | |
| 670 | bResult = true; | |
| 671 | break; | |
| 672 | default: | |
| 673 | bResult = false; | |
| 674 | break; | |
| 675 | } | |
| 676 | return bResult; | |
| 5449c685 FB |
677 | } |
| 678 | ||
| 679 | /* | |
| 680 | * Description: Write WakeProgSyn | |
| 681 | * | |
| 682 | * Parameters: | |
| 683 | * In: | |
| 684 | * dwIoBase - I/O base address | |
| 685 | * uChannel - channel number | |
| 686 | * bySleepCnt - SleepProgSyn count | |
| 687 | * | |
| 688 | * Return Value: None. | |
| 689 | * | |
| 690 | */ | |
| 63e8d787 MP |
691 | bool RFvWriteWakeProgSyn(struct vnt_private *priv, unsigned char byRFType, |
| 692 | u16 uChannel) | |
| 5449c685 | 693 | { |
| 817c985b | 694 | void __iomem *dwIoBase = priv->PortOffset; |
| 3bd1996e JP |
695 | int ii; |
| 696 | unsigned char byInitCount = 0; | |
| 697 | unsigned char bySleepCount = 0; | |
| 698 | ||
| 699 | VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, 0); | |
| 700 | switch (byRFType) { | |
| 701 | case RF_AIROHA: | |
| 702 | case RF_AL2230S: | |
| 703 | ||
| 704 | if (uChannel > CB_MAX_CHANNEL_24G) | |
| 705 | return false; | |
| 706 | ||
| 74ed42c7 MP |
707 | /* Init Reg + Channel Reg (2) */ |
| 708 | byInitCount = CB_AL2230_INIT_SEQ + 2; | |
| 3bd1996e | 709 | bySleepCount = 0; |
| bc5cf656 | 710 | if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) |
| 3bd1996e | 711 | return false; |
| 3bd1996e | 712 | |
| bc5cf656 | 713 | for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++) |
| 3bd1996e | 714 | MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230InitTable[ii]); |
| bc5cf656 | 715 | |
| 3bd1996e JP |
716 | MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable0[uChannel-1]); |
| 717 | ii++; | |
| 718 | MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable1[uChannel-1]); | |
| 719 | break; | |
| 720 | ||
| 74ed42c7 | 721 | /* Need to check, PLLON need to be low for channel setting */ |
| 3bd1996e | 722 | case RF_AIROHA7230: |
| 74ed42c7 MP |
723 | /* Init Reg + Channel Reg (3) */ |
| 724 | byInitCount = CB_AL7230_INIT_SEQ + 3; | |
| 3bd1996e | 725 | bySleepCount = 0; |
| bc5cf656 | 726 | if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) |
| 3bd1996e | 727 | return false; |
| 3bd1996e | 728 | |
| 5e0cc8a2 | 729 | if (uChannel <= CB_MAX_CHANNEL_24G) { |
| bc5cf656 | 730 | for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) |
| 3bd1996e | 731 | MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTable[ii]); |
| 5e0cc8a2 | 732 | } else { |
| bc5cf656 | 733 | for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) |
| 3bd1996e | 734 | MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTableAMode[ii]); |
| 3bd1996e JP |
735 | } |
| 736 | ||
| 737 | MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable0[uChannel-1]); | |
| 738 | ii++; | |
| 739 | MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable1[uChannel-1]); | |
| 740 | ii++; | |
| 741 | MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable2[uChannel-1]); | |
| 742 | break; | |
| 3bd1996e JP |
743 | |
| 744 | case RF_NOTHING: | |
| 745 | return true; | |
| 3bd1996e JP |
746 | |
| 747 | default: | |
| 748 | return false; | |
| 3bd1996e JP |
749 | } |
| 750 | ||
| 751 | MACvSetMISCFifo(dwIoBase, MISCFIFO_SYNINFO_IDX, (unsigned long)MAKEWORD(bySleepCount, byInitCount)); | |
| 752 | ||
| 753 | return true; | |
| 5449c685 FB |
754 | } |
| 755 | ||
| 756 | /* | |
| 757 | * Description: Set Tx power | |
| 758 | * | |
| 759 | * Parameters: | |
| 760 | * In: | |
| 761 | * dwIoBase - I/O base address | |
| 762 | * dwRFPowerTable - RF Tx Power Setting | |
| 763 | * Out: | |
| 764 | * none | |
| 765 | * | |
| 5a5a2a6a | 766 | * Return Value: true if succeeded; false if failed. |
| 5449c685 FB |
767 | * |
| 768 | */ | |
| 3bd1996e | 769 | bool RFbSetPower( |
| ac3e134a | 770 | struct vnt_private *priv, |
| 3bd1996e | 771 | unsigned int uRATE, |
| 63e8d787 | 772 | u16 uCH |
| 3bd1996e | 773 | ) |
| 5449c685 | 774 | { |
| 3bd1996e JP |
775 | bool bResult = true; |
| 776 | unsigned char byPwr = 0; | |
| 777 | unsigned char byDec = 0; | |
| 3bd1996e | 778 | |
| ac3e134a | 779 | if (priv->dwDiagRefCount != 0) |
| 3bd1996e | 780 | return true; |
| bc5cf656 GM |
781 | |
| 782 | if ((uCH < 1) || (uCH > CB_MAX_CHANNEL)) | |
| 3bd1996e | 783 | return false; |
| 3bd1996e JP |
784 | |
| 785 | switch (uRATE) { | |
| 786 | case RATE_1M: | |
| 787 | case RATE_2M: | |
| 788 | case RATE_5M: | |
| 789 | case RATE_11M: | |
| b0c5881e MP |
790 | if (uCH > CB_MAX_CHANNEL_24G) |
| 791 | return false; | |
| 792 | ||
| ac3e134a | 793 | byPwr = priv->abyCCKPwrTbl[uCH]; |
| 5449c685 | 794 | break; |
| 3bd1996e JP |
795 | case RATE_6M: |
| 796 | case RATE_9M: | |
| 40c8790b | 797 | case RATE_12M: |
| 3bd1996e | 798 | case RATE_18M: |
| ac3e134a MP |
799 | byPwr = priv->abyOFDMPwrTbl[uCH]; |
| 800 | if (priv->byRFType == RF_UW2452) | |
| 3bd1996e | 801 | byDec = byPwr + 14; |
| bc5cf656 | 802 | else |
| 3bd1996e | 803 | byDec = byPwr + 10; |
| bc5cf656 | 804 | |
| ac3e134a MP |
805 | if (byDec >= priv->byMaxPwrLevel) |
| 806 | byDec = priv->byMaxPwrLevel-1; | |
| bc5cf656 | 807 | |
| 3bd1996e | 808 | byPwr = byDec; |
| 5449c685 | 809 | break; |
| 3bd1996e JP |
810 | case RATE_24M: |
| 811 | case RATE_36M: | |
| 812 | case RATE_48M: | |
| 813 | case RATE_54M: | |
| ac3e134a | 814 | byPwr = priv->abyOFDMPwrTbl[uCH]; |
| 5449c685 | 815 | break; |
| 3bd1996e | 816 | } |
| 5449c685 | 817 | |
| ac3e134a | 818 | if (priv->byCurPwr == byPwr) |
| 3bd1996e | 819 | return true; |
| a7307538 | 820 | |
| ac3e134a | 821 | bResult = RFbRawSetPower(priv, byPwr, uRATE); |
| bc5cf656 | 822 | if (bResult) |
| ac3e134a | 823 | priv->byCurPwr = byPwr; |
| bc5cf656 | 824 | |
| 3bd1996e | 825 | return bResult; |
| 5449c685 FB |
826 | } |
| 827 | ||
| 828 | /* | |
| 829 | * Description: Set Tx power | |
| 830 | * | |
| 831 | * Parameters: | |
| 832 | * In: | |
| 833 | * dwIoBase - I/O base address | |
| 834 | * dwRFPowerTable - RF Tx Power Setting | |
| 835 | * Out: | |
| 836 | * none | |
| 837 | * | |
| 5a5a2a6a | 838 | * Return Value: true if succeeded; false if failed. |
| 5449c685 FB |
839 | * |
| 840 | */ | |
| 841 | ||
| 3bd1996e | 842 | bool RFbRawSetPower( |
| ac3e134a | 843 | struct vnt_private *priv, |
| 3bd1996e JP |
844 | unsigned char byPwr, |
| 845 | unsigned int uRATE | |
| 846 | ) | |
| 5449c685 | 847 | { |
| 3bd1996e JP |
848 | bool bResult = true; |
| 849 | unsigned long dwMax7230Pwr = 0; | |
| 850 | ||
| ac3e134a | 851 | if (byPwr >= priv->byMaxPwrLevel) |
| a4ef27ad | 852 | return false; |
| bc5cf656 | 853 | |
| ac3e134a | 854 | switch (priv->byRFType) { |
| 3bd1996e | 855 | case RF_AIROHA: |
| ac3e134a | 856 | bResult &= IFRFbWriteEmbedded(priv, dwAL2230PowerTable[byPwr]); |
| bc5cf656 | 857 | if (uRATE <= RATE_11M) |
| ac3e134a | 858 | bResult &= IFRFbWriteEmbedded(priv, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); |
| bc5cf656 | 859 | else |
| ac3e134a | 860 | bResult &= IFRFbWriteEmbedded(priv, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); |
| bc5cf656 | 861 | |
| 3bd1996e JP |
862 | break; |
| 863 | ||
| 3bd1996e | 864 | case RF_AL2230S: |
| ac3e134a | 865 | bResult &= IFRFbWriteEmbedded(priv, dwAL2230PowerTable[byPwr]); |
| 3bd1996e | 866 | if (uRATE <= RATE_11M) { |
| ac3e134a MP |
867 | bResult &= IFRFbWriteEmbedded(priv, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); |
| 868 | bResult &= IFRFbWriteEmbedded(priv, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); | |
| 3bd1996e | 869 | } else { |
| ac3e134a MP |
870 | bResult &= IFRFbWriteEmbedded(priv, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); |
| 871 | bResult &= IFRFbWriteEmbedded(priv, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); | |
| 3bd1996e JP |
872 | } |
| 873 | ||
| 874 | break; | |
| 875 | ||
| 876 | case RF_AIROHA7230: | |
| 74ed42c7 MP |
877 | /* 0x080F1B00 for 3 wire control TxGain(D10) |
| 878 | * and 0x31 as TX Gain value */ | |
| 3bd1996e JP |
879 | dwMax7230Pwr = 0x080C0B00 | ((byPwr) << 12) | |
| 880 | (BY_AL7230_REG_LEN << 3) | IFREGCTL_REGW; | |
| 881 | ||
| ac3e134a | 882 | bResult &= IFRFbWriteEmbedded(priv, dwMax7230Pwr); |
| 3bd1996e JP |
883 | break; |
| 884 | ||
| 3bd1996e JP |
885 | default: |
| 886 | break; | |
| 887 | } | |
| 888 | return bResult; | |
| 5449c685 FB |
889 | } |
| 890 | ||
| 891 | /*+ | |
| 892 | * | |
| 893 | * Routine Description: | |
| 894 | * Translate RSSI to dBm | |
| 895 | * | |
| 896 | * Parameters: | |
| 897 | * In: | |
| ac3e134a | 898 | * priv - The adapter to be translated |
| 5449c685 FB |
899 | * byCurrRSSI - RSSI to be translated |
| 900 | * Out: | |
| 901 | * pdwdbm - Translated dbm number | |
| 902 | * | |
| 903 | * Return Value: none | |
| 904 | * | |
| 3bd1996e | 905 | -*/ |
| 6b35b7b3 | 906 | void |
| 3bd1996e | 907 | RFvRSSITodBm( |
| ac3e134a | 908 | struct vnt_private *priv, |
| 3bd1996e JP |
909 | unsigned char byCurrRSSI, |
| 910 | long *pldBm | |
| 911 | ) | |
| 5449c685 | 912 | { |
| 3bd1996e JP |
913 | unsigned char byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03); |
| 914 | long b = (byCurrRSSI & 0x3F); | |
| 915 | long a = 0; | |
| 916 | unsigned char abyAIROHARF[4] = {0, 18, 0, 40}; | |
| 917 | ||
| ac3e134a | 918 | switch (priv->byRFType) { |
| 3bd1996e JP |
919 | case RF_AIROHA: |
| 920 | case RF_AL2230S: | |
| 0a5ea1e3 | 921 | case RF_AIROHA7230: |
| 3bd1996e JP |
922 | a = abyAIROHARF[byIdx]; |
| 923 | break; | |
| 924 | default: | |
| 925 | break; | |
| 926 | } | |
| 927 | ||
| 928 | *pldBm = -1 * (a + b * 2); | |
| 5449c685 FB |
929 | } |
| 930 | ||
| 74ed42c7 MP |
931 | /* Post processing for the 11b/g and 11a. |
| 932 | * for save time on changing Reg2,3,5,7,10,12,15 */ | |
| 817c985b | 933 | bool RFbAL7230SelectChannelPostProcess(struct vnt_private *priv, |
| 63e8d787 MP |
934 | u16 byOldChannel, |
| 935 | u16 byNewChannel) | |
| 5449c685 | 936 | { |
| 3bd1996e JP |
937 | bool bResult; |
| 938 | ||
| 939 | bResult = true; | |
| 940 | ||
| 74ed42c7 MP |
941 | /* if change between 11 b/g and 11a need to update the following |
| 942 | * register | |
| 943 | * Channel Index 1~14 */ | |
| 5e0cc8a2 | 944 | if ((byOldChannel <= CB_MAX_CHANNEL_24G) && (byNewChannel > CB_MAX_CHANNEL_24G)) { |
| b310a0cd MP |
945 | /* Change from 2.4G to 5G [Reg] */ |
| 946 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[2]); | |
| 947 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[3]); | |
| 948 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[5]); | |
| 949 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[7]); | |
| 950 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[10]); | |
| 951 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[12]); | |
| 952 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[15]); | |
| 5e0cc8a2 | 953 | } else if ((byOldChannel > CB_MAX_CHANNEL_24G) && (byNewChannel <= CB_MAX_CHANNEL_24G)) { |
| b310a0cd MP |
954 | /* Change from 5G to 2.4G [Reg] */ |
| 955 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[2]); | |
| 956 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[3]); | |
| 957 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[5]); | |
| 958 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[7]); | |
| 959 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[10]); | |
| 960 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[12]); | |
| 961 | bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[15]); | |
| 3bd1996e JP |
962 | } |
| 963 | ||
| 964 | return bResult; | |
| 5449c685 | 965 | } |