Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
[linux-2.6-block.git] / drivers / staging / vt6655 / device.h
CommitLineData
84580771 1/* SPDX-License-Identifier: GPL-2.0+ */
5449c685
FB
2/*
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
4 * All rights reserved.
5 *
5449c685
FB
6 * File: device.h
7 *
8 * Purpose: MAC Data structure
9 *
10 * Author: Tevin Chen
11 *
12 * Date: Mar 17, 1997
13 *
14 */
15
16#ifndef __DEVICE_H__
17#define __DEVICE_H__
18
5449c685 19#include <linux/module.h>
5449c685 20#include <linux/types.h>
5449c685 21#include <linux/pci.h>
5449c685
FB
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
5449c685 24#include <linux/interrupt.h>
b39d60c1 25#include <linux/crc32.h>
33b1c8c1 26#include <net/mac80211.h>
5449c685 27
81a4e959 28/* device specific */
612822f5 29
5449c685 30#include "device_cfg.h"
33785983 31#include "card.h"
5449c685 32#include "srom.h"
5449c685 33#include "desc.h"
5449c685 34#include "key.h"
5449c685 35#include "mac.h"
5449c685 36
5449c685
FB
37/*--------------------- Export Definitions -------------------------*/
38
b0437f28
MP
39#define RATE_1M 0
40#define RATE_2M 1
41#define RATE_5M 2
42#define RATE_11M 3
43#define RATE_6M 4
44#define RATE_9M 5
45#define RATE_12M 6
46#define RATE_18M 7
47#define RATE_24M 8
48#define RATE_36M 9
49#define RATE_48M 10
50#define RATE_54M 11
b0437f28
MP
51#define MAX_RATE 12
52
5449c685
FB
53#define AUTO_FB_NONE 0
54#define AUTO_FB_0 1
55#define AUTO_FB_1 2
56
57#define FB_RATE0 0
58#define FB_RATE1 1
59
81a4e959 60/* Antenna Mode */
5449c685
FB
61#define ANT_A 0
62#define ANT_B 1
63#define ANT_DIVERSITY 2
64#define ANT_RXD_TXA 3
65#define ANT_RXD_TXB 4
66#define ANT_UNKNOWN 0xFF
67
5449c685
FB
68#define BB_VGA_LEVEL 4
69#define BB_VGA_CHANGE_THRESHOLD 16
70
c3fb4642
MP
71#define MAKE_BEACON_RESERVED 10 /* (us) */
72
81a4e959 73/* BUILD OBJ mode */
5449c685 74
bc667b99 75#define AVAIL_TD(p, q) ((p)->opts.tx_descs[(q)] - ((p)->iTDUsed[(q)]))
5449c685 76
81a4e959 77/* 0:11A 1:11B 2:11G */
ff8d9f08
MP
78#define BB_TYPE_11A 0
79#define BB_TYPE_11B 1
80#define BB_TYPE_11G 2
5449c685 81
bf8918de
MP
82/* 0:11a, 1:11b, 2:11gb (only CCK in BasicRate), 3:11ga (OFDM in BasicRate) */
83#define PK_TYPE_11A 0
84#define PK_TYPE_11B 1
85#define PK_TYPE_11GB 2
86#define PK_TYPE_11GA 3
5449c685 87
28c777cb
MP
88#define OWNED_BY_HOST 0
89#define OWNED_BY_NIC 1
5449c685 90
bed02d93
MP
91struct vnt_options {
92 int rx_descs0; /* Number of RX descriptors0 */
93 int rx_descs1; /* Number of RX descriptors1 */
94 int tx_descs[2]; /* Number of TX descriptors 0, 1 */
95 int int_works; /* interrupt limits */
96 int short_retry;
97 int long_retry;
98 int bbp_type;
99 u32 flags;
100};
5449c685 101
80f598ae 102struct vnt_private {
4ec4aa4a 103 struct pci_dev *pcid;
33b1c8c1
MP
104 /* mac80211 */
105 struct ieee80211_hw *hw;
106 struct ieee80211_vif *vif;
fee7506a 107 unsigned long key_entry_inuse;
67013f2c 108 u32 basic_rates;
89cf9be6 109 u16 current_aid;
67013f2c
MP
110 int mc_list_count;
111 u8 mac_hw;
5449c685 112
81a4e959 113/* dma addr, rx/tx pool */
4ec4aa4a
JP
114 dma_addr_t pool_dma;
115 dma_addr_t rd0_pool_dma;
116 dma_addr_t rd1_pool_dma;
5449c685 117
4ec4aa4a
JP
118 dma_addr_t td0_pool_dma;
119 dma_addr_t td1_pool_dma;
5449c685 120
4ec4aa4a
JP
121 dma_addr_t tx_bufs_dma0;
122 dma_addr_t tx_bufs_dma1;
123 dma_addr_t tx_beacon_dma;
5449c685 124
4ec4aa4a
JP
125 unsigned char *tx0_bufs;
126 unsigned char *tx1_bufs;
127 unsigned char *tx_beacon_bufs;
5449c685 128
16834405 129 void __iomem *PortOffset;
4ec4aa4a
JP
130 u32 memaddr;
131 u32 ioaddr;
5449c685 132
2359b5c2 133 unsigned char byRxMode;
5449c685 134
2359b5c2
AM
135 spinlock_t lock;
136
4ec4aa4a 137 volatile int iTDUsed[TYPE_MAXTD];
5449c685 138
e2357271
MP
139 struct vnt_tx_desc *apCurrTD[TYPE_MAXTD];
140 struct vnt_tx_desc *apTailTD[TYPE_MAXTD];
5449c685 141
e2357271
MP
142 struct vnt_tx_desc *apTD0Rings;
143 struct vnt_tx_desc *apTD1Rings;
5449c685 144
9cb693f6
MP
145 struct vnt_rx_desc *aRD0Ring;
146 struct vnt_rx_desc *aRD1Ring;
147 struct vnt_rx_desc *pCurrRD[TYPE_MAXRD];
5449c685 148
bc667b99 149 struct vnt_options opts;
5449c685 150
4ec4aa4a 151 u32 flags;
5449c685 152
4ec4aa4a 153 u32 rx_buf_sz;
33b1c8c1 154 u8 rx_rate;
9a802f2e 155
4ec4aa4a
JP
156 u32 rx_bytes;
157
81a4e959 158 /* Version control */
4ec4aa4a
JP
159 unsigned char byLocalID;
160 unsigned char byRFType;
161
162 unsigned char byMaxPwrLevel;
163 unsigned char byZoneType;
164 bool bZoneRegExist;
165 unsigned char byOriginalZonetype;
14676105 166
c397d46f 167 unsigned char abyCurrentNetAddr[ETH_ALEN]; __aligned(2)
81a4e959 168 bool bLinkPass; /* link status: OK or fail */
4ec4aa4a 169
4ec4aa4a
JP
170 unsigned int uCurrRSSI;
171 unsigned char byCurrSQ;
172
173 unsigned long dwTxAntennaSel;
174 unsigned long dwRxAntennaSel;
175 unsigned char byAntennaCount;
176 unsigned char byRxAntennaMode;
177 unsigned char byTxAntennaMode;
178 bool bTxRxAntInv;
179
180 unsigned char *pbyTmpBuff;
81a4e959
VK
181 unsigned int uSIFS; /* Current SIFS */
182 unsigned int uDIFS; /* Current DIFS */
183 unsigned int uEIFS; /* Current EIFS */
184 unsigned int uSlot; /* Current SlotTime */
185 unsigned int uCwMin; /* Current CwMin */
186 unsigned int uCwMax; /* CwMax is fixed on 1023. */
187 /* PHY parameter */
4ec4aa4a
JP
188 unsigned char bySIFS;
189 unsigned char byDIFS;
190 unsigned char byEIFS;
191 unsigned char bySlot;
192 unsigned char byCWMaxMin;
81a4e959 193
ff8d9f08 194 u8 byBBType; /* 0:11A, 1:11B, 2:11G */
bf8918de
MP
195 u8 byPacketType; /*
196 * 0:11a,1:11b,2:11gb (only CCK
197 * in BasicRate), 3:11ga (OFDM in
198 * Basic Rate)
199 */
4ec4aa4a
JP
200 unsigned short wBasicRate;
201 unsigned char byACKRate;
202 unsigned char byTopOFDMBasicRate;
203 unsigned char byTopCCKBasicRate;
204
205 unsigned char byMinChannel;
206 unsigned char byMaxChannel;
4ec4aa4a
JP
207
208 unsigned char byPreambleType;
209 unsigned char byShortPreamble;
210
211 unsigned short wCurrentRate;
4ec4aa4a
JP
212 unsigned char byShortRetryLimit;
213 unsigned char byLongRetryLimit;
a9873673 214 enum nl80211_iftype op_mode;
4ec4aa4a
JP
215 bool bBSSIDFilter;
216 unsigned short wMaxTransmitMSDULifetime;
4ec4aa4a 217
4ec4aa4a
JP
218 bool bEncryptionEnable;
219 bool bLongHeader;
220 bool bShortSlotTime;
221 bool bProtectMode;
222 bool bNonERPPresent;
223 bool bBarkerPreambleMd;
224
4ec4aa4a
JP
225 bool bRadioControlOff;
226 bool bRadioOff;
227 bool bEnablePSMode;
228 unsigned short wListenInterval;
229 bool bPWBitOn;
4ec4aa4a 230
81a4e959 231 /* GPIO Radio Control */
4ec4aa4a
JP
232 unsigned char byRadioCtl;
233 unsigned char byGPIO;
234 bool bHWRadioOff;
235 bool bPrvActive4RadioOFF;
236 bool bGPIOBlockRead;
237
81a4e959 238 /* Beacon related */
4ec4aa4a
JP
239 unsigned short wSeqCounter;
240 unsigned short wBCNBufLen;
241 bool bBeaconBufReady;
242 bool bBeaconSent;
243 bool bIsBeaconBufReadySet;
244 unsigned int cbBeaconBufReadySetCnt;
245 bool bFixRate;
63e8d787 246 u16 byCurrentCh;
5449c685 247
4ec4aa4a 248 bool bAES;
5449c685 249
4ec4aa4a 250 unsigned char byAutoFBCtrl;
5449c685 251
81a4e959 252 /* For Update BaseBand VGA Gain Offset */
4ec4aa4a
JP
253 bool bUpdateBBVGA;
254 unsigned int uBBVGADiffCount;
255 unsigned char byBBVGANew;
256 unsigned char byBBVGACurrent;
257 unsigned char abyBBVGA[BB_VGA_LEVEL];
258 long ldBmThreshold[BB_VGA_LEVEL];
5449c685 259
4ec4aa4a
JP
260 unsigned char byBBPreEDRSSI;
261 unsigned char byBBPreEDIndex;
5449c685 262
4ec4aa4a 263 unsigned long dwDiagRefCount;
5449c685 264
81a4e959 265 /* For FOE Tuning */
4ec4aa4a 266 unsigned char byFOETuning;
5449c685 267
81a4e959 268 /* For RF Power table */
4ec4aa4a
JP
269 unsigned char byCCKPwr;
270 unsigned char byOFDMPwrG;
271 unsigned char byCurPwr;
272 char byCurPwrdBm;
bee80f29
VR
273 unsigned char abyCCKPwrTbl[CB_MAX_CHANNEL_24G + 1];
274 unsigned char abyOFDMPwrTbl[CB_MAX_CHANNEL + 1];
275 char abyCCKDefaultPwr[CB_MAX_CHANNEL_24G + 1];
276 char abyOFDMDefaultPwr[CB_MAX_CHANNEL + 1];
277 char abyRegPwr[CB_MAX_CHANNEL + 1];
278 char abyLocalPwr[CB_MAX_CHANNEL + 1];
5449c685 279
81a4e959 280 /* BaseBand Loopback Use */
4ec4aa4a
JP
281 unsigned char byBBCR4d;
282 unsigned char byBBCRc9;
283 unsigned char byBBCR88;
284 unsigned char byBBCR09;
5449c685 285
81a4e959 286 unsigned char abyEEPROM[EEP_MAX_CONTEXT_SIZE]; /* unsigned long alignment */
4ec4aa4a 287
4ec4aa4a 288 unsigned short wBeaconInterval;
3e7921a0 289 u16 wake_up_count;
700f6c02 290
ff1ce1a8
MP
291 struct work_struct interrupt_work;
292
700f6c02 293 struct ieee80211_low_level_stats low_stats;
80f598ae 294};
5449c685 295
5449c685 296#endif