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Merge branch 'trivial' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild-2.6
[linux-2.6-block.git] / drivers / staging / tm6000 / tm6000-core.c
CommitLineData
9701dc94 1/*
d0058645
RP		 2 * tm6000-core.c - driver for TM5600/TM6000/TM6010 USB video capture devices
3 *
4 * Copyright (C) 2006-2007 Mauro Carvalho Chehab <mchehab@infradead.org>
5 *
6 * Copyright (C) 2007 Michel Ludwig <michel.ludwig@gmail.com>
7 * - DVB-T support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation version 2
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
9701dc94
MCC		 21 */
22
23#include <linux/module.h>
24#include <linux/kernel.h>
4ef09889 25#include <linux/slab.h>
9701dc94
MCC		 26#include <linux/usb.h>
27#include <linux/i2c.h>
9701dc94
MCC		 28#include "tm6000.h"
29#include "tm6000-regs.h"
30#include <media/v4l2-common.h>
31#include <media/tuner.h>
32
4363a0b8 33#define USB_TIMEOUT (5 * HZ) /* ms */
9701dc94 34
52e0a72a
TT		 35int tm6000_read_write_usb(struct tm6000_core *dev, u8 req_type, u8 req,
36 u16 value, u16 index, u8 *buf, u16 len)
9701dc94
MCC		 37{
38 int ret, i;
39 unsigned int pipe;
52e0a72a 40 u8 *data = NULL;
9701dc94
MCC		 41
42 if (len)
43 data = kzalloc(len, GFP_KERNEL);
44
45
46 if (req_type & USB_DIR_IN)
52e0a72a 47 pipe = usb_rcvctrlpipe(dev->udev, 0);
9701dc94 48 else {
52e0a72a 49 pipe = usb_sndctrlpipe(dev->udev, 0);
9701dc94
MCC		 50 memcpy(data, buf, len);
51 }
52
edecce0a 53 if (tm6000_debug & V4L2_DEBUG_I2C) {
638054ab 54 printk("(dev %p, pipe %08x): ", dev->udev, pipe);
9701dc94 55
638054ab 56 printk("%s: %02x %02x %02x %02x %02x %02x %02x %02x ",
52e0a72a 57 (req_type & USB_DIR_IN) ? " IN" : "OUT",
52e0a72a
TT		 58 req_type, req, value&0xff, value>>8, index&0xff,
59 index>>8, len&0xff, len>>8);
9701dc94 60
52e0a72a 61 if (!(req_type & USB_DIR_IN)) {
9701dc94 62 printk(">>> ");
52e0a72a
TT		 63 for (i = 0; i < len; i++)
64 printk(" %02x", buf[i]);
8ae1fc6e 65 printk("\n");
9701dc94
MCC		 66 }
67 }
68
52e0a72a
TT		 69 ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index,
70 data, len, USB_TIMEOUT);
9701dc94
MCC		 71
72 if (req_type & USB_DIR_IN)
73 memcpy(buf, data, len);
74
edecce0a 75 if (tm6000_debug & V4L2_DEBUG_I2C) {
52e0a72a 76 if (ret < 0) {
9701dc94 77 if (req_type & USB_DIR_IN)
52e0a72a 78 printk("<<< (len=%d)\n", len);
9701dc94
MCC		 79
80 printk("%s: Error #%d\n", __FUNCTION__, ret);
81 } else if (req_type & USB_DIR_IN) {
82 printk("<<< ");
52e0a72a
TT		 83 for (i = 0; i < len; i++)
84 printk(" %02x", buf[i]);
9701dc94
MCC		 85 printk("\n");
86 }
87 }
88
89 kfree(data);
90
a5adfbed
ML		 91 msleep(5);
92
9701dc94
MCC		 93 return ret;
94}
95
52e0a72a 96int tm6000_set_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index)
9701dc94
MCC		 97{
98 return
52e0a72a
TT		 99 tm6000_read_write_usb(dev, USB_DIR_OUT | USB_TYPE_VENDOR,
100 req, value, index, NULL, 0);
9701dc94 101}
29ec15e9 102EXPORT_SYMBOL_GPL(tm6000_set_reg);
9701dc94 103
52e0a72a 104int tm6000_get_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index)
9701dc94
MCC		 105{
106 int rc;
107 u8 buf[1];
108
52e0a72a
TT		 109 rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
110 value, index, buf, 1);
9701dc94 111
52e0a72a 112 if (rc < 0)
9701dc94
MCC		 113 return rc;
114
115 return *buf;
116}
29ec15e9 117EXPORT_SYMBOL_GPL(tm6000_get_reg);
9701dc94 118
8aff8ba9
DB		 119int tm6000_set_reg_mask(struct tm6000_core *dev, u8 req, u16 value,
120 u16 index, u16 mask)
121{
122 int rc;
123 u8 buf[1];
124 u8 new_index;
125
126 rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
127 value, index, buf, 1);
128
129 if (rc < 0)
130 return rc;
131
132 new_index = (buf[0] & ~mask) | (index & mask);
133
134 if (new_index == index)
135 return 0;
136
137 return tm6000_read_write_usb(dev, USB_DIR_OUT | USB_TYPE_VENDOR,
138 req, value, new_index, NULL, 0);
139}
140EXPORT_SYMBOL_GPL(tm6000_set_reg_mask);
141
52e0a72a 142int tm6000_get_reg16(struct tm6000_core *dev, u8 req, u16 value, u16 index)
9701dc94
MCC		 143{
144 int rc;
145 u8 buf[2];
146
52e0a72a
TT		 147 rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
148 value, index, buf, 2);
9701dc94 149
52e0a72a 150 if (rc < 0)
9701dc94
MCC		 151 return rc;
152
153 return buf[1]|buf[0]<<8;
154}
155
52e0a72a 156int tm6000_get_reg32(struct tm6000_core *dev, u8 req, u16 value, u16 index)
2f790884
SR		 157{
158 int rc;
159 u8 buf[4];
160
52e0a72a
TT		 161 rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
162 value, index, buf, 4);
2f790884 163
52e0a72a 164 if (rc < 0)
2f790884
SR		 165 return rc;
166
167 return buf[3] | buf[2] << 8 | buf[1] << 16 | buf[0] << 24;
168}
169
2a15ac7a
DB		 170int tm6000_i2c_reset(struct tm6000_core *dev, u16 tsleep)
171{
172 int rc;
173
174 rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 0);
175 if (rc < 0)
176 return rc;
177
178 msleep(tsleep);
179
180 rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 1);
181 msleep(tsleep);
182
183 return rc;
184}
185
9701dc94
MCC		 186void tm6000_set_fourcc_format(struct tm6000_core *dev)
187{
717ecd2b 188 if (dev->dev_type == TM6010) {
42238713
MCC		 189 int val;
190
191 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0) & 0xfc;
717ecd2b 192 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
42238713 193 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
717ecd2b 194 else
42238713 195 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val | 1);
9701dc94 196 } else {
717ecd2b 197 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
9afec493 198 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
717ecd2b 199 else
9afec493 200 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0x90);
9701dc94
MCC		 201 }
202}
203
589851d5 204static void tm6000_set_vbi(struct tm6000_core *dev)
9701dc94 205{
589851d5
MCC		 206 /*
207 * FIXME:
208 * VBI lines and start/end are different between 60Hz and 50Hz
209 * So, it is very likely that we need to change the config to
210 * something that takes it into account, doing something different
211 * if (dev->norm & V4L2_STD_525_60)
212 */
94d4350c 213
29c389be 214 if (dev->dev_type == TM6010) {
120756e1
SR		 215 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
216 tm6000_set_reg(dev, TM6010_REQ07_R41_TELETEXT_VBI_CODE1, 0x27);
217 tm6000_set_reg(dev, TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55);
218 tm6000_set_reg(dev, TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7, 0x66);
219 tm6000_set_reg(dev, TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8, 0x66);
220 tm6000_set_reg(dev, TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9, 0x66);
221 tm6000_set_reg(dev,
222 TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10, 0x66);
223 tm6000_set_reg(dev,
224 TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11, 0x66);
225 tm6000_set_reg(dev,
226 TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12, 0x66);
227 tm6000_set_reg(dev,
228 TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13, 0x66);
229 tm6000_set_reg(dev,
230 TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14, 0x66);
231 tm6000_set_reg(dev,
232 TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15, 0x66);
233 tm6000_set_reg(dev,
234 TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16, 0x66);
235 tm6000_set_reg(dev,
236 TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17, 0x66);
237 tm6000_set_reg(dev,
238 TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18, 0x66);
239 tm6000_set_reg(dev,
240 TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19, 0x66);
241 tm6000_set_reg(dev,
242 TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20, 0x66);
243 tm6000_set_reg(dev,
244 TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x66);
245 tm6000_set_reg(dev,
246 TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22, 0x66);
247 tm6000_set_reg(dev,
248 TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23, 0x00);
249 tm6000_set_reg(dev,
250 TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES, 0x00);
251 tm6000_set_reg(dev,
252 TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01);
253 tm6000_set_reg(dev,
254 TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN, 0x00);
255 tm6000_set_reg(dev,
256 TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02);
257 tm6000_set_reg(dev, TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35);
258 tm6000_set_reg(dev, TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0);
259 tm6000_set_reg(dev, TM6010_REQ07_R5A_VBI_TELETEXT_DTO1, 0x11);
260 tm6000_set_reg(dev, TM6010_REQ07_R5B_VBI_TELETEXT_DTO0, 0x4c);
261 tm6000_set_reg(dev, TM6010_REQ07_R40_TELETEXT_VBI_CODE0, 0x01);
262 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
589851d5
MCC		 263 }
264}
265
266int tm6000_init_analog_mode(struct tm6000_core *dev)
267{
268 struct v4l2_frequency f;
269
270 if (dev->dev_type == TM6010) {
f010dca2 271 /* Enable video and audio */
8aff8ba9
DB		 272 tm6000_set_reg_mask(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF,
273 0x60, 0x60);
f010dca2 274 /* Disable TS input */
8aff8ba9
DB		 275 tm6000_set_reg_mask(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE,
276 0x00, 0x40);
9701dc94 277 } else {
29c389be 278 /* Enables soft reset */
9afec493 279 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
29c389be 280
52e0a72a 281 if (dev->scaler)
f010dca2 282 /* Disable Hfilter and Enable TS Drop err */
9afec493 283 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20);
52e0a72a 284 else /* Enable Hfilter and disable TS Drop err */
9afec493 285 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80);
9701dc94 286
9afec493 287 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x88);
9839029b 288 tm6000_set_reg(dev, TM6000_REQ07_RDA_CLK_SEL, 0x23);
9afec493
MCC		 289 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xc0);
290 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xd8);
291 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x06);
9839029b 292 tm6000_set_reg(dev, TM6000_REQ07_RDF_PWDOWN_ACLK, 0x1f);
9701dc94 293
29c389be 294 /* AP Software reset */
9afec493
MCC		 295 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
296 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
9701dc94 297
29c389be 298 tm6000_set_fourcc_format(dev);
9701dc94 299
29c389be 300 /* Disables soft reset */
9afec493 301 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
29c389be 302 }
9701dc94
MCC		 303 msleep(20);
304
29c389be
MCC		 305 /* Tuner firmware can now be loaded */
306
94d4350c
MCC		 307 /*
308 * FIXME: This is a hack! xc3028 "sleeps" when no channel is detected
309 * for more than a few seconds. Not sure why, as this behavior does
310 * not happen on other devices with xc3028. So, I suspect that it
311 * is yet another bug at tm6000. After start sleeping, decoding
312 * doesn't start automatically. Instead, it requires some
313 * I2C commands to wake it up. As we want to have image at the
314 * beginning, we needed to add this hack. The better would be to
315 * discover some way to make tm6000 to wake up without this hack.
316 */
52e0a72a 317 f.frequency = dev->freq;
427f7fac 318 v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f);
9701dc94
MCC		 319
320 msleep(100);
0f6040e8 321 tm6000_set_standard(dev);
589851d5 322 tm6000_set_vbi(dev);
52e0a72a 323 tm6000_set_audio_bitrate(dev, 48000);
9701dc94 324
f36cc034
SR		 325 /* switch dvb led off */
326 if (dev->gpio.dvb_led) {
327 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
328 dev->gpio.dvb_led, 0x01);
329 }
330
9701dc94
MCC		 331 return 0;
332}
333
52e0a72a 334int tm6000_init_digital_mode(struct tm6000_core *dev)
3169c9b2 335{
c733a4d5 336 if (dev->dev_type == TM6010) {
f010dca2
SR		 337 /* Disable video and audio */
338 tm6000_set_reg_mask(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF,
339 0x00, 0x60);
340 /* Enable TS input */
341 tm6000_set_reg_mask(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE,
342 0x40, 0x40);
343 /* all power down, but not the digital data port */
9afec493
MCC		 344 tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28);
345 tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc);
346 tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff);
c733a4d5 347 } else {
9afec493
MCC		 348 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
349 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
350 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
9839029b
SR		 351 tm6000_set_reg(dev, TM6000_REQ07_RDF_PWDOWN_ACLK, 0x08);
352 tm6000_set_reg(dev, TM6000_REQ07_RE2_VADC_STATUS_CTL, 0x0c);
353 tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0xff);
354 tm6000_set_reg(dev, TM6000_REQ07_REB_VADC_AADC_MODE, 0xd8);
9afec493
MCC		 355 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x40);
356 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
357 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x09);
9839029b 358 tm6000_set_reg(dev, TM6000_REQ07_RDA_CLK_SEL, 0x37);
9afec493
MCC		 359 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xd8);
360 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xc0);
361 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x60);
362
9839029b
SR		 363 tm6000_set_reg(dev, TM6000_REQ07_RE2_VADC_STATUS_CTL, 0x0c);
364 tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0xff);
365 tm6000_set_reg(dev, TM6000_REQ07_REB_VADC_AADC_MODE, 0x08);
c733a4d5
SR		 366 msleep(50);
367
52e0a72a 368 tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
c733a4d5 369 msleep(50);
52e0a72a 370 tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01);
c733a4d5 371 msleep(50);
52e0a72a 372 tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
c733a4d5
SR		 373 msleep(100);
374 }
f36cc034
SR		 375
376 /* switch dvb led on */
377 if (dev->gpio.dvb_led) {
378 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
379 dev->gpio.dvb_led, 0x00);
380 }
381
3169c9b2
ML		 382 return 0;
383}
cee3926f 384EXPORT_SYMBOL(tm6000_init_digital_mode);
9701dc94 385
29c389be
MCC		 386struct reg_init {
387 u8 req;
388 u8 reg;
389 u8 val;
390};
391
9701dc94 392/* The meaning of those initializations are unknown */
29c389be 393struct reg_init tm6000_init_tab[] = {
9701dc94 394 /* REG VALUE */
9839029b 395 { TM6000_REQ07_RDF_PWDOWN_ACLK, 0x1f },
9afec493
MCC		 396 { TM6010_REQ07_RFF_SOFT_RESET, 0x08 },
397 { TM6010_REQ07_RFF_SOFT_RESET, 0x00 },
398 { TM6010_REQ07_RD5_POWERSAVE, 0x4f },
9839029b
SR		 399 { TM6000_REQ07_RDA_CLK_SEL, 0x23 },
400 { TM6000_REQ07_RDB_OUT_SEL, 0x08 },
401 { TM6000_REQ07_RE2_VADC_STATUS_CTL, 0x00 },
402 { TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x10 },
403 { TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x00 },
404 { TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x00 },
405 { TM6000_REQ07_REB_VADC_AADC_MODE, 0x64 }, /* 48000 bits/sample, external input */
406 { TM6000_REQ07_REE_VADC_CTRL_SEL_CONTROL, 0xc2 },
407
9afec493
MCC		 408 { TM6010_REQ07_R3F_RESET, 0x01 }, /* Start of soft reset */
409 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
410 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
411 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
412 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
413 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
414 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
415 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
416 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
417 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
418 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
419 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
420 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
421 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
422 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
423 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
424 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
425 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
426 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
427 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
428 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
429 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
430 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
431 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
432 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
433 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
434 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
435 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
436 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
437 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
438 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
439 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
440 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
441 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
442 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
443 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
444 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
445 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
446 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
447 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
448 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
449 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
450 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
451 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
452 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
453 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
454 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
455 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
456 { TM6010_REQ07_RC3_HSTART1, 0x88 },
457 { TM6010_REQ07_R3F_RESET, 0x00 }, /* End of the soft reset */
2415a2c1 458 { TM6010_REQ05_R18_IMASK7, 0x00 },
29c389be
MCC		 459};
460
461struct reg_init tm6010_init_tab[] = {
9afec493
MCC		 462 { TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x00 },
463 { TM6010_REQ07_RC4_HSTART0, 0xa0 },
464 { TM6010_REQ07_RC6_HEND0, 0x40 },
465 { TM6010_REQ07_RCA_VEND0, 0x31 },
466 { TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0xe1 },
467 { TM6010_REQ07_RE0_DVIDEO_SOURCE, 0x03 },
468 { TM6010_REQ07_RFE_POWER_DOWN, 0x7f },
469
470 { TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0 },
471 { TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4 },
472 { TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8 },
473 { TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00 },
474 { TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2 },
475 { TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 },
476 { TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 },
477 { TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 },
478 { TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc },
479
480 { TM6010_REQ07_R3F_RESET, 0x01 },
481 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
482 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
483 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
484 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
485 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
486 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
487 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
488 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
489 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
490 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
491 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
492 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
493 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
494 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
495 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
496 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
497 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
498 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
499 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
500 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
501 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
502 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
503 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
504 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
505 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
506 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
507 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
508 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
509 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
510 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
511 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
512 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
513 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
514 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
515 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
516 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
517 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
518 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
519 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
520 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
521 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
522 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
523 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
524 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
525 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
526 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
527 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
528 { TM6010_REQ07_RC3_HSTART1, 0x88 },
529 { TM6010_REQ07_R3F_RESET, 0x00 },
29c389be 530
2415a2c1 531 { TM6010_REQ05_R18_IMASK7, 0x00 },
29c389be 532
9afec493
MCC		 533 { TM6010_REQ07_RD8_IR_LEADER1, 0xaa },
534 { TM6010_REQ07_RD8_IR_LEADER0, 0x30 },
535 { TM6010_REQ07_RD8_IR_PULSE_CNT1, 0x20 },
536 { TM6010_REQ07_RD8_IR_PULSE_CNT0, 0xd0 },
d46ca932 537 { REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 },
9afec493 538 { TM6010_REQ07_RD8_IR, 0x2f },
d46ca932 539
29c389be 540 /* set remote wakeup key:any key wakeup */
9afec493
MCC		 541 { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0xfe },
542 { TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0xff },
9701dc94
MCC		 543};
544
52e0a72a 545int tm6000_init(struct tm6000_core *dev)
9701dc94 546{
52e0a72a 547 int board, rc = 0, i, size;
29c389be
MCC		 548 struct reg_init *tab;
549
c1937f8e
SR		 550 /* Check board revision */
551 board = tm6000_get_reg32(dev, REQ_40_GET_VERSION, 0, 0);
552 if (board >= 0) {
553 switch (board & 0xff) {
554 case 0xf3:
555 printk(KERN_INFO "Found tm6000\n");
556 if (dev->dev_type != TM6000)
557 dev->dev_type = TM6000;
558 break;
559 case 0xf4:
560 printk(KERN_INFO "Found tm6010\n");
561 if (dev->dev_type != TM6010)
562 dev->dev_type = TM6010;
563 break;
564 default:
565 printk(KERN_INFO "Unknown board version = 0x%08x\n", board);
566 }
567 } else
568 printk(KERN_ERR "Error %i while retrieving board version\n", board);
569
29c389be
MCC		 570 if (dev->dev_type == TM6010) {
571 tab = tm6010_init_tab;
572 size = ARRAY_SIZE(tm6010_init_tab);
573 } else {
574 tab = tm6000_init_tab;
575 size = ARRAY_SIZE(tm6000_init_tab);
576 }
9701dc94 577
9701dc94 578 /* Load board's initialization table */
52e0a72a
TT		 579 for (i = 0; i < size; i++) {
580 rc = tm6000_set_reg(dev, tab[i].req, tab[i].reg, tab[i].val);
581 if (rc < 0) {
582 printk(KERN_ERR "Error %i while setting req %d, "
583 "reg %d to value %d\n", rc,
584 tab[i].req, tab[i].reg, tab[i].val);
9701dc94
MCC		 585 return rc;
586 }
587 }
588
29c389be
MCC		 589 msleep(5); /* Just to be conservative */
590
e3ee9e5e 591 rc = tm6000_cards_setup(dev);
a5adfbed 592
e3ee9e5e 593 return rc;
9701dc94
MCC		 594}
595
44351aa0 596int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate)
9701dc94 597{
8aff8ba9
DB		 598 int val = 0;
599 u8 areg_f0 = 0x60; /* ADC MCLK = 250 Fs */
600 u8 areg_0a = 0x91; /* SIF 48KHz */
601
602 switch (bitrate) {
603 case 48000:
604 areg_f0 = 0x60; /* ADC MCLK = 250 Fs */
605 areg_0a = 0x91; /* SIF 48KHz */
606 dev->audio_bitrate = bitrate;
607 break;
608 case 32000:
609 areg_f0 = 0x00; /* ADC MCLK = 375 Fs */
610 areg_0a = 0x90; /* SIF 32KHz */
611 dev->audio_bitrate = bitrate;
612 break;
613 default:
614 return -EINVAL;
615 }
616
9701dc94 617
9839029b 618 /* enable I2S, if we use sif or external I2S device */
a59bff37 619 if (dev->dev_type == TM6010) {
8aff8ba9 620 val = tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, areg_0a);
a59bff37
MCC		 621 if (val < 0)
622 return val;
a59bff37 623
8aff8ba9
DB		 624 val = tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
625 areg_f0, 0xf0);
9839029b
SR		 626 if (val < 0)
627 return val;
628 } else {
8aff8ba9
DB		 629 val = tm6000_set_reg_mask(dev, TM6000_REQ07_REB_VADC_AADC_MODE,
630 areg_f0, 0xf0);
9839029b
SR		 631 if (val < 0)
632 return val;
633 }
8aff8ba9
DB		 634 return 0;
635}
636EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);
9701dc94 637
0f6040e8 638int tm6000_set_audio_rinput(struct tm6000_core *dev)
8aff8ba9
DB		 639{
640 if (dev->dev_type == TM6010) {
641 /* Audio crossbar setting, default SIF1 */
fb7ef983 642 u8 areg_f0;
8aff8ba9 643
fb7ef983
SR		 644 switch (dev->rinput.amux) {
645 case TM6000_AMUX_SIF1:
646 case TM6000_AMUX_SIF2:
8aff8ba9
DB		 647 areg_f0 = 0x03;
648 break;
fb7ef983 649 case TM6000_AMUX_ADC1:
8aff8ba9
DB		 650 areg_f0 = 0x00;
651 break;
fb7ef983 652 case TM6000_AMUX_ADC2:
8aff8ba9
DB		 653 areg_f0 = 0x08;
654 break;
fb7ef983
SR		 655 case TM6000_AMUX_I2S:
656 areg_f0 = 0x04;
657 break;
8aff8ba9 658 default:
fb7ef983
SR		 659 printk(KERN_INFO "%s: audio input dosn't support\n",
660 dev->name);
8aff8ba9
DB		 661 return 0;
662 break;
663 }
664 /* Set audio input crossbar */
665 tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
666 areg_f0, 0x0f);
667 } else {
fb7ef983 668 u8 areg_eb;
8aff8ba9 669 /* Audio setting, default LINE1 */
fb7ef983
SR		 670 switch (dev->rinput.amux) {
671 case TM6000_AMUX_ADC1:
8aff8ba9
DB		 672 areg_eb = 0x00;
673 break;
fb7ef983 674 case TM6000_AMUX_ADC2:
8aff8ba9
DB		 675 areg_eb = 0x04;
676 break;
677 default:
fb7ef983
SR		 678 printk(KERN_INFO "%s: audio input dosn't support\n",
679 dev->name);
8aff8ba9
DB		 680 return 0;
681 break;
682 }
683 /* Set audio input */
684 tm6000_set_reg_mask(dev, TM6000_REQ07_REB_VADC_AADC_MODE,
685 areg_eb, 0x0f);
686 }
687 return 0;
688}
8aff8ba9
DB		 689
690void tm6010_set_mute_sif(struct tm6000_core *dev, u8 mute)
691{
692 u8 mute_reg = 0;
693
694 if (mute)
695 mute_reg = 0x08;
696
697 tm6000_set_reg_mask(dev, TM6010_REQ08_R0A_A_I2S_MOD, mute_reg, 0x08);
698}
699
700void tm6010_set_mute_adc(struct tm6000_core *dev, u8 mute)
701{
702 u8 mute_reg = 0;
703
704 if (mute)
705 mute_reg = 0x20;
706
707 if (dev->dev_type == TM6010) {
708 tm6000_set_reg_mask(dev, TM6010_REQ08_RF2_LEFT_CHANNEL_VOL,
709 mute_reg, 0x20);
710 tm6000_set_reg_mask(dev, TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL,
711 mute_reg, 0x20);
712 } else {
713 tm6000_set_reg_mask(dev, TM6000_REQ07_REC_VADC_AADC_LVOL,
714 mute_reg, 0x20);
715 tm6000_set_reg_mask(dev, TM6000_REQ07_RED_VADC_AADC_RVOL,
716 mute_reg, 0x20);
717 }
718}
719
720int tm6000_tvaudio_set_mute(struct tm6000_core *dev, u8 mute)
721{
fb7ef983 722 enum tm6000_mux mux;
8aff8ba9
DB		 723
724 if (dev->radio)
fb7ef983 725 mux = dev->rinput.amux;
8aff8ba9 726 else
fb7ef983 727 mux = dev->vinput[dev->input].amux;
8aff8ba9 728
fb7ef983
SR		 729 switch (mux) {
730 case TM6000_AMUX_SIF1:
731 case TM6000_AMUX_SIF2:
8aff8ba9
DB		 732 if (dev->dev_type == TM6010)
733 tm6010_set_mute_sif(dev, mute);
734 else {
735 printk(KERN_INFO "ERROR: TM5600 and TM6000 don't has"
736 " SIF audio inputs. Please check the %s"
737 " configuration.\n", dev->name);
738 return -EINVAL;
739 }
9701dc94 740 break;
fb7ef983
SR		 741 case TM6000_AMUX_ADC1:
742 case TM6000_AMUX_ADC2:
8aff8ba9
DB		 743 tm6010_set_mute_adc(dev, mute);
744 break;
745 default:
746 return -EINVAL;
9701dc94
MCC		 747 break;
748 }
8aff8ba9
DB		 749 return 0;
750}
8aff8ba9
DB		 751
752void tm6010_set_volume_sif(struct tm6000_core *dev, int vol)
753{
754 u8 vol_reg;
9701dc94 755
8aff8ba9
DB		 756 vol_reg = vol & 0x0F;
757
758 if (vol < 0)
759 vol_reg |= 0x40;
760
761 tm6000_set_reg(dev, TM6010_REQ08_R07_A_LEFT_VOL, vol_reg);
762 tm6000_set_reg(dev, TM6010_REQ08_R08_A_RIGHT_VOL, vol_reg);
9701dc94 763}
8aff8ba9
DB		 764
765void tm6010_set_volume_adc(struct tm6000_core *dev, int vol)
766{
767 u8 vol_reg;
768
769 vol_reg = (vol + 0x10) & 0x1f;
770
771 if (dev->dev_type == TM6010) {
772 tm6000_set_reg(dev, TM6010_REQ08_RF2_LEFT_CHANNEL_VOL, vol_reg);
773 tm6000_set_reg(dev, TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL, vol_reg);
774 } else {
775 tm6000_set_reg(dev, TM6000_REQ07_REC_VADC_AADC_LVOL, vol_reg);
776 tm6000_set_reg(dev, TM6000_REQ07_RED_VADC_AADC_RVOL, vol_reg);
777 }
778}
779
780void tm6000_set_volume(struct tm6000_core *dev, int vol)
781{
fb7ef983 782 enum tm6000_mux mux;
8aff8ba9
DB		 783
784 if (dev->radio) {
fb7ef983 785 mux = dev->rinput.amux;
8aff8ba9
DB		 786 vol += 8; /* Offset to 0 dB */
787 } else
fb7ef983 788 mux = dev->vinput[dev->input].amux;
8aff8ba9 789
fb7ef983
SR		 790 switch (mux) {
791 case TM6000_AMUX_SIF1:
792 case TM6000_AMUX_SIF2:
8aff8ba9
DB		 793 if (dev->dev_type == TM6010)
794 tm6010_set_volume_sif(dev, vol);
795 else
796 printk(KERN_INFO "ERROR: TM5600 and TM6000 don't has"
797 " SIF audio inputs. Please check the %s"
798 " configuration.\n", dev->name);
799 break;
fb7ef983
SR		 800 case TM6000_AMUX_ADC1:
801 case TM6000_AMUX_ADC2:
8aff8ba9
DB		 802 tm6010_set_volume_adc(dev, vol);
803 break;
804 default:
805 break;
806 }
807}
0439db75
SR		 808
809static LIST_HEAD(tm6000_devlist);
810static DEFINE_MUTEX(tm6000_devlist_mutex);
811
812/*
813 * tm6000_realease_resource()
814 */
815
816void tm6000_remove_from_devlist(struct tm6000_core *dev)
817{
818 mutex_lock(&tm6000_devlist_mutex);
819 list_del(&dev->devlist);
820 mutex_unlock(&tm6000_devlist_mutex);
821};
822
823void tm6000_add_into_devlist(struct tm6000_core *dev)
824{
825 mutex_lock(&tm6000_devlist_mutex);
826 list_add_tail(&dev->devlist, &tm6000_devlist);
827 mutex_unlock(&tm6000_devlist_mutex);
828};
829
830/*
831 * Extension interface
832 */
833
834static LIST_HEAD(tm6000_extension_devlist);
0439db75 835
b17b8699
MCC		 836int tm6000_call_fillbuf(struct tm6000_core *dev, enum tm6000_ops_type type,
837 char *buf, int size)
838{
839 struct tm6000_ops *ops = NULL;
840
841 /* FIXME: tm6000_extension_devlist_lock should be a spinlock */
842
843 if (!list_empty(&tm6000_extension_devlist)) {
844 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
845 if (ops->fillbuf && ops->type == type)
846 ops->fillbuf(dev, buf, size);
847 }
848 }
849
850 return 0;
851}
852
0439db75
SR		 853int tm6000_register_extension(struct tm6000_ops *ops)
854{
855 struct tm6000_core *dev = NULL;
856
857 mutex_lock(&tm6000_devlist_mutex);
0439db75
SR		 858 list_add_tail(&ops->next, &tm6000_extension_devlist);
859 list_for_each_entry(dev, &tm6000_devlist, devlist) {
3f23a81a
MCC		 860 ops->init(dev);
861 printk(KERN_INFO "%s: Initialized (%s) extension\n",
862 dev->name, ops->name);
0439db75 863 }
0439db75
SR		 864 mutex_unlock(&tm6000_devlist_mutex);
865 return 0;
866}
867EXPORT_SYMBOL(tm6000_register_extension);
868
869void tm6000_unregister_extension(struct tm6000_ops *ops)
870{
871 struct tm6000_core *dev = NULL;
872
873 mutex_lock(&tm6000_devlist_mutex);
a3d7fc5c
JL		 874 list_for_each_entry(dev, &tm6000_devlist, devlist)
875 ops->fini(dev);
0439db75 876
0439db75
SR		 877 printk(KERN_INFO "tm6000: Remove (%s) extension\n", ops->name);
878 list_del(&ops->next);
0439db75
SR		 879 mutex_unlock(&tm6000_devlist_mutex);
880}
881EXPORT_SYMBOL(tm6000_unregister_extension);
882
883void tm6000_init_extension(struct tm6000_core *dev)
884{
885 struct tm6000_ops *ops = NULL;
886
4ae18398 887 mutex_lock(&tm6000_devlist_mutex);
0439db75
SR		 888 if (!list_empty(&tm6000_extension_devlist)) {
889 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
890 if (ops->init)
891 ops->init(dev);
892 }
893 }
4ae18398 894 mutex_unlock(&tm6000_devlist_mutex);
0439db75
SR		 895}
896
897void tm6000_close_extension(struct tm6000_core *dev)
898{
899 struct tm6000_ops *ops = NULL;
900
4ae18398 901 mutex_lock(&tm6000_devlist_mutex);
0439db75
SR		 902 if (!list_empty(&tm6000_extension_devlist)) {
903 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
904 if (ops->fini)
905 ops->fini(dev);
906 }
907 }
427aacfe 908 mutex_unlock(&tm6000_devlist_mutex);
0439db75 909}
Linux 6.x block layer and io_uring tree(s)