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6280238c ORL |
1 | /* |
2 | * _chnl_sm.h | |
3 | * | |
4 | * DSP-BIOS Bridge driver support functions for TI OMAP processors. | |
5 | * | |
6 | * Private header file defining channel manager and channel objects for | |
7 | * a shared memory channel driver. | |
8 | * | |
9 | * Shared between the modules implementing the shared memory channel class | |
10 | * library. | |
11 | * | |
12 | * Copyright (C) 2005-2006 Texas Instruments, Inc. | |
13 | * | |
14 | * This package is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | * | |
18 | * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR | |
19 | * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED | |
20 | * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
21 | */ | |
22 | ||
23 | #ifndef _CHNL_SM_ | |
24 | #define _CHNL_SM_ | |
25 | ||
26 | #include <dspbridge/dspapi.h> | |
27 | #include <dspbridge/dspdefs.h> | |
28 | ||
3c6bf30f | 29 | #include <linux/list.h> |
6280238c ORL |
30 | #include <dspbridge/ntfy.h> |
31 | ||
32 | /* | |
33 | * These target side symbols define the beginning and ending addresses | |
34 | * of shared memory buffer. They are defined in the *cfg.cmd file by | |
35 | * cdb code. | |
36 | */ | |
37 | #define CHNL_SHARED_BUFFER_BASE_SYM "_SHM_BEG" | |
38 | #define CHNL_SHARED_BUFFER_LIMIT_SYM "_SHM_END" | |
39 | #define BRIDGEINIT_BIOSGPTIMER "_BRIDGEINIT_BIOSGPTIMER" | |
40 | #define BRIDGEINIT_LOADMON_GPTIMER "_BRIDGEINIT_LOADMON_GPTIMER" | |
41 | ||
42 | #ifndef _CHNL_WORDSIZE | |
43 | #define _CHNL_WORDSIZE 4 /* default _CHNL_WORDSIZE is 2 bytes/word */ | |
44 | #endif | |
45 | ||
46 | #define MAXOPPS 16 | |
47 | ||
48 | /* Shared memory config options */ | |
49 | #define SHM_CURROPP 0 /* Set current OPP in shm */ | |
50 | #define SHM_OPPINFO 1 /* Set dsp voltage and freq table values */ | |
51 | #define SHM_GETOPP 2 /* Get opp requested by DSP */ | |
52 | ||
53 | struct opp_table_entry { | |
54 | u32 voltage; | |
55 | u32 frequency; | |
56 | u32 min_freq; | |
57 | u32 max_freq; | |
58 | }; | |
59 | ||
60 | struct opp_struct { | |
61 | u32 curr_opp_pt; | |
62 | u32 num_opp_pts; | |
63 | struct opp_table_entry opp_point[MAXOPPS]; | |
64 | }; | |
65 | ||
66 | /* Request to MPU */ | |
67 | struct opp_rqst_struct { | |
68 | u32 rqst_dsp_freq; | |
69 | u32 rqst_opp_pt; | |
70 | }; | |
71 | ||
72 | /* Info to MPU */ | |
73 | struct load_mon_struct { | |
74 | u32 curr_dsp_load; | |
75 | u32 curr_dsp_freq; | |
76 | u32 pred_dsp_load; | |
77 | u32 pred_dsp_freq; | |
78 | }; | |
79 | ||
80 | /* Structure in shared between DSP and PC for communication. */ | |
81 | struct shm { | |
82 | u32 dsp_free_mask; /* Written by DSP, read by PC. */ | |
83 | u32 host_free_mask; /* Written by PC, read by DSP */ | |
84 | ||
85 | u32 input_full; /* Input channel has unread data. */ | |
86 | u32 input_id; /* Channel for which input is available. */ | |
87 | u32 input_size; /* Size of data block (in DSP words). */ | |
88 | ||
89 | u32 output_full; /* Output channel has unread data. */ | |
90 | u32 output_id; /* Channel for which output is available. */ | |
91 | u32 output_size; /* Size of data block (in DSP words). */ | |
92 | ||
93 | u32 arg; /* Arg for Issue/Reclaim (23 bits for 55x). */ | |
94 | u32 resvd; /* Keep structure size even for 32-bit DSPs */ | |
95 | ||
96 | /* Operating Point structure */ | |
97 | struct opp_struct opp_table_struct; | |
98 | /* Operating Point Request structure */ | |
99 | struct opp_rqst_struct opp_request; | |
100 | /* load monitor information structure */ | |
101 | struct load_mon_struct load_mon_info; | |
b3d23688 | 102 | #ifdef CONFIG_TIDSPBRIDGE_WDT3 |
6280238c ORL |
103 | /* Flag for WDT enable/disable F/I clocks */ |
104 | u32 wdt_setclocks; | |
105 | u32 wdt_overflow; /* WDT overflow time */ | |
106 | char dummy[176]; /* padding to 256 byte boundary */ | |
107 | #else | |
108 | char dummy[184]; /* padding to 256 byte boundary */ | |
109 | #endif | |
110 | u32 shm_dbg_var[64]; /* shared memory debug variables */ | |
111 | }; | |
112 | ||
113 | /* Channel Manager: only one created per board: */ | |
114 | struct chnl_mgr { | |
115 | /* Function interface to Bridge driver */ | |
116 | struct bridge_drv_interface *intf_fxns; | |
121e8f9b | 117 | struct io_mgr *iomgr; /* IO manager */ |
6280238c | 118 | /* Device this board represents */ |
085467b8 | 119 | struct dev_object *dev_obj; |
6280238c ORL |
120 | |
121 | /* These fields initialized in bridge_chnl_create(): */ | |
5108de0a RS |
122 | u32 output_mask; /* Host output channels w/ full buffers */ |
123 | u32 last_output; /* Last output channel fired from DPC */ | |
6280238c ORL |
124 | /* Critical section object handle */ |
125 | spinlock_t chnl_mgr_lock; | |
126 | u32 word_size; /* Size in bytes of DSP word */ | |
127 | u8 max_channels; /* Total number of channels */ | |
128 | u8 open_channels; /* Total number of open channels */ | |
121e8f9b | 129 | struct chnl_object **channels; /* Array of channels */ |
3c882de5 | 130 | u8 type; /* Type of channel class library */ |
6280238c ORL |
131 | /* If no shm syms, return for CHNL_Open */ |
132 | int chnl_open_status; | |
133 | }; | |
134 | ||
135 | /* | |
136 | * Channel: up to CHNL_MAXCHANNELS per board or if DSP-DMA supported then | |
137 | * up to CHNL_MAXCHANNELS + CHNL_MAXDDMACHNLS per board. | |
138 | */ | |
139 | struct chnl_object { | |
140 | /* Pointer back to channel manager */ | |
141 | struct chnl_mgr *chnl_mgr_obj; | |
142 | u32 chnl_id; /* Channel id */ | |
3c882de5 | 143 | u8 state; /* Current channel state */ |
6280238c ORL |
144 | s8 chnl_mode; /* Chnl mode and attributes */ |
145 | /* Chnl I/O completion event (user mode) */ | |
146 | void *user_event; | |
25985edc | 147 | /* Abstract synchronization object */ |
6280238c ORL |
148 | struct sync_object *sync_event; |
149 | u32 process; /* Process which created this channel */ | |
ee4317f7 | 150 | u32 cb_arg; /* Argument to use with callback */ |
121e8f9b | 151 | struct list_head io_requests; /* List of IOR's to driver */ |
6280238c ORL |
152 | s32 cio_cs; /* Number of IOC's in queue */ |
153 | s32 cio_reqs; /* Number of IORequests in queue */ | |
154 | s32 chnl_packets; /* Initial number of free Irps */ | |
155 | /* List of IOC's from driver */ | |
121e8f9b | 156 | struct list_head io_completions; |
3c6bf30f | 157 | struct list_head free_packets_list; /* List of free Irps */ |
6280238c | 158 | struct ntfy_object *ntfy_obj; |
25985edc | 159 | u32 bytes_moved; /* Total number of bytes transferred */ |
6280238c ORL |
160 | |
161 | /* For DSP-DMA */ | |
162 | ||
163 | /* Type of chnl transport:CHNL_[PCPY][DDMA] */ | |
164 | u32 chnl_type; | |
165 | }; | |
166 | ||
167 | /* I/O Request/completion packet: */ | |
168 | struct chnl_irp { | |
169 | struct list_head link; /* Link to next CHIRP in queue. */ | |
170 | /* Buffer to be filled/emptied. (User) */ | |
171 | u8 *host_user_buf; | |
172 | /* Buffer to be filled/emptied. (System) */ | |
173 | u8 *host_sys_buf; | |
b4da7fc3 | 174 | u32 arg; /* Issue/Reclaim argument. */ |
6280238c ORL |
175 | u32 dsp_tx_addr; /* Transfer address on DSP side. */ |
176 | u32 byte_size; /* Bytes transferred. */ | |
177 | u32 buf_size; /* Actual buffer size when allocated. */ | |
178 | u32 status; /* Status of IO completion. */ | |
179 | }; | |
180 | ||
181 | #endif /* _CHNL_SM_ */ |