projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 81dee67e SM |
1 | #ifndef DDK750_REG_H__ |
| 2 | #define DDK750_REG_H__ | |
| 3 | ||
| 4 | /* New register for SM750LE */ | |
| 5 | #define DE_STATE1 0x100054 | |
| c808d6ce | 6 | #define DE_STATE1_DE_ABORT BIT(0) |
| 81dee67e SM |
7 | |
| 8 | #define DE_STATE2 0x100058 | |
| ae6061db MR |
9 | #define DE_STATE2_DE_FIFO_EMPTY BIT(3) |
| 10 | #define DE_STATE2_DE_STATUS_BUSY BIT(2) | |
| 11 | #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1) | |
| 81dee67e SM |
12 | |
| 13 | #define SYSTEM_CTRL 0x000000 | |
| a8856ff8 MR |
14 | #define SYSTEM_CTRL_DPMS_MASK (0x3 << 30) |
| 15 | #define SYSTEM_CTRL_DPMS_VPHP (0x0 << 30) | |
| 16 | #define SYSTEM_CTRL_DPMS_VPHN (0x1 << 30) | |
| 17 | #define SYSTEM_CTRL_DPMS_VNHP (0x2 << 30) | |
| 18 | #define SYSTEM_CTRL_DPMS_VNHN (0x3 << 30) | |
| 410c756d MR |
19 | #define SYSTEM_CTRL_PCI_BURST BIT(29) |
| 20 | #define SYSTEM_CTRL_PCI_MASTER BIT(25) | |
| 21 | #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24) | |
| 22 | #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23) | |
| 23 | #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22) | |
| 24 | #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21) | |
| 25 | #define SYSTEM_CTRL_CSC_STATUS_BUSY BIT(20) | |
| 26 | #define SYSTEM_CTRL_CRT_VSYNC_ACTIVE BIT(19) | |
| 27 | #define SYSTEM_CTRL_PANEL_VSYNC_ACTIVE BIT(18) | |
| 28 | #define SYSTEM_CTRL_CURRENT_BUFFER_FLIP_PENDING BIT(17) | |
| 29 | #define SYSTEM_CTRL_DMA_STATUS_BUSY BIT(16) | |
| 30 | #define SYSTEM_CTRL_PCI_BURST_READ BIT(15) | |
| 31 | #define SYSTEM_CTRL_DE_ABORT BIT(13) | |
| 32 | #define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK BIT(11) | |
| 33 | #define SYSTEM_CTRL_PCI_RETRY_OFF BIT(7) | |
| a8856ff8 MR |
34 | #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_MASK (0x3 << 4) |
| 35 | #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1 (0x0 << 4) | |
| 36 | #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2 (0x1 << 4) | |
| 37 | #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4 (0x2 << 4) | |
| 38 | #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8 (0x3 << 4) | |
| 410c756d MR |
39 | #define SYSTEM_CTRL_CRT_TRISTATE BIT(3) |
| 40 | #define SYSTEM_CTRL_PCIMEM_TRISTATE BIT(2) | |
| 41 | #define SYSTEM_CTRL_LOCALMEM_TRISTATE BIT(1) | |
| 42 | #define SYSTEM_CTRL_PANEL_TRISTATE BIT(0) | |
| 81dee67e SM |
43 | |
| 44 | #define MISC_CTRL 0x000004 | |
| 5372350b | 45 | #define MISC_CTRL_DRAM_RERESH_COUNT BIT(27) |
| 5538d5c8 MR |
46 | #define MISC_CTRL_DRAM_REFRESH_TIME_MASK (0x3 << 25) |
| 47 | #define MISC_CTRL_DRAM_REFRESH_TIME_8 (0x0 << 25) | |
| 48 | #define MISC_CTRL_DRAM_REFRESH_TIME_16 (0x1 << 25) | |
| 49 | #define MISC_CTRL_DRAM_REFRESH_TIME_32 (0x2 << 25) | |
| 50 | #define MISC_CTRL_DRAM_REFRESH_TIME_64 (0x3 << 25) | |
| 5372350b MR |
51 | #define MISC_CTRL_INT_OUTPUT_INVERT BIT(24) |
| 52 | #define MISC_CTRL_PLL_CLK_COUNT BIT(23) | |
| 53 | #define MISC_CTRL_DAC_POWER_OFF BIT(20) | |
| 54 | #define MISC_CTRL_CLK_SELECT_TESTCLK BIT(16) | |
| 5538d5c8 MR |
55 | #define MISC_CTRL_DRAM_COLUMN_SIZE_MASK (0x3 << 14) |
| 56 | #define MISC_CTRL_DRAM_COLUMN_SIZE_256 (0x0 << 14) | |
| 57 | #define MISC_CTRL_DRAM_COLUMN_SIZE_512 (0x1 << 14) | |
| 58 | #define MISC_CTRL_DRAM_COLUMN_SIZE_1024 (0x2 << 14) | |
| 59 | #define MISC_CTRL_LOCALMEM_SIZE_MASK (0x3 << 12) | |
| 60 | #define MISC_CTRL_LOCALMEM_SIZE_8M (0x3 << 12) | |
| 61 | #define MISC_CTRL_LOCALMEM_SIZE_16M (0x0 << 12) | |
| 62 | #define MISC_CTRL_LOCALMEM_SIZE_32M (0x1 << 12) | |
| 63 | #define MISC_CTRL_LOCALMEM_SIZE_64M (0x2 << 12) | |
| 5372350b MR |
64 | #define MISC_CTRL_DRAM_TWTR BIT(11) |
| 65 | #define MISC_CTRL_DRAM_TWR BIT(10) | |
| 66 | #define MISC_CTRL_DRAM_TRP BIT(9) | |
| 67 | #define MISC_CTRL_DRAM_TRFC BIT(8) | |
| 68 | #define MISC_CTRL_DRAM_TRAS BIT(7) | |
| 69 | #define MISC_CTRL_LOCALMEM_RESET BIT(6) | |
| 70 | #define MISC_CTRL_LOCALMEM_STATE_INACTIVE BIT(5) | |
| 71 | #define MISC_CTRL_CPU_CAS_LATENCY BIT(4) | |
| 72 | #define MISC_CTRL_DLL_OFF BIT(3) | |
| 73 | #define MISC_CTRL_DRAM_OUTPUT_HIGH BIT(2) | |
| 74 | #define MISC_CTRL_LOCALMEM_BUS_SIZE BIT(1) | |
| 75 | #define MISC_CTRL_EMBEDDED_LOCALMEM_OFF BIT(0) | |
| 81dee67e SM |
76 | |
| 77 | #define GPIO_MUX 0x000008 | |
| 2a5149e0 MR |
78 | #define GPIO_MUX_31 BIT(31) |
| 79 | #define GPIO_MUX_30 BIT(30) | |
| 80 | #define GPIO_MUX_29 BIT(29) | |
| 81 | #define GPIO_MUX_28 BIT(28) | |
| 82 | #define GPIO_MUX_27 BIT(27) | |
| 83 | #define GPIO_MUX_26 BIT(26) | |
| 84 | #define GPIO_MUX_25 BIT(25) | |
| 85 | #define GPIO_MUX_24 BIT(24) | |
| 86 | #define GPIO_MUX_23 BIT(23) | |
| 87 | #define GPIO_MUX_22 BIT(22) | |
| 88 | #define GPIO_MUX_21 BIT(21) | |
| 89 | #define GPIO_MUX_20 BIT(20) | |
| 90 | #define GPIO_MUX_19 BIT(19) | |
| 91 | #define GPIO_MUX_18 BIT(18) | |
| 92 | #define GPIO_MUX_17 BIT(17) | |
| 93 | #define GPIO_MUX_16 BIT(16) | |
| 94 | #define GPIO_MUX_15 BIT(15) | |
| 95 | #define GPIO_MUX_14 BIT(14) | |
| 96 | #define GPIO_MUX_13 BIT(13) | |
| 97 | #define GPIO_MUX_12 BIT(12) | |
| 98 | #define GPIO_MUX_11 BIT(11) | |
| 99 | #define GPIO_MUX_10 BIT(10) | |
| 100 | #define GPIO_MUX_9 BIT(9) | |
| 101 | #define GPIO_MUX_8 BIT(8) | |
| 102 | #define GPIO_MUX_7 BIT(7) | |
| 103 | #define GPIO_MUX_6 BIT(6) | |
| 104 | #define GPIO_MUX_5 BIT(5) | |
| 105 | #define GPIO_MUX_4 BIT(4) | |
| 106 | #define GPIO_MUX_3 BIT(3) | |
| 107 | #define GPIO_MUX_2 BIT(2) | |
| 108 | #define GPIO_MUX_1 BIT(1) | |
| 109 | #define GPIO_MUX_0 BIT(0) | |
| 81dee67e SM |
110 | |
| 111 | #define LOCALMEM_ARBITRATION 0x00000C | |
| 112 | #define LOCALMEM_ARBITRATION_ROTATE 28:28 | |
| 113 | #define LOCALMEM_ARBITRATION_ROTATE_OFF 0 | |
| 114 | #define LOCALMEM_ARBITRATION_ROTATE_ON 1 | |
| 115 | #define LOCALMEM_ARBITRATION_VGA 26:24 | |
| 116 | #define LOCALMEM_ARBITRATION_VGA_OFF 0 | |
| 117 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_1 1 | |
| 118 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_2 2 | |
| 119 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_3 3 | |
| 120 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_4 4 | |
| 121 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_5 5 | |
| 122 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_6 6 | |
| 123 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_7 7 | |
| 124 | #define LOCALMEM_ARBITRATION_DMA 22:20 | |
| 125 | #define LOCALMEM_ARBITRATION_DMA_OFF 0 | |
| 126 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_1 1 | |
| 127 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_2 2 | |
| 128 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_3 3 | |
| 129 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_4 4 | |
| 130 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_5 5 | |
| 131 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_6 6 | |
| 132 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_7 7 | |
| 133 | #define LOCALMEM_ARBITRATION_ZVPORT1 18:16 | |
| 134 | #define LOCALMEM_ARBITRATION_ZVPORT1_OFF 0 | |
| 135 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_1 1 | |
| 136 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_2 2 | |
| 137 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_3 3 | |
| 138 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_4 4 | |
| 139 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_5 5 | |
| 140 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_6 6 | |
| 141 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_7 7 | |
| 142 | #define LOCALMEM_ARBITRATION_ZVPORT0 14:12 | |
| 143 | #define LOCALMEM_ARBITRATION_ZVPORT0_OFF 0 | |
| 144 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_1 1 | |
| 145 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_2 2 | |
| 146 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_3 3 | |
| 147 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_4 4 | |
| 148 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_5 5 | |
| 149 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_6 6 | |
| 150 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_7 7 | |
| 151 | #define LOCALMEM_ARBITRATION_VIDEO 10:8 | |
| 152 | #define LOCALMEM_ARBITRATION_VIDEO_OFF 0 | |
| 153 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_1 1 | |
| 154 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_2 2 | |
| 155 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_3 3 | |
| 156 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_4 4 | |
| 157 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_5 5 | |
| 158 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_6 6 | |
| 159 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_7 7 | |
| 160 | #define LOCALMEM_ARBITRATION_PANEL 6:4 | |
| 161 | #define LOCALMEM_ARBITRATION_PANEL_OFF 0 | |
| 162 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_1 1 | |
| 163 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_2 2 | |
| 164 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_3 3 | |
| 165 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_4 4 | |
| 166 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_5 5 | |
| 167 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_6 6 | |
| 168 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_7 7 | |
| 169 | #define LOCALMEM_ARBITRATION_CRT 2:0 | |
| 170 | #define LOCALMEM_ARBITRATION_CRT_OFF 0 | |
| 171 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_1 1 | |
| 172 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_2 2 | |
| 173 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_3 3 | |
| 174 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_4 4 | |
| 175 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_5 5 | |
| 176 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_6 6 | |
| 177 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_7 7 | |
| 178 | ||
| 179 | #define PCIMEM_ARBITRATION 0x000010 | |
| 180 | #define PCIMEM_ARBITRATION_ROTATE 28:28 | |
| 181 | #define PCIMEM_ARBITRATION_ROTATE_OFF 0 | |
| 182 | #define PCIMEM_ARBITRATION_ROTATE_ON 1 | |
| 183 | #define PCIMEM_ARBITRATION_VGA 26:24 | |
| 184 | #define PCIMEM_ARBITRATION_VGA_OFF 0 | |
| 185 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_1 1 | |
| 186 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_2 2 | |
| 187 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_3 3 | |
| 188 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_4 4 | |
| 189 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_5 5 | |
| 190 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_6 6 | |
| 191 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_7 7 | |
| 192 | #define PCIMEM_ARBITRATION_DMA 22:20 | |
| 193 | #define PCIMEM_ARBITRATION_DMA_OFF 0 | |
| 194 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_1 1 | |
| 195 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_2 2 | |
| 196 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_3 3 | |
| 197 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_4 4 | |
| 198 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_5 5 | |
| 199 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_6 6 | |
| 200 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_7 7 | |
| 201 | #define PCIMEM_ARBITRATION_ZVPORT1 18:16 | |
| 202 | #define PCIMEM_ARBITRATION_ZVPORT1_OFF 0 | |
| 203 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_1 1 | |
| 204 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_2 2 | |
| 205 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_3 3 | |
| 206 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_4 4 | |
| 207 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_5 5 | |
| 208 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_6 6 | |
| 209 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_7 7 | |
| 210 | #define PCIMEM_ARBITRATION_ZVPORT0 14:12 | |
| 211 | #define PCIMEM_ARBITRATION_ZVPORT0_OFF 0 | |
| 212 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_1 1 | |
| 213 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_2 2 | |
| 214 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_3 3 | |
| 215 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_4 4 | |
| 216 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_5 5 | |
| 217 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_6 6 | |
| 218 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_7 7 | |
| 219 | #define PCIMEM_ARBITRATION_VIDEO 10:8 | |
| 220 | #define PCIMEM_ARBITRATION_VIDEO_OFF 0 | |
| 221 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_1 1 | |
| 222 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_2 2 | |
| 223 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_3 3 | |
| 224 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_4 4 | |
| 225 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_5 5 | |
| 226 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_6 6 | |
| 227 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_7 7 | |
| 228 | #define PCIMEM_ARBITRATION_PANEL 6:4 | |
| 229 | #define PCIMEM_ARBITRATION_PANEL_OFF 0 | |
| 230 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_1 1 | |
| 231 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_2 2 | |
| 232 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_3 3 | |
| 233 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_4 4 | |
| 234 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_5 5 | |
| 235 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_6 6 | |
| 236 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_7 7 | |
| 237 | #define PCIMEM_ARBITRATION_CRT 2:0 | |
| 238 | #define PCIMEM_ARBITRATION_CRT_OFF 0 | |
| 239 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_1 1 | |
| 240 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_2 2 | |
| 241 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_3 3 | |
| 242 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_4 4 | |
| 243 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_5 5 | |
| 244 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_6 6 | |
| 245 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_7 7 | |
| 246 | ||
| 247 | #define RAW_INT 0x000020 | |
| 248 | #define RAW_INT_ZVPORT1_VSYNC 4:4 | |
| 249 | #define RAW_INT_ZVPORT1_VSYNC_INACTIVE 0 | |
| 250 | #define RAW_INT_ZVPORT1_VSYNC_ACTIVE 1 | |
| 251 | #define RAW_INT_ZVPORT1_VSYNC_CLEAR 1 | |
| 252 | #define RAW_INT_ZVPORT0_VSYNC 3:3 | |
| 253 | #define RAW_INT_ZVPORT0_VSYNC_INACTIVE 0 | |
| 254 | #define RAW_INT_ZVPORT0_VSYNC_ACTIVE 1 | |
| 255 | #define RAW_INT_ZVPORT0_VSYNC_CLEAR 1 | |
| 256 | #define RAW_INT_CRT_VSYNC 2:2 | |
| 257 | #define RAW_INT_CRT_VSYNC_INACTIVE 0 | |
| 258 | #define RAW_INT_CRT_VSYNC_ACTIVE 1 | |
| 259 | #define RAW_INT_CRT_VSYNC_CLEAR 1 | |
| 260 | #define RAW_INT_PANEL_VSYNC 1:1 | |
| 261 | #define RAW_INT_PANEL_VSYNC_INACTIVE 0 | |
| 262 | #define RAW_INT_PANEL_VSYNC_ACTIVE 1 | |
| 263 | #define RAW_INT_PANEL_VSYNC_CLEAR 1 | |
| 264 | #define RAW_INT_VGA_VSYNC 0:0 | |
| 265 | #define RAW_INT_VGA_VSYNC_INACTIVE 0 | |
| 266 | #define RAW_INT_VGA_VSYNC_ACTIVE 1 | |
| 267 | #define RAW_INT_VGA_VSYNC_CLEAR 1 | |
| 268 | ||
| 269 | #define INT_STATUS 0x000024 | |
| 270 | #define INT_STATUS_GPIO31 31:31 | |
| 271 | #define INT_STATUS_GPIO31_INACTIVE 0 | |
| 272 | #define INT_STATUS_GPIO31_ACTIVE 1 | |
| 273 | #define INT_STATUS_GPIO30 30:30 | |
| 274 | #define INT_STATUS_GPIO30_INACTIVE 0 | |
| 275 | #define INT_STATUS_GPIO30_ACTIVE 1 | |
| 276 | #define INT_STATUS_GPIO29 29:29 | |
| 277 | #define INT_STATUS_GPIO29_INACTIVE 0 | |
| 278 | #define INT_STATUS_GPIO29_ACTIVE 1 | |
| 279 | #define INT_STATUS_GPIO28 28:28 | |
| 280 | #define INT_STATUS_GPIO28_INACTIVE 0 | |
| 281 | #define INT_STATUS_GPIO28_ACTIVE 1 | |
| 282 | #define INT_STATUS_GPIO27 27:27 | |
| 283 | #define INT_STATUS_GPIO27_INACTIVE 0 | |
| 284 | #define INT_STATUS_GPIO27_ACTIVE 1 | |
| 285 | #define INT_STATUS_GPIO26 26:26 | |
| 286 | #define INT_STATUS_GPIO26_INACTIVE 0 | |
| 287 | #define INT_STATUS_GPIO26_ACTIVE 1 | |
| 288 | #define INT_STATUS_GPIO25 25:25 | |
| 289 | #define INT_STATUS_GPIO25_INACTIVE 0 | |
| 290 | #define INT_STATUS_GPIO25_ACTIVE 1 | |
| 291 | #define INT_STATUS_I2C 12:12 | |
| 292 | #define INT_STATUS_I2C_INACTIVE 0 | |
| 293 | #define INT_STATUS_I2C_ACTIVE 1 | |
| 294 | #define INT_STATUS_PWM 11:11 | |
| 295 | #define INT_STATUS_PWM_INACTIVE 0 | |
| 296 | #define INT_STATUS_PWM_ACTIVE 1 | |
| 297 | #define INT_STATUS_DMA1 10:10 | |
| 298 | #define INT_STATUS_DMA1_INACTIVE 0 | |
| 299 | #define INT_STATUS_DMA1_ACTIVE 1 | |
| 300 | #define INT_STATUS_DMA0 9:9 | |
| 301 | #define INT_STATUS_DMA0_INACTIVE 0 | |
| 302 | #define INT_STATUS_DMA0_ACTIVE 1 | |
| 303 | #define INT_STATUS_PCI 8:8 | |
| 304 | #define INT_STATUS_PCI_INACTIVE 0 | |
| 305 | #define INT_STATUS_PCI_ACTIVE 1 | |
| 306 | #define INT_STATUS_SSP1 7:7 | |
| 307 | #define INT_STATUS_SSP1_INACTIVE 0 | |
| 308 | #define INT_STATUS_SSP1_ACTIVE 1 | |
| 309 | #define INT_STATUS_SSP0 6:6 | |
| 310 | #define INT_STATUS_SSP0_INACTIVE 0 | |
| 311 | #define INT_STATUS_SSP0_ACTIVE 1 | |
| 312 | #define INT_STATUS_DE 5:5 | |
| 313 | #define INT_STATUS_DE_INACTIVE 0 | |
| 314 | #define INT_STATUS_DE_ACTIVE 1 | |
| 315 | #define INT_STATUS_ZVPORT1_VSYNC 4:4 | |
| 316 | #define INT_STATUS_ZVPORT1_VSYNC_INACTIVE 0 | |
| 317 | #define INT_STATUS_ZVPORT1_VSYNC_ACTIVE 1 | |
| 318 | #define INT_STATUS_ZVPORT0_VSYNC 3:3 | |
| 319 | #define INT_STATUS_ZVPORT0_VSYNC_INACTIVE 0 | |
| 320 | #define INT_STATUS_ZVPORT0_VSYNC_ACTIVE 1 | |
| 321 | #define INT_STATUS_CRT_VSYNC 2:2 | |
| 322 | #define INT_STATUS_CRT_VSYNC_INACTIVE 0 | |
| 323 | #define INT_STATUS_CRT_VSYNC_ACTIVE 1 | |
| 324 | #define INT_STATUS_PANEL_VSYNC 1:1 | |
| 325 | #define INT_STATUS_PANEL_VSYNC_INACTIVE 0 | |
| 326 | #define INT_STATUS_PANEL_VSYNC_ACTIVE 1 | |
| 327 | #define INT_STATUS_VGA_VSYNC 0:0 | |
| 328 | #define INT_STATUS_VGA_VSYNC_INACTIVE 0 | |
| 329 | #define INT_STATUS_VGA_VSYNC_ACTIVE 1 | |
| 330 | ||
| 331 | #define INT_MASK 0x000028 | |
| 332 | #define INT_MASK_GPIO31 31:31 | |
| 333 | #define INT_MASK_GPIO31_DISABLE 0 | |
| 334 | #define INT_MASK_GPIO31_ENABLE 1 | |
| 335 | #define INT_MASK_GPIO30 30:30 | |
| 336 | #define INT_MASK_GPIO30_DISABLE 0 | |
| 337 | #define INT_MASK_GPIO30_ENABLE 1 | |
| 338 | #define INT_MASK_GPIO29 29:29 | |
| 339 | #define INT_MASK_GPIO29_DISABLE 0 | |
| 340 | #define INT_MASK_GPIO29_ENABLE 1 | |
| 341 | #define INT_MASK_GPIO28 28:28 | |
| 342 | #define INT_MASK_GPIO28_DISABLE 0 | |
| 343 | #define INT_MASK_GPIO28_ENABLE 1 | |
| 344 | #define INT_MASK_GPIO27 27:27 | |
| 345 | #define INT_MASK_GPIO27_DISABLE 0 | |
| 346 | #define INT_MASK_GPIO27_ENABLE 1 | |
| 347 | #define INT_MASK_GPIO26 26:26 | |
| 348 | #define INT_MASK_GPIO26_DISABLE 0 | |
| 349 | #define INT_MASK_GPIO26_ENABLE 1 | |
| 350 | #define INT_MASK_GPIO25 25:25 | |
| 351 | #define INT_MASK_GPIO25_DISABLE 0 | |
| 352 | #define INT_MASK_GPIO25_ENABLE 1 | |
| 353 | #define INT_MASK_I2C 12:12 | |
| 354 | #define INT_MASK_I2C_DISABLE 0 | |
| 355 | #define INT_MASK_I2C_ENABLE 1 | |
| 356 | #define INT_MASK_PWM 11:11 | |
| 357 | #define INT_MASK_PWM_DISABLE 0 | |
| 358 | #define INT_MASK_PWM_ENABLE 1 | |
| 359 | #define INT_MASK_DMA1 10:10 | |
| 360 | #define INT_MASK_DMA1_DISABLE 0 | |
| 361 | #define INT_MASK_DMA1_ENABLE 1 | |
| 362 | #define INT_MASK_DMA 9:9 | |
| 363 | #define INT_MASK_DMA_DISABLE 0 | |
| 364 | #define INT_MASK_DMA_ENABLE 1 | |
| 365 | #define INT_MASK_PCI 8:8 | |
| 366 | #define INT_MASK_PCI_DISABLE 0 | |
| 367 | #define INT_MASK_PCI_ENABLE 1 | |
| 368 | #define INT_MASK_SSP1 7:7 | |
| 369 | #define INT_MASK_SSP1_DISABLE 0 | |
| 370 | #define INT_MASK_SSP1_ENABLE 1 | |
| 371 | #define INT_MASK_SSP0 6:6 | |
| 372 | #define INT_MASK_SSP0_DISABLE 0 | |
| 373 | #define INT_MASK_SSP0_ENABLE 1 | |
| 374 | #define INT_MASK_DE 5:5 | |
| 375 | #define INT_MASK_DE_DISABLE 0 | |
| 376 | #define INT_MASK_DE_ENABLE 1 | |
| 377 | #define INT_MASK_ZVPORT1_VSYNC 4:4 | |
| 378 | #define INT_MASK_ZVPORT1_VSYNC_DISABLE 0 | |
| 379 | #define INT_MASK_ZVPORT1_VSYNC_ENABLE 1 | |
| 380 | #define INT_MASK_ZVPORT0_VSYNC 3:3 | |
| 381 | #define INT_MASK_ZVPORT0_VSYNC_DISABLE 0 | |
| 382 | #define INT_MASK_ZVPORT0_VSYNC_ENABLE 1 | |
| 383 | #define INT_MASK_CRT_VSYNC 2:2 | |
| 384 | #define INT_MASK_CRT_VSYNC_DISABLE 0 | |
| 385 | #define INT_MASK_CRT_VSYNC_ENABLE 1 | |
| 386 | #define INT_MASK_PANEL_VSYNC 1:1 | |
| 387 | #define INT_MASK_PANEL_VSYNC_DISABLE 0 | |
| 388 | #define INT_MASK_PANEL_VSYNC_ENABLE 1 | |
| 389 | #define INT_MASK_VGA_VSYNC 0:0 | |
| 390 | #define INT_MASK_VGA_VSYNC_DISABLE 0 | |
| 391 | #define INT_MASK_VGA_VSYNC_ENABLE 1 | |
| 392 | ||
| 393 | #define CURRENT_GATE 0x000040 | |
| 6e8aa4a1 | 394 | #define CURRENT_GATE_MCLK_MASK (0x3 << 14) |
| 81dee67e | 395 | #ifdef VALIDATION_CHIP |
| 6e8aa4a1 MR |
396 | #define CURRENT_GATE_MCLK_112MHZ (0x0 << 14) |
| 397 | #define CURRENT_GATE_MCLK_84MHZ (0x1 << 14) | |
| 398 | #define CURRENT_GATE_MCLK_56MHZ (0x2 << 14) | |
| 399 | #define CURRENT_GATE_MCLK_42MHZ (0x3 << 14) | |
| 81dee67e | 400 | #else |
| 6e8aa4a1 MR |
401 | #define CURRENT_GATE_MCLK_DIV_3 (0x0 << 14) |
| 402 | #define CURRENT_GATE_MCLK_DIV_4 (0x1 << 14) | |
| 403 | #define CURRENT_GATE_MCLK_DIV_6 (0x2 << 14) | |
| 404 | #define CURRENT_GATE_MCLK_DIV_8 (0x3 << 14) | |
| 81dee67e | 405 | #endif |
| 6e8aa4a1 | 406 | #define CURRENT_GATE_M2XCLK_MASK (0x3 << 12) |
| 81dee67e | 407 | #ifdef VALIDATION_CHIP |
| 6e8aa4a1 MR |
408 | #define CURRENT_GATE_M2XCLK_336MHZ (0x0 << 12) |
| 409 | #define CURRENT_GATE_M2XCLK_168MHZ (0x1 << 12) | |
| 410 | #define CURRENT_GATE_M2XCLK_112MHZ (0x2 << 12) | |
| 411 | #define CURRENT_GATE_M2XCLK_84MHZ (0x3 << 12) | |
| 81dee67e | 412 | #else |
| 6e8aa4a1 MR |
413 | #define CURRENT_GATE_M2XCLK_DIV_1 (0x0 << 12) |
| 414 | #define CURRENT_GATE_M2XCLK_DIV_2 (0x1 << 12) | |
| 415 | #define CURRENT_GATE_M2XCLK_DIV_3 (0x2 << 12) | |
| 416 | #define CURRENT_GATE_M2XCLK_DIV_4 (0x3 << 12) | |
| 81dee67e | 417 | #endif |
| 90946e52 MR |
418 | #define CURRENT_GATE_VGA BIT(10) |
| 419 | #define CURRENT_GATE_PWM BIT(9) | |
| 420 | #define CURRENT_GATE_I2C BIT(8) | |
| 421 | #define CURRENT_GATE_SSP BIT(7) | |
| 422 | #define CURRENT_GATE_GPIO BIT(6) | |
| 423 | #define CURRENT_GATE_ZVPORT BIT(5) | |
| 424 | #define CURRENT_GATE_CSC BIT(4) | |
| 425 | #define CURRENT_GATE_DE BIT(3) | |
| 426 | #define CURRENT_GATE_DISPLAY BIT(2) | |
| 427 | #define CURRENT_GATE_LOCALMEM BIT(1) | |
| 428 | #define CURRENT_GATE_DMA BIT(0) | |
| 81dee67e SM |
429 | |
| 430 | #define MODE0_GATE 0x000044 | |
| a9412451 MR |
431 | #define MODE0_GATE_MCLK_MASK (0x3 << 14) |
| 432 | #define MODE0_GATE_MCLK_112MHZ (0x0 << 14) | |
| 433 | #define MODE0_GATE_MCLK_84MHZ (0x1 << 14) | |
| 434 | #define MODE0_GATE_MCLK_56MHZ (0x2 << 14) | |
| 435 | #define MODE0_GATE_MCLK_42MHZ (0x3 << 14) | |
| 436 | #define MODE0_GATE_M2XCLK_MASK (0x3 << 12) | |
| 437 | #define MODE0_GATE_M2XCLK_336MHZ (0x0 << 12) | |
| 438 | #define MODE0_GATE_M2XCLK_168MHZ (0x1 << 12) | |
| 439 | #define MODE0_GATE_M2XCLK_112MHZ (0x2 << 12) | |
| 440 | #define MODE0_GATE_M2XCLK_84MHZ (0x3 << 12) | |
| 05e9d9ea MR |
441 | #define MODE0_GATE_VGA BIT(10) |
| 442 | #define MODE0_GATE_PWM BIT(9) | |
| 443 | #define MODE0_GATE_I2C BIT(8) | |
| 444 | #define MODE0_GATE_SSP BIT(7) | |
| 445 | #define MODE0_GATE_GPIO BIT(6) | |
| 446 | #define MODE0_GATE_ZVPORT BIT(5) | |
| 447 | #define MODE0_GATE_CSC BIT(4) | |
| 448 | #define MODE0_GATE_DE BIT(3) | |
| 449 | #define MODE0_GATE_DISPLAY BIT(2) | |
| 450 | #define MODE0_GATE_LOCALMEM BIT(1) | |
| 451 | #define MODE0_GATE_DMA BIT(0) | |
| 81dee67e SM |
452 | |
| 453 | #define MODE1_GATE 0x000048 | |
| 454 | #define MODE1_GATE_MCLK 15:14 | |
| 455 | #define MODE1_GATE_MCLK_112MHZ 0 | |
| 456 | #define MODE1_GATE_MCLK_84MHZ 1 | |
| 457 | #define MODE1_GATE_MCLK_56MHZ 2 | |
| 458 | #define MODE1_GATE_MCLK_42MHZ 3 | |
| 459 | #define MODE1_GATE_M2XCLK 13:12 | |
| 460 | #define MODE1_GATE_M2XCLK_336MHZ 0 | |
| 461 | #define MODE1_GATE_M2XCLK_168MHZ 1 | |
| 462 | #define MODE1_GATE_M2XCLK_112MHZ 2 | |
| 463 | #define MODE1_GATE_M2XCLK_84MHZ 3 | |
| 464 | #define MODE1_GATE_VGA 10:10 | |
| 465 | #define MODE1_GATE_VGA_OFF 0 | |
| 466 | #define MODE1_GATE_VGA_ON 1 | |
| 467 | #define MODE1_GATE_PWM 9:9 | |
| 468 | #define MODE1_GATE_PWM_OFF 0 | |
| 469 | #define MODE1_GATE_PWM_ON 1 | |
| 470 | #define MODE1_GATE_I2C 8:8 | |
| 471 | #define MODE1_GATE_I2C_OFF 0 | |
| 472 | #define MODE1_GATE_I2C_ON 1 | |
| 473 | #define MODE1_GATE_SSP 7:7 | |
| 474 | #define MODE1_GATE_SSP_OFF 0 | |
| 475 | #define MODE1_GATE_SSP_ON 1 | |
| 476 | #define MODE1_GATE_GPIO 6:6 | |
| 477 | #define MODE1_GATE_GPIO_OFF 0 | |
| 478 | #define MODE1_GATE_GPIO_ON 1 | |
| 479 | #define MODE1_GATE_ZVPORT 5:5 | |
| 480 | #define MODE1_GATE_ZVPORT_OFF 0 | |
| 481 | #define MODE1_GATE_ZVPORT_ON 1 | |
| 482 | #define MODE1_GATE_CSC 4:4 | |
| 483 | #define MODE1_GATE_CSC_OFF 0 | |
| 484 | #define MODE1_GATE_CSC_ON 1 | |
| 485 | #define MODE1_GATE_DE 3:3 | |
| 486 | #define MODE1_GATE_DE_OFF 0 | |
| 487 | #define MODE1_GATE_DE_ON 1 | |
| 488 | #define MODE1_GATE_DISPLAY 2:2 | |
| 489 | #define MODE1_GATE_DISPLAY_OFF 0 | |
| 490 | #define MODE1_GATE_DISPLAY_ON 1 | |
| 491 | #define MODE1_GATE_LOCALMEM 1:1 | |
| 492 | #define MODE1_GATE_LOCALMEM_OFF 0 | |
| 493 | #define MODE1_GATE_LOCALMEM_ON 1 | |
| 494 | #define MODE1_GATE_DMA 0:0 | |
| 495 | #define MODE1_GATE_DMA_OFF 0 | |
| 496 | #define MODE1_GATE_DMA_ON 1 | |
| 497 | ||
| 498 | #define POWER_MODE_CTRL 0x00004C | |
| 499 | #ifdef VALIDATION_CHIP | |
| 776980cf | 500 | #define POWER_MODE_CTRL_336CLK BIT(4) |
| 81dee67e | 501 | #endif |
| 776980cf MR |
502 | #define POWER_MODE_CTRL_OSC_INPUT BIT(3) |
| 503 | #define POWER_MODE_CTRL_ACPI BIT(2) | |
| f41b17fc MR |
504 | #define POWER_MODE_CTRL_MODE_MASK (0x3 << 0) |
| 505 | #define POWER_MODE_CTRL_MODE_MODE0 (0x0 << 0) | |
| 506 | #define POWER_MODE_CTRL_MODE_MODE1 (0x1 << 0) | |
| 507 | #define POWER_MODE_CTRL_MODE_SLEEP (0x2 << 0) | |
| 81dee67e SM |
508 | |
| 509 | #define PCI_MASTER_BASE 0x000050 | |
| 510 | #define PCI_MASTER_BASE_ADDRESS 7:0 | |
| 511 | ||
| 512 | #define DEVICE_ID 0x000054 | |
| 513 | #define DEVICE_ID_DEVICE_ID 31:16 | |
| 514 | #define DEVICE_ID_REVISION_ID 7:0 | |
| 515 | ||
| 516 | #define PLL_CLK_COUNT 0x000058 | |
| 517 | #define PLL_CLK_COUNT_COUNTER 15:0 | |
| 518 | ||
| 519 | #define PANEL_PLL_CTRL 0x00005C | |
| 5557eb17 MR |
520 | #define PLL_CTRL_BYPASS BIT(18) |
| 521 | #define PLL_CTRL_POWER BIT(17) | |
| 522 | #define PLL_CTRL_INPUT BIT(16) | |
| 81dee67e | 523 | #ifdef VALIDATION_CHIP |
| cdd5df64 MR |
524 | #define PLL_CTRL_OD_SHIFT 14 |
| 525 | #define PLL_CTRL_OD_MASK (0x3 << 14) | |
| 81dee67e | 526 | #else |
| cdd5df64 MR |
527 | #define PLL_CTRL_POD_SHIFT 14 |
| 528 | #define PLL_CTRL_POD_MASK (0x3 << 14) | |
| 529 | #define PLL_CTRL_OD_SHIFT 12 | |
| 530 | #define PLL_CTRL_OD_MASK (0x3 << 12) | |
| 81dee67e | 531 | #endif |
| cdd5df64 MR |
532 | #define PLL_CTRL_N_SHIFT 8 |
| 533 | #define PLL_CTRL_N_MASK (0xf << 8) | |
| 534 | #define PLL_CTRL_M_SHIFT 0 | |
| 535 | #define PLL_CTRL_M_MASK 0xff | |
| 81dee67e SM |
536 | |
| 537 | #define CRT_PLL_CTRL 0x000060 | |
| 81dee67e SM |
538 | |
| 539 | #define VGA_PLL0_CTRL 0x000064 | |
| 81dee67e SM |
540 | |
| 541 | #define VGA_PLL1_CTRL 0x000068 | |
| 81dee67e SM |
542 | |
| 543 | #define SCRATCH_DATA 0x00006c | |
| 544 | ||
| 545 | #ifndef VALIDATION_CHIP | |
| 546 | ||
| 547 | #define MXCLK_PLL_CTRL 0x000070 | |
| 81dee67e SM |
548 | |
| 549 | #define VGA_CONFIGURATION 0x000088 | |
| e6f10d28 | 550 | #define VGA_CONFIGURATION_USER_DEFINE_MASK (0x3 << 4) |
| d9798143 MR |
551 | #define VGA_CONFIGURATION_PLL BIT(2) |
| 552 | #define VGA_CONFIGURATION_MODE BIT(1) | |
| 81dee67e SM |
553 | |
| 554 | #endif | |
| 555 | ||
| 556 | #define GPIO_DATA 0x010000 | |
| 557 | #define GPIO_DATA_31 31:31 | |
| 558 | #define GPIO_DATA_30 30:30 | |
| 559 | #define GPIO_DATA_29 29:29 | |
| 560 | #define GPIO_DATA_28 28:28 | |
| 561 | #define GPIO_DATA_27 27:27 | |
| 562 | #define GPIO_DATA_26 26:26 | |
| 563 | #define GPIO_DATA_25 25:25 | |
| 564 | #define GPIO_DATA_24 24:24 | |
| 565 | #define GPIO_DATA_23 23:23 | |
| 566 | #define GPIO_DATA_22 22:22 | |
| 567 | #define GPIO_DATA_21 21:21 | |
| 568 | #define GPIO_DATA_20 20:20 | |
| 569 | #define GPIO_DATA_19 19:19 | |
| 570 | #define GPIO_DATA_18 18:18 | |
| 571 | #define GPIO_DATA_17 17:17 | |
| 572 | #define GPIO_DATA_16 16:16 | |
| 573 | #define GPIO_DATA_15 15:15 | |
| 574 | #define GPIO_DATA_14 14:14 | |
| 575 | #define GPIO_DATA_13 13:13 | |
| 576 | #define GPIO_DATA_12 12:12 | |
| 577 | #define GPIO_DATA_11 11:11 | |
| 578 | #define GPIO_DATA_10 10:10 | |
| 579 | #define GPIO_DATA_9 9:9 | |
| 580 | #define GPIO_DATA_8 8:8 | |
| 581 | #define GPIO_DATA_7 7:7 | |
| 582 | #define GPIO_DATA_6 6:6 | |
| 583 | #define GPIO_DATA_5 5:5 | |
| 584 | #define GPIO_DATA_4 4:4 | |
| 585 | #define GPIO_DATA_3 3:3 | |
| 586 | #define GPIO_DATA_2 2:2 | |
| 587 | #define GPIO_DATA_1 1:1 | |
| 588 | #define GPIO_DATA_0 0:0 | |
| 589 | ||
| 590 | #define GPIO_DATA_DIRECTION 0x010004 | |
| 591 | #define GPIO_DATA_DIRECTION_31 31:31 | |
| 592 | #define GPIO_DATA_DIRECTION_31_INPUT 0 | |
| 593 | #define GPIO_DATA_DIRECTION_31_OUTPUT 1 | |
| 594 | #define GPIO_DATA_DIRECTION_30 30:30 | |
| 595 | #define GPIO_DATA_DIRECTION_30_INPUT 0 | |
| 596 | #define GPIO_DATA_DIRECTION_30_OUTPUT 1 | |
| 597 | #define GPIO_DATA_DIRECTION_29 29:29 | |
| 598 | #define GPIO_DATA_DIRECTION_29_INPUT 0 | |
| 599 | #define GPIO_DATA_DIRECTION_29_OUTPUT 1 | |
| 600 | #define GPIO_DATA_DIRECTION_28 28:28 | |
| 601 | #define GPIO_DATA_DIRECTION_28_INPUT 0 | |
| 602 | #define GPIO_DATA_DIRECTION_28_OUTPUT 1 | |
| 603 | #define GPIO_DATA_DIRECTION_27 27:27 | |
| 604 | #define GPIO_DATA_DIRECTION_27_INPUT 0 | |
| 605 | #define GPIO_DATA_DIRECTION_27_OUTPUT 1 | |
| 606 | #define GPIO_DATA_DIRECTION_26 26:26 | |
| 607 | #define GPIO_DATA_DIRECTION_26_INPUT 0 | |
| 608 | #define GPIO_DATA_DIRECTION_26_OUTPUT 1 | |
| 609 | #define GPIO_DATA_DIRECTION_25 25:25 | |
| 610 | #define GPIO_DATA_DIRECTION_25_INPUT 0 | |
| 611 | #define GPIO_DATA_DIRECTION_25_OUTPUT 1 | |
| 612 | #define GPIO_DATA_DIRECTION_24 24:24 | |
| 613 | #define GPIO_DATA_DIRECTION_24_INPUT 0 | |
| 614 | #define GPIO_DATA_DIRECTION_24_OUTPUT 1 | |
| 615 | #define GPIO_DATA_DIRECTION_23 23:23 | |
| 616 | #define GPIO_DATA_DIRECTION_23_INPUT 0 | |
| 617 | #define GPIO_DATA_DIRECTION_23_OUTPUT 1 | |
| 618 | #define GPIO_DATA_DIRECTION_22 22:22 | |
| 619 | #define GPIO_DATA_DIRECTION_22_INPUT 0 | |
| 620 | #define GPIO_DATA_DIRECTION_22_OUTPUT 1 | |
| 621 | #define GPIO_DATA_DIRECTION_21 21:21 | |
| 622 | #define GPIO_DATA_DIRECTION_21_INPUT 0 | |
| 623 | #define GPIO_DATA_DIRECTION_21_OUTPUT 1 | |
| 624 | #define GPIO_DATA_DIRECTION_20 20:20 | |
| 625 | #define GPIO_DATA_DIRECTION_20_INPUT 0 | |
| 626 | #define GPIO_DATA_DIRECTION_20_OUTPUT 1 | |
| 627 | #define GPIO_DATA_DIRECTION_19 19:19 | |
| 628 | #define GPIO_DATA_DIRECTION_19_INPUT 0 | |
| 629 | #define GPIO_DATA_DIRECTION_19_OUTPUT 1 | |
| 630 | #define GPIO_DATA_DIRECTION_18 18:18 | |
| 631 | #define GPIO_DATA_DIRECTION_18_INPUT 0 | |
| 632 | #define GPIO_DATA_DIRECTION_18_OUTPUT 1 | |
| 633 | #define GPIO_DATA_DIRECTION_17 17:17 | |
| 634 | #define GPIO_DATA_DIRECTION_17_INPUT 0 | |
| 635 | #define GPIO_DATA_DIRECTION_17_OUTPUT 1 | |
| 636 | #define GPIO_DATA_DIRECTION_16 16:16 | |
| 637 | #define GPIO_DATA_DIRECTION_16_INPUT 0 | |
| 638 | #define GPIO_DATA_DIRECTION_16_OUTPUT 1 | |
| 639 | #define GPIO_DATA_DIRECTION_15 15:15 | |
| 640 | #define GPIO_DATA_DIRECTION_15_INPUT 0 | |
| 641 | #define GPIO_DATA_DIRECTION_15_OUTPUT 1 | |
| 642 | #define GPIO_DATA_DIRECTION_14 14:14 | |
| 643 | #define GPIO_DATA_DIRECTION_14_INPUT 0 | |
| 644 | #define GPIO_DATA_DIRECTION_14_OUTPUT 1 | |
| 645 | #define GPIO_DATA_DIRECTION_13 13:13 | |
| 646 | #define GPIO_DATA_DIRECTION_13_INPUT 0 | |
| 647 | #define GPIO_DATA_DIRECTION_13_OUTPUT 1 | |
| 648 | #define GPIO_DATA_DIRECTION_12 12:12 | |
| 649 | #define GPIO_DATA_DIRECTION_12_INPUT 0 | |
| 650 | #define GPIO_DATA_DIRECTION_12_OUTPUT 1 | |
| 651 | #define GPIO_DATA_DIRECTION_11 11:11 | |
| 652 | #define GPIO_DATA_DIRECTION_11_INPUT 0 | |
| 653 | #define GPIO_DATA_DIRECTION_11_OUTPUT 1 | |
| 654 | #define GPIO_DATA_DIRECTION_10 10:10 | |
| 655 | #define GPIO_DATA_DIRECTION_10_INPUT 0 | |
| 656 | #define GPIO_DATA_DIRECTION_10_OUTPUT 1 | |
| 657 | #define GPIO_DATA_DIRECTION_9 9:9 | |
| 658 | #define GPIO_DATA_DIRECTION_9_INPUT 0 | |
| 659 | #define GPIO_DATA_DIRECTION_9_OUTPUT 1 | |
| 660 | #define GPIO_DATA_DIRECTION_8 8:8 | |
| 661 | #define GPIO_DATA_DIRECTION_8_INPUT 0 | |
| 662 | #define GPIO_DATA_DIRECTION_8_OUTPUT 1 | |
| 663 | #define GPIO_DATA_DIRECTION_7 7:7 | |
| 664 | #define GPIO_DATA_DIRECTION_7_INPUT 0 | |
| 665 | #define GPIO_DATA_DIRECTION_7_OUTPUT 1 | |
| 666 | #define GPIO_DATA_DIRECTION_6 6:6 | |
| 667 | #define GPIO_DATA_DIRECTION_6_INPUT 0 | |
| 668 | #define GPIO_DATA_DIRECTION_6_OUTPUT 1 | |
| 669 | #define GPIO_DATA_DIRECTION_5 5:5 | |
| 670 | #define GPIO_DATA_DIRECTION_5_INPUT 0 | |
| 671 | #define GPIO_DATA_DIRECTION_5_OUTPUT 1 | |
| 672 | #define GPIO_DATA_DIRECTION_4 4:4 | |
| 673 | #define GPIO_DATA_DIRECTION_4_INPUT 0 | |
| 674 | #define GPIO_DATA_DIRECTION_4_OUTPUT 1 | |
| 675 | #define GPIO_DATA_DIRECTION_3 3:3 | |
| 676 | #define GPIO_DATA_DIRECTION_3_INPUT 0 | |
| 677 | #define GPIO_DATA_DIRECTION_3_OUTPUT 1 | |
| 678 | #define GPIO_DATA_DIRECTION_2 2:2 | |
| 679 | #define GPIO_DATA_DIRECTION_2_INPUT 0 | |
| 680 | #define GPIO_DATA_DIRECTION_2_OUTPUT 1 | |
| 681 | #define GPIO_DATA_DIRECTION_1 131 | |
| 682 | #define GPIO_DATA_DIRECTION_1_INPUT 0 | |
| 683 | #define GPIO_DATA_DIRECTION_1_OUTPUT 1 | |
| 684 | #define GPIO_DATA_DIRECTION_0 0:0 | |
| 685 | #define GPIO_DATA_DIRECTION_0_INPUT 0 | |
| 686 | #define GPIO_DATA_DIRECTION_0_OUTPUT 1 | |
| 687 | ||
| 688 | #define GPIO_INTERRUPT_SETUP 0x010008 | |
| 689 | #define GPIO_INTERRUPT_SETUP_TRIGGER_31 22:22 | |
| 690 | #define GPIO_INTERRUPT_SETUP_TRIGGER_31_EDGE 0 | |
| 691 | #define GPIO_INTERRUPT_SETUP_TRIGGER_31_LEVEL 1 | |
| 692 | #define GPIO_INTERRUPT_SETUP_TRIGGER_30 21:21 | |
| 693 | #define GPIO_INTERRUPT_SETUP_TRIGGER_30_EDGE 0 | |
| 694 | #define GPIO_INTERRUPT_SETUP_TRIGGER_30_LEVEL 1 | |
| 695 | #define GPIO_INTERRUPT_SETUP_TRIGGER_29 20:20 | |
| 696 | #define GPIO_INTERRUPT_SETUP_TRIGGER_29_EDGE 0 | |
| 697 | #define GPIO_INTERRUPT_SETUP_TRIGGER_29_LEVEL 1 | |
| 698 | #define GPIO_INTERRUPT_SETUP_TRIGGER_28 19:19 | |
| 699 | #define GPIO_INTERRUPT_SETUP_TRIGGER_28_EDGE 0 | |
| 700 | #define GPIO_INTERRUPT_SETUP_TRIGGER_28_LEVEL 1 | |
| 701 | #define GPIO_INTERRUPT_SETUP_TRIGGER_27 18:18 | |
| 702 | #define GPIO_INTERRUPT_SETUP_TRIGGER_27_EDGE 0 | |
| 703 | #define GPIO_INTERRUPT_SETUP_TRIGGER_27_LEVEL 1 | |
| 704 | #define GPIO_INTERRUPT_SETUP_TRIGGER_26 17:17 | |
| 705 | #define GPIO_INTERRUPT_SETUP_TRIGGER_26_EDGE 0 | |
| 706 | #define GPIO_INTERRUPT_SETUP_TRIGGER_26_LEVEL 1 | |
| 707 | #define GPIO_INTERRUPT_SETUP_TRIGGER_25 16:16 | |
| 708 | #define GPIO_INTERRUPT_SETUP_TRIGGER_25_EDGE 0 | |
| 709 | #define GPIO_INTERRUPT_SETUP_TRIGGER_25_LEVEL 1 | |
| 710 | #define GPIO_INTERRUPT_SETUP_ACTIVE_31 14:14 | |
| 711 | #define GPIO_INTERRUPT_SETUP_ACTIVE_31_LOW 0 | |
| 712 | #define GPIO_INTERRUPT_SETUP_ACTIVE_31_HIGH 1 | |
| 713 | #define GPIO_INTERRUPT_SETUP_ACTIVE_30 13:13 | |
| 714 | #define GPIO_INTERRUPT_SETUP_ACTIVE_30_LOW 0 | |
| 715 | #define GPIO_INTERRUPT_SETUP_ACTIVE_30_HIGH 1 | |
| 716 | #define GPIO_INTERRUPT_SETUP_ACTIVE_29 12:12 | |
| 717 | #define GPIO_INTERRUPT_SETUP_ACTIVE_29_LOW 0 | |
| 718 | #define GPIO_INTERRUPT_SETUP_ACTIVE_29_HIGH 1 | |
| 719 | #define GPIO_INTERRUPT_SETUP_ACTIVE_28 11:11 | |
| 720 | #define GPIO_INTERRUPT_SETUP_ACTIVE_28_LOW 0 | |
| 721 | #define GPIO_INTERRUPT_SETUP_ACTIVE_28_HIGH 1 | |
| 722 | #define GPIO_INTERRUPT_SETUP_ACTIVE_27 10:10 | |
| 723 | #define GPIO_INTERRUPT_SETUP_ACTIVE_27_LOW 0 | |
| 724 | #define GPIO_INTERRUPT_SETUP_ACTIVE_27_HIGH 1 | |
| 725 | #define GPIO_INTERRUPT_SETUP_ACTIVE_26 9:9 | |
| 726 | #define GPIO_INTERRUPT_SETUP_ACTIVE_26_LOW 0 | |
| 727 | #define GPIO_INTERRUPT_SETUP_ACTIVE_26_HIGH 1 | |
| 728 | #define GPIO_INTERRUPT_SETUP_ACTIVE_25 8:8 | |
| 729 | #define GPIO_INTERRUPT_SETUP_ACTIVE_25_LOW 0 | |
| 730 | #define GPIO_INTERRUPT_SETUP_ACTIVE_25_HIGH 1 | |
| 731 | #define GPIO_INTERRUPT_SETUP_ENABLE_31 6:6 | |
| 732 | #define GPIO_INTERRUPT_SETUP_ENABLE_31_GPIO 0 | |
| 733 | #define GPIO_INTERRUPT_SETUP_ENABLE_31_INTERRUPT 1 | |
| 734 | #define GPIO_INTERRUPT_SETUP_ENABLE_30 5:5 | |
| 735 | #define GPIO_INTERRUPT_SETUP_ENABLE_30_GPIO 0 | |
| 736 | #define GPIO_INTERRUPT_SETUP_ENABLE_30_INTERRUPT 1 | |
| 737 | #define GPIO_INTERRUPT_SETUP_ENABLE_29 4:4 | |
| 738 | #define GPIO_INTERRUPT_SETUP_ENABLE_29_GPIO 0 | |
| 739 | #define GPIO_INTERRUPT_SETUP_ENABLE_29_INTERRUPT 1 | |
| 740 | #define GPIO_INTERRUPT_SETUP_ENABLE_28 3:3 | |
| 741 | #define GPIO_INTERRUPT_SETUP_ENABLE_28_GPIO 0 | |
| 742 | #define GPIO_INTERRUPT_SETUP_ENABLE_28_INTERRUPT 1 | |
| 743 | #define GPIO_INTERRUPT_SETUP_ENABLE_27 2:2 | |
| 744 | #define GPIO_INTERRUPT_SETUP_ENABLE_27_GPIO 0 | |
| 745 | #define GPIO_INTERRUPT_SETUP_ENABLE_27_INTERRUPT 1 | |
| 746 | #define GPIO_INTERRUPT_SETUP_ENABLE_26 1:1 | |
| 747 | #define GPIO_INTERRUPT_SETUP_ENABLE_26_GPIO 0 | |
| 748 | #define GPIO_INTERRUPT_SETUP_ENABLE_26_INTERRUPT 1 | |
| 749 | #define GPIO_INTERRUPT_SETUP_ENABLE_25 0:0 | |
| 750 | #define GPIO_INTERRUPT_SETUP_ENABLE_25_GPIO 0 | |
| 751 | #define GPIO_INTERRUPT_SETUP_ENABLE_25_INTERRUPT 1 | |
| 752 | ||
| 753 | #define GPIO_INTERRUPT_STATUS 0x01000C | |
| 754 | #define GPIO_INTERRUPT_STATUS_31 22:22 | |
| 755 | #define GPIO_INTERRUPT_STATUS_31_INACTIVE 0 | |
| 756 | #define GPIO_INTERRUPT_STATUS_31_ACTIVE 1 | |
| 757 | #define GPIO_INTERRUPT_STATUS_31_RESET 1 | |
| 758 | #define GPIO_INTERRUPT_STATUS_30 21:21 | |
| 759 | #define GPIO_INTERRUPT_STATUS_30_INACTIVE 0 | |
| 760 | #define GPIO_INTERRUPT_STATUS_30_ACTIVE 1 | |
| 761 | #define GPIO_INTERRUPT_STATUS_30_RESET 1 | |
| 762 | #define GPIO_INTERRUPT_STATUS_29 20:20 | |
| 763 | #define GPIO_INTERRUPT_STATUS_29_INACTIVE 0 | |
| 764 | #define GPIO_INTERRUPT_STATUS_29_ACTIVE 1 | |
| 765 | #define GPIO_INTERRUPT_STATUS_29_RESET 1 | |
| 766 | #define GPIO_INTERRUPT_STATUS_28 19:19 | |
| 767 | #define GPIO_INTERRUPT_STATUS_28_INACTIVE 0 | |
| 768 | #define GPIO_INTERRUPT_STATUS_28_ACTIVE 1 | |
| 769 | #define GPIO_INTERRUPT_STATUS_28_RESET 1 | |
| 770 | #define GPIO_INTERRUPT_STATUS_27 18:18 | |
| 771 | #define GPIO_INTERRUPT_STATUS_27_INACTIVE 0 | |
| 772 | #define GPIO_INTERRUPT_STATUS_27_ACTIVE 1 | |
| 773 | #define GPIO_INTERRUPT_STATUS_27_RESET 1 | |
| 774 | #define GPIO_INTERRUPT_STATUS_26 17:17 | |
| 775 | #define GPIO_INTERRUPT_STATUS_26_INACTIVE 0 | |
| 776 | #define GPIO_INTERRUPT_STATUS_26_ACTIVE 1 | |
| 777 | #define GPIO_INTERRUPT_STATUS_26_RESET 1 | |
| 778 | #define GPIO_INTERRUPT_STATUS_25 16:16 | |
| 779 | #define GPIO_INTERRUPT_STATUS_25_INACTIVE 0 | |
| 780 | #define GPIO_INTERRUPT_STATUS_25_ACTIVE 1 | |
| 781 | #define GPIO_INTERRUPT_STATUS_25_RESET 1 | |
| 782 | ||
| 783 | ||
| 784 | #define PANEL_DISPLAY_CTRL 0x080000 | |
| 9bd2c86b | 785 | #define PANEL_DISPLAY_CTRL_RESERVED_MASK 0xc0f08000 |
| c4e893b7 MR |
786 | #define PANEL_DISPLAY_CTRL_SELECT_SHIFT 28 |
| 787 | #define PANEL_DISPLAY_CTRL_SELECT_MASK (0x3 << 28) | |
| 788 | #define PANEL_DISPLAY_CTRL_SELECT_PANEL (0x0 << 28) | |
| 789 | #define PANEL_DISPLAY_CTRL_SELECT_VGA (0x1 << 28) | |
| 790 | #define PANEL_DISPLAY_CTRL_SELECT_CRT (0x2 << 28) | |
| 6fba39cf MR |
791 | #define PANEL_DISPLAY_CTRL_FPEN BIT(27) |
| 792 | #define PANEL_DISPLAY_CTRL_VBIASEN BIT(26) | |
| 793 | #define PANEL_DISPLAY_CTRL_DATA BIT(25) | |
| 794 | #define PANEL_DISPLAY_CTRL_FPVDDEN BIT(24) | |
| 6fba39cf MR |
795 | #define PANEL_DISPLAY_CTRL_DUAL_DISPLAY BIT(19) |
| 796 | #define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL BIT(18) | |
| c4e893b7 MR |
797 | #define PANEL_DISPLAY_CTRL_FIFO (0x3 << 16) |
| 798 | #define PANEL_DISPLAY_CTRL_FIFO_1 (0x0 << 16) | |
| 799 | #define PANEL_DISPLAY_CTRL_FIFO_3 (0x1 << 16) | |
| 800 | #define PANEL_DISPLAY_CTRL_FIFO_7 (0x2 << 16) | |
| 801 | #define PANEL_DISPLAY_CTRL_FIFO_11 (0x3 << 16) | |
| 6fba39cf MR |
802 | #define DISPLAY_CTRL_CLOCK_PHASE BIT(14) |
| 803 | #define DISPLAY_CTRL_VSYNC_PHASE BIT(13) | |
| 804 | #define DISPLAY_CTRL_HSYNC_PHASE BIT(12) | |
| 805 | #define PANEL_DISPLAY_CTRL_VSYNC BIT(11) | |
| 806 | #define PANEL_DISPLAY_CTRL_CAPTURE_TIMING BIT(10) | |
| 807 | #define PANEL_DISPLAY_CTRL_COLOR_KEY BIT(9) | |
| 808 | #define DISPLAY_CTRL_TIMING BIT(8) | |
| 809 | #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR BIT(7) | |
| 810 | #define PANEL_DISPLAY_CTRL_VERTICAL_PAN BIT(6) | |
| 811 | #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR BIT(5) | |
| 812 | #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN BIT(4) | |
| 813 | #define DISPLAY_CTRL_GAMMA BIT(3) | |
| 814 | #define DISPLAY_CTRL_PLANE BIT(2) | |
| c4e893b7 MR |
815 | #define PANEL_DISPLAY_CTRL_FORMAT (0x3 << 0) |
| 816 | #define PANEL_DISPLAY_CTRL_FORMAT_8 (0x0 << 0) | |
| 817 | #define PANEL_DISPLAY_CTRL_FORMAT_16 (0x1 << 0) | |
| 818 | #define PANEL_DISPLAY_CTRL_FORMAT_32 (0x2 << 0) | |
| 81dee67e SM |
819 | |
| 820 | #define PANEL_PAN_CTRL 0x080004 | |
| 821 | #define PANEL_PAN_CTRL_VERTICAL_PAN 31:24 | |
| 822 | #define PANEL_PAN_CTRL_VERTICAL_VSYNC 21:16 | |
| 823 | #define PANEL_PAN_CTRL_HORIZONTAL_PAN 15:8 | |
| 824 | #define PANEL_PAN_CTRL_HORIZONTAL_VSYNC 5:0 | |
| 825 | ||
| 826 | #define PANEL_COLOR_KEY 0x080008 | |
| 827 | #define PANEL_COLOR_KEY_MASK 31:16 | |
| 828 | #define PANEL_COLOR_KEY_VALUE 15:0 | |
| 829 | ||
| 830 | #define PANEL_FB_ADDRESS 0x08000C | |
| 4463690a MR |
831 | #define PANEL_FB_ADDRESS_STATUS BIT(31) |
| 832 | #define PANEL_FB_ADDRESS_EXT BIT(27) | |
| 833 | #define PANEL_FB_ADDRESS_ADDRESS_MASK 0x1ffffff | |
| 81dee67e SM |
834 | |
| 835 | #define PANEL_FB_WIDTH 0x080010 | |
| 26a3cc90 MR |
836 | #define PANEL_FB_WIDTH_WIDTH_SHIFT 16 |
| 837 | #define PANEL_FB_WIDTH_WIDTH_MASK (0x3fff << 16) | |
| 838 | #define PANEL_FB_WIDTH_OFFSET_MASK 0x3fff | |
| 81dee67e SM |
839 | |
| 840 | #define PANEL_WINDOW_WIDTH 0x080014 | |
| 4c221d82 MR |
841 | #define PANEL_WINDOW_WIDTH_WIDTH_SHIFT 16 |
| 842 | #define PANEL_WINDOW_WIDTH_WIDTH_MASK (0xfff << 16) | |
| 843 | #define PANEL_WINDOW_WIDTH_X_MASK 0xfff | |
| 81dee67e SM |
844 | |
| 845 | #define PANEL_WINDOW_HEIGHT 0x080018 | |
| f91969f7 MR |
846 | #define PANEL_WINDOW_HEIGHT_HEIGHT_SHIFT 16 |
| 847 | #define PANEL_WINDOW_HEIGHT_HEIGHT_MASK (0xfff << 16) | |
| 848 | #define PANEL_WINDOW_HEIGHT_Y_MASK 0xfff | |
| 81dee67e SM |
849 | |
| 850 | #define PANEL_PLANE_TL 0x08001C | |
| 30ca5cb6 MR |
851 | #define PANEL_PLANE_TL_TOP_SHIFT 16 |
| 852 | #define PANEL_PLANE_TL_TOP_MASK (0xeff << 16) | |
| 853 | #define PANEL_PLANE_TL_LEFT_MASK 0xeff | |
| 81dee67e SM |
854 | |
| 855 | #define PANEL_PLANE_BR 0x080020 | |
| 27b047bb MR |
856 | #define PANEL_PLANE_BR_BOTTOM_SHIFT 16 |
| 857 | #define PANEL_PLANE_BR_BOTTOM_MASK (0xeff << 16) | |
| 858 | #define PANEL_PLANE_BR_RIGHT_MASK 0xeff | |
| 81dee67e SM |
859 | |
| 860 | #define PANEL_HORIZONTAL_TOTAL 0x080024 | |
| 60112069 MR |
861 | #define PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT 16 |
| 862 | #define PANEL_HORIZONTAL_TOTAL_TOTAL_MASK (0xfff << 16) | |
| 863 | #define PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK 0xfff | |
| 81dee67e SM |
864 | |
| 865 | #define PANEL_HORIZONTAL_SYNC 0x080028 | |
| a6f17bc4 MR |
866 | #define PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT 16 |
| 867 | #define PANEL_HORIZONTAL_SYNC_WIDTH_MASK (0xff << 16) | |
| 868 | #define PANEL_HORIZONTAL_SYNC_START_MASK 0xfff | |
| 81dee67e SM |
869 | |
| 870 | #define PANEL_VERTICAL_TOTAL 0x08002C | |
| 871 | #define PANEL_VERTICAL_TOTAL_TOTAL 26:16 | |
| 872 | #define PANEL_VERTICAL_TOTAL_DISPLAY_END 10:0 | |
| 873 | ||
| 874 | #define PANEL_VERTICAL_SYNC 0x080030 | |
| 875 | #define PANEL_VERTICAL_SYNC_HEIGHT 21:16 | |
| 876 | #define PANEL_VERTICAL_SYNC_START 10:0 | |
| 877 | ||
| 878 | #define PANEL_CURRENT_LINE 0x080034 | |
| 879 | #define PANEL_CURRENT_LINE_LINE 10:0 | |
| 880 | ||
| 881 | /* Video Control */ | |
| 882 | ||
| 883 | #define VIDEO_DISPLAY_CTRL 0x080040 | |
| 884 | #define VIDEO_DISPLAY_CTRL_LINE_BUFFER 18:18 | |
| 885 | #define VIDEO_DISPLAY_CTRL_LINE_BUFFER_DISABLE 0 | |
| 886 | #define VIDEO_DISPLAY_CTRL_LINE_BUFFER_ENABLE 1 | |
| 887 | #define VIDEO_DISPLAY_CTRL_FIFO 17:16 | |
| 888 | #define VIDEO_DISPLAY_CTRL_FIFO_1 0 | |
| 889 | #define VIDEO_DISPLAY_CTRL_FIFO_3 1 | |
| 890 | #define VIDEO_DISPLAY_CTRL_FIFO_7 2 | |
| 891 | #define VIDEO_DISPLAY_CTRL_FIFO_11 3 | |
| 892 | #define VIDEO_DISPLAY_CTRL_BUFFER 15:15 | |
| 893 | #define VIDEO_DISPLAY_CTRL_BUFFER_0 0 | |
| 894 | #define VIDEO_DISPLAY_CTRL_BUFFER_1 1 | |
| 895 | #define VIDEO_DISPLAY_CTRL_CAPTURE 14:14 | |
| 896 | #define VIDEO_DISPLAY_CTRL_CAPTURE_DISABLE 0 | |
| 897 | #define VIDEO_DISPLAY_CTRL_CAPTURE_ENABLE 1 | |
| 898 | #define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER 13:13 | |
| 899 | #define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER_DISABLE 0 | |
| 900 | #define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER_ENABLE 1 | |
| 901 | #define VIDEO_DISPLAY_CTRL_BYTE_SWAP 12:12 | |
| 902 | #define VIDEO_DISPLAY_CTRL_BYTE_SWAP_DISABLE 0 | |
| 903 | #define VIDEO_DISPLAY_CTRL_BYTE_SWAP_ENABLE 1 | |
| 904 | #define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE 11:11 | |
| 905 | #define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE_NORMAL 0 | |
| 906 | #define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE_HALF 1 | |
| 907 | #define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE 10:10 | |
| 908 | #define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE_NORMAL 0 | |
| 909 | #define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE_HALF 1 | |
| 910 | #define VIDEO_DISPLAY_CTRL_VERTICAL_MODE 9:9 | |
| 911 | #define VIDEO_DISPLAY_CTRL_VERTICAL_MODE_REPLICATE 0 | |
| 912 | #define VIDEO_DISPLAY_CTRL_VERTICAL_MODE_INTERPOLATE 1 | |
| 913 | #define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE 8:8 | |
| 914 | #define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE_REPLICATE 0 | |
| 915 | #define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE_INTERPOLATE 1 | |
| 916 | #define VIDEO_DISPLAY_CTRL_PIXEL 7:4 | |
| 917 | #define VIDEO_DISPLAY_CTRL_GAMMA 3:3 | |
| 918 | #define VIDEO_DISPLAY_CTRL_GAMMA_DISABLE 0 | |
| 919 | #define VIDEO_DISPLAY_CTRL_GAMMA_ENABLE 1 | |
| 81dee67e SM |
920 | #define VIDEO_DISPLAY_CTRL_FORMAT 1:0 |
| 921 | #define VIDEO_DISPLAY_CTRL_FORMAT_8 0 | |
| 922 | #define VIDEO_DISPLAY_CTRL_FORMAT_16 1 | |
| 923 | #define VIDEO_DISPLAY_CTRL_FORMAT_32 2 | |
| 924 | #define VIDEO_DISPLAY_CTRL_FORMAT_YUV 3 | |
| 925 | ||
| 926 | #define VIDEO_FB_0_ADDRESS 0x080044 | |
| 927 | #define VIDEO_FB_0_ADDRESS_STATUS 31:31 | |
| 928 | #define VIDEO_FB_0_ADDRESS_STATUS_CURRENT 0 | |
| 929 | #define VIDEO_FB_0_ADDRESS_STATUS_PENDING 1 | |
| 930 | #define VIDEO_FB_0_ADDRESS_EXT 27:27 | |
| 931 | #define VIDEO_FB_0_ADDRESS_EXT_LOCAL 0 | |
| 932 | #define VIDEO_FB_0_ADDRESS_EXT_EXTERNAL 1 | |
| 933 | #define VIDEO_FB_0_ADDRESS_ADDRESS 25:0 | |
| 934 | ||
| 935 | #define VIDEO_FB_WIDTH 0x080048 | |
| 936 | #define VIDEO_FB_WIDTH_WIDTH 29:16 | |
| 937 | #define VIDEO_FB_WIDTH_OFFSET 13:0 | |
| 938 | ||
| 939 | #define VIDEO_FB_0_LAST_ADDRESS 0x08004C | |
| 940 | #define VIDEO_FB_0_LAST_ADDRESS_EXT 27:27 | |
| 941 | #define VIDEO_FB_0_LAST_ADDRESS_EXT_LOCAL 0 | |
| 942 | #define VIDEO_FB_0_LAST_ADDRESS_EXT_EXTERNAL 1 | |
| 943 | #define VIDEO_FB_0_LAST_ADDRESS_ADDRESS 25:0 | |
| 944 | ||
| 945 | #define VIDEO_PLANE_TL 0x080050 | |
| 946 | #define VIDEO_PLANE_TL_TOP 26:16 | |
| 947 | #define VIDEO_PLANE_TL_LEFT 10:0 | |
| 948 | ||
| 949 | #define VIDEO_PLANE_BR 0x080054 | |
| 950 | #define VIDEO_PLANE_BR_BOTTOM 26:16 | |
| 951 | #define VIDEO_PLANE_BR_RIGHT 10:0 | |
| 952 | ||
| 953 | #define VIDEO_SCALE 0x080058 | |
| 954 | #define VIDEO_SCALE_VERTICAL_MODE 31:31 | |
| 955 | #define VIDEO_SCALE_VERTICAL_MODE_EXPAND 0 | |
| 956 | #define VIDEO_SCALE_VERTICAL_MODE_SHRINK 1 | |
| 957 | #define VIDEO_SCALE_VERTICAL_SCALE 27:16 | |
| 958 | #define VIDEO_SCALE_HORIZONTAL_MODE 15:15 | |
| 959 | #define VIDEO_SCALE_HORIZONTAL_MODE_EXPAND 0 | |
| 960 | #define VIDEO_SCALE_HORIZONTAL_MODE_SHRINK 1 | |
| 961 | #define VIDEO_SCALE_HORIZONTAL_SCALE 11:0 | |
| 962 | ||
| 963 | #define VIDEO_INITIAL_SCALE 0x08005C | |
| 964 | #define VIDEO_INITIAL_SCALE_FB_1 27:16 | |
| 965 | #define VIDEO_INITIAL_SCALE_FB_0 11:0 | |
| 966 | ||
| 967 | #define VIDEO_YUV_CONSTANTS 0x080060 | |
| 968 | #define VIDEO_YUV_CONSTANTS_Y 31:24 | |
| 969 | #define VIDEO_YUV_CONSTANTS_R 23:16 | |
| 970 | #define VIDEO_YUV_CONSTANTS_G 15:8 | |
| 971 | #define VIDEO_YUV_CONSTANTS_B 7:0 | |
| 972 | ||
| 973 | #define VIDEO_FB_1_ADDRESS 0x080064 | |
| 974 | #define VIDEO_FB_1_ADDRESS_STATUS 31:31 | |
| 975 | #define VIDEO_FB_1_ADDRESS_STATUS_CURRENT 0 | |
| 976 | #define VIDEO_FB_1_ADDRESS_STATUS_PENDING 1 | |
| 977 | #define VIDEO_FB_1_ADDRESS_EXT 27:27 | |
| 978 | #define VIDEO_FB_1_ADDRESS_EXT_LOCAL 0 | |
| 979 | #define VIDEO_FB_1_ADDRESS_EXT_EXTERNAL 1 | |
| 980 | #define VIDEO_FB_1_ADDRESS_ADDRESS 25:0 | |
| 981 | ||
| 982 | #define VIDEO_FB_1_LAST_ADDRESS 0x080068 | |
| 983 | #define VIDEO_FB_1_LAST_ADDRESS_EXT 27:27 | |
| 984 | #define VIDEO_FB_1_LAST_ADDRESS_EXT_LOCAL 0 | |
| 985 | #define VIDEO_FB_1_LAST_ADDRESS_EXT_EXTERNAL 1 | |
| 986 | #define VIDEO_FB_1_LAST_ADDRESS_ADDRESS 25:0 | |
| 987 | ||
| 988 | /* Video Alpha Control */ | |
| 989 | ||
| 990 | #define VIDEO_ALPHA_DISPLAY_CTRL 0x080080 | |
| 991 | #define VIDEO_ALPHA_DISPLAY_CTRL_SELECT 28:28 | |
| 992 | #define VIDEO_ALPHA_DISPLAY_CTRL_SELECT_PER_PIXEL 0 | |
| 993 | #define VIDEO_ALPHA_DISPLAY_CTRL_SELECT_ALPHA 1 | |
| 994 | #define VIDEO_ALPHA_DISPLAY_CTRL_ALPHA 27:24 | |
| 995 | #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO 17:16 | |
| 996 | #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_1 0 | |
| 997 | #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_3 1 | |
| 998 | #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_7 2 | |
| 999 | #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_11 3 | |
| 1000 | #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE 11:11 | |
| 1001 | #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE_NORMAL 0 | |
| 1002 | #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE_HALF 1 | |
| 1003 | #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE 10:10 | |
| 1004 | #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE_NORMAL 0 | |
| 1005 | #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE_HALF 1 | |
| 1006 | #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE 9:9 | |
| 1007 | #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE_REPLICATE 0 | |
| 1008 | #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE_INTERPOLATE 1 | |
| 1009 | #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE 8:8 | |
| 1010 | #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE_REPLICATE 0 | |
| 1011 | #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE_INTERPOLATE 1 | |
| 1012 | #define VIDEO_ALPHA_DISPLAY_CTRL_PIXEL 7:4 | |
| 1013 | #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3 | |
| 1014 | #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0 | |
| 1015 | #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1 | |
| 81dee67e SM |
1016 | #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT 1:0 |
| 1017 | #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_8 0 | |
| 1018 | #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_16 1 | |
| 1019 | #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 2 | |
| 1020 | #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4 3 | |
| 1021 | ||
| 1022 | #define VIDEO_ALPHA_FB_ADDRESS 0x080084 | |
| 1023 | #define VIDEO_ALPHA_FB_ADDRESS_STATUS 31:31 | |
| 1024 | #define VIDEO_ALPHA_FB_ADDRESS_STATUS_CURRENT 0 | |
| 1025 | #define VIDEO_ALPHA_FB_ADDRESS_STATUS_PENDING 1 | |
| 1026 | #define VIDEO_ALPHA_FB_ADDRESS_EXT 27:27 | |
| 1027 | #define VIDEO_ALPHA_FB_ADDRESS_EXT_LOCAL 0 | |
| 1028 | #define VIDEO_ALPHA_FB_ADDRESS_EXT_EXTERNAL 1 | |
| 1029 | #define VIDEO_ALPHA_FB_ADDRESS_ADDRESS 25:0 | |
| 1030 | ||
| 1031 | #define VIDEO_ALPHA_FB_WIDTH 0x080088 | |
| 1032 | #define VIDEO_ALPHA_FB_WIDTH_WIDTH 29:16 | |
| 1033 | #define VIDEO_ALPHA_FB_WIDTH_OFFSET 13:0 | |
| 1034 | ||
| 1035 | #define VIDEO_ALPHA_FB_LAST_ADDRESS 0x08008C | |
| 1036 | #define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT 27:27 | |
| 1037 | #define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT_LOCAL 0 | |
| 1038 | #define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT_EXTERNAL 1 | |
| 1039 | #define VIDEO_ALPHA_FB_LAST_ADDRESS_ADDRESS 25:0 | |
| 1040 | ||
| 1041 | #define VIDEO_ALPHA_PLANE_TL 0x080090 | |
| 1042 | #define VIDEO_ALPHA_PLANE_TL_TOP 26:16 | |
| 1043 | #define VIDEO_ALPHA_PLANE_TL_LEFT 10:0 | |
| 1044 | ||
| 1045 | #define VIDEO_ALPHA_PLANE_BR 0x080094 | |
| 1046 | #define VIDEO_ALPHA_PLANE_BR_BOTTOM 26:16 | |
| 1047 | #define VIDEO_ALPHA_PLANE_BR_RIGHT 10:0 | |
| 1048 | ||
| 1049 | #define VIDEO_ALPHA_SCALE 0x080098 | |
| 1050 | #define VIDEO_ALPHA_SCALE_VERTICAL_MODE 31:31 | |
| 1051 | #define VIDEO_ALPHA_SCALE_VERTICAL_MODE_EXPAND 0 | |
| 1052 | #define VIDEO_ALPHA_SCALE_VERTICAL_MODE_SHRINK 1 | |
| 1053 | #define VIDEO_ALPHA_SCALE_VERTICAL_SCALE 27:16 | |
| 1054 | #define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE 15:15 | |
| 1055 | #define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE_EXPAND 0 | |
| 1056 | #define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE_SHRINK 1 | |
| 1057 | #define VIDEO_ALPHA_SCALE_HORIZONTAL_SCALE 11:0 | |
| 1058 | ||
| 1059 | #define VIDEO_ALPHA_INITIAL_SCALE 0x08009C | |
| 1060 | #define VIDEO_ALPHA_INITIAL_SCALE_VERTICAL 27:16 | |
| 1061 | #define VIDEO_ALPHA_INITIAL_SCALE_HORIZONTAL 11:0 | |
| 1062 | ||
| 1063 | #define VIDEO_ALPHA_CHROMA_KEY 0x0800A0 | |
| 1064 | #define VIDEO_ALPHA_CHROMA_KEY_MASK 31:16 | |
| 1065 | #define VIDEO_ALPHA_CHROMA_KEY_VALUE 15:0 | |
| 1066 | ||
| 1067 | #define VIDEO_ALPHA_COLOR_LOOKUP_01 0x0800A4 | |
| 1068 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_1 31:16 | |
| 1069 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_RED 31:27 | |
| 1070 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_GREEN 26:21 | |
| 1071 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_BLUE 20:16 | |
| 1072 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_0 15:0 | |
| 1073 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_RED 15:11 | |
| 1074 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_GREEN 10:5 | |
| 1075 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_BLUE 4:0 | |
| 1076 | ||
| 1077 | #define VIDEO_ALPHA_COLOR_LOOKUP_23 0x0800A8 | |
| 1078 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_3 31:16 | |
| 1079 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_RED 31:27 | |
| 1080 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_GREEN 26:21 | |
| 1081 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_BLUE 20:16 | |
| 1082 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_2 15:0 | |
| 1083 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_RED 15:11 | |
| 1084 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_GREEN 10:5 | |
| 1085 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_BLUE 4:0 | |
| 1086 | ||
| 1087 | #define VIDEO_ALPHA_COLOR_LOOKUP_45 0x0800AC | |
| 1088 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_5 31:16 | |
| 1089 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_RED 31:27 | |
| 1090 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_GREEN 26:21 | |
| 1091 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_BLUE 20:16 | |
| 1092 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_4 15:0 | |
| 1093 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_RED 15:11 | |
| 1094 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_GREEN 10:5 | |
| 1095 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_BLUE 4:0 | |
| 1096 | ||
| 1097 | #define VIDEO_ALPHA_COLOR_LOOKUP_67 0x0800B0 | |
| 1098 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_7 31:16 | |
| 1099 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_RED 31:27 | |
| 1100 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_GREEN 26:21 | |
| 1101 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_BLUE 20:16 | |
| 1102 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_6 15:0 | |
| 1103 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_RED 15:11 | |
| 1104 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_GREEN 10:5 | |
| 1105 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_BLUE 4:0 | |
| 1106 | ||
| 1107 | #define VIDEO_ALPHA_COLOR_LOOKUP_89 0x0800B4 | |
| 1108 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_9 31:16 | |
| 1109 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_RED 31:27 | |
| 1110 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_GREEN 26:21 | |
| 1111 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_BLUE 20:16 | |
| 1112 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_8 15:0 | |
| 1113 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_RED 15:11 | |
| 1114 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_GREEN 10:5 | |
| 1115 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_BLUE 4:0 | |
| 1116 | ||
| 1117 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB 0x0800B8 | |
| 1118 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B 31:16 | |
| 1119 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_RED 31:27 | |
| 1120 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_GREEN 26:21 | |
| 1121 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_BLUE 20:16 | |
| 1122 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A 15:0 | |
| 1123 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_RED 15:11 | |
| 1124 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_GREEN 10:5 | |
| 1125 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_BLUE 4:0 | |
| 1126 | ||
| 1127 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD 0x0800BC | |
| 1128 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D 31:16 | |
| 1129 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_RED 31:27 | |
| 1130 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_GREEN 26:21 | |
| 1131 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_BLUE 20:16 | |
| 1132 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C 15:0 | |
| 1133 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_RED 15:11 | |
| 1134 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_GREEN 10:5 | |
| 1135 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_BLUE 4:0 | |
| 1136 | ||
| 1137 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF 0x0800C0 | |
| 1138 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F 31:16 | |
| 1139 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_RED 31:27 | |
| 1140 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_GREEN 26:21 | |
| 1141 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_BLUE 20:16 | |
| 1142 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E 15:0 | |
| 1143 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_RED 15:11 | |
| 1144 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_GREEN 10:5 | |
| 1145 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_BLUE 4:0 | |
| 1146 | ||
| 1147 | /* Panel Cursor Control */ | |
| 1148 | ||
| 1149 | #define PANEL_HWC_ADDRESS 0x0800F0 | |
| 1150 | #define PANEL_HWC_ADDRESS_ENABLE 31:31 | |
| 1151 | #define PANEL_HWC_ADDRESS_ENABLE_DISABLE 0 | |
| 1152 | #define PANEL_HWC_ADDRESS_ENABLE_ENABLE 1 | |
| 1153 | #define PANEL_HWC_ADDRESS_EXT 27:27 | |
| 1154 | #define PANEL_HWC_ADDRESS_EXT_LOCAL 0 | |
| 1155 | #define PANEL_HWC_ADDRESS_EXT_EXTERNAL 1 | |
| 1156 | #define PANEL_HWC_ADDRESS_ADDRESS 25:0 | |
| 1157 | ||
| 1158 | #define PANEL_HWC_LOCATION 0x0800F4 | |
| 1159 | #define PANEL_HWC_LOCATION_TOP 27:27 | |
| 1160 | #define PANEL_HWC_LOCATION_TOP_INSIDE 0 | |
| 1161 | #define PANEL_HWC_LOCATION_TOP_OUTSIDE 1 | |
| 1162 | #define PANEL_HWC_LOCATION_Y 26:16 | |
| 1163 | #define PANEL_HWC_LOCATION_LEFT 11:11 | |
| 1164 | #define PANEL_HWC_LOCATION_LEFT_INSIDE 0 | |
| 1165 | #define PANEL_HWC_LOCATION_LEFT_OUTSIDE 1 | |
| 1166 | #define PANEL_HWC_LOCATION_X 10:0 | |
| 1167 | ||
| 1168 | #define PANEL_HWC_COLOR_12 0x0800F8 | |
| 1169 | #define PANEL_HWC_COLOR_12_2_RGB565 31:16 | |
| 1170 | #define PANEL_HWC_COLOR_12_1_RGB565 15:0 | |
| 1171 | ||
| 1172 | #define PANEL_HWC_COLOR_3 0x0800FC | |
| 1173 | #define PANEL_HWC_COLOR_3_RGB565 15:0 | |
| 1174 | ||
| 1175 | /* Old Definitions +++ */ | |
| 1176 | #define PANEL_HWC_COLOR_01 0x0800F8 | |
| 1177 | #define PANEL_HWC_COLOR_01_1_RED 31:27 | |
| 1178 | #define PANEL_HWC_COLOR_01_1_GREEN 26:21 | |
| 1179 | #define PANEL_HWC_COLOR_01_1_BLUE 20:16 | |
| 1180 | #define PANEL_HWC_COLOR_01_0_RED 15:11 | |
| 1181 | #define PANEL_HWC_COLOR_01_0_GREEN 10:5 | |
| 1182 | #define PANEL_HWC_COLOR_01_0_BLUE 4:0 | |
| 1183 | ||
| 1184 | #define PANEL_HWC_COLOR_2 0x0800FC | |
| 1185 | #define PANEL_HWC_COLOR_2_RED 15:11 | |
| 1186 | #define PANEL_HWC_COLOR_2_GREEN 10:5 | |
| 1187 | #define PANEL_HWC_COLOR_2_BLUE 4:0 | |
| 1188 | /* Old Definitions --- */ | |
| 1189 | ||
| 1190 | /* Alpha Control */ | |
| 1191 | ||
| 1192 | #define ALPHA_DISPLAY_CTRL 0x080100 | |
| 1193 | #define ALPHA_DISPLAY_CTRL_SELECT 28:28 | |
| 1194 | #define ALPHA_DISPLAY_CTRL_SELECT_PER_PIXEL 0 | |
| 1195 | #define ALPHA_DISPLAY_CTRL_SELECT_ALPHA 1 | |
| 1196 | #define ALPHA_DISPLAY_CTRL_ALPHA 27:24 | |
| 1197 | #define ALPHA_DISPLAY_CTRL_FIFO 17:16 | |
| 1198 | #define ALPHA_DISPLAY_CTRL_FIFO_1 0 | |
| 1199 | #define ALPHA_DISPLAY_CTRL_FIFO_3 1 | |
| 1200 | #define ALPHA_DISPLAY_CTRL_FIFO_7 2 | |
| 1201 | #define ALPHA_DISPLAY_CTRL_FIFO_11 3 | |
| 1202 | #define ALPHA_DISPLAY_CTRL_PIXEL 7:4 | |
| 1203 | #define ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3 | |
| 1204 | #define ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0 | |
| 1205 | #define ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1 | |
| 81dee67e SM |
1206 | #define ALPHA_DISPLAY_CTRL_FORMAT 1:0 |
| 1207 | #define ALPHA_DISPLAY_CTRL_FORMAT_16 1 | |
| 1208 | #define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 2 | |
| 1209 | #define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4 3 | |
| 1210 | ||
| 1211 | #define ALPHA_FB_ADDRESS 0x080104 | |
| 1212 | #define ALPHA_FB_ADDRESS_STATUS 31:31 | |
| 1213 | #define ALPHA_FB_ADDRESS_STATUS_CURRENT 0 | |
| 1214 | #define ALPHA_FB_ADDRESS_STATUS_PENDING 1 | |
| 1215 | #define ALPHA_FB_ADDRESS_EXT 27:27 | |
| 1216 | #define ALPHA_FB_ADDRESS_EXT_LOCAL 0 | |
| 1217 | #define ALPHA_FB_ADDRESS_EXT_EXTERNAL 1 | |
| 1218 | #define ALPHA_FB_ADDRESS_ADDRESS 25:0 | |
| 1219 | ||
| 1220 | #define ALPHA_FB_WIDTH 0x080108 | |
| 1221 | #define ALPHA_FB_WIDTH_WIDTH 29:16 | |
| 1222 | #define ALPHA_FB_WIDTH_OFFSET 13:0 | |
| 1223 | ||
| 1224 | #define ALPHA_PLANE_TL 0x08010C | |
| 1225 | #define ALPHA_PLANE_TL_TOP 26:16 | |
| 1226 | #define ALPHA_PLANE_TL_LEFT 10:0 | |
| 1227 | ||
| 1228 | #define ALPHA_PLANE_BR 0x080110 | |
| 1229 | #define ALPHA_PLANE_BR_BOTTOM 26:16 | |
| 1230 | #define ALPHA_PLANE_BR_RIGHT 10:0 | |
| 1231 | ||
| 1232 | #define ALPHA_CHROMA_KEY 0x080114 | |
| 1233 | #define ALPHA_CHROMA_KEY_MASK 31:16 | |
| 1234 | #define ALPHA_CHROMA_KEY_VALUE 15:0 | |
| 1235 | ||
| 1236 | #define ALPHA_COLOR_LOOKUP_01 0x080118 | |
| 1237 | #define ALPHA_COLOR_LOOKUP_01_1 31:16 | |
| 1238 | #define ALPHA_COLOR_LOOKUP_01_1_RED 31:27 | |
| 1239 | #define ALPHA_COLOR_LOOKUP_01_1_GREEN 26:21 | |
| 1240 | #define ALPHA_COLOR_LOOKUP_01_1_BLUE 20:16 | |
| 1241 | #define ALPHA_COLOR_LOOKUP_01_0 15:0 | |
| 1242 | #define ALPHA_COLOR_LOOKUP_01_0_RED 15:11 | |
| 1243 | #define ALPHA_COLOR_LOOKUP_01_0_GREEN 10:5 | |
| 1244 | #define ALPHA_COLOR_LOOKUP_01_0_BLUE 4:0 | |
| 1245 | ||
| 1246 | #define ALPHA_COLOR_LOOKUP_23 0x08011C | |
| 1247 | #define ALPHA_COLOR_LOOKUP_23_3 31:16 | |
| 1248 | #define ALPHA_COLOR_LOOKUP_23_3_RED 31:27 | |
| 1249 | #define ALPHA_COLOR_LOOKUP_23_3_GREEN 26:21 | |
| 1250 | #define ALPHA_COLOR_LOOKUP_23_3_BLUE 20:16 | |
| 1251 | #define ALPHA_COLOR_LOOKUP_23_2 15:0 | |
| 1252 | #define ALPHA_COLOR_LOOKUP_23_2_RED 15:11 | |
| 1253 | #define ALPHA_COLOR_LOOKUP_23_2_GREEN 10:5 | |
| 1254 | #define ALPHA_COLOR_LOOKUP_23_2_BLUE 4:0 | |
| 1255 | ||
| 1256 | #define ALPHA_COLOR_LOOKUP_45 0x080120 | |
| 1257 | #define ALPHA_COLOR_LOOKUP_45_5 31:16 | |
| 1258 | #define ALPHA_COLOR_LOOKUP_45_5_RED 31:27 | |
| 1259 | #define ALPHA_COLOR_LOOKUP_45_5_GREEN 26:21 | |
| 1260 | #define ALPHA_COLOR_LOOKUP_45_5_BLUE 20:16 | |
| 1261 | #define ALPHA_COLOR_LOOKUP_45_4 15:0 | |
| 1262 | #define ALPHA_COLOR_LOOKUP_45_4_RED 15:11 | |
| 1263 | #define ALPHA_COLOR_LOOKUP_45_4_GREEN 10:5 | |
| 1264 | #define ALPHA_COLOR_LOOKUP_45_4_BLUE 4:0 | |
| 1265 | ||
| 1266 | #define ALPHA_COLOR_LOOKUP_67 0x080124 | |
| 1267 | #define ALPHA_COLOR_LOOKUP_67_7 31:16 | |
| 1268 | #define ALPHA_COLOR_LOOKUP_67_7_RED 31:27 | |
| 1269 | #define ALPHA_COLOR_LOOKUP_67_7_GREEN 26:21 | |
| 1270 | #define ALPHA_COLOR_LOOKUP_67_7_BLUE 20:16 | |
| 1271 | #define ALPHA_COLOR_LOOKUP_67_6 15:0 | |
| 1272 | #define ALPHA_COLOR_LOOKUP_67_6_RED 15:11 | |
| 1273 | #define ALPHA_COLOR_LOOKUP_67_6_GREEN 10:5 | |
| 1274 | #define ALPHA_COLOR_LOOKUP_67_6_BLUE 4:0 | |
| 1275 | ||
| 1276 | #define ALPHA_COLOR_LOOKUP_89 0x080128 | |
| 1277 | #define ALPHA_COLOR_LOOKUP_89_9 31:16 | |
| 1278 | #define ALPHA_COLOR_LOOKUP_89_9_RED 31:27 | |
| 1279 | #define ALPHA_COLOR_LOOKUP_89_9_GREEN 26:21 | |
| 1280 | #define ALPHA_COLOR_LOOKUP_89_9_BLUE 20:16 | |
| 1281 | #define ALPHA_COLOR_LOOKUP_89_8 15:0 | |
| 1282 | #define ALPHA_COLOR_LOOKUP_89_8_RED 15:11 | |
| 1283 | #define ALPHA_COLOR_LOOKUP_89_8_GREEN 10:5 | |
| 1284 | #define ALPHA_COLOR_LOOKUP_89_8_BLUE 4:0 | |
| 1285 | ||
| 1286 | #define ALPHA_COLOR_LOOKUP_AB 0x08012C | |
| 1287 | #define ALPHA_COLOR_LOOKUP_AB_B 31:16 | |
| 1288 | #define ALPHA_COLOR_LOOKUP_AB_B_RED 31:27 | |
| 1289 | #define ALPHA_COLOR_LOOKUP_AB_B_GREEN 26:21 | |
| 1290 | #define ALPHA_COLOR_LOOKUP_AB_B_BLUE 20:16 | |
| 1291 | #define ALPHA_COLOR_LOOKUP_AB_A 15:0 | |
| 1292 | #define ALPHA_COLOR_LOOKUP_AB_A_RED 15:11 | |
| 1293 | #define ALPHA_COLOR_LOOKUP_AB_A_GREEN 10:5 | |
| 1294 | #define ALPHA_COLOR_LOOKUP_AB_A_BLUE 4:0 | |
| 1295 | ||
| 1296 | #define ALPHA_COLOR_LOOKUP_CD 0x080130 | |
| 1297 | #define ALPHA_COLOR_LOOKUP_CD_D 31:16 | |
| 1298 | #define ALPHA_COLOR_LOOKUP_CD_D_RED 31:27 | |
| 1299 | #define ALPHA_COLOR_LOOKUP_CD_D_GREEN 26:21 | |
| 1300 | #define ALPHA_COLOR_LOOKUP_CD_D_BLUE 20:16 | |
| 1301 | #define ALPHA_COLOR_LOOKUP_CD_C 15:0 | |
| 1302 | #define ALPHA_COLOR_LOOKUP_CD_C_RED 15:11 | |
| 1303 | #define ALPHA_COLOR_LOOKUP_CD_C_GREEN 10:5 | |
| 1304 | #define ALPHA_COLOR_LOOKUP_CD_C_BLUE 4:0 | |
| 1305 | ||
| 1306 | #define ALPHA_COLOR_LOOKUP_EF 0x080134 | |
| 1307 | #define ALPHA_COLOR_LOOKUP_EF_F 31:16 | |
| 1308 | #define ALPHA_COLOR_LOOKUP_EF_F_RED 31:27 | |
| 1309 | #define ALPHA_COLOR_LOOKUP_EF_F_GREEN 26:21 | |
| 1310 | #define ALPHA_COLOR_LOOKUP_EF_F_BLUE 20:16 | |
| 1311 | #define ALPHA_COLOR_LOOKUP_EF_E 15:0 | |
| 1312 | #define ALPHA_COLOR_LOOKUP_EF_E_RED 15:11 | |
| 1313 | #define ALPHA_COLOR_LOOKUP_EF_E_GREEN 10:5 | |
| 1314 | #define ALPHA_COLOR_LOOKUP_EF_E_BLUE 4:0 | |
| 1315 | ||
| 1316 | /* CRT Graphics Control */ | |
| 1317 | ||
| 1318 | #define CRT_DISPLAY_CTRL 0x080200 | |
| 9bd2c86b | 1319 | #define CRT_DISPLAY_CTRL_RESERVED_MASK 0xfb008200 |
| 81dee67e SM |
1320 | |
| 1321 | /* SM750LE definition */ | |
| cdce1f18 MR |
1322 | #define CRT_DISPLAY_CTRL_DPMS_SHIFT 30 |
| 1323 | #define CRT_DISPLAY_CTRL_DPMS_MASK (0x3 << 30) | |
| 1324 | #define CRT_DISPLAY_CTRL_DPMS_0 (0x0 << 30) | |
| 1325 | #define CRT_DISPLAY_CTRL_DPMS_1 (0x1 << 30) | |
| 1326 | #define CRT_DISPLAY_CTRL_DPMS_2 (0x2 << 30) | |
| 1327 | #define CRT_DISPLAY_CTRL_DPMS_3 (0x3 << 30) | |
| 1328 | #define CRT_DISPLAY_CTRL_CLK_MASK (0x7 << 27) | |
| 1329 | #define CRT_DISPLAY_CTRL_CLK_PLL25 (0x0 << 27) | |
| 1330 | #define CRT_DISPLAY_CTRL_CLK_PLL41 (0x1 << 27) | |
| 1331 | #define CRT_DISPLAY_CTRL_CLK_PLL62 (0x2 << 27) | |
| 1332 | #define CRT_DISPLAY_CTRL_CLK_PLL65 (0x3 << 27) | |
| 1333 | #define CRT_DISPLAY_CTRL_CLK_PLL74 (0x4 << 27) | |
| 1334 | #define CRT_DISPLAY_CTRL_CLK_PLL80 (0x5 << 27) | |
| 1335 | #define CRT_DISPLAY_CTRL_CLK_PLL108 (0x6 << 27) | |
| 1336 | #define CRT_DISPLAY_CTRL_CLK_RESERVED (0x7 << 27) | |
| d8264edf | 1337 | #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC BIT(26) |
| 81dee67e | 1338 | |
| 81dee67e | 1339 | /* SM750LE definition */ |
| d8264edf MR |
1340 | #define CRT_DISPLAY_CTRL_CRTSELECT BIT(25) |
| 1341 | #define CRT_DISPLAY_CTRL_RGBBIT BIT(24) | |
| 81dee67e | 1342 | |
| 81dee67e | 1343 | #ifndef VALIDATION_CHIP |
| d8264edf | 1344 | #define CRT_DISPLAY_CTRL_CENTERING BIT(24) |
| 81dee67e | 1345 | #endif |
| d8264edf MR |
1346 | #define CRT_DISPLAY_CTRL_LOCK_TIMING BIT(23) |
| 1347 | #define CRT_DISPLAY_CTRL_EXPANSION BIT(22) | |
| 1348 | #define CRT_DISPLAY_CTRL_VERTICAL_MODE BIT(21) | |
| 1349 | #define CRT_DISPLAY_CTRL_HORIZONTAL_MODE BIT(20) | |
| cdce1f18 MR |
1350 | #define CRT_DISPLAY_CTRL_SELECT_SHIFT 18 |
| 1351 | #define CRT_DISPLAY_CTRL_SELECT_MASK (0x3 << 18) | |
| 1352 | #define CRT_DISPLAY_CTRL_SELECT_PANEL (0x0 << 18) | |
| 1353 | #define CRT_DISPLAY_CTRL_SELECT_VGA (0x1 << 18) | |
| 1354 | #define CRT_DISPLAY_CTRL_SELECT_CRT (0x2 << 18) | |
| 1355 | #define CRT_DISPLAY_CTRL_FIFO_MASK (0x3 << 16) | |
| 1356 | #define CRT_DISPLAY_CTRL_FIFO_1 (0x0 << 16) | |
| 1357 | #define CRT_DISPLAY_CTRL_FIFO_3 (0x1 << 16) | |
| 1358 | #define CRT_DISPLAY_CTRL_FIFO_7 (0x2 << 16) | |
| 1359 | #define CRT_DISPLAY_CTRL_FIFO_11 (0x3 << 16) | |
| d8264edf | 1360 | #define CRT_DISPLAY_CTRL_BLANK BIT(10) |
| cdce1f18 MR |
1361 | #define CRT_DISPLAY_CTRL_PIXEL_MASK (0xf << 4) |
| 1362 | #define CRT_DISPLAY_CTRL_FORMAT_MASK (0x3 << 0) | |
| 1363 | #define CRT_DISPLAY_CTRL_FORMAT_8 (0x0 << 0) | |
| 1364 | #define CRT_DISPLAY_CTRL_FORMAT_16 (0x1 << 0) | |
| 1365 | #define CRT_DISPLAY_CTRL_FORMAT_32 (0x2 << 0) | |
| 81dee67e SM |
1366 | |
| 1367 | #define CRT_FB_ADDRESS 0x080204 | |
| 1368 | #define CRT_FB_ADDRESS_STATUS 31:31 | |
| 1369 | #define CRT_FB_ADDRESS_STATUS_CURRENT 0 | |
| 1370 | #define CRT_FB_ADDRESS_STATUS_PENDING 1 | |
| 1371 | #define CRT_FB_ADDRESS_EXT 27:27 | |
| 1372 | #define CRT_FB_ADDRESS_EXT_LOCAL 0 | |
| 1373 | #define CRT_FB_ADDRESS_EXT_EXTERNAL 1 | |
| 1374 | #define CRT_FB_ADDRESS_ADDRESS 25:0 | |
| 1375 | ||
| 1376 | #define CRT_FB_WIDTH 0x080208 | |
| 1377 | #define CRT_FB_WIDTH_WIDTH 29:16 | |
| 1378 | #define CRT_FB_WIDTH_OFFSET 13:0 | |
| 1379 | ||
| 1380 | #define CRT_HORIZONTAL_TOTAL 0x08020C | |
| 32849f85 MR |
1381 | #define CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT 16 |
| 1382 | #define CRT_HORIZONTAL_TOTAL_TOTAL_MASK (0xfff << 16) | |
| 1383 | #define CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK 0xfff | |
| 81dee67e SM |
1384 | |
| 1385 | #define CRT_HORIZONTAL_SYNC 0x080210 | |
| 1adb3c23 MR |
1386 | #define CRT_HORIZONTAL_SYNC_WIDTH_SHIFT 16 |
| 1387 | #define CRT_HORIZONTAL_SYNC_WIDTH_MASK (0xff << 16) | |
| 1388 | #define CRT_HORIZONTAL_SYNC_START_MASK 0xfff | |
| 81dee67e SM |
1389 | |
| 1390 | #define CRT_VERTICAL_TOTAL 0x080214 | |
| 3d5158d3 MR |
1391 | #define CRT_VERTICAL_TOTAL_TOTAL_SHIFT 16 |
| 1392 | #define CRT_VERTICAL_TOTAL_TOTAL_MASK (0x7ff << 16) | |
| 1393 | #define CRT_VERTICAL_TOTAL_DISPLAY_END_MASK (0x7ff) | |
| 81dee67e SM |
1394 | |
| 1395 | #define CRT_VERTICAL_SYNC 0x080218 | |
| 620c3912 MR |
1396 | #define CRT_VERTICAL_SYNC_HEIGHT_SHIFT 16 |
| 1397 | #define CRT_VERTICAL_SYNC_HEIGHT_MASK (0x3f << 16) | |
| 1398 | #define CRT_VERTICAL_SYNC_START_MASK 0x7ff | |
| 81dee67e SM |
1399 | |
| 1400 | #define CRT_SIGNATURE_ANALYZER 0x08021C | |
| 1401 | #define CRT_SIGNATURE_ANALYZER_STATUS 31:16 | |
| 1402 | #define CRT_SIGNATURE_ANALYZER_ENABLE 3:3 | |
| 1403 | #define CRT_SIGNATURE_ANALYZER_ENABLE_DISABLE 0 | |
| 1404 | #define CRT_SIGNATURE_ANALYZER_ENABLE_ENABLE 1 | |
| 1405 | #define CRT_SIGNATURE_ANALYZER_RESET 2:2 | |
| 1406 | #define CRT_SIGNATURE_ANALYZER_RESET_NORMAL 0 | |
| 1407 | #define CRT_SIGNATURE_ANALYZER_RESET_RESET 1 | |
| 1408 | #define CRT_SIGNATURE_ANALYZER_SOURCE 1:0 | |
| 1409 | #define CRT_SIGNATURE_ANALYZER_SOURCE_RED 0 | |
| 1410 | #define CRT_SIGNATURE_ANALYZER_SOURCE_GREEN 1 | |
| 1411 | #define CRT_SIGNATURE_ANALYZER_SOURCE_BLUE 2 | |
| 1412 | ||
| 1413 | #define CRT_CURRENT_LINE 0x080220 | |
| 1414 | #define CRT_CURRENT_LINE_LINE 10:0 | |
| 1415 | ||
| 1416 | #define CRT_MONITOR_DETECT 0x080224 | |
| 1417 | #define CRT_MONITOR_DETECT_VALUE 25:25 | |
| 1418 | #define CRT_MONITOR_DETECT_VALUE_DISABLE 0 | |
| 1419 | #define CRT_MONITOR_DETECT_VALUE_ENABLE 1 | |
| 1420 | #define CRT_MONITOR_DETECT_ENABLE 24:24 | |
| 1421 | #define CRT_MONITOR_DETECT_ENABLE_DISABLE 0 | |
| 1422 | #define CRT_MONITOR_DETECT_ENABLE_ENABLE 1 | |
| 1423 | #define CRT_MONITOR_DETECT_RED 23:16 | |
| 1424 | #define CRT_MONITOR_DETECT_GREEN 15:8 | |
| 1425 | #define CRT_MONITOR_DETECT_BLUE 7:0 | |
| 1426 | ||
| 1427 | #define CRT_SCALE 0x080228 | |
| 1428 | #define CRT_SCALE_VERTICAL_MODE 31:31 | |
| 1429 | #define CRT_SCALE_VERTICAL_MODE_EXPAND 0 | |
| 1430 | #define CRT_SCALE_VERTICAL_MODE_SHRINK 1 | |
| 1431 | #define CRT_SCALE_VERTICAL_SCALE 27:16 | |
| 1432 | #define CRT_SCALE_HORIZONTAL_MODE 15:15 | |
| 1433 | #define CRT_SCALE_HORIZONTAL_MODE_EXPAND 0 | |
| 1434 | #define CRT_SCALE_HORIZONTAL_MODE_SHRINK 1 | |
| 1435 | #define CRT_SCALE_HORIZONTAL_SCALE 11:0 | |
| 1436 | ||
| 1437 | /* CRT Cursor Control */ | |
| 1438 | ||
| 1439 | #define CRT_HWC_ADDRESS 0x080230 | |
| 1440 | #define CRT_HWC_ADDRESS_ENABLE 31:31 | |
| 1441 | #define CRT_HWC_ADDRESS_ENABLE_DISABLE 0 | |
| 1442 | #define CRT_HWC_ADDRESS_ENABLE_ENABLE 1 | |
| 1443 | #define CRT_HWC_ADDRESS_EXT 27:27 | |
| 1444 | #define CRT_HWC_ADDRESS_EXT_LOCAL 0 | |
| 1445 | #define CRT_HWC_ADDRESS_EXT_EXTERNAL 1 | |
| 1446 | #define CRT_HWC_ADDRESS_ADDRESS 25:0 | |
| 1447 | ||
| 1448 | #define CRT_HWC_LOCATION 0x080234 | |
| 1449 | #define CRT_HWC_LOCATION_TOP 27:27 | |
| 1450 | #define CRT_HWC_LOCATION_TOP_INSIDE 0 | |
| 1451 | #define CRT_HWC_LOCATION_TOP_OUTSIDE 1 | |
| 1452 | #define CRT_HWC_LOCATION_Y 26:16 | |
| 1453 | #define CRT_HWC_LOCATION_LEFT 11:11 | |
| 1454 | #define CRT_HWC_LOCATION_LEFT_INSIDE 0 | |
| 1455 | #define CRT_HWC_LOCATION_LEFT_OUTSIDE 1 | |
| 1456 | #define CRT_HWC_LOCATION_X 10:0 | |
| 1457 | ||
| 1458 | #define CRT_HWC_COLOR_12 0x080238 | |
| 1459 | #define CRT_HWC_COLOR_12_2_RGB565 31:16 | |
| 1460 | #define CRT_HWC_COLOR_12_1_RGB565 15:0 | |
| 1461 | ||
| 1462 | #define CRT_HWC_COLOR_3 0x08023C | |
| 1463 | #define CRT_HWC_COLOR_3_RGB565 15:0 | |
| 1464 | ||
| 81dee67e SM |
1465 | /* This vertical expansion below start at 0x080240 ~ 0x080264 */ |
| 1466 | #define CRT_VERTICAL_EXPANSION 0x080240 | |
| 1467 | #ifndef VALIDATION_CHIP | |
| 1468 | #define CRT_VERTICAL_CENTERING_VALUE 31:24 | |
| 1469 | #endif | |
| 1470 | #define CRT_VERTICAL_EXPANSION_COMPARE_VALUE 23:16 | |
| 1471 | #define CRT_VERTICAL_EXPANSION_LINE_BUFFER 15:12 | |
| 1472 | #define CRT_VERTICAL_EXPANSION_SCALE_FACTOR 11:0 | |
| 1473 | ||
| 1474 | /* This horizontal expansion below start at 0x080268 ~ 0x08027C */ | |
| 1475 | #define CRT_HORIZONTAL_EXPANSION 0x080268 | |
| 1476 | #ifndef VALIDATION_CHIP | |
| 1477 | #define CRT_HORIZONTAL_CENTERING_VALUE 31:24 | |
| 1478 | #endif | |
| 1479 | #define CRT_HORIZONTAL_EXPANSION_COMPARE_VALUE 23:16 | |
| 1480 | #define CRT_HORIZONTAL_EXPANSION_SCALE_FACTOR 11:0 | |
| 1481 | ||
| 1482 | #ifndef VALIDATION_CHIP | |
| 1483 | /* Auto Centering */ | |
| 1484 | #define CRT_AUTO_CENTERING_TL 0x080280 | |
| 85943dae MR |
1485 | #define CRT_AUTO_CENTERING_TL_TOP_MASK (0x7ff << 16) |
| 1486 | #define CRT_AUTO_CENTERING_TL_LEFT_MASK 0x7ff | |
| 81dee67e SM |
1487 | |
| 1488 | #define CRT_AUTO_CENTERING_BR 0x080284 | |
| aed4b787 MR |
1489 | #define CRT_AUTO_CENTERING_BR_BOTTOM_MASK (0x7ff << 16) |
| 1490 | #define CRT_AUTO_CENTERING_BR_BOTTOM_SHIFT 16 | |
| 1491 | #define CRT_AUTO_CENTERING_BR_RIGHT_MASK 0x7ff | |
| 81dee67e SM |
1492 | #endif |
| 1493 | ||
| 1494 | /* sm750le new register to control panel output */ | |
| 78376535 | 1495 | #define DISPLAY_CONTROL_750LE 0x80288 |
| 81dee67e SM |
1496 | /* Palette RAM */ |
| 1497 | ||
| 69e98df7 | 1498 | /* Panel Palette register starts at 0x080400 ~ 0x0807FC */ |
| 81dee67e SM |
1499 | #define PANEL_PALETTE_RAM 0x080400 |
| 1500 | ||
| 69e98df7 | 1501 | /* Panel Palette register starts at 0x080C00 ~ 0x080FFC */ |
| 81dee67e SM |
1502 | #define CRT_PALETTE_RAM 0x080C00 |
| 1503 | ||
| 81dee67e SM |
1504 | /* Color Space Conversion registers. */ |
| 1505 | ||
| 1506 | #define CSC_Y_SOURCE_BASE 0x1000C8 | |
| 1507 | #define CSC_Y_SOURCE_BASE_EXT 27:27 | |
| 1508 | #define CSC_Y_SOURCE_BASE_EXT_LOCAL 0 | |
| 1509 | #define CSC_Y_SOURCE_BASE_EXT_EXTERNAL 1 | |
| 1510 | #define CSC_Y_SOURCE_BASE_CS 26:26 | |
| 1511 | #define CSC_Y_SOURCE_BASE_CS_0 0 | |
| 1512 | #define CSC_Y_SOURCE_BASE_CS_1 1 | |
| 1513 | #define CSC_Y_SOURCE_BASE_ADDRESS 25:0 | |
| 1514 | ||
| 1515 | #define CSC_CONSTANTS 0x1000CC | |
| 1516 | #define CSC_CONSTANTS_Y 31:24 | |
| 1517 | #define CSC_CONSTANTS_R 23:16 | |
| 1518 | #define CSC_CONSTANTS_G 15:8 | |
| 1519 | #define CSC_CONSTANTS_B 7:0 | |
| 1520 | ||
| 1521 | #define CSC_Y_SOURCE_X 0x1000D0 | |
| 1522 | #define CSC_Y_SOURCE_X_INTEGER 26:16 | |
| 1523 | #define CSC_Y_SOURCE_X_FRACTION 15:3 | |
| 1524 | ||
| 1525 | #define CSC_Y_SOURCE_Y 0x1000D4 | |
| 1526 | #define CSC_Y_SOURCE_Y_INTEGER 27:16 | |
| 1527 | #define CSC_Y_SOURCE_Y_FRACTION 15:3 | |
| 1528 | ||
| 1529 | #define CSC_U_SOURCE_BASE 0x1000D8 | |
| 1530 | #define CSC_U_SOURCE_BASE_EXT 27:27 | |
| 1531 | #define CSC_U_SOURCE_BASE_EXT_LOCAL 0 | |
| 1532 | #define CSC_U_SOURCE_BASE_EXT_EXTERNAL 1 | |
| 1533 | #define CSC_U_SOURCE_BASE_CS 26:26 | |
| 1534 | #define CSC_U_SOURCE_BASE_CS_0 0 | |
| 1535 | #define CSC_U_SOURCE_BASE_CS_1 1 | |
| 1536 | #define CSC_U_SOURCE_BASE_ADDRESS 25:0 | |
| 1537 | ||
| 1538 | #define CSC_V_SOURCE_BASE 0x1000DC | |
| 1539 | #define CSC_V_SOURCE_BASE_EXT 27:27 | |
| 1540 | #define CSC_V_SOURCE_BASE_EXT_LOCAL 0 | |
| 1541 | #define CSC_V_SOURCE_BASE_EXT_EXTERNAL 1 | |
| 1542 | #define CSC_V_SOURCE_BASE_CS 26:26 | |
| 1543 | #define CSC_V_SOURCE_BASE_CS_0 0 | |
| 1544 | #define CSC_V_SOURCE_BASE_CS_1 1 | |
| 1545 | #define CSC_V_SOURCE_BASE_ADDRESS 25:0 | |
| 1546 | ||
| 1547 | #define CSC_SOURCE_DIMENSION 0x1000E0 | |
| 1548 | #define CSC_SOURCE_DIMENSION_X 31:16 | |
| 1549 | #define CSC_SOURCE_DIMENSION_Y 15:0 | |
| 1550 | ||
| 1551 | #define CSC_SOURCE_PITCH 0x1000E4 | |
| 1552 | #define CSC_SOURCE_PITCH_Y 31:16 | |
| 1553 | #define CSC_SOURCE_PITCH_UV 15:0 | |
| 1554 | ||
| 1555 | #define CSC_DESTINATION 0x1000E8 | |
| 1556 | #define CSC_DESTINATION_WRAP 31:31 | |
| 1557 | #define CSC_DESTINATION_WRAP_DISABLE 0 | |
| 1558 | #define CSC_DESTINATION_WRAP_ENABLE 1 | |
| 1559 | #define CSC_DESTINATION_X 27:16 | |
| 1560 | #define CSC_DESTINATION_Y 11:0 | |
| 1561 | ||
| 1562 | #define CSC_DESTINATION_DIMENSION 0x1000EC | |
| 1563 | #define CSC_DESTINATION_DIMENSION_X 31:16 | |
| 1564 | #define CSC_DESTINATION_DIMENSION_Y 15:0 | |
| 1565 | ||
| 1566 | #define CSC_DESTINATION_PITCH 0x1000F0 | |
| 1567 | #define CSC_DESTINATION_PITCH_X 31:16 | |
| 1568 | #define CSC_DESTINATION_PITCH_Y 15:0 | |
| 1569 | ||
| 1570 | #define CSC_SCALE_FACTOR 0x1000F4 | |
| 1571 | #define CSC_SCALE_FACTOR_HORIZONTAL 31:16 | |
| 1572 | #define CSC_SCALE_FACTOR_VERTICAL 15:0 | |
| 1573 | ||
| 1574 | #define CSC_DESTINATION_BASE 0x1000F8 | |
| 1575 | #define CSC_DESTINATION_BASE_EXT 27:27 | |
| 1576 | #define CSC_DESTINATION_BASE_EXT_LOCAL 0 | |
| 1577 | #define CSC_DESTINATION_BASE_EXT_EXTERNAL 1 | |
| 1578 | #define CSC_DESTINATION_BASE_CS 26:26 | |
| 1579 | #define CSC_DESTINATION_BASE_CS_0 0 | |
| 1580 | #define CSC_DESTINATION_BASE_CS_1 1 | |
| 1581 | #define CSC_DESTINATION_BASE_ADDRESS 25:0 | |
| 1582 | ||
| 1583 | #define CSC_CONTROL 0x1000FC | |
| 1584 | #define CSC_CONTROL_STATUS 31:31 | |
| 1585 | #define CSC_CONTROL_STATUS_STOP 0 | |
| 1586 | #define CSC_CONTROL_STATUS_START 1 | |
| 1587 | #define CSC_CONTROL_SOURCE_FORMAT 30:28 | |
| 1588 | #define CSC_CONTROL_SOURCE_FORMAT_YUV422 0 | |
| 1589 | #define CSC_CONTROL_SOURCE_FORMAT_YUV420I 1 | |
| 1590 | #define CSC_CONTROL_SOURCE_FORMAT_YUV420 2 | |
| 1591 | #define CSC_CONTROL_SOURCE_FORMAT_YVU9 3 | |
| 1592 | #define CSC_CONTROL_SOURCE_FORMAT_IYU1 4 | |
| 1593 | #define CSC_CONTROL_SOURCE_FORMAT_IYU2 5 | |
| 1594 | #define CSC_CONTROL_SOURCE_FORMAT_RGB565 6 | |
| 1595 | #define CSC_CONTROL_SOURCE_FORMAT_RGB8888 7 | |
| 1596 | #define CSC_CONTROL_DESTINATION_FORMAT 27:26 | |
| 1597 | #define CSC_CONTROL_DESTINATION_FORMAT_RGB565 0 | |
| 1598 | #define CSC_CONTROL_DESTINATION_FORMAT_RGB8888 1 | |
| 1599 | #define CSC_CONTROL_HORIZONTAL_FILTER 25:25 | |
| 1600 | #define CSC_CONTROL_HORIZONTAL_FILTER_DISABLE 0 | |
| 1601 | #define CSC_CONTROL_HORIZONTAL_FILTER_ENABLE 1 | |
| 1602 | #define CSC_CONTROL_VERTICAL_FILTER 24:24 | |
| 1603 | #define CSC_CONTROL_VERTICAL_FILTER_DISABLE 0 | |
| 1604 | #define CSC_CONTROL_VERTICAL_FILTER_ENABLE 1 | |
| 1605 | #define CSC_CONTROL_BYTE_ORDER 23:23 | |
| 1606 | #define CSC_CONTROL_BYTE_ORDER_YUYV 0 | |
| 1607 | #define CSC_CONTROL_BYTE_ORDER_UYVY 1 | |
| 1608 | ||
| 1609 | #define DE_DATA_PORT 0x110000 | |
| 1610 | ||
| 1611 | #define I2C_BYTE_COUNT 0x010040 | |
| 1612 | #define I2C_BYTE_COUNT_COUNT 3:0 | |
| 1613 | ||
| 1614 | #define I2C_CTRL 0x010041 | |
| b71413e0 MR |
1615 | #define I2C_CTRL_INT BIT(4) |
| 1616 | #define I2C_CTRL_DIR BIT(3) | |
| 1617 | #define I2C_CTRL_CTRL BIT(2) | |
| 1618 | #define I2C_CTRL_MODE BIT(1) | |
| 1619 | #define I2C_CTRL_EN BIT(0) | |
| 81dee67e SM |
1620 | |
| 1621 | #define I2C_STATUS 0x010042 | |
| 3e155b81 MR |
1622 | #define I2C_STATUS_TX BIT(3) |
| 1623 | #define I2C_STATUS_ERR BIT(2) | |
| 1624 | #define I2C_STATUS_ACK BIT(1) | |
| 1625 | #define I2C_STATUS_BSY BIT(0) | |
| 81dee67e SM |
1626 | |
| 1627 | #define I2C_RESET 0x010042 | |
| 1628 | #define I2C_RESET_BUS_ERROR 2:2 | |
| 1629 | #define I2C_RESET_BUS_ERROR_CLEAR 0 | |
| 1630 | ||
| 1631 | #define I2C_SLAVE_ADDRESS 0x010043 | |
| 1632 | #define I2C_SLAVE_ADDRESS_ADDRESS 7:1 | |
| 1633 | #define I2C_SLAVE_ADDRESS_RW 0:0 | |
| 1634 | #define I2C_SLAVE_ADDRESS_RW_W 0 | |
| 1635 | #define I2C_SLAVE_ADDRESS_RW_R 1 | |
| 1636 | ||
| 1637 | #define I2C_DATA0 0x010044 | |
| 1638 | #define I2C_DATA1 0x010045 | |
| 1639 | #define I2C_DATA2 0x010046 | |
| 1640 | #define I2C_DATA3 0x010047 | |
| 1641 | #define I2C_DATA4 0x010048 | |
| 1642 | #define I2C_DATA5 0x010049 | |
| 1643 | #define I2C_DATA6 0x01004A | |
| 1644 | #define I2C_DATA7 0x01004B | |
| 1645 | #define I2C_DATA8 0x01004C | |
| 1646 | #define I2C_DATA9 0x01004D | |
| 1647 | #define I2C_DATA10 0x01004E | |
| 1648 | #define I2C_DATA11 0x01004F | |
| 1649 | #define I2C_DATA12 0x010050 | |
| 1650 | #define I2C_DATA13 0x010051 | |
| 1651 | #define I2C_DATA14 0x010052 | |
| 1652 | #define I2C_DATA15 0x010053 | |
| 1653 | ||
| 1654 | ||
| 1655 | #define ZV0_CAPTURE_CTRL 0x090000 | |
| 1656 | #define ZV0_CAPTURE_CTRL_FIELD_INPUT 27:27 | |
| 1657 | #define ZV0_CAPTURE_CTRL_FIELD_INPUT_EVEN_FIELD 0 | |
| 1658 | #define ZV0_CAPTURE_CTRL_FIELD_INPUT_ODD_FIELD 1 | |
| 1659 | #define ZV0_CAPTURE_CTRL_SCAN 26:26 | |
| 1660 | #define ZV0_CAPTURE_CTRL_SCAN_PROGRESSIVE 0 | |
| 1661 | #define ZV0_CAPTURE_CTRL_SCAN_INTERLACE 1 | |
| 1662 | #define ZV0_CAPTURE_CTRL_CURRENT_BUFFER 25:25 | |
| 1663 | #define ZV0_CAPTURE_CTRL_CURRENT_BUFFER_0 0 | |
| 1664 | #define ZV0_CAPTURE_CTRL_CURRENT_BUFFER_1 1 | |
| 1665 | #define ZV0_CAPTURE_CTRL_VERTICAL_SYNC 24:24 | |
| 1666 | #define ZV0_CAPTURE_CTRL_VERTICAL_SYNC_INACTIVE 0 | |
| 1667 | #define ZV0_CAPTURE_CTRL_VERTICAL_SYNC_ACTIVE 1 | |
| 1668 | #define ZV0_CAPTURE_CTRL_ADJ 19:19 | |
| 1669 | #define ZV0_CAPTURE_CTRL_ADJ_NORMAL 0 | |
| 1670 | #define ZV0_CAPTURE_CTRL_ADJ_DELAY 1 | |
| 1671 | #define ZV0_CAPTURE_CTRL_HA 18:18 | |
| 1672 | #define ZV0_CAPTURE_CTRL_HA_DISABLE 0 | |
| 1673 | #define ZV0_CAPTURE_CTRL_HA_ENABLE 1 | |
| 1674 | #define ZV0_CAPTURE_CTRL_VSK 17:17 | |
| 1675 | #define ZV0_CAPTURE_CTRL_VSK_DISABLE 0 | |
| 1676 | #define ZV0_CAPTURE_CTRL_VSK_ENABLE 1 | |
| 1677 | #define ZV0_CAPTURE_CTRL_HSK 16:16 | |
| 1678 | #define ZV0_CAPTURE_CTRL_HSK_DISABLE 0 | |
| 1679 | #define ZV0_CAPTURE_CTRL_HSK_ENABLE 1 | |
| 1680 | #define ZV0_CAPTURE_CTRL_FD 15:15 | |
| 1681 | #define ZV0_CAPTURE_CTRL_FD_RISING 0 | |
| 1682 | #define ZV0_CAPTURE_CTRL_FD_FALLING 1 | |
| 1683 | #define ZV0_CAPTURE_CTRL_VP 14:14 | |
| 1684 | #define ZV0_CAPTURE_CTRL_VP_HIGH 0 | |
| 1685 | #define ZV0_CAPTURE_CTRL_VP_LOW 1 | |
| 1686 | #define ZV0_CAPTURE_CTRL_HP 13:13 | |
| 1687 | #define ZV0_CAPTURE_CTRL_HP_HIGH 0 | |
| 1688 | #define ZV0_CAPTURE_CTRL_HP_LOW 1 | |
| 1689 | #define ZV0_CAPTURE_CTRL_CP 12:12 | |
| 1690 | #define ZV0_CAPTURE_CTRL_CP_HIGH 0 | |
| 1691 | #define ZV0_CAPTURE_CTRL_CP_LOW 1 | |
| 1692 | #define ZV0_CAPTURE_CTRL_UVS 11:11 | |
| 1693 | #define ZV0_CAPTURE_CTRL_UVS_DISABLE 0 | |
| 1694 | #define ZV0_CAPTURE_CTRL_UVS_ENABLE 1 | |
| 1695 | #define ZV0_CAPTURE_CTRL_BS 10:10 | |
| 1696 | #define ZV0_CAPTURE_CTRL_BS_DISABLE 0 | |
| 1697 | #define ZV0_CAPTURE_CTRL_BS_ENABLE 1 | |
| 1698 | #define ZV0_CAPTURE_CTRL_CS 9:9 | |
| 1699 | #define ZV0_CAPTURE_CTRL_CS_16 0 | |
| 1700 | #define ZV0_CAPTURE_CTRL_CS_8 1 | |
| 1701 | #define ZV0_CAPTURE_CTRL_CF 8:8 | |
| 1702 | #define ZV0_CAPTURE_CTRL_CF_YUV 0 | |
| 1703 | #define ZV0_CAPTURE_CTRL_CF_RGB 1 | |
| 1704 | #define ZV0_CAPTURE_CTRL_FS 7:7 | |
| 1705 | #define ZV0_CAPTURE_CTRL_FS_DISABLE 0 | |
| 1706 | #define ZV0_CAPTURE_CTRL_FS_ENABLE 1 | |
| 1707 | #define ZV0_CAPTURE_CTRL_WEAVE 6:6 | |
| 1708 | #define ZV0_CAPTURE_CTRL_WEAVE_DISABLE 0 | |
| 1709 | #define ZV0_CAPTURE_CTRL_WEAVE_ENABLE 1 | |
| 1710 | #define ZV0_CAPTURE_CTRL_BOB 5:5 | |
| 1711 | #define ZV0_CAPTURE_CTRL_BOB_DISABLE 0 | |
| 1712 | #define ZV0_CAPTURE_CTRL_BOB_ENABLE 1 | |
| 1713 | #define ZV0_CAPTURE_CTRL_DB 4:4 | |
| 1714 | #define ZV0_CAPTURE_CTRL_DB_DISABLE 0 | |
| 1715 | #define ZV0_CAPTURE_CTRL_DB_ENABLE 1 | |
| 1716 | #define ZV0_CAPTURE_CTRL_CC 3:3 | |
| 1717 | #define ZV0_CAPTURE_CTRL_CC_CONTINUE 0 | |
| 1718 | #define ZV0_CAPTURE_CTRL_CC_CONDITION 1 | |
| 1719 | #define ZV0_CAPTURE_CTRL_RGB 2:2 | |
| 1720 | #define ZV0_CAPTURE_CTRL_RGB_DISABLE 0 | |
| 1721 | #define ZV0_CAPTURE_CTRL_RGB_ENABLE 1 | |
| 1722 | #define ZV0_CAPTURE_CTRL_656 1:1 | |
| 1723 | #define ZV0_CAPTURE_CTRL_656_DISABLE 0 | |
| 1724 | #define ZV0_CAPTURE_CTRL_656_ENABLE 1 | |
| 1725 | #define ZV0_CAPTURE_CTRL_CAP 0:0 | |
| 1726 | #define ZV0_CAPTURE_CTRL_CAP_DISABLE 0 | |
| 1727 | #define ZV0_CAPTURE_CTRL_CAP_ENABLE 1 | |
| 1728 | ||
| 1729 | #define ZV0_CAPTURE_CLIP 0x090004 | |
| 1730 | #define ZV0_CAPTURE_CLIP_YCLIP_EVEN_FIELD 25:16 | |
| 1731 | #define ZV0_CAPTURE_CLIP_YCLIP 25:16 | |
| 1732 | #define ZV0_CAPTURE_CLIP_XCLIP 9:0 | |
| 1733 | ||
| 1734 | #define ZV0_CAPTURE_SIZE 0x090008 | |
| 1735 | #define ZV0_CAPTURE_SIZE_HEIGHT 26:16 | |
| 1736 | #define ZV0_CAPTURE_SIZE_WIDTH 10:0 | |
| 1737 | ||
| 1738 | #define ZV0_CAPTURE_BUF0_ADDRESS 0x09000C | |
| 1739 | #define ZV0_CAPTURE_BUF0_ADDRESS_STATUS 31:31 | |
| 1740 | #define ZV0_CAPTURE_BUF0_ADDRESS_STATUS_CURRENT 0 | |
| 1741 | #define ZV0_CAPTURE_BUF0_ADDRESS_STATUS_PENDING 1 | |
| 1742 | #define ZV0_CAPTURE_BUF0_ADDRESS_EXT 27:27 | |
| 1743 | #define ZV0_CAPTURE_BUF0_ADDRESS_EXT_LOCAL 0 | |
| 1744 | #define ZV0_CAPTURE_BUF0_ADDRESS_EXT_EXTERNAL 1 | |
| 1745 | #define ZV0_CAPTURE_BUF0_ADDRESS_CS 26:26 | |
| 1746 | #define ZV0_CAPTURE_BUF0_ADDRESS_CS_0 0 | |
| 1747 | #define ZV0_CAPTURE_BUF0_ADDRESS_CS_1 1 | |
| 1748 | #define ZV0_CAPTURE_BUF0_ADDRESS_ADDRESS 25:0 | |
| 1749 | ||
| 1750 | #define ZV0_CAPTURE_BUF1_ADDRESS 0x090010 | |
| 1751 | #define ZV0_CAPTURE_BUF1_ADDRESS_STATUS 31:31 | |
| 1752 | #define ZV0_CAPTURE_BUF1_ADDRESS_STATUS_CURRENT 0 | |
| 1753 | #define ZV0_CAPTURE_BUF1_ADDRESS_STATUS_PENDING 1 | |
| 1754 | #define ZV0_CAPTURE_BUF1_ADDRESS_EXT 27:27 | |
| 1755 | #define ZV0_CAPTURE_BUF1_ADDRESS_EXT_LOCAL 0 | |
| 1756 | #define ZV0_CAPTURE_BUF1_ADDRESS_EXT_EXTERNAL 1 | |
| 1757 | #define ZV0_CAPTURE_BUF1_ADDRESS_CS 26:26 | |
| 1758 | #define ZV0_CAPTURE_BUF1_ADDRESS_CS_0 0 | |
| 1759 | #define ZV0_CAPTURE_BUF1_ADDRESS_CS_1 1 | |
| 1760 | #define ZV0_CAPTURE_BUF1_ADDRESS_ADDRESS 25:0 | |
| 1761 | ||
| 1762 | #define ZV0_CAPTURE_BUF_OFFSET 0x090014 | |
| 1763 | #ifndef VALIDATION_CHIP | |
| 1764 | #define ZV0_CAPTURE_BUF_OFFSET_YCLIP_ODD_FIELD 25:16 | |
| 1765 | #endif | |
| 1766 | #define ZV0_CAPTURE_BUF_OFFSET_OFFSET 15:0 | |
| 1767 | ||
| 1768 | #define ZV0_CAPTURE_FIFO_CTRL 0x090018 | |
| 1769 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO 2:0 | |
| 1770 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_0 0 | |
| 1771 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_1 1 | |
| 1772 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_2 2 | |
| 1773 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_3 3 | |
| 1774 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_4 4 | |
| 1775 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_5 5 | |
| 1776 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_6 6 | |
| 1777 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_7 7 | |
| 1778 | ||
| 1779 | #define ZV0_CAPTURE_YRGB_CONST 0x09001C | |
| 1780 | #define ZV0_CAPTURE_YRGB_CONST_Y 31:24 | |
| 1781 | #define ZV0_CAPTURE_YRGB_CONST_R 23:16 | |
| 1782 | #define ZV0_CAPTURE_YRGB_CONST_G 15:8 | |
| 1783 | #define ZV0_CAPTURE_YRGB_CONST_B 7:0 | |
| 1784 | ||
| 1785 | #define ZV0_CAPTURE_LINE_COMP 0x090020 | |
| 1786 | #define ZV0_CAPTURE_LINE_COMP_LC 10:0 | |
| 1787 | ||
| 1788 | /* ZV1 */ | |
| 1789 | ||
| 1790 | #define ZV1_CAPTURE_CTRL 0x098000 | |
| 1791 | #define ZV1_CAPTURE_CTRL_FIELD_INPUT 27:27 | |
| 1792 | #define ZV1_CAPTURE_CTRL_FIELD_INPUT_EVEN_FIELD 0 | |
| 1793 | #define ZV1_CAPTURE_CTRL_FIELD_INPUT_ODD_FIELD 0 | |
| 1794 | #define ZV1_CAPTURE_CTRL_SCAN 26:26 | |
| 1795 | #define ZV1_CAPTURE_CTRL_SCAN_PROGRESSIVE 0 | |
| 1796 | #define ZV1_CAPTURE_CTRL_SCAN_INTERLACE 1 | |
| 1797 | #define ZV1_CAPTURE_CTRL_CURRENT_BUFFER 25:25 | |
| 1798 | #define ZV1_CAPTURE_CTRL_CURRENT_BUFFER_0 0 | |
| 1799 | #define ZV1_CAPTURE_CTRL_CURRENT_BUFFER_1 1 | |
| 1800 | #define ZV1_CAPTURE_CTRL_VERTICAL_SYNC 24:24 | |
| 1801 | #define ZV1_CAPTURE_CTRL_VERTICAL_SYNC_INACTIVE 0 | |
| 1802 | #define ZV1_CAPTURE_CTRL_VERTICAL_SYNC_ACTIVE 1 | |
| 1803 | #define ZV1_CAPTURE_CTRL_PANEL 20:20 | |
| 1804 | #define ZV1_CAPTURE_CTRL_PANEL_DISABLE 0 | |
| 1805 | #define ZV1_CAPTURE_CTRL_PANEL_ENABLE 1 | |
| 1806 | #define ZV1_CAPTURE_CTRL_ADJ 19:19 | |
| 1807 | #define ZV1_CAPTURE_CTRL_ADJ_NORMAL 0 | |
| 1808 | #define ZV1_CAPTURE_CTRL_ADJ_DELAY 1 | |
| 1809 | #define ZV1_CAPTURE_CTRL_HA 18:18 | |
| 1810 | #define ZV1_CAPTURE_CTRL_HA_DISABLE 0 | |
| 1811 | #define ZV1_CAPTURE_CTRL_HA_ENABLE 1 | |
| 1812 | #define ZV1_CAPTURE_CTRL_VSK 17:17 | |
| 1813 | #define ZV1_CAPTURE_CTRL_VSK_DISABLE 0 | |
| 1814 | #define ZV1_CAPTURE_CTRL_VSK_ENABLE 1 | |
| 1815 | #define ZV1_CAPTURE_CTRL_HSK 16:16 | |
| 1816 | #define ZV1_CAPTURE_CTRL_HSK_DISABLE 0 | |
| 1817 | #define ZV1_CAPTURE_CTRL_HSK_ENABLE 1 | |
| 1818 | #define ZV1_CAPTURE_CTRL_FD 15:15 | |
| 1819 | #define ZV1_CAPTURE_CTRL_FD_RISING 0 | |
| 1820 | #define ZV1_CAPTURE_CTRL_FD_FALLING 1 | |
| 1821 | #define ZV1_CAPTURE_CTRL_VP 14:14 | |
| 1822 | #define ZV1_CAPTURE_CTRL_VP_HIGH 0 | |
| 1823 | #define ZV1_CAPTURE_CTRL_VP_LOW 1 | |
| 1824 | #define ZV1_CAPTURE_CTRL_HP 13:13 | |
| 1825 | #define ZV1_CAPTURE_CTRL_HP_HIGH 0 | |
| 1826 | #define ZV1_CAPTURE_CTRL_HP_LOW 1 | |
| 1827 | #define ZV1_CAPTURE_CTRL_CP 12:12 | |
| 1828 | #define ZV1_CAPTURE_CTRL_CP_HIGH 0 | |
| 1829 | #define ZV1_CAPTURE_CTRL_CP_LOW 1 | |
| 1830 | #define ZV1_CAPTURE_CTRL_UVS 11:11 | |
| 1831 | #define ZV1_CAPTURE_CTRL_UVS_DISABLE 0 | |
| 1832 | #define ZV1_CAPTURE_CTRL_UVS_ENABLE 1 | |
| 1833 | #define ZV1_CAPTURE_CTRL_BS 10:10 | |
| 1834 | #define ZV1_CAPTURE_CTRL_BS_DISABLE 0 | |
| 1835 | #define ZV1_CAPTURE_CTRL_BS_ENABLE 1 | |
| 1836 | #define ZV1_CAPTURE_CTRL_CS 9:9 | |
| 1837 | #define ZV1_CAPTURE_CTRL_CS_16 0 | |
| 1838 | #define ZV1_CAPTURE_CTRL_CS_8 1 | |
| 1839 | #define ZV1_CAPTURE_CTRL_CF 8:8 | |
| 1840 | #define ZV1_CAPTURE_CTRL_CF_YUV 0 | |
| 1841 | #define ZV1_CAPTURE_CTRL_CF_RGB 1 | |
| 1842 | #define ZV1_CAPTURE_CTRL_FS 7:7 | |
| 1843 | #define ZV1_CAPTURE_CTRL_FS_DISABLE 0 | |
| 1844 | #define ZV1_CAPTURE_CTRL_FS_ENABLE 1 | |
| 1845 | #define ZV1_CAPTURE_CTRL_WEAVE 6:6 | |
| 1846 | #define ZV1_CAPTURE_CTRL_WEAVE_DISABLE 0 | |
| 1847 | #define ZV1_CAPTURE_CTRL_WEAVE_ENABLE 1 | |
| 1848 | #define ZV1_CAPTURE_CTRL_BOB 5:5 | |
| 1849 | #define ZV1_CAPTURE_CTRL_BOB_DISABLE 0 | |
| 1850 | #define ZV1_CAPTURE_CTRL_BOB_ENABLE 1 | |
| 1851 | #define ZV1_CAPTURE_CTRL_DB 4:4 | |
| 1852 | #define ZV1_CAPTURE_CTRL_DB_DISABLE 0 | |
| 1853 | #define ZV1_CAPTURE_CTRL_DB_ENABLE 1 | |
| 1854 | #define ZV1_CAPTURE_CTRL_CC 3:3 | |
| 1855 | #define ZV1_CAPTURE_CTRL_CC_CONTINUE 0 | |
| 1856 | #define ZV1_CAPTURE_CTRL_CC_CONDITION 1 | |
| 1857 | #define ZV1_CAPTURE_CTRL_RGB 2:2 | |
| 1858 | #define ZV1_CAPTURE_CTRL_RGB_DISABLE 0 | |
| 1859 | #define ZV1_CAPTURE_CTRL_RGB_ENABLE 1 | |
| 1860 | #define ZV1_CAPTURE_CTRL_656 1:1 | |
| 1861 | #define ZV1_CAPTURE_CTRL_656_DISABLE 0 | |
| 1862 | #define ZV1_CAPTURE_CTRL_656_ENABLE 1 | |
| 1863 | #define ZV1_CAPTURE_CTRL_CAP 0:0 | |
| 1864 | #define ZV1_CAPTURE_CTRL_CAP_DISABLE 0 | |
| 1865 | #define ZV1_CAPTURE_CTRL_CAP_ENABLE 1 | |
| 1866 | ||
| 1867 | #define ZV1_CAPTURE_CLIP 0x098004 | |
| 1868 | #define ZV1_CAPTURE_CLIP_YCLIP 25:16 | |
| 1869 | #define ZV1_CAPTURE_CLIP_XCLIP 9:0 | |
| 1870 | ||
| 1871 | #define ZV1_CAPTURE_SIZE 0x098008 | |
| 1872 | #define ZV1_CAPTURE_SIZE_HEIGHT 26:16 | |
| 1873 | #define ZV1_CAPTURE_SIZE_WIDTH 10:0 | |
| 1874 | ||
| 1875 | #define ZV1_CAPTURE_BUF0_ADDRESS 0x09800C | |
| 1876 | #define ZV1_CAPTURE_BUF0_ADDRESS_STATUS 31:31 | |
| 1877 | #define ZV1_CAPTURE_BUF0_ADDRESS_STATUS_CURRENT 0 | |
| 1878 | #define ZV1_CAPTURE_BUF0_ADDRESS_STATUS_PENDING 1 | |
| 1879 | #define ZV1_CAPTURE_BUF0_ADDRESS_EXT 27:27 | |
| 1880 | #define ZV1_CAPTURE_BUF0_ADDRESS_EXT_LOCAL 0 | |
| 1881 | #define ZV1_CAPTURE_BUF0_ADDRESS_EXT_EXTERNAL 1 | |
| 1882 | #define ZV1_CAPTURE_BUF0_ADDRESS_CS 26:26 | |
| 1883 | #define ZV1_CAPTURE_BUF0_ADDRESS_CS_0 0 | |
| 1884 | #define ZV1_CAPTURE_BUF0_ADDRESS_CS_1 1 | |
| 1885 | #define ZV1_CAPTURE_BUF0_ADDRESS_ADDRESS 25:0 | |
| 1886 | ||
| 1887 | #define ZV1_CAPTURE_BUF1_ADDRESS 0x098010 | |
| 1888 | #define ZV1_CAPTURE_BUF1_ADDRESS_STATUS 31:31 | |
| 1889 | #define ZV1_CAPTURE_BUF1_ADDRESS_STATUS_CURRENT 0 | |
| 1890 | #define ZV1_CAPTURE_BUF1_ADDRESS_STATUS_PENDING 1 | |
| 1891 | #define ZV1_CAPTURE_BUF1_ADDRESS_EXT 27:27 | |
| 1892 | #define ZV1_CAPTURE_BUF1_ADDRESS_EXT_LOCAL 0 | |
| 1893 | #define ZV1_CAPTURE_BUF1_ADDRESS_EXT_EXTERNAL 1 | |
| 1894 | #define ZV1_CAPTURE_BUF1_ADDRESS_CS 26:26 | |
| 1895 | #define ZV1_CAPTURE_BUF1_ADDRESS_CS_0 0 | |
| 1896 | #define ZV1_CAPTURE_BUF1_ADDRESS_CS_1 1 | |
| 1897 | #define ZV1_CAPTURE_BUF1_ADDRESS_ADDRESS 25:0 | |
| 1898 | ||
| 1899 | #define ZV1_CAPTURE_BUF_OFFSET 0x098014 | |
| 1900 | #define ZV1_CAPTURE_BUF_OFFSET_OFFSET 15:0 | |
| 1901 | ||
| 1902 | #define ZV1_CAPTURE_FIFO_CTRL 0x098018 | |
| 1903 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO 2:0 | |
| 1904 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_0 0 | |
| 1905 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_1 1 | |
| 1906 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_2 2 | |
| 1907 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_3 3 | |
| 1908 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_4 4 | |
| 1909 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_5 5 | |
| 1910 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_6 6 | |
| 1911 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_7 7 | |
| 1912 | ||
| 1913 | #define ZV1_CAPTURE_YRGB_CONST 0x09801C | |
| 1914 | #define ZV1_CAPTURE_YRGB_CONST_Y 31:24 | |
| 1915 | #define ZV1_CAPTURE_YRGB_CONST_R 23:16 | |
| 1916 | #define ZV1_CAPTURE_YRGB_CONST_G 15:8 | |
| 1917 | #define ZV1_CAPTURE_YRGB_CONST_B 7:0 | |
| 1918 | ||
| 1919 | #define DMA_1_SOURCE 0x0D0010 | |
| 1920 | #define DMA_1_SOURCE_ADDRESS_EXT 27:27 | |
| 1921 | #define DMA_1_SOURCE_ADDRESS_EXT_LOCAL 0 | |
| 1922 | #define DMA_1_SOURCE_ADDRESS_EXT_EXTERNAL 1 | |
| 1923 | #define DMA_1_SOURCE_ADDRESS_CS 26:26 | |
| 1924 | #define DMA_1_SOURCE_ADDRESS_CS_0 0 | |
| 1925 | #define DMA_1_SOURCE_ADDRESS_CS_1 1 | |
| 1926 | #define DMA_1_SOURCE_ADDRESS 25:0 | |
| 1927 | ||
| 1928 | #define DMA_1_DESTINATION 0x0D0014 | |
| 1929 | #define DMA_1_DESTINATION_ADDRESS_EXT 27:27 | |
| 1930 | #define DMA_1_DESTINATION_ADDRESS_EXT_LOCAL 0 | |
| 1931 | #define DMA_1_DESTINATION_ADDRESS_EXT_EXTERNAL 1 | |
| 1932 | #define DMA_1_DESTINATION_ADDRESS_CS 26:26 | |
| 1933 | #define DMA_1_DESTINATION_ADDRESS_CS_0 0 | |
| 1934 | #define DMA_1_DESTINATION_ADDRESS_CS_1 1 | |
| 1935 | #define DMA_1_DESTINATION_ADDRESS 25:0 | |
| 1936 | ||
| 1937 | #define DMA_1_SIZE_CONTROL 0x0D0018 | |
| 1938 | #define DMA_1_SIZE_CONTROL_STATUS 31:31 | |
| 1939 | #define DMA_1_SIZE_CONTROL_STATUS_IDLE 0 | |
| 1940 | #define DMA_1_SIZE_CONTROL_STATUS_ACTIVE 1 | |
| 1941 | #define DMA_1_SIZE_CONTROL_SIZE 23:0 | |
| 1942 | ||
| 1943 | #define DMA_ABORT_INTERRUPT 0x0D0020 | |
| 0f23be70 MR |
1944 | #define DMA_ABORT_INTERRUPT_ABORT_1 BIT(5) |
| 1945 | #define DMA_ABORT_INTERRUPT_ABORT_0 BIT(4) | |
| 1946 | #define DMA_ABORT_INTERRUPT_INT_1 BIT(1) | |
| 1947 | #define DMA_ABORT_INTERRUPT_INT_0 BIT(0) | |
| 81dee67e SM |
1948 | |
| 1949 | /* Default i2c CLK and Data GPIO. These are the default i2c pins */ | |
| 1950 | #define DEFAULT_I2C_SCL 30 | |
| 1951 | #define DEFAULT_I2C_SDA 31 | |
| 1952 | ||
| 1953 | ||
| 1954 | #define GPIO_DATA_SM750LE 0x020018 | |
| 1955 | #define GPIO_DATA_SM750LE_1 1:1 | |
| 1956 | #define GPIO_DATA_SM750LE_0 0:0 | |
| 1957 | ||
| 1958 | #define GPIO_DATA_DIRECTION_SM750LE 0x02001C | |
| 1959 | #define GPIO_DATA_DIRECTION_SM750LE_1 1:1 | |
| 1960 | #define GPIO_DATA_DIRECTION_SM750LE_1_INPUT 0 | |
| 1961 | #define GPIO_DATA_DIRECTION_SM750LE_1_OUTPUT 1 | |
| 1962 | #define GPIO_DATA_DIRECTION_SM750LE_0 0:0 | |
| 1963 | #define GPIO_DATA_DIRECTION_SM750LE_0_INPUT 0 | |
| 1964 | #define GPIO_DATA_DIRECTION_SM750LE_0_OUTPUT 1 | |
| 1965 | ||
| 1966 | ||
| 1967 | #endif |