Commit | Line | Data |
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81dee67e SM |
1 | #ifndef DDK750_REG_H__ |
2 | #define DDK750_REG_H__ | |
3 | ||
4 | /* New register for SM750LE */ | |
5 | #define DE_STATE1 0x100054 | |
c808d6ce | 6 | #define DE_STATE1_DE_ABORT BIT(0) |
81dee67e SM |
7 | |
8 | #define DE_STATE2 0x100058 | |
ae6061db MR |
9 | #define DE_STATE2_DE_FIFO_EMPTY BIT(3) |
10 | #define DE_STATE2_DE_STATUS_BUSY BIT(2) | |
11 | #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1) | |
81dee67e SM |
12 | |
13 | #define SYSTEM_CTRL 0x000000 | |
a8856ff8 MR |
14 | #define SYSTEM_CTRL_DPMS_MASK (0x3 << 30) |
15 | #define SYSTEM_CTRL_DPMS_VPHP (0x0 << 30) | |
16 | #define SYSTEM_CTRL_DPMS_VPHN (0x1 << 30) | |
17 | #define SYSTEM_CTRL_DPMS_VNHP (0x2 << 30) | |
18 | #define SYSTEM_CTRL_DPMS_VNHN (0x3 << 30) | |
410c756d MR |
19 | #define SYSTEM_CTRL_PCI_BURST BIT(29) |
20 | #define SYSTEM_CTRL_PCI_MASTER BIT(25) | |
21 | #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24) | |
22 | #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23) | |
23 | #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22) | |
24 | #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21) | |
25 | #define SYSTEM_CTRL_CSC_STATUS_BUSY BIT(20) | |
26 | #define SYSTEM_CTRL_CRT_VSYNC_ACTIVE BIT(19) | |
27 | #define SYSTEM_CTRL_PANEL_VSYNC_ACTIVE BIT(18) | |
28 | #define SYSTEM_CTRL_CURRENT_BUFFER_FLIP_PENDING BIT(17) | |
29 | #define SYSTEM_CTRL_DMA_STATUS_BUSY BIT(16) | |
30 | #define SYSTEM_CTRL_PCI_BURST_READ BIT(15) | |
31 | #define SYSTEM_CTRL_DE_ABORT BIT(13) | |
32 | #define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK BIT(11) | |
33 | #define SYSTEM_CTRL_PCI_RETRY_OFF BIT(7) | |
a8856ff8 MR |
34 | #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_MASK (0x3 << 4) |
35 | #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1 (0x0 << 4) | |
36 | #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2 (0x1 << 4) | |
37 | #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4 (0x2 << 4) | |
38 | #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8 (0x3 << 4) | |
410c756d MR |
39 | #define SYSTEM_CTRL_CRT_TRISTATE BIT(3) |
40 | #define SYSTEM_CTRL_PCIMEM_TRISTATE BIT(2) | |
41 | #define SYSTEM_CTRL_LOCALMEM_TRISTATE BIT(1) | |
42 | #define SYSTEM_CTRL_PANEL_TRISTATE BIT(0) | |
81dee67e SM |
43 | |
44 | #define MISC_CTRL 0x000004 | |
5372350b | 45 | #define MISC_CTRL_DRAM_RERESH_COUNT BIT(27) |
5538d5c8 MR |
46 | #define MISC_CTRL_DRAM_REFRESH_TIME_MASK (0x3 << 25) |
47 | #define MISC_CTRL_DRAM_REFRESH_TIME_8 (0x0 << 25) | |
48 | #define MISC_CTRL_DRAM_REFRESH_TIME_16 (0x1 << 25) | |
49 | #define MISC_CTRL_DRAM_REFRESH_TIME_32 (0x2 << 25) | |
50 | #define MISC_CTRL_DRAM_REFRESH_TIME_64 (0x3 << 25) | |
5372350b MR |
51 | #define MISC_CTRL_INT_OUTPUT_INVERT BIT(24) |
52 | #define MISC_CTRL_PLL_CLK_COUNT BIT(23) | |
53 | #define MISC_CTRL_DAC_POWER_OFF BIT(20) | |
54 | #define MISC_CTRL_CLK_SELECT_TESTCLK BIT(16) | |
5538d5c8 MR |
55 | #define MISC_CTRL_DRAM_COLUMN_SIZE_MASK (0x3 << 14) |
56 | #define MISC_CTRL_DRAM_COLUMN_SIZE_256 (0x0 << 14) | |
57 | #define MISC_CTRL_DRAM_COLUMN_SIZE_512 (0x1 << 14) | |
58 | #define MISC_CTRL_DRAM_COLUMN_SIZE_1024 (0x2 << 14) | |
59 | #define MISC_CTRL_LOCALMEM_SIZE_MASK (0x3 << 12) | |
60 | #define MISC_CTRL_LOCALMEM_SIZE_8M (0x3 << 12) | |
61 | #define MISC_CTRL_LOCALMEM_SIZE_16M (0x0 << 12) | |
62 | #define MISC_CTRL_LOCALMEM_SIZE_32M (0x1 << 12) | |
63 | #define MISC_CTRL_LOCALMEM_SIZE_64M (0x2 << 12) | |
5372350b MR |
64 | #define MISC_CTRL_DRAM_TWTR BIT(11) |
65 | #define MISC_CTRL_DRAM_TWR BIT(10) | |
66 | #define MISC_CTRL_DRAM_TRP BIT(9) | |
67 | #define MISC_CTRL_DRAM_TRFC BIT(8) | |
68 | #define MISC_CTRL_DRAM_TRAS BIT(7) | |
69 | #define MISC_CTRL_LOCALMEM_RESET BIT(6) | |
70 | #define MISC_CTRL_LOCALMEM_STATE_INACTIVE BIT(5) | |
71 | #define MISC_CTRL_CPU_CAS_LATENCY BIT(4) | |
72 | #define MISC_CTRL_DLL_OFF BIT(3) | |
73 | #define MISC_CTRL_DRAM_OUTPUT_HIGH BIT(2) | |
74 | #define MISC_CTRL_LOCALMEM_BUS_SIZE BIT(1) | |
75 | #define MISC_CTRL_EMBEDDED_LOCALMEM_OFF BIT(0) | |
81dee67e SM |
76 | |
77 | #define GPIO_MUX 0x000008 | |
2a5149e0 MR |
78 | #define GPIO_MUX_31 BIT(31) |
79 | #define GPIO_MUX_30 BIT(30) | |
80 | #define GPIO_MUX_29 BIT(29) | |
81 | #define GPIO_MUX_28 BIT(28) | |
82 | #define GPIO_MUX_27 BIT(27) | |
83 | #define GPIO_MUX_26 BIT(26) | |
84 | #define GPIO_MUX_25 BIT(25) | |
85 | #define GPIO_MUX_24 BIT(24) | |
86 | #define GPIO_MUX_23 BIT(23) | |
87 | #define GPIO_MUX_22 BIT(22) | |
88 | #define GPIO_MUX_21 BIT(21) | |
89 | #define GPIO_MUX_20 BIT(20) | |
90 | #define GPIO_MUX_19 BIT(19) | |
91 | #define GPIO_MUX_18 BIT(18) | |
92 | #define GPIO_MUX_17 BIT(17) | |
93 | #define GPIO_MUX_16 BIT(16) | |
94 | #define GPIO_MUX_15 BIT(15) | |
95 | #define GPIO_MUX_14 BIT(14) | |
96 | #define GPIO_MUX_13 BIT(13) | |
97 | #define GPIO_MUX_12 BIT(12) | |
98 | #define GPIO_MUX_11 BIT(11) | |
99 | #define GPIO_MUX_10 BIT(10) | |
100 | #define GPIO_MUX_9 BIT(9) | |
101 | #define GPIO_MUX_8 BIT(8) | |
102 | #define GPIO_MUX_7 BIT(7) | |
103 | #define GPIO_MUX_6 BIT(6) | |
104 | #define GPIO_MUX_5 BIT(5) | |
105 | #define GPIO_MUX_4 BIT(4) | |
106 | #define GPIO_MUX_3 BIT(3) | |
107 | #define GPIO_MUX_2 BIT(2) | |
108 | #define GPIO_MUX_1 BIT(1) | |
109 | #define GPIO_MUX_0 BIT(0) | |
81dee67e SM |
110 | |
111 | #define LOCALMEM_ARBITRATION 0x00000C | |
112 | #define LOCALMEM_ARBITRATION_ROTATE 28:28 | |
113 | #define LOCALMEM_ARBITRATION_ROTATE_OFF 0 | |
114 | #define LOCALMEM_ARBITRATION_ROTATE_ON 1 | |
115 | #define LOCALMEM_ARBITRATION_VGA 26:24 | |
116 | #define LOCALMEM_ARBITRATION_VGA_OFF 0 | |
117 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_1 1 | |
118 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_2 2 | |
119 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_3 3 | |
120 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_4 4 | |
121 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_5 5 | |
122 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_6 6 | |
123 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_7 7 | |
124 | #define LOCALMEM_ARBITRATION_DMA 22:20 | |
125 | #define LOCALMEM_ARBITRATION_DMA_OFF 0 | |
126 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_1 1 | |
127 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_2 2 | |
128 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_3 3 | |
129 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_4 4 | |
130 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_5 5 | |
131 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_6 6 | |
132 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_7 7 | |
133 | #define LOCALMEM_ARBITRATION_ZVPORT1 18:16 | |
134 | #define LOCALMEM_ARBITRATION_ZVPORT1_OFF 0 | |
135 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_1 1 | |
136 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_2 2 | |
137 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_3 3 | |
138 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_4 4 | |
139 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_5 5 | |
140 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_6 6 | |
141 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_7 7 | |
142 | #define LOCALMEM_ARBITRATION_ZVPORT0 14:12 | |
143 | #define LOCALMEM_ARBITRATION_ZVPORT0_OFF 0 | |
144 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_1 1 | |
145 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_2 2 | |
146 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_3 3 | |
147 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_4 4 | |
148 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_5 5 | |
149 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_6 6 | |
150 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_7 7 | |
151 | #define LOCALMEM_ARBITRATION_VIDEO 10:8 | |
152 | #define LOCALMEM_ARBITRATION_VIDEO_OFF 0 | |
153 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_1 1 | |
154 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_2 2 | |
155 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_3 3 | |
156 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_4 4 | |
157 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_5 5 | |
158 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_6 6 | |
159 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_7 7 | |
160 | #define LOCALMEM_ARBITRATION_PANEL 6:4 | |
161 | #define LOCALMEM_ARBITRATION_PANEL_OFF 0 | |
162 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_1 1 | |
163 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_2 2 | |
164 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_3 3 | |
165 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_4 4 | |
166 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_5 5 | |
167 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_6 6 | |
168 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_7 7 | |
169 | #define LOCALMEM_ARBITRATION_CRT 2:0 | |
170 | #define LOCALMEM_ARBITRATION_CRT_OFF 0 | |
171 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_1 1 | |
172 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_2 2 | |
173 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_3 3 | |
174 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_4 4 | |
175 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_5 5 | |
176 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_6 6 | |
177 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_7 7 | |
178 | ||
179 | #define PCIMEM_ARBITRATION 0x000010 | |
180 | #define PCIMEM_ARBITRATION_ROTATE 28:28 | |
181 | #define PCIMEM_ARBITRATION_ROTATE_OFF 0 | |
182 | #define PCIMEM_ARBITRATION_ROTATE_ON 1 | |
183 | #define PCIMEM_ARBITRATION_VGA 26:24 | |
184 | #define PCIMEM_ARBITRATION_VGA_OFF 0 | |
185 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_1 1 | |
186 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_2 2 | |
187 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_3 3 | |
188 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_4 4 | |
189 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_5 5 | |
190 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_6 6 | |
191 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_7 7 | |
192 | #define PCIMEM_ARBITRATION_DMA 22:20 | |
193 | #define PCIMEM_ARBITRATION_DMA_OFF 0 | |
194 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_1 1 | |
195 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_2 2 | |
196 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_3 3 | |
197 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_4 4 | |
198 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_5 5 | |
199 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_6 6 | |
200 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_7 7 | |
201 | #define PCIMEM_ARBITRATION_ZVPORT1 18:16 | |
202 | #define PCIMEM_ARBITRATION_ZVPORT1_OFF 0 | |
203 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_1 1 | |
204 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_2 2 | |
205 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_3 3 | |
206 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_4 4 | |
207 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_5 5 | |
208 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_6 6 | |
209 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_7 7 | |
210 | #define PCIMEM_ARBITRATION_ZVPORT0 14:12 | |
211 | #define PCIMEM_ARBITRATION_ZVPORT0_OFF 0 | |
212 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_1 1 | |
213 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_2 2 | |
214 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_3 3 | |
215 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_4 4 | |
216 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_5 5 | |
217 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_6 6 | |
218 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_7 7 | |
219 | #define PCIMEM_ARBITRATION_VIDEO 10:8 | |
220 | #define PCIMEM_ARBITRATION_VIDEO_OFF 0 | |
221 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_1 1 | |
222 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_2 2 | |
223 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_3 3 | |
224 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_4 4 | |
225 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_5 5 | |
226 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_6 6 | |
227 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_7 7 | |
228 | #define PCIMEM_ARBITRATION_PANEL 6:4 | |
229 | #define PCIMEM_ARBITRATION_PANEL_OFF 0 | |
230 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_1 1 | |
231 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_2 2 | |
232 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_3 3 | |
233 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_4 4 | |
234 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_5 5 | |
235 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_6 6 | |
236 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_7 7 | |
237 | #define PCIMEM_ARBITRATION_CRT 2:0 | |
238 | #define PCIMEM_ARBITRATION_CRT_OFF 0 | |
239 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_1 1 | |
240 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_2 2 | |
241 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_3 3 | |
242 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_4 4 | |
243 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_5 5 | |
244 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_6 6 | |
245 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_7 7 | |
246 | ||
247 | #define RAW_INT 0x000020 | |
248 | #define RAW_INT_ZVPORT1_VSYNC 4:4 | |
249 | #define RAW_INT_ZVPORT1_VSYNC_INACTIVE 0 | |
250 | #define RAW_INT_ZVPORT1_VSYNC_ACTIVE 1 | |
251 | #define RAW_INT_ZVPORT1_VSYNC_CLEAR 1 | |
252 | #define RAW_INT_ZVPORT0_VSYNC 3:3 | |
253 | #define RAW_INT_ZVPORT0_VSYNC_INACTIVE 0 | |
254 | #define RAW_INT_ZVPORT0_VSYNC_ACTIVE 1 | |
255 | #define RAW_INT_ZVPORT0_VSYNC_CLEAR 1 | |
256 | #define RAW_INT_CRT_VSYNC 2:2 | |
257 | #define RAW_INT_CRT_VSYNC_INACTIVE 0 | |
258 | #define RAW_INT_CRT_VSYNC_ACTIVE 1 | |
259 | #define RAW_INT_CRT_VSYNC_CLEAR 1 | |
260 | #define RAW_INT_PANEL_VSYNC 1:1 | |
261 | #define RAW_INT_PANEL_VSYNC_INACTIVE 0 | |
262 | #define RAW_INT_PANEL_VSYNC_ACTIVE 1 | |
263 | #define RAW_INT_PANEL_VSYNC_CLEAR 1 | |
264 | #define RAW_INT_VGA_VSYNC 0:0 | |
265 | #define RAW_INT_VGA_VSYNC_INACTIVE 0 | |
266 | #define RAW_INT_VGA_VSYNC_ACTIVE 1 | |
267 | #define RAW_INT_VGA_VSYNC_CLEAR 1 | |
268 | ||
269 | #define INT_STATUS 0x000024 | |
270 | #define INT_STATUS_GPIO31 31:31 | |
271 | #define INT_STATUS_GPIO31_INACTIVE 0 | |
272 | #define INT_STATUS_GPIO31_ACTIVE 1 | |
273 | #define INT_STATUS_GPIO30 30:30 | |
274 | #define INT_STATUS_GPIO30_INACTIVE 0 | |
275 | #define INT_STATUS_GPIO30_ACTIVE 1 | |
276 | #define INT_STATUS_GPIO29 29:29 | |
277 | #define INT_STATUS_GPIO29_INACTIVE 0 | |
278 | #define INT_STATUS_GPIO29_ACTIVE 1 | |
279 | #define INT_STATUS_GPIO28 28:28 | |
280 | #define INT_STATUS_GPIO28_INACTIVE 0 | |
281 | #define INT_STATUS_GPIO28_ACTIVE 1 | |
282 | #define INT_STATUS_GPIO27 27:27 | |
283 | #define INT_STATUS_GPIO27_INACTIVE 0 | |
284 | #define INT_STATUS_GPIO27_ACTIVE 1 | |
285 | #define INT_STATUS_GPIO26 26:26 | |
286 | #define INT_STATUS_GPIO26_INACTIVE 0 | |
287 | #define INT_STATUS_GPIO26_ACTIVE 1 | |
288 | #define INT_STATUS_GPIO25 25:25 | |
289 | #define INT_STATUS_GPIO25_INACTIVE 0 | |
290 | #define INT_STATUS_GPIO25_ACTIVE 1 | |
291 | #define INT_STATUS_I2C 12:12 | |
292 | #define INT_STATUS_I2C_INACTIVE 0 | |
293 | #define INT_STATUS_I2C_ACTIVE 1 | |
294 | #define INT_STATUS_PWM 11:11 | |
295 | #define INT_STATUS_PWM_INACTIVE 0 | |
296 | #define INT_STATUS_PWM_ACTIVE 1 | |
297 | #define INT_STATUS_DMA1 10:10 | |
298 | #define INT_STATUS_DMA1_INACTIVE 0 | |
299 | #define INT_STATUS_DMA1_ACTIVE 1 | |
300 | #define INT_STATUS_DMA0 9:9 | |
301 | #define INT_STATUS_DMA0_INACTIVE 0 | |
302 | #define INT_STATUS_DMA0_ACTIVE 1 | |
303 | #define INT_STATUS_PCI 8:8 | |
304 | #define INT_STATUS_PCI_INACTIVE 0 | |
305 | #define INT_STATUS_PCI_ACTIVE 1 | |
306 | #define INT_STATUS_SSP1 7:7 | |
307 | #define INT_STATUS_SSP1_INACTIVE 0 | |
308 | #define INT_STATUS_SSP1_ACTIVE 1 | |
309 | #define INT_STATUS_SSP0 6:6 | |
310 | #define INT_STATUS_SSP0_INACTIVE 0 | |
311 | #define INT_STATUS_SSP0_ACTIVE 1 | |
312 | #define INT_STATUS_DE 5:5 | |
313 | #define INT_STATUS_DE_INACTIVE 0 | |
314 | #define INT_STATUS_DE_ACTIVE 1 | |
315 | #define INT_STATUS_ZVPORT1_VSYNC 4:4 | |
316 | #define INT_STATUS_ZVPORT1_VSYNC_INACTIVE 0 | |
317 | #define INT_STATUS_ZVPORT1_VSYNC_ACTIVE 1 | |
318 | #define INT_STATUS_ZVPORT0_VSYNC 3:3 | |
319 | #define INT_STATUS_ZVPORT0_VSYNC_INACTIVE 0 | |
320 | #define INT_STATUS_ZVPORT0_VSYNC_ACTIVE 1 | |
321 | #define INT_STATUS_CRT_VSYNC 2:2 | |
322 | #define INT_STATUS_CRT_VSYNC_INACTIVE 0 | |
323 | #define INT_STATUS_CRT_VSYNC_ACTIVE 1 | |
324 | #define INT_STATUS_PANEL_VSYNC 1:1 | |
325 | #define INT_STATUS_PANEL_VSYNC_INACTIVE 0 | |
326 | #define INT_STATUS_PANEL_VSYNC_ACTIVE 1 | |
327 | #define INT_STATUS_VGA_VSYNC 0:0 | |
328 | #define INT_STATUS_VGA_VSYNC_INACTIVE 0 | |
329 | #define INT_STATUS_VGA_VSYNC_ACTIVE 1 | |
330 | ||
331 | #define INT_MASK 0x000028 | |
332 | #define INT_MASK_GPIO31 31:31 | |
333 | #define INT_MASK_GPIO31_DISABLE 0 | |
334 | #define INT_MASK_GPIO31_ENABLE 1 | |
335 | #define INT_MASK_GPIO30 30:30 | |
336 | #define INT_MASK_GPIO30_DISABLE 0 | |
337 | #define INT_MASK_GPIO30_ENABLE 1 | |
338 | #define INT_MASK_GPIO29 29:29 | |
339 | #define INT_MASK_GPIO29_DISABLE 0 | |
340 | #define INT_MASK_GPIO29_ENABLE 1 | |
341 | #define INT_MASK_GPIO28 28:28 | |
342 | #define INT_MASK_GPIO28_DISABLE 0 | |
343 | #define INT_MASK_GPIO28_ENABLE 1 | |
344 | #define INT_MASK_GPIO27 27:27 | |
345 | #define INT_MASK_GPIO27_DISABLE 0 | |
346 | #define INT_MASK_GPIO27_ENABLE 1 | |
347 | #define INT_MASK_GPIO26 26:26 | |
348 | #define INT_MASK_GPIO26_DISABLE 0 | |
349 | #define INT_MASK_GPIO26_ENABLE 1 | |
350 | #define INT_MASK_GPIO25 25:25 | |
351 | #define INT_MASK_GPIO25_DISABLE 0 | |
352 | #define INT_MASK_GPIO25_ENABLE 1 | |
353 | #define INT_MASK_I2C 12:12 | |
354 | #define INT_MASK_I2C_DISABLE 0 | |
355 | #define INT_MASK_I2C_ENABLE 1 | |
356 | #define INT_MASK_PWM 11:11 | |
357 | #define INT_MASK_PWM_DISABLE 0 | |
358 | #define INT_MASK_PWM_ENABLE 1 | |
359 | #define INT_MASK_DMA1 10:10 | |
360 | #define INT_MASK_DMA1_DISABLE 0 | |
361 | #define INT_MASK_DMA1_ENABLE 1 | |
362 | #define INT_MASK_DMA 9:9 | |
363 | #define INT_MASK_DMA_DISABLE 0 | |
364 | #define INT_MASK_DMA_ENABLE 1 | |
365 | #define INT_MASK_PCI 8:8 | |
366 | #define INT_MASK_PCI_DISABLE 0 | |
367 | #define INT_MASK_PCI_ENABLE 1 | |
368 | #define INT_MASK_SSP1 7:7 | |
369 | #define INT_MASK_SSP1_DISABLE 0 | |
370 | #define INT_MASK_SSP1_ENABLE 1 | |
371 | #define INT_MASK_SSP0 6:6 | |
372 | #define INT_MASK_SSP0_DISABLE 0 | |
373 | #define INT_MASK_SSP0_ENABLE 1 | |
374 | #define INT_MASK_DE 5:5 | |
375 | #define INT_MASK_DE_DISABLE 0 | |
376 | #define INT_MASK_DE_ENABLE 1 | |
377 | #define INT_MASK_ZVPORT1_VSYNC 4:4 | |
378 | #define INT_MASK_ZVPORT1_VSYNC_DISABLE 0 | |
379 | #define INT_MASK_ZVPORT1_VSYNC_ENABLE 1 | |
380 | #define INT_MASK_ZVPORT0_VSYNC 3:3 | |
381 | #define INT_MASK_ZVPORT0_VSYNC_DISABLE 0 | |
382 | #define INT_MASK_ZVPORT0_VSYNC_ENABLE 1 | |
383 | #define INT_MASK_CRT_VSYNC 2:2 | |
384 | #define INT_MASK_CRT_VSYNC_DISABLE 0 | |
385 | #define INT_MASK_CRT_VSYNC_ENABLE 1 | |
386 | #define INT_MASK_PANEL_VSYNC 1:1 | |
387 | #define INT_MASK_PANEL_VSYNC_DISABLE 0 | |
388 | #define INT_MASK_PANEL_VSYNC_ENABLE 1 | |
389 | #define INT_MASK_VGA_VSYNC 0:0 | |
390 | #define INT_MASK_VGA_VSYNC_DISABLE 0 | |
391 | #define INT_MASK_VGA_VSYNC_ENABLE 1 | |
392 | ||
393 | #define CURRENT_GATE 0x000040 | |
6e8aa4a1 | 394 | #define CURRENT_GATE_MCLK_MASK (0x3 << 14) |
81dee67e | 395 | #ifdef VALIDATION_CHIP |
6e8aa4a1 MR |
396 | #define CURRENT_GATE_MCLK_112MHZ (0x0 << 14) |
397 | #define CURRENT_GATE_MCLK_84MHZ (0x1 << 14) | |
398 | #define CURRENT_GATE_MCLK_56MHZ (0x2 << 14) | |
399 | #define CURRENT_GATE_MCLK_42MHZ (0x3 << 14) | |
81dee67e | 400 | #else |
6e8aa4a1 MR |
401 | #define CURRENT_GATE_MCLK_DIV_3 (0x0 << 14) |
402 | #define CURRENT_GATE_MCLK_DIV_4 (0x1 << 14) | |
403 | #define CURRENT_GATE_MCLK_DIV_6 (0x2 << 14) | |
404 | #define CURRENT_GATE_MCLK_DIV_8 (0x3 << 14) | |
81dee67e | 405 | #endif |
6e8aa4a1 | 406 | #define CURRENT_GATE_M2XCLK_MASK (0x3 << 12) |
81dee67e | 407 | #ifdef VALIDATION_CHIP |
6e8aa4a1 MR |
408 | #define CURRENT_GATE_M2XCLK_336MHZ (0x0 << 12) |
409 | #define CURRENT_GATE_M2XCLK_168MHZ (0x1 << 12) | |
410 | #define CURRENT_GATE_M2XCLK_112MHZ (0x2 << 12) | |
411 | #define CURRENT_GATE_M2XCLK_84MHZ (0x3 << 12) | |
81dee67e | 412 | #else |
6e8aa4a1 MR |
413 | #define CURRENT_GATE_M2XCLK_DIV_1 (0x0 << 12) |
414 | #define CURRENT_GATE_M2XCLK_DIV_2 (0x1 << 12) | |
415 | #define CURRENT_GATE_M2XCLK_DIV_3 (0x2 << 12) | |
416 | #define CURRENT_GATE_M2XCLK_DIV_4 (0x3 << 12) | |
81dee67e | 417 | #endif |
90946e52 MR |
418 | #define CURRENT_GATE_VGA BIT(10) |
419 | #define CURRENT_GATE_PWM BIT(9) | |
420 | #define CURRENT_GATE_I2C BIT(8) | |
421 | #define CURRENT_GATE_SSP BIT(7) | |
422 | #define CURRENT_GATE_GPIO BIT(6) | |
423 | #define CURRENT_GATE_ZVPORT BIT(5) | |
424 | #define CURRENT_GATE_CSC BIT(4) | |
425 | #define CURRENT_GATE_DE BIT(3) | |
426 | #define CURRENT_GATE_DISPLAY BIT(2) | |
427 | #define CURRENT_GATE_LOCALMEM BIT(1) | |
428 | #define CURRENT_GATE_DMA BIT(0) | |
81dee67e SM |
429 | |
430 | #define MODE0_GATE 0x000044 | |
a9412451 MR |
431 | #define MODE0_GATE_MCLK_MASK (0x3 << 14) |
432 | #define MODE0_GATE_MCLK_112MHZ (0x0 << 14) | |
433 | #define MODE0_GATE_MCLK_84MHZ (0x1 << 14) | |
434 | #define MODE0_GATE_MCLK_56MHZ (0x2 << 14) | |
435 | #define MODE0_GATE_MCLK_42MHZ (0x3 << 14) | |
436 | #define MODE0_GATE_M2XCLK_MASK (0x3 << 12) | |
437 | #define MODE0_GATE_M2XCLK_336MHZ (0x0 << 12) | |
438 | #define MODE0_GATE_M2XCLK_168MHZ (0x1 << 12) | |
439 | #define MODE0_GATE_M2XCLK_112MHZ (0x2 << 12) | |
440 | #define MODE0_GATE_M2XCLK_84MHZ (0x3 << 12) | |
05e9d9ea MR |
441 | #define MODE0_GATE_VGA BIT(10) |
442 | #define MODE0_GATE_PWM BIT(9) | |
443 | #define MODE0_GATE_I2C BIT(8) | |
444 | #define MODE0_GATE_SSP BIT(7) | |
445 | #define MODE0_GATE_GPIO BIT(6) | |
446 | #define MODE0_GATE_ZVPORT BIT(5) | |
447 | #define MODE0_GATE_CSC BIT(4) | |
448 | #define MODE0_GATE_DE BIT(3) | |
449 | #define MODE0_GATE_DISPLAY BIT(2) | |
450 | #define MODE0_GATE_LOCALMEM BIT(1) | |
451 | #define MODE0_GATE_DMA BIT(0) | |
81dee67e SM |
452 | |
453 | #define MODE1_GATE 0x000048 | |
454 | #define MODE1_GATE_MCLK 15:14 | |
455 | #define MODE1_GATE_MCLK_112MHZ 0 | |
456 | #define MODE1_GATE_MCLK_84MHZ 1 | |
457 | #define MODE1_GATE_MCLK_56MHZ 2 | |
458 | #define MODE1_GATE_MCLK_42MHZ 3 | |
459 | #define MODE1_GATE_M2XCLK 13:12 | |
460 | #define MODE1_GATE_M2XCLK_336MHZ 0 | |
461 | #define MODE1_GATE_M2XCLK_168MHZ 1 | |
462 | #define MODE1_GATE_M2XCLK_112MHZ 2 | |
463 | #define MODE1_GATE_M2XCLK_84MHZ 3 | |
464 | #define MODE1_GATE_VGA 10:10 | |
465 | #define MODE1_GATE_VGA_OFF 0 | |
466 | #define MODE1_GATE_VGA_ON 1 | |
467 | #define MODE1_GATE_PWM 9:9 | |
468 | #define MODE1_GATE_PWM_OFF 0 | |
469 | #define MODE1_GATE_PWM_ON 1 | |
470 | #define MODE1_GATE_I2C 8:8 | |
471 | #define MODE1_GATE_I2C_OFF 0 | |
472 | #define MODE1_GATE_I2C_ON 1 | |
473 | #define MODE1_GATE_SSP 7:7 | |
474 | #define MODE1_GATE_SSP_OFF 0 | |
475 | #define MODE1_GATE_SSP_ON 1 | |
476 | #define MODE1_GATE_GPIO 6:6 | |
477 | #define MODE1_GATE_GPIO_OFF 0 | |
478 | #define MODE1_GATE_GPIO_ON 1 | |
479 | #define MODE1_GATE_ZVPORT 5:5 | |
480 | #define MODE1_GATE_ZVPORT_OFF 0 | |
481 | #define MODE1_GATE_ZVPORT_ON 1 | |
482 | #define MODE1_GATE_CSC 4:4 | |
483 | #define MODE1_GATE_CSC_OFF 0 | |
484 | #define MODE1_GATE_CSC_ON 1 | |
485 | #define MODE1_GATE_DE 3:3 | |
486 | #define MODE1_GATE_DE_OFF 0 | |
487 | #define MODE1_GATE_DE_ON 1 | |
488 | #define MODE1_GATE_DISPLAY 2:2 | |
489 | #define MODE1_GATE_DISPLAY_OFF 0 | |
490 | #define MODE1_GATE_DISPLAY_ON 1 | |
491 | #define MODE1_GATE_LOCALMEM 1:1 | |
492 | #define MODE1_GATE_LOCALMEM_OFF 0 | |
493 | #define MODE1_GATE_LOCALMEM_ON 1 | |
494 | #define MODE1_GATE_DMA 0:0 | |
495 | #define MODE1_GATE_DMA_OFF 0 | |
496 | #define MODE1_GATE_DMA_ON 1 | |
497 | ||
498 | #define POWER_MODE_CTRL 0x00004C | |
499 | #ifdef VALIDATION_CHIP | |
776980cf | 500 | #define POWER_MODE_CTRL_336CLK BIT(4) |
81dee67e | 501 | #endif |
776980cf MR |
502 | #define POWER_MODE_CTRL_OSC_INPUT BIT(3) |
503 | #define POWER_MODE_CTRL_ACPI BIT(2) | |
f41b17fc MR |
504 | #define POWER_MODE_CTRL_MODE_MASK (0x3 << 0) |
505 | #define POWER_MODE_CTRL_MODE_MODE0 (0x0 << 0) | |
506 | #define POWER_MODE_CTRL_MODE_MODE1 (0x1 << 0) | |
507 | #define POWER_MODE_CTRL_MODE_SLEEP (0x2 << 0) | |
81dee67e SM |
508 | |
509 | #define PCI_MASTER_BASE 0x000050 | |
510 | #define PCI_MASTER_BASE_ADDRESS 7:0 | |
511 | ||
512 | #define DEVICE_ID 0x000054 | |
513 | #define DEVICE_ID_DEVICE_ID 31:16 | |
514 | #define DEVICE_ID_REVISION_ID 7:0 | |
515 | ||
516 | #define PLL_CLK_COUNT 0x000058 | |
517 | #define PLL_CLK_COUNT_COUNTER 15:0 | |
518 | ||
519 | #define PANEL_PLL_CTRL 0x00005C | |
5557eb17 MR |
520 | #define PLL_CTRL_BYPASS BIT(18) |
521 | #define PLL_CTRL_POWER BIT(17) | |
522 | #define PLL_CTRL_INPUT BIT(16) | |
81dee67e | 523 | #ifdef VALIDATION_CHIP |
54feb931 | 524 | #define PLL_CTRL_OD 15:14 |
81dee67e | 525 | #else |
54feb931 MR |
526 | #define PLL_CTRL_POD 15:14 |
527 | #define PLL_CTRL_OD 13:12 | |
81dee67e | 528 | #endif |
54feb931 MR |
529 | #define PLL_CTRL_N 11:8 |
530 | #define PLL_CTRL_M 7:0 | |
81dee67e SM |
531 | |
532 | #define CRT_PLL_CTRL 0x000060 | |
533 | #define CRT_PLL_CTRL_BYPASS 18:18 | |
534 | #define CRT_PLL_CTRL_BYPASS_OFF 0 | |
535 | #define CRT_PLL_CTRL_BYPASS_ON 1 | |
536 | #define CRT_PLL_CTRL_POWER 17:17 | |
537 | #define CRT_PLL_CTRL_POWER_OFF 0 | |
538 | #define CRT_PLL_CTRL_POWER_ON 1 | |
539 | #define CRT_PLL_CTRL_INPUT 16:16 | |
540 | #define CRT_PLL_CTRL_INPUT_OSC 0 | |
541 | #define CRT_PLL_CTRL_INPUT_TESTCLK 1 | |
542 | #ifdef VALIDATION_CHIP | |
543 | #define CRT_PLL_CTRL_OD 15:14 | |
544 | #else | |
545 | #define CRT_PLL_CTRL_POD 15:14 | |
546 | #define CRT_PLL_CTRL_OD 13:12 | |
547 | #endif | |
548 | #define CRT_PLL_CTRL_N 11:8 | |
549 | #define CRT_PLL_CTRL_M 7:0 | |
550 | ||
551 | #define VGA_PLL0_CTRL 0x000064 | |
552 | #define VGA_PLL0_CTRL_BYPASS 18:18 | |
553 | #define VGA_PLL0_CTRL_BYPASS_OFF 0 | |
554 | #define VGA_PLL0_CTRL_BYPASS_ON 1 | |
555 | #define VGA_PLL0_CTRL_POWER 17:17 | |
556 | #define VGA_PLL0_CTRL_POWER_OFF 0 | |
557 | #define VGA_PLL0_CTRL_POWER_ON 1 | |
558 | #define VGA_PLL0_CTRL_INPUT 16:16 | |
559 | #define VGA_PLL0_CTRL_INPUT_OSC 0 | |
560 | #define VGA_PLL0_CTRL_INPUT_TESTCLK 1 | |
561 | #ifdef VALIDATION_CHIP | |
562 | #define VGA_PLL0_CTRL_OD 15:14 | |
563 | #else | |
564 | #define VGA_PLL0_CTRL_POD 15:14 | |
565 | #define VGA_PLL0_CTRL_OD 13:12 | |
566 | #endif | |
567 | #define VGA_PLL0_CTRL_N 11:8 | |
568 | #define VGA_PLL0_CTRL_M 7:0 | |
569 | ||
570 | #define VGA_PLL1_CTRL 0x000068 | |
571 | #define VGA_PLL1_CTRL_BYPASS 18:18 | |
572 | #define VGA_PLL1_CTRL_BYPASS_OFF 0 | |
573 | #define VGA_PLL1_CTRL_BYPASS_ON 1 | |
574 | #define VGA_PLL1_CTRL_POWER 17:17 | |
575 | #define VGA_PLL1_CTRL_POWER_OFF 0 | |
576 | #define VGA_PLL1_CTRL_POWER_ON 1 | |
577 | #define VGA_PLL1_CTRL_INPUT 16:16 | |
578 | #define VGA_PLL1_CTRL_INPUT_OSC 0 | |
579 | #define VGA_PLL1_CTRL_INPUT_TESTCLK 1 | |
580 | #ifdef VALIDATION_CHIP | |
581 | #define VGA_PLL1_CTRL_OD 15:14 | |
582 | #else | |
583 | #define VGA_PLL1_CTRL_POD 15:14 | |
584 | #define VGA_PLL1_CTRL_OD 13:12 | |
585 | #endif | |
586 | #define VGA_PLL1_CTRL_N 11:8 | |
587 | #define VGA_PLL1_CTRL_M 7:0 | |
588 | ||
589 | #define SCRATCH_DATA 0x00006c | |
590 | ||
591 | #ifndef VALIDATION_CHIP | |
592 | ||
593 | #define MXCLK_PLL_CTRL 0x000070 | |
594 | #define MXCLK_PLL_CTRL_BYPASS 18:18 | |
595 | #define MXCLK_PLL_CTRL_BYPASS_OFF 0 | |
596 | #define MXCLK_PLL_CTRL_BYPASS_ON 1 | |
597 | #define MXCLK_PLL_CTRL_POWER 17:17 | |
598 | #define MXCLK_PLL_CTRL_POWER_OFF 0 | |
599 | #define MXCLK_PLL_CTRL_POWER_ON 1 | |
600 | #define MXCLK_PLL_CTRL_INPUT 16:16 | |
601 | #define MXCLK_PLL_CTRL_INPUT_OSC 0 | |
602 | #define MXCLK_PLL_CTRL_INPUT_TESTCLK 1 | |
603 | #define MXCLK_PLL_CTRL_POD 15:14 | |
604 | #define MXCLK_PLL_CTRL_OD 13:12 | |
605 | #define MXCLK_PLL_CTRL_N 11:8 | |
606 | #define MXCLK_PLL_CTRL_M 7:0 | |
607 | ||
608 | #define VGA_CONFIGURATION 0x000088 | |
609 | #define VGA_CONFIGURATION_USER_DEFINE 5:4 | |
610 | #define VGA_CONFIGURATION_PLL 2:2 | |
611 | #define VGA_CONFIGURATION_PLL_VGA 0 | |
612 | #define VGA_CONFIGURATION_PLL_PANEL 1 | |
613 | #define VGA_CONFIGURATION_MODE 1:1 | |
614 | #define VGA_CONFIGURATION_MODE_TEXT 0 | |
615 | #define VGA_CONFIGURATION_MODE_GRAPHIC 1 | |
616 | ||
617 | #endif | |
618 | ||
619 | #define GPIO_DATA 0x010000 | |
620 | #define GPIO_DATA_31 31:31 | |
621 | #define GPIO_DATA_30 30:30 | |
622 | #define GPIO_DATA_29 29:29 | |
623 | #define GPIO_DATA_28 28:28 | |
624 | #define GPIO_DATA_27 27:27 | |
625 | #define GPIO_DATA_26 26:26 | |
626 | #define GPIO_DATA_25 25:25 | |
627 | #define GPIO_DATA_24 24:24 | |
628 | #define GPIO_DATA_23 23:23 | |
629 | #define GPIO_DATA_22 22:22 | |
630 | #define GPIO_DATA_21 21:21 | |
631 | #define GPIO_DATA_20 20:20 | |
632 | #define GPIO_DATA_19 19:19 | |
633 | #define GPIO_DATA_18 18:18 | |
634 | #define GPIO_DATA_17 17:17 | |
635 | #define GPIO_DATA_16 16:16 | |
636 | #define GPIO_DATA_15 15:15 | |
637 | #define GPIO_DATA_14 14:14 | |
638 | #define GPIO_DATA_13 13:13 | |
639 | #define GPIO_DATA_12 12:12 | |
640 | #define GPIO_DATA_11 11:11 | |
641 | #define GPIO_DATA_10 10:10 | |
642 | #define GPIO_DATA_9 9:9 | |
643 | #define GPIO_DATA_8 8:8 | |
644 | #define GPIO_DATA_7 7:7 | |
645 | #define GPIO_DATA_6 6:6 | |
646 | #define GPIO_DATA_5 5:5 | |
647 | #define GPIO_DATA_4 4:4 | |
648 | #define GPIO_DATA_3 3:3 | |
649 | #define GPIO_DATA_2 2:2 | |
650 | #define GPIO_DATA_1 1:1 | |
651 | #define GPIO_DATA_0 0:0 | |
652 | ||
653 | #define GPIO_DATA_DIRECTION 0x010004 | |
654 | #define GPIO_DATA_DIRECTION_31 31:31 | |
655 | #define GPIO_DATA_DIRECTION_31_INPUT 0 | |
656 | #define GPIO_DATA_DIRECTION_31_OUTPUT 1 | |
657 | #define GPIO_DATA_DIRECTION_30 30:30 | |
658 | #define GPIO_DATA_DIRECTION_30_INPUT 0 | |
659 | #define GPIO_DATA_DIRECTION_30_OUTPUT 1 | |
660 | #define GPIO_DATA_DIRECTION_29 29:29 | |
661 | #define GPIO_DATA_DIRECTION_29_INPUT 0 | |
662 | #define GPIO_DATA_DIRECTION_29_OUTPUT 1 | |
663 | #define GPIO_DATA_DIRECTION_28 28:28 | |
664 | #define GPIO_DATA_DIRECTION_28_INPUT 0 | |
665 | #define GPIO_DATA_DIRECTION_28_OUTPUT 1 | |
666 | #define GPIO_DATA_DIRECTION_27 27:27 | |
667 | #define GPIO_DATA_DIRECTION_27_INPUT 0 | |
668 | #define GPIO_DATA_DIRECTION_27_OUTPUT 1 | |
669 | #define GPIO_DATA_DIRECTION_26 26:26 | |
670 | #define GPIO_DATA_DIRECTION_26_INPUT 0 | |
671 | #define GPIO_DATA_DIRECTION_26_OUTPUT 1 | |
672 | #define GPIO_DATA_DIRECTION_25 25:25 | |
673 | #define GPIO_DATA_DIRECTION_25_INPUT 0 | |
674 | #define GPIO_DATA_DIRECTION_25_OUTPUT 1 | |
675 | #define GPIO_DATA_DIRECTION_24 24:24 | |
676 | #define GPIO_DATA_DIRECTION_24_INPUT 0 | |
677 | #define GPIO_DATA_DIRECTION_24_OUTPUT 1 | |
678 | #define GPIO_DATA_DIRECTION_23 23:23 | |
679 | #define GPIO_DATA_DIRECTION_23_INPUT 0 | |
680 | #define GPIO_DATA_DIRECTION_23_OUTPUT 1 | |
681 | #define GPIO_DATA_DIRECTION_22 22:22 | |
682 | #define GPIO_DATA_DIRECTION_22_INPUT 0 | |
683 | #define GPIO_DATA_DIRECTION_22_OUTPUT 1 | |
684 | #define GPIO_DATA_DIRECTION_21 21:21 | |
685 | #define GPIO_DATA_DIRECTION_21_INPUT 0 | |
686 | #define GPIO_DATA_DIRECTION_21_OUTPUT 1 | |
687 | #define GPIO_DATA_DIRECTION_20 20:20 | |
688 | #define GPIO_DATA_DIRECTION_20_INPUT 0 | |
689 | #define GPIO_DATA_DIRECTION_20_OUTPUT 1 | |
690 | #define GPIO_DATA_DIRECTION_19 19:19 | |
691 | #define GPIO_DATA_DIRECTION_19_INPUT 0 | |
692 | #define GPIO_DATA_DIRECTION_19_OUTPUT 1 | |
693 | #define GPIO_DATA_DIRECTION_18 18:18 | |
694 | #define GPIO_DATA_DIRECTION_18_INPUT 0 | |
695 | #define GPIO_DATA_DIRECTION_18_OUTPUT 1 | |
696 | #define GPIO_DATA_DIRECTION_17 17:17 | |
697 | #define GPIO_DATA_DIRECTION_17_INPUT 0 | |
698 | #define GPIO_DATA_DIRECTION_17_OUTPUT 1 | |
699 | #define GPIO_DATA_DIRECTION_16 16:16 | |
700 | #define GPIO_DATA_DIRECTION_16_INPUT 0 | |
701 | #define GPIO_DATA_DIRECTION_16_OUTPUT 1 | |
702 | #define GPIO_DATA_DIRECTION_15 15:15 | |
703 | #define GPIO_DATA_DIRECTION_15_INPUT 0 | |
704 | #define GPIO_DATA_DIRECTION_15_OUTPUT 1 | |
705 | #define GPIO_DATA_DIRECTION_14 14:14 | |
706 | #define GPIO_DATA_DIRECTION_14_INPUT 0 | |
707 | #define GPIO_DATA_DIRECTION_14_OUTPUT 1 | |
708 | #define GPIO_DATA_DIRECTION_13 13:13 | |
709 | #define GPIO_DATA_DIRECTION_13_INPUT 0 | |
710 | #define GPIO_DATA_DIRECTION_13_OUTPUT 1 | |
711 | #define GPIO_DATA_DIRECTION_12 12:12 | |
712 | #define GPIO_DATA_DIRECTION_12_INPUT 0 | |
713 | #define GPIO_DATA_DIRECTION_12_OUTPUT 1 | |
714 | #define GPIO_DATA_DIRECTION_11 11:11 | |
715 | #define GPIO_DATA_DIRECTION_11_INPUT 0 | |
716 | #define GPIO_DATA_DIRECTION_11_OUTPUT 1 | |
717 | #define GPIO_DATA_DIRECTION_10 10:10 | |
718 | #define GPIO_DATA_DIRECTION_10_INPUT 0 | |
719 | #define GPIO_DATA_DIRECTION_10_OUTPUT 1 | |
720 | #define GPIO_DATA_DIRECTION_9 9:9 | |
721 | #define GPIO_DATA_DIRECTION_9_INPUT 0 | |
722 | #define GPIO_DATA_DIRECTION_9_OUTPUT 1 | |
723 | #define GPIO_DATA_DIRECTION_8 8:8 | |
724 | #define GPIO_DATA_DIRECTION_8_INPUT 0 | |
725 | #define GPIO_DATA_DIRECTION_8_OUTPUT 1 | |
726 | #define GPIO_DATA_DIRECTION_7 7:7 | |
727 | #define GPIO_DATA_DIRECTION_7_INPUT 0 | |
728 | #define GPIO_DATA_DIRECTION_7_OUTPUT 1 | |
729 | #define GPIO_DATA_DIRECTION_6 6:6 | |
730 | #define GPIO_DATA_DIRECTION_6_INPUT 0 | |
731 | #define GPIO_DATA_DIRECTION_6_OUTPUT 1 | |
732 | #define GPIO_DATA_DIRECTION_5 5:5 | |
733 | #define GPIO_DATA_DIRECTION_5_INPUT 0 | |
734 | #define GPIO_DATA_DIRECTION_5_OUTPUT 1 | |
735 | #define GPIO_DATA_DIRECTION_4 4:4 | |
736 | #define GPIO_DATA_DIRECTION_4_INPUT 0 | |
737 | #define GPIO_DATA_DIRECTION_4_OUTPUT 1 | |
738 | #define GPIO_DATA_DIRECTION_3 3:3 | |
739 | #define GPIO_DATA_DIRECTION_3_INPUT 0 | |
740 | #define GPIO_DATA_DIRECTION_3_OUTPUT 1 | |
741 | #define GPIO_DATA_DIRECTION_2 2:2 | |
742 | #define GPIO_DATA_DIRECTION_2_INPUT 0 | |
743 | #define GPIO_DATA_DIRECTION_2_OUTPUT 1 | |
744 | #define GPIO_DATA_DIRECTION_1 131 | |
745 | #define GPIO_DATA_DIRECTION_1_INPUT 0 | |
746 | #define GPIO_DATA_DIRECTION_1_OUTPUT 1 | |
747 | #define GPIO_DATA_DIRECTION_0 0:0 | |
748 | #define GPIO_DATA_DIRECTION_0_INPUT 0 | |
749 | #define GPIO_DATA_DIRECTION_0_OUTPUT 1 | |
750 | ||
751 | #define GPIO_INTERRUPT_SETUP 0x010008 | |
752 | #define GPIO_INTERRUPT_SETUP_TRIGGER_31 22:22 | |
753 | #define GPIO_INTERRUPT_SETUP_TRIGGER_31_EDGE 0 | |
754 | #define GPIO_INTERRUPT_SETUP_TRIGGER_31_LEVEL 1 | |
755 | #define GPIO_INTERRUPT_SETUP_TRIGGER_30 21:21 | |
756 | #define GPIO_INTERRUPT_SETUP_TRIGGER_30_EDGE 0 | |
757 | #define GPIO_INTERRUPT_SETUP_TRIGGER_30_LEVEL 1 | |
758 | #define GPIO_INTERRUPT_SETUP_TRIGGER_29 20:20 | |
759 | #define GPIO_INTERRUPT_SETUP_TRIGGER_29_EDGE 0 | |
760 | #define GPIO_INTERRUPT_SETUP_TRIGGER_29_LEVEL 1 | |
761 | #define GPIO_INTERRUPT_SETUP_TRIGGER_28 19:19 | |
762 | #define GPIO_INTERRUPT_SETUP_TRIGGER_28_EDGE 0 | |
763 | #define GPIO_INTERRUPT_SETUP_TRIGGER_28_LEVEL 1 | |
764 | #define GPIO_INTERRUPT_SETUP_TRIGGER_27 18:18 | |
765 | #define GPIO_INTERRUPT_SETUP_TRIGGER_27_EDGE 0 | |
766 | #define GPIO_INTERRUPT_SETUP_TRIGGER_27_LEVEL 1 | |
767 | #define GPIO_INTERRUPT_SETUP_TRIGGER_26 17:17 | |
768 | #define GPIO_INTERRUPT_SETUP_TRIGGER_26_EDGE 0 | |
769 | #define GPIO_INTERRUPT_SETUP_TRIGGER_26_LEVEL 1 | |
770 | #define GPIO_INTERRUPT_SETUP_TRIGGER_25 16:16 | |
771 | #define GPIO_INTERRUPT_SETUP_TRIGGER_25_EDGE 0 | |
772 | #define GPIO_INTERRUPT_SETUP_TRIGGER_25_LEVEL 1 | |
773 | #define GPIO_INTERRUPT_SETUP_ACTIVE_31 14:14 | |
774 | #define GPIO_INTERRUPT_SETUP_ACTIVE_31_LOW 0 | |
775 | #define GPIO_INTERRUPT_SETUP_ACTIVE_31_HIGH 1 | |
776 | #define GPIO_INTERRUPT_SETUP_ACTIVE_30 13:13 | |
777 | #define GPIO_INTERRUPT_SETUP_ACTIVE_30_LOW 0 | |
778 | #define GPIO_INTERRUPT_SETUP_ACTIVE_30_HIGH 1 | |
779 | #define GPIO_INTERRUPT_SETUP_ACTIVE_29 12:12 | |
780 | #define GPIO_INTERRUPT_SETUP_ACTIVE_29_LOW 0 | |
781 | #define GPIO_INTERRUPT_SETUP_ACTIVE_29_HIGH 1 | |
782 | #define GPIO_INTERRUPT_SETUP_ACTIVE_28 11:11 | |
783 | #define GPIO_INTERRUPT_SETUP_ACTIVE_28_LOW 0 | |
784 | #define GPIO_INTERRUPT_SETUP_ACTIVE_28_HIGH 1 | |
785 | #define GPIO_INTERRUPT_SETUP_ACTIVE_27 10:10 | |
786 | #define GPIO_INTERRUPT_SETUP_ACTIVE_27_LOW 0 | |
787 | #define GPIO_INTERRUPT_SETUP_ACTIVE_27_HIGH 1 | |
788 | #define GPIO_INTERRUPT_SETUP_ACTIVE_26 9:9 | |
789 | #define GPIO_INTERRUPT_SETUP_ACTIVE_26_LOW 0 | |
790 | #define GPIO_INTERRUPT_SETUP_ACTIVE_26_HIGH 1 | |
791 | #define GPIO_INTERRUPT_SETUP_ACTIVE_25 8:8 | |
792 | #define GPIO_INTERRUPT_SETUP_ACTIVE_25_LOW 0 | |
793 | #define GPIO_INTERRUPT_SETUP_ACTIVE_25_HIGH 1 | |
794 | #define GPIO_INTERRUPT_SETUP_ENABLE_31 6:6 | |
795 | #define GPIO_INTERRUPT_SETUP_ENABLE_31_GPIO 0 | |
796 | #define GPIO_INTERRUPT_SETUP_ENABLE_31_INTERRUPT 1 | |
797 | #define GPIO_INTERRUPT_SETUP_ENABLE_30 5:5 | |
798 | #define GPIO_INTERRUPT_SETUP_ENABLE_30_GPIO 0 | |
799 | #define GPIO_INTERRUPT_SETUP_ENABLE_30_INTERRUPT 1 | |
800 | #define GPIO_INTERRUPT_SETUP_ENABLE_29 4:4 | |
801 | #define GPIO_INTERRUPT_SETUP_ENABLE_29_GPIO 0 | |
802 | #define GPIO_INTERRUPT_SETUP_ENABLE_29_INTERRUPT 1 | |
803 | #define GPIO_INTERRUPT_SETUP_ENABLE_28 3:3 | |
804 | #define GPIO_INTERRUPT_SETUP_ENABLE_28_GPIO 0 | |
805 | #define GPIO_INTERRUPT_SETUP_ENABLE_28_INTERRUPT 1 | |
806 | #define GPIO_INTERRUPT_SETUP_ENABLE_27 2:2 | |
807 | #define GPIO_INTERRUPT_SETUP_ENABLE_27_GPIO 0 | |
808 | #define GPIO_INTERRUPT_SETUP_ENABLE_27_INTERRUPT 1 | |
809 | #define GPIO_INTERRUPT_SETUP_ENABLE_26 1:1 | |
810 | #define GPIO_INTERRUPT_SETUP_ENABLE_26_GPIO 0 | |
811 | #define GPIO_INTERRUPT_SETUP_ENABLE_26_INTERRUPT 1 | |
812 | #define GPIO_INTERRUPT_SETUP_ENABLE_25 0:0 | |
813 | #define GPIO_INTERRUPT_SETUP_ENABLE_25_GPIO 0 | |
814 | #define GPIO_INTERRUPT_SETUP_ENABLE_25_INTERRUPT 1 | |
815 | ||
816 | #define GPIO_INTERRUPT_STATUS 0x01000C | |
817 | #define GPIO_INTERRUPT_STATUS_31 22:22 | |
818 | #define GPIO_INTERRUPT_STATUS_31_INACTIVE 0 | |
819 | #define GPIO_INTERRUPT_STATUS_31_ACTIVE 1 | |
820 | #define GPIO_INTERRUPT_STATUS_31_RESET 1 | |
821 | #define GPIO_INTERRUPT_STATUS_30 21:21 | |
822 | #define GPIO_INTERRUPT_STATUS_30_INACTIVE 0 | |
823 | #define GPIO_INTERRUPT_STATUS_30_ACTIVE 1 | |
824 | #define GPIO_INTERRUPT_STATUS_30_RESET 1 | |
825 | #define GPIO_INTERRUPT_STATUS_29 20:20 | |
826 | #define GPIO_INTERRUPT_STATUS_29_INACTIVE 0 | |
827 | #define GPIO_INTERRUPT_STATUS_29_ACTIVE 1 | |
828 | #define GPIO_INTERRUPT_STATUS_29_RESET 1 | |
829 | #define GPIO_INTERRUPT_STATUS_28 19:19 | |
830 | #define GPIO_INTERRUPT_STATUS_28_INACTIVE 0 | |
831 | #define GPIO_INTERRUPT_STATUS_28_ACTIVE 1 | |
832 | #define GPIO_INTERRUPT_STATUS_28_RESET 1 | |
833 | #define GPIO_INTERRUPT_STATUS_27 18:18 | |
834 | #define GPIO_INTERRUPT_STATUS_27_INACTIVE 0 | |
835 | #define GPIO_INTERRUPT_STATUS_27_ACTIVE 1 | |
836 | #define GPIO_INTERRUPT_STATUS_27_RESET 1 | |
837 | #define GPIO_INTERRUPT_STATUS_26 17:17 | |
838 | #define GPIO_INTERRUPT_STATUS_26_INACTIVE 0 | |
839 | #define GPIO_INTERRUPT_STATUS_26_ACTIVE 1 | |
840 | #define GPIO_INTERRUPT_STATUS_26_RESET 1 | |
841 | #define GPIO_INTERRUPT_STATUS_25 16:16 | |
842 | #define GPIO_INTERRUPT_STATUS_25_INACTIVE 0 | |
843 | #define GPIO_INTERRUPT_STATUS_25_ACTIVE 1 | |
844 | #define GPIO_INTERRUPT_STATUS_25_RESET 1 | |
845 | ||
846 | ||
847 | #define PANEL_DISPLAY_CTRL 0x080000 | |
848 | #define PANEL_DISPLAY_CTRL_RESERVED_1_MASK 31:30 | |
849 | #define PANEL_DISPLAY_CTRL_RESERVED_1_MASK_DISABLE 0 | |
850 | #define PANEL_DISPLAY_CTRL_RESERVED_1_MASK_ENABLE 3 | |
851 | #define PANEL_DISPLAY_CTRL_SELECT 29:28 | |
852 | #define PANEL_DISPLAY_CTRL_SELECT_PANEL 0 | |
853 | #define PANEL_DISPLAY_CTRL_SELECT_VGA 1 | |
854 | #define PANEL_DISPLAY_CTRL_SELECT_CRT 2 | |
855 | #define PANEL_DISPLAY_CTRL_FPEN 27:27 | |
856 | #define PANEL_DISPLAY_CTRL_FPEN_LOW 0 | |
857 | #define PANEL_DISPLAY_CTRL_FPEN_HIGH 1 | |
858 | #define PANEL_DISPLAY_CTRL_VBIASEN 26:26 | |
859 | #define PANEL_DISPLAY_CTRL_VBIASEN_LOW 0 | |
860 | #define PANEL_DISPLAY_CTRL_VBIASEN_HIGH 1 | |
861 | #define PANEL_DISPLAY_CTRL_DATA 25:25 | |
862 | #define PANEL_DISPLAY_CTRL_DATA_DISABLE 0 | |
863 | #define PANEL_DISPLAY_CTRL_DATA_ENABLE 1 | |
864 | #define PANEL_DISPLAY_CTRL_FPVDDEN 24:24 | |
865 | #define PANEL_DISPLAY_CTRL_FPVDDEN_LOW 0 | |
866 | #define PANEL_DISPLAY_CTRL_FPVDDEN_HIGH 1 | |
867 | #define PANEL_DISPLAY_CTRL_RESERVED_2_MASK 23:20 | |
868 | #define PANEL_DISPLAY_CTRL_RESERVED_2_MASK_DISABLE 0 | |
869 | #define PANEL_DISPLAY_CTRL_RESERVED_2_MASK_ENABLE 15 | |
870 | ||
871 | #define PANEL_DISPLAY_CTRL_TFT_DISP 19:18 | |
872 | #define PANEL_DISPLAY_CTRL_TFT_DISP_24 0 | |
873 | #define PANEL_DISPLAY_CTRL_TFT_DISP_36 1 | |
874 | #define PANEL_DISPLAY_CTRL_TFT_DISP_18 2 | |
875 | ||
876 | ||
877 | #define PANEL_DISPLAY_CTRL_DUAL_DISPLAY 19:19 | |
878 | #define PANEL_DISPLAY_CTRL_DUAL_DISPLAY_DISABLE 0 | |
879 | #define PANEL_DISPLAY_CTRL_DUAL_DISPLAY_ENABLE 1 | |
880 | #define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL 18:18 | |
881 | #define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL_DISABLE 0 | |
882 | #define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL_ENABLE 1 | |
883 | #define PANEL_DISPLAY_CTRL_FIFO 17:16 | |
884 | #define PANEL_DISPLAY_CTRL_FIFO_1 0 | |
885 | #define PANEL_DISPLAY_CTRL_FIFO_3 1 | |
886 | #define PANEL_DISPLAY_CTRL_FIFO_7 2 | |
887 | #define PANEL_DISPLAY_CTRL_FIFO_11 3 | |
888 | #define PANEL_DISPLAY_CTRL_RESERVED_3_MASK 15:15 | |
889 | #define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_DISABLE 0 | |
890 | #define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_ENABLE 1 | |
891 | #define PANEL_DISPLAY_CTRL_CLOCK_PHASE 14:14 | |
892 | #define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0 | |
893 | #define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1 | |
894 | #define PANEL_DISPLAY_CTRL_VSYNC_PHASE 13:13 | |
895 | #define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0 | |
896 | #define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1 | |
897 | #define PANEL_DISPLAY_CTRL_HSYNC_PHASE 12:12 | |
898 | #define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0 | |
899 | #define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1 | |
900 | #define PANEL_DISPLAY_CTRL_VSYNC 11:11 | |
901 | #define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_HIGH 0 | |
902 | #define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_LOW 1 | |
903 | #define PANEL_DISPLAY_CTRL_CAPTURE_TIMING 10:10 | |
904 | #define PANEL_DISPLAY_CTRL_CAPTURE_TIMING_DISABLE 0 | |
905 | #define PANEL_DISPLAY_CTRL_CAPTURE_TIMING_ENABLE 1 | |
906 | #define PANEL_DISPLAY_CTRL_COLOR_KEY 9:9 | |
907 | #define PANEL_DISPLAY_CTRL_COLOR_KEY_DISABLE 0 | |
908 | #define PANEL_DISPLAY_CTRL_COLOR_KEY_ENABLE 1 | |
909 | #define PANEL_DISPLAY_CTRL_TIMING 8:8 | |
910 | #define PANEL_DISPLAY_CTRL_TIMING_DISABLE 0 | |
911 | #define PANEL_DISPLAY_CTRL_TIMING_ENABLE 1 | |
912 | #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR 7:7 | |
913 | #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_DOWN 0 | |
914 | #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_UP 1 | |
915 | #define PANEL_DISPLAY_CTRL_VERTICAL_PAN 6:6 | |
916 | #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DISABLE 0 | |
917 | #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_ENABLE 1 | |
918 | #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR 5:5 | |
919 | #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_RIGHT 0 | |
920 | #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_LEFT 1 | |
921 | #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN 4:4 | |
922 | #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DISABLE 0 | |
923 | #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_ENABLE 1 | |
924 | #define PANEL_DISPLAY_CTRL_GAMMA 3:3 | |
925 | #define PANEL_DISPLAY_CTRL_GAMMA_DISABLE 0 | |
926 | #define PANEL_DISPLAY_CTRL_GAMMA_ENABLE 1 | |
927 | #define PANEL_DISPLAY_CTRL_PLANE 2:2 | |
928 | #define PANEL_DISPLAY_CTRL_PLANE_DISABLE 0 | |
929 | #define PANEL_DISPLAY_CTRL_PLANE_ENABLE 1 | |
930 | #define PANEL_DISPLAY_CTRL_FORMAT 1:0 | |
931 | #define PANEL_DISPLAY_CTRL_FORMAT_8 0 | |
932 | #define PANEL_DISPLAY_CTRL_FORMAT_16 1 | |
933 | #define PANEL_DISPLAY_CTRL_FORMAT_32 2 | |
934 | ||
935 | #define PANEL_PAN_CTRL 0x080004 | |
936 | #define PANEL_PAN_CTRL_VERTICAL_PAN 31:24 | |
937 | #define PANEL_PAN_CTRL_VERTICAL_VSYNC 21:16 | |
938 | #define PANEL_PAN_CTRL_HORIZONTAL_PAN 15:8 | |
939 | #define PANEL_PAN_CTRL_HORIZONTAL_VSYNC 5:0 | |
940 | ||
941 | #define PANEL_COLOR_KEY 0x080008 | |
942 | #define PANEL_COLOR_KEY_MASK 31:16 | |
943 | #define PANEL_COLOR_KEY_VALUE 15:0 | |
944 | ||
945 | #define PANEL_FB_ADDRESS 0x08000C | |
946 | #define PANEL_FB_ADDRESS_STATUS 31:31 | |
947 | #define PANEL_FB_ADDRESS_STATUS_CURRENT 0 | |
948 | #define PANEL_FB_ADDRESS_STATUS_PENDING 1 | |
949 | #define PANEL_FB_ADDRESS_EXT 27:27 | |
950 | #define PANEL_FB_ADDRESS_EXT_LOCAL 0 | |
951 | #define PANEL_FB_ADDRESS_EXT_EXTERNAL 1 | |
952 | #define PANEL_FB_ADDRESS_ADDRESS 25:0 | |
953 | ||
954 | #define PANEL_FB_WIDTH 0x080010 | |
955 | #define PANEL_FB_WIDTH_WIDTH 29:16 | |
956 | #define PANEL_FB_WIDTH_OFFSET 13:0 | |
957 | ||
958 | #define PANEL_WINDOW_WIDTH 0x080014 | |
959 | #define PANEL_WINDOW_WIDTH_WIDTH 27:16 | |
960 | #define PANEL_WINDOW_WIDTH_X 11:0 | |
961 | ||
962 | #define PANEL_WINDOW_HEIGHT 0x080018 | |
963 | #define PANEL_WINDOW_HEIGHT_HEIGHT 27:16 | |
964 | #define PANEL_WINDOW_HEIGHT_Y 11:0 | |
965 | ||
966 | #define PANEL_PLANE_TL 0x08001C | |
967 | #define PANEL_PLANE_TL_TOP 26:16 | |
968 | #define PANEL_PLANE_TL_LEFT 10:0 | |
969 | ||
970 | #define PANEL_PLANE_BR 0x080020 | |
971 | #define PANEL_PLANE_BR_BOTTOM 26:16 | |
972 | #define PANEL_PLANE_BR_RIGHT 10:0 | |
973 | ||
974 | #define PANEL_HORIZONTAL_TOTAL 0x080024 | |
975 | #define PANEL_HORIZONTAL_TOTAL_TOTAL 27:16 | |
976 | #define PANEL_HORIZONTAL_TOTAL_DISPLAY_END 11:0 | |
977 | ||
978 | #define PANEL_HORIZONTAL_SYNC 0x080028 | |
979 | #define PANEL_HORIZONTAL_SYNC_WIDTH 23:16 | |
980 | #define PANEL_HORIZONTAL_SYNC_START 11:0 | |
981 | ||
982 | #define PANEL_VERTICAL_TOTAL 0x08002C | |
983 | #define PANEL_VERTICAL_TOTAL_TOTAL 26:16 | |
984 | #define PANEL_VERTICAL_TOTAL_DISPLAY_END 10:0 | |
985 | ||
986 | #define PANEL_VERTICAL_SYNC 0x080030 | |
987 | #define PANEL_VERTICAL_SYNC_HEIGHT 21:16 | |
988 | #define PANEL_VERTICAL_SYNC_START 10:0 | |
989 | ||
990 | #define PANEL_CURRENT_LINE 0x080034 | |
991 | #define PANEL_CURRENT_LINE_LINE 10:0 | |
992 | ||
993 | /* Video Control */ | |
994 | ||
995 | #define VIDEO_DISPLAY_CTRL 0x080040 | |
996 | #define VIDEO_DISPLAY_CTRL_LINE_BUFFER 18:18 | |
997 | #define VIDEO_DISPLAY_CTRL_LINE_BUFFER_DISABLE 0 | |
998 | #define VIDEO_DISPLAY_CTRL_LINE_BUFFER_ENABLE 1 | |
999 | #define VIDEO_DISPLAY_CTRL_FIFO 17:16 | |
1000 | #define VIDEO_DISPLAY_CTRL_FIFO_1 0 | |
1001 | #define VIDEO_DISPLAY_CTRL_FIFO_3 1 | |
1002 | #define VIDEO_DISPLAY_CTRL_FIFO_7 2 | |
1003 | #define VIDEO_DISPLAY_CTRL_FIFO_11 3 | |
1004 | #define VIDEO_DISPLAY_CTRL_BUFFER 15:15 | |
1005 | #define VIDEO_DISPLAY_CTRL_BUFFER_0 0 | |
1006 | #define VIDEO_DISPLAY_CTRL_BUFFER_1 1 | |
1007 | #define VIDEO_DISPLAY_CTRL_CAPTURE 14:14 | |
1008 | #define VIDEO_DISPLAY_CTRL_CAPTURE_DISABLE 0 | |
1009 | #define VIDEO_DISPLAY_CTRL_CAPTURE_ENABLE 1 | |
1010 | #define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER 13:13 | |
1011 | #define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER_DISABLE 0 | |
1012 | #define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER_ENABLE 1 | |
1013 | #define VIDEO_DISPLAY_CTRL_BYTE_SWAP 12:12 | |
1014 | #define VIDEO_DISPLAY_CTRL_BYTE_SWAP_DISABLE 0 | |
1015 | #define VIDEO_DISPLAY_CTRL_BYTE_SWAP_ENABLE 1 | |
1016 | #define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE 11:11 | |
1017 | #define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE_NORMAL 0 | |
1018 | #define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE_HALF 1 | |
1019 | #define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE 10:10 | |
1020 | #define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE_NORMAL 0 | |
1021 | #define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE_HALF 1 | |
1022 | #define VIDEO_DISPLAY_CTRL_VERTICAL_MODE 9:9 | |
1023 | #define VIDEO_DISPLAY_CTRL_VERTICAL_MODE_REPLICATE 0 | |
1024 | #define VIDEO_DISPLAY_CTRL_VERTICAL_MODE_INTERPOLATE 1 | |
1025 | #define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE 8:8 | |
1026 | #define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE_REPLICATE 0 | |
1027 | #define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE_INTERPOLATE 1 | |
1028 | #define VIDEO_DISPLAY_CTRL_PIXEL 7:4 | |
1029 | #define VIDEO_DISPLAY_CTRL_GAMMA 3:3 | |
1030 | #define VIDEO_DISPLAY_CTRL_GAMMA_DISABLE 0 | |
1031 | #define VIDEO_DISPLAY_CTRL_GAMMA_ENABLE 1 | |
1032 | #define VIDEO_DISPLAY_CTRL_PLANE 2:2 | |
1033 | #define VIDEO_DISPLAY_CTRL_PLANE_DISABLE 0 | |
1034 | #define VIDEO_DISPLAY_CTRL_PLANE_ENABLE 1 | |
1035 | #define VIDEO_DISPLAY_CTRL_FORMAT 1:0 | |
1036 | #define VIDEO_DISPLAY_CTRL_FORMAT_8 0 | |
1037 | #define VIDEO_DISPLAY_CTRL_FORMAT_16 1 | |
1038 | #define VIDEO_DISPLAY_CTRL_FORMAT_32 2 | |
1039 | #define VIDEO_DISPLAY_CTRL_FORMAT_YUV 3 | |
1040 | ||
1041 | #define VIDEO_FB_0_ADDRESS 0x080044 | |
1042 | #define VIDEO_FB_0_ADDRESS_STATUS 31:31 | |
1043 | #define VIDEO_FB_0_ADDRESS_STATUS_CURRENT 0 | |
1044 | #define VIDEO_FB_0_ADDRESS_STATUS_PENDING 1 | |
1045 | #define VIDEO_FB_0_ADDRESS_EXT 27:27 | |
1046 | #define VIDEO_FB_0_ADDRESS_EXT_LOCAL 0 | |
1047 | #define VIDEO_FB_0_ADDRESS_EXT_EXTERNAL 1 | |
1048 | #define VIDEO_FB_0_ADDRESS_ADDRESS 25:0 | |
1049 | ||
1050 | #define VIDEO_FB_WIDTH 0x080048 | |
1051 | #define VIDEO_FB_WIDTH_WIDTH 29:16 | |
1052 | #define VIDEO_FB_WIDTH_OFFSET 13:0 | |
1053 | ||
1054 | #define VIDEO_FB_0_LAST_ADDRESS 0x08004C | |
1055 | #define VIDEO_FB_0_LAST_ADDRESS_EXT 27:27 | |
1056 | #define VIDEO_FB_0_LAST_ADDRESS_EXT_LOCAL 0 | |
1057 | #define VIDEO_FB_0_LAST_ADDRESS_EXT_EXTERNAL 1 | |
1058 | #define VIDEO_FB_0_LAST_ADDRESS_ADDRESS 25:0 | |
1059 | ||
1060 | #define VIDEO_PLANE_TL 0x080050 | |
1061 | #define VIDEO_PLANE_TL_TOP 26:16 | |
1062 | #define VIDEO_PLANE_TL_LEFT 10:0 | |
1063 | ||
1064 | #define VIDEO_PLANE_BR 0x080054 | |
1065 | #define VIDEO_PLANE_BR_BOTTOM 26:16 | |
1066 | #define VIDEO_PLANE_BR_RIGHT 10:0 | |
1067 | ||
1068 | #define VIDEO_SCALE 0x080058 | |
1069 | #define VIDEO_SCALE_VERTICAL_MODE 31:31 | |
1070 | #define VIDEO_SCALE_VERTICAL_MODE_EXPAND 0 | |
1071 | #define VIDEO_SCALE_VERTICAL_MODE_SHRINK 1 | |
1072 | #define VIDEO_SCALE_VERTICAL_SCALE 27:16 | |
1073 | #define VIDEO_SCALE_HORIZONTAL_MODE 15:15 | |
1074 | #define VIDEO_SCALE_HORIZONTAL_MODE_EXPAND 0 | |
1075 | #define VIDEO_SCALE_HORIZONTAL_MODE_SHRINK 1 | |
1076 | #define VIDEO_SCALE_HORIZONTAL_SCALE 11:0 | |
1077 | ||
1078 | #define VIDEO_INITIAL_SCALE 0x08005C | |
1079 | #define VIDEO_INITIAL_SCALE_FB_1 27:16 | |
1080 | #define VIDEO_INITIAL_SCALE_FB_0 11:0 | |
1081 | ||
1082 | #define VIDEO_YUV_CONSTANTS 0x080060 | |
1083 | #define VIDEO_YUV_CONSTANTS_Y 31:24 | |
1084 | #define VIDEO_YUV_CONSTANTS_R 23:16 | |
1085 | #define VIDEO_YUV_CONSTANTS_G 15:8 | |
1086 | #define VIDEO_YUV_CONSTANTS_B 7:0 | |
1087 | ||
1088 | #define VIDEO_FB_1_ADDRESS 0x080064 | |
1089 | #define VIDEO_FB_1_ADDRESS_STATUS 31:31 | |
1090 | #define VIDEO_FB_1_ADDRESS_STATUS_CURRENT 0 | |
1091 | #define VIDEO_FB_1_ADDRESS_STATUS_PENDING 1 | |
1092 | #define VIDEO_FB_1_ADDRESS_EXT 27:27 | |
1093 | #define VIDEO_FB_1_ADDRESS_EXT_LOCAL 0 | |
1094 | #define VIDEO_FB_1_ADDRESS_EXT_EXTERNAL 1 | |
1095 | #define VIDEO_FB_1_ADDRESS_ADDRESS 25:0 | |
1096 | ||
1097 | #define VIDEO_FB_1_LAST_ADDRESS 0x080068 | |
1098 | #define VIDEO_FB_1_LAST_ADDRESS_EXT 27:27 | |
1099 | #define VIDEO_FB_1_LAST_ADDRESS_EXT_LOCAL 0 | |
1100 | #define VIDEO_FB_1_LAST_ADDRESS_EXT_EXTERNAL 1 | |
1101 | #define VIDEO_FB_1_LAST_ADDRESS_ADDRESS 25:0 | |
1102 | ||
1103 | /* Video Alpha Control */ | |
1104 | ||
1105 | #define VIDEO_ALPHA_DISPLAY_CTRL 0x080080 | |
1106 | #define VIDEO_ALPHA_DISPLAY_CTRL_SELECT 28:28 | |
1107 | #define VIDEO_ALPHA_DISPLAY_CTRL_SELECT_PER_PIXEL 0 | |
1108 | #define VIDEO_ALPHA_DISPLAY_CTRL_SELECT_ALPHA 1 | |
1109 | #define VIDEO_ALPHA_DISPLAY_CTRL_ALPHA 27:24 | |
1110 | #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO 17:16 | |
1111 | #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_1 0 | |
1112 | #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_3 1 | |
1113 | #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_7 2 | |
1114 | #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_11 3 | |
1115 | #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE 11:11 | |
1116 | #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE_NORMAL 0 | |
1117 | #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE_HALF 1 | |
1118 | #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE 10:10 | |
1119 | #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE_NORMAL 0 | |
1120 | #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE_HALF 1 | |
1121 | #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE 9:9 | |
1122 | #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE_REPLICATE 0 | |
1123 | #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE_INTERPOLATE 1 | |
1124 | #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE 8:8 | |
1125 | #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE_REPLICATE 0 | |
1126 | #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE_INTERPOLATE 1 | |
1127 | #define VIDEO_ALPHA_DISPLAY_CTRL_PIXEL 7:4 | |
1128 | #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3 | |
1129 | #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0 | |
1130 | #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1 | |
1131 | #define VIDEO_ALPHA_DISPLAY_CTRL_PLANE 2:2 | |
1132 | #define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_DISABLE 0 | |
1133 | #define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_ENABLE 1 | |
1134 | #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT 1:0 | |
1135 | #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_8 0 | |
1136 | #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_16 1 | |
1137 | #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 2 | |
1138 | #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4 3 | |
1139 | ||
1140 | #define VIDEO_ALPHA_FB_ADDRESS 0x080084 | |
1141 | #define VIDEO_ALPHA_FB_ADDRESS_STATUS 31:31 | |
1142 | #define VIDEO_ALPHA_FB_ADDRESS_STATUS_CURRENT 0 | |
1143 | #define VIDEO_ALPHA_FB_ADDRESS_STATUS_PENDING 1 | |
1144 | #define VIDEO_ALPHA_FB_ADDRESS_EXT 27:27 | |
1145 | #define VIDEO_ALPHA_FB_ADDRESS_EXT_LOCAL 0 | |
1146 | #define VIDEO_ALPHA_FB_ADDRESS_EXT_EXTERNAL 1 | |
1147 | #define VIDEO_ALPHA_FB_ADDRESS_ADDRESS 25:0 | |
1148 | ||
1149 | #define VIDEO_ALPHA_FB_WIDTH 0x080088 | |
1150 | #define VIDEO_ALPHA_FB_WIDTH_WIDTH 29:16 | |
1151 | #define VIDEO_ALPHA_FB_WIDTH_OFFSET 13:0 | |
1152 | ||
1153 | #define VIDEO_ALPHA_FB_LAST_ADDRESS 0x08008C | |
1154 | #define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT 27:27 | |
1155 | #define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT_LOCAL 0 | |
1156 | #define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT_EXTERNAL 1 | |
1157 | #define VIDEO_ALPHA_FB_LAST_ADDRESS_ADDRESS 25:0 | |
1158 | ||
1159 | #define VIDEO_ALPHA_PLANE_TL 0x080090 | |
1160 | #define VIDEO_ALPHA_PLANE_TL_TOP 26:16 | |
1161 | #define VIDEO_ALPHA_PLANE_TL_LEFT 10:0 | |
1162 | ||
1163 | #define VIDEO_ALPHA_PLANE_BR 0x080094 | |
1164 | #define VIDEO_ALPHA_PLANE_BR_BOTTOM 26:16 | |
1165 | #define VIDEO_ALPHA_PLANE_BR_RIGHT 10:0 | |
1166 | ||
1167 | #define VIDEO_ALPHA_SCALE 0x080098 | |
1168 | #define VIDEO_ALPHA_SCALE_VERTICAL_MODE 31:31 | |
1169 | #define VIDEO_ALPHA_SCALE_VERTICAL_MODE_EXPAND 0 | |
1170 | #define VIDEO_ALPHA_SCALE_VERTICAL_MODE_SHRINK 1 | |
1171 | #define VIDEO_ALPHA_SCALE_VERTICAL_SCALE 27:16 | |
1172 | #define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE 15:15 | |
1173 | #define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE_EXPAND 0 | |
1174 | #define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE_SHRINK 1 | |
1175 | #define VIDEO_ALPHA_SCALE_HORIZONTAL_SCALE 11:0 | |
1176 | ||
1177 | #define VIDEO_ALPHA_INITIAL_SCALE 0x08009C | |
1178 | #define VIDEO_ALPHA_INITIAL_SCALE_VERTICAL 27:16 | |
1179 | #define VIDEO_ALPHA_INITIAL_SCALE_HORIZONTAL 11:0 | |
1180 | ||
1181 | #define VIDEO_ALPHA_CHROMA_KEY 0x0800A0 | |
1182 | #define VIDEO_ALPHA_CHROMA_KEY_MASK 31:16 | |
1183 | #define VIDEO_ALPHA_CHROMA_KEY_VALUE 15:0 | |
1184 | ||
1185 | #define VIDEO_ALPHA_COLOR_LOOKUP_01 0x0800A4 | |
1186 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_1 31:16 | |
1187 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_RED 31:27 | |
1188 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_GREEN 26:21 | |
1189 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_BLUE 20:16 | |
1190 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_0 15:0 | |
1191 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_RED 15:11 | |
1192 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_GREEN 10:5 | |
1193 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_BLUE 4:0 | |
1194 | ||
1195 | #define VIDEO_ALPHA_COLOR_LOOKUP_23 0x0800A8 | |
1196 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_3 31:16 | |
1197 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_RED 31:27 | |
1198 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_GREEN 26:21 | |
1199 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_BLUE 20:16 | |
1200 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_2 15:0 | |
1201 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_RED 15:11 | |
1202 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_GREEN 10:5 | |
1203 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_BLUE 4:0 | |
1204 | ||
1205 | #define VIDEO_ALPHA_COLOR_LOOKUP_45 0x0800AC | |
1206 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_5 31:16 | |
1207 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_RED 31:27 | |
1208 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_GREEN 26:21 | |
1209 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_BLUE 20:16 | |
1210 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_4 15:0 | |
1211 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_RED 15:11 | |
1212 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_GREEN 10:5 | |
1213 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_BLUE 4:0 | |
1214 | ||
1215 | #define VIDEO_ALPHA_COLOR_LOOKUP_67 0x0800B0 | |
1216 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_7 31:16 | |
1217 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_RED 31:27 | |
1218 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_GREEN 26:21 | |
1219 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_BLUE 20:16 | |
1220 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_6 15:0 | |
1221 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_RED 15:11 | |
1222 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_GREEN 10:5 | |
1223 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_BLUE 4:0 | |
1224 | ||
1225 | #define VIDEO_ALPHA_COLOR_LOOKUP_89 0x0800B4 | |
1226 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_9 31:16 | |
1227 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_RED 31:27 | |
1228 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_GREEN 26:21 | |
1229 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_BLUE 20:16 | |
1230 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_8 15:0 | |
1231 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_RED 15:11 | |
1232 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_GREEN 10:5 | |
1233 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_BLUE 4:0 | |
1234 | ||
1235 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB 0x0800B8 | |
1236 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B 31:16 | |
1237 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_RED 31:27 | |
1238 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_GREEN 26:21 | |
1239 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_BLUE 20:16 | |
1240 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A 15:0 | |
1241 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_RED 15:11 | |
1242 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_GREEN 10:5 | |
1243 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_BLUE 4:0 | |
1244 | ||
1245 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD 0x0800BC | |
1246 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D 31:16 | |
1247 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_RED 31:27 | |
1248 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_GREEN 26:21 | |
1249 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_BLUE 20:16 | |
1250 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C 15:0 | |
1251 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_RED 15:11 | |
1252 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_GREEN 10:5 | |
1253 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_BLUE 4:0 | |
1254 | ||
1255 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF 0x0800C0 | |
1256 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F 31:16 | |
1257 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_RED 31:27 | |
1258 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_GREEN 26:21 | |
1259 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_BLUE 20:16 | |
1260 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E 15:0 | |
1261 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_RED 15:11 | |
1262 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_GREEN 10:5 | |
1263 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_BLUE 4:0 | |
1264 | ||
1265 | /* Panel Cursor Control */ | |
1266 | ||
1267 | #define PANEL_HWC_ADDRESS 0x0800F0 | |
1268 | #define PANEL_HWC_ADDRESS_ENABLE 31:31 | |
1269 | #define PANEL_HWC_ADDRESS_ENABLE_DISABLE 0 | |
1270 | #define PANEL_HWC_ADDRESS_ENABLE_ENABLE 1 | |
1271 | #define PANEL_HWC_ADDRESS_EXT 27:27 | |
1272 | #define PANEL_HWC_ADDRESS_EXT_LOCAL 0 | |
1273 | #define PANEL_HWC_ADDRESS_EXT_EXTERNAL 1 | |
1274 | #define PANEL_HWC_ADDRESS_ADDRESS 25:0 | |
1275 | ||
1276 | #define PANEL_HWC_LOCATION 0x0800F4 | |
1277 | #define PANEL_HWC_LOCATION_TOP 27:27 | |
1278 | #define PANEL_HWC_LOCATION_TOP_INSIDE 0 | |
1279 | #define PANEL_HWC_LOCATION_TOP_OUTSIDE 1 | |
1280 | #define PANEL_HWC_LOCATION_Y 26:16 | |
1281 | #define PANEL_HWC_LOCATION_LEFT 11:11 | |
1282 | #define PANEL_HWC_LOCATION_LEFT_INSIDE 0 | |
1283 | #define PANEL_HWC_LOCATION_LEFT_OUTSIDE 1 | |
1284 | #define PANEL_HWC_LOCATION_X 10:0 | |
1285 | ||
1286 | #define PANEL_HWC_COLOR_12 0x0800F8 | |
1287 | #define PANEL_HWC_COLOR_12_2_RGB565 31:16 | |
1288 | #define PANEL_HWC_COLOR_12_1_RGB565 15:0 | |
1289 | ||
1290 | #define PANEL_HWC_COLOR_3 0x0800FC | |
1291 | #define PANEL_HWC_COLOR_3_RGB565 15:0 | |
1292 | ||
1293 | /* Old Definitions +++ */ | |
1294 | #define PANEL_HWC_COLOR_01 0x0800F8 | |
1295 | #define PANEL_HWC_COLOR_01_1_RED 31:27 | |
1296 | #define PANEL_HWC_COLOR_01_1_GREEN 26:21 | |
1297 | #define PANEL_HWC_COLOR_01_1_BLUE 20:16 | |
1298 | #define PANEL_HWC_COLOR_01_0_RED 15:11 | |
1299 | #define PANEL_HWC_COLOR_01_0_GREEN 10:5 | |
1300 | #define PANEL_HWC_COLOR_01_0_BLUE 4:0 | |
1301 | ||
1302 | #define PANEL_HWC_COLOR_2 0x0800FC | |
1303 | #define PANEL_HWC_COLOR_2_RED 15:11 | |
1304 | #define PANEL_HWC_COLOR_2_GREEN 10:5 | |
1305 | #define PANEL_HWC_COLOR_2_BLUE 4:0 | |
1306 | /* Old Definitions --- */ | |
1307 | ||
1308 | /* Alpha Control */ | |
1309 | ||
1310 | #define ALPHA_DISPLAY_CTRL 0x080100 | |
1311 | #define ALPHA_DISPLAY_CTRL_SELECT 28:28 | |
1312 | #define ALPHA_DISPLAY_CTRL_SELECT_PER_PIXEL 0 | |
1313 | #define ALPHA_DISPLAY_CTRL_SELECT_ALPHA 1 | |
1314 | #define ALPHA_DISPLAY_CTRL_ALPHA 27:24 | |
1315 | #define ALPHA_DISPLAY_CTRL_FIFO 17:16 | |
1316 | #define ALPHA_DISPLAY_CTRL_FIFO_1 0 | |
1317 | #define ALPHA_DISPLAY_CTRL_FIFO_3 1 | |
1318 | #define ALPHA_DISPLAY_CTRL_FIFO_7 2 | |
1319 | #define ALPHA_DISPLAY_CTRL_FIFO_11 3 | |
1320 | #define ALPHA_DISPLAY_CTRL_PIXEL 7:4 | |
1321 | #define ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3 | |
1322 | #define ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0 | |
1323 | #define ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1 | |
1324 | #define ALPHA_DISPLAY_CTRL_PLANE 2:2 | |
1325 | #define ALPHA_DISPLAY_CTRL_PLANE_DISABLE 0 | |
1326 | #define ALPHA_DISPLAY_CTRL_PLANE_ENABLE 1 | |
1327 | #define ALPHA_DISPLAY_CTRL_FORMAT 1:0 | |
1328 | #define ALPHA_DISPLAY_CTRL_FORMAT_16 1 | |
1329 | #define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 2 | |
1330 | #define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4 3 | |
1331 | ||
1332 | #define ALPHA_FB_ADDRESS 0x080104 | |
1333 | #define ALPHA_FB_ADDRESS_STATUS 31:31 | |
1334 | #define ALPHA_FB_ADDRESS_STATUS_CURRENT 0 | |
1335 | #define ALPHA_FB_ADDRESS_STATUS_PENDING 1 | |
1336 | #define ALPHA_FB_ADDRESS_EXT 27:27 | |
1337 | #define ALPHA_FB_ADDRESS_EXT_LOCAL 0 | |
1338 | #define ALPHA_FB_ADDRESS_EXT_EXTERNAL 1 | |
1339 | #define ALPHA_FB_ADDRESS_ADDRESS 25:0 | |
1340 | ||
1341 | #define ALPHA_FB_WIDTH 0x080108 | |
1342 | #define ALPHA_FB_WIDTH_WIDTH 29:16 | |
1343 | #define ALPHA_FB_WIDTH_OFFSET 13:0 | |
1344 | ||
1345 | #define ALPHA_PLANE_TL 0x08010C | |
1346 | #define ALPHA_PLANE_TL_TOP 26:16 | |
1347 | #define ALPHA_PLANE_TL_LEFT 10:0 | |
1348 | ||
1349 | #define ALPHA_PLANE_BR 0x080110 | |
1350 | #define ALPHA_PLANE_BR_BOTTOM 26:16 | |
1351 | #define ALPHA_PLANE_BR_RIGHT 10:0 | |
1352 | ||
1353 | #define ALPHA_CHROMA_KEY 0x080114 | |
1354 | #define ALPHA_CHROMA_KEY_MASK 31:16 | |
1355 | #define ALPHA_CHROMA_KEY_VALUE 15:0 | |
1356 | ||
1357 | #define ALPHA_COLOR_LOOKUP_01 0x080118 | |
1358 | #define ALPHA_COLOR_LOOKUP_01_1 31:16 | |
1359 | #define ALPHA_COLOR_LOOKUP_01_1_RED 31:27 | |
1360 | #define ALPHA_COLOR_LOOKUP_01_1_GREEN 26:21 | |
1361 | #define ALPHA_COLOR_LOOKUP_01_1_BLUE 20:16 | |
1362 | #define ALPHA_COLOR_LOOKUP_01_0 15:0 | |
1363 | #define ALPHA_COLOR_LOOKUP_01_0_RED 15:11 | |
1364 | #define ALPHA_COLOR_LOOKUP_01_0_GREEN 10:5 | |
1365 | #define ALPHA_COLOR_LOOKUP_01_0_BLUE 4:0 | |
1366 | ||
1367 | #define ALPHA_COLOR_LOOKUP_23 0x08011C | |
1368 | #define ALPHA_COLOR_LOOKUP_23_3 31:16 | |
1369 | #define ALPHA_COLOR_LOOKUP_23_3_RED 31:27 | |
1370 | #define ALPHA_COLOR_LOOKUP_23_3_GREEN 26:21 | |
1371 | #define ALPHA_COLOR_LOOKUP_23_3_BLUE 20:16 | |
1372 | #define ALPHA_COLOR_LOOKUP_23_2 15:0 | |
1373 | #define ALPHA_COLOR_LOOKUP_23_2_RED 15:11 | |
1374 | #define ALPHA_COLOR_LOOKUP_23_2_GREEN 10:5 | |
1375 | #define ALPHA_COLOR_LOOKUP_23_2_BLUE 4:0 | |
1376 | ||
1377 | #define ALPHA_COLOR_LOOKUP_45 0x080120 | |
1378 | #define ALPHA_COLOR_LOOKUP_45_5 31:16 | |
1379 | #define ALPHA_COLOR_LOOKUP_45_5_RED 31:27 | |
1380 | #define ALPHA_COLOR_LOOKUP_45_5_GREEN 26:21 | |
1381 | #define ALPHA_COLOR_LOOKUP_45_5_BLUE 20:16 | |
1382 | #define ALPHA_COLOR_LOOKUP_45_4 15:0 | |
1383 | #define ALPHA_COLOR_LOOKUP_45_4_RED 15:11 | |
1384 | #define ALPHA_COLOR_LOOKUP_45_4_GREEN 10:5 | |
1385 | #define ALPHA_COLOR_LOOKUP_45_4_BLUE 4:0 | |
1386 | ||
1387 | #define ALPHA_COLOR_LOOKUP_67 0x080124 | |
1388 | #define ALPHA_COLOR_LOOKUP_67_7 31:16 | |
1389 | #define ALPHA_COLOR_LOOKUP_67_7_RED 31:27 | |
1390 | #define ALPHA_COLOR_LOOKUP_67_7_GREEN 26:21 | |
1391 | #define ALPHA_COLOR_LOOKUP_67_7_BLUE 20:16 | |
1392 | #define ALPHA_COLOR_LOOKUP_67_6 15:0 | |
1393 | #define ALPHA_COLOR_LOOKUP_67_6_RED 15:11 | |
1394 | #define ALPHA_COLOR_LOOKUP_67_6_GREEN 10:5 | |
1395 | #define ALPHA_COLOR_LOOKUP_67_6_BLUE 4:0 | |
1396 | ||
1397 | #define ALPHA_COLOR_LOOKUP_89 0x080128 | |
1398 | #define ALPHA_COLOR_LOOKUP_89_9 31:16 | |
1399 | #define ALPHA_COLOR_LOOKUP_89_9_RED 31:27 | |
1400 | #define ALPHA_COLOR_LOOKUP_89_9_GREEN 26:21 | |
1401 | #define ALPHA_COLOR_LOOKUP_89_9_BLUE 20:16 | |
1402 | #define ALPHA_COLOR_LOOKUP_89_8 15:0 | |
1403 | #define ALPHA_COLOR_LOOKUP_89_8_RED 15:11 | |
1404 | #define ALPHA_COLOR_LOOKUP_89_8_GREEN 10:5 | |
1405 | #define ALPHA_COLOR_LOOKUP_89_8_BLUE 4:0 | |
1406 | ||
1407 | #define ALPHA_COLOR_LOOKUP_AB 0x08012C | |
1408 | #define ALPHA_COLOR_LOOKUP_AB_B 31:16 | |
1409 | #define ALPHA_COLOR_LOOKUP_AB_B_RED 31:27 | |
1410 | #define ALPHA_COLOR_LOOKUP_AB_B_GREEN 26:21 | |
1411 | #define ALPHA_COLOR_LOOKUP_AB_B_BLUE 20:16 | |
1412 | #define ALPHA_COLOR_LOOKUP_AB_A 15:0 | |
1413 | #define ALPHA_COLOR_LOOKUP_AB_A_RED 15:11 | |
1414 | #define ALPHA_COLOR_LOOKUP_AB_A_GREEN 10:5 | |
1415 | #define ALPHA_COLOR_LOOKUP_AB_A_BLUE 4:0 | |
1416 | ||
1417 | #define ALPHA_COLOR_LOOKUP_CD 0x080130 | |
1418 | #define ALPHA_COLOR_LOOKUP_CD_D 31:16 | |
1419 | #define ALPHA_COLOR_LOOKUP_CD_D_RED 31:27 | |
1420 | #define ALPHA_COLOR_LOOKUP_CD_D_GREEN 26:21 | |
1421 | #define ALPHA_COLOR_LOOKUP_CD_D_BLUE 20:16 | |
1422 | #define ALPHA_COLOR_LOOKUP_CD_C 15:0 | |
1423 | #define ALPHA_COLOR_LOOKUP_CD_C_RED 15:11 | |
1424 | #define ALPHA_COLOR_LOOKUP_CD_C_GREEN 10:5 | |
1425 | #define ALPHA_COLOR_LOOKUP_CD_C_BLUE 4:0 | |
1426 | ||
1427 | #define ALPHA_COLOR_LOOKUP_EF 0x080134 | |
1428 | #define ALPHA_COLOR_LOOKUP_EF_F 31:16 | |
1429 | #define ALPHA_COLOR_LOOKUP_EF_F_RED 31:27 | |
1430 | #define ALPHA_COLOR_LOOKUP_EF_F_GREEN 26:21 | |
1431 | #define ALPHA_COLOR_LOOKUP_EF_F_BLUE 20:16 | |
1432 | #define ALPHA_COLOR_LOOKUP_EF_E 15:0 | |
1433 | #define ALPHA_COLOR_LOOKUP_EF_E_RED 15:11 | |
1434 | #define ALPHA_COLOR_LOOKUP_EF_E_GREEN 10:5 | |
1435 | #define ALPHA_COLOR_LOOKUP_EF_E_BLUE 4:0 | |
1436 | ||
1437 | /* CRT Graphics Control */ | |
1438 | ||
1439 | #define CRT_DISPLAY_CTRL 0x080200 | |
78376535 JL |
1440 | #define CRT_DISPLAY_CTRL_RESERVED_1_MASK 31:27 |
1441 | #define CRT_DISPLAY_CTRL_RESERVED_1_MASK_DISABLE 0 | |
1442 | #define CRT_DISPLAY_CTRL_RESERVED_1_MASK_ENABLE 0x1F | |
81dee67e SM |
1443 | |
1444 | /* SM750LE definition */ | |
1445 | #define CRT_DISPLAY_CTRL_DPMS 31:30 | |
1446 | #define CRT_DISPLAY_CTRL_DPMS_0 0 | |
1447 | #define CRT_DISPLAY_CTRL_DPMS_1 1 | |
1448 | #define CRT_DISPLAY_CTRL_DPMS_2 2 | |
1449 | #define CRT_DISPLAY_CTRL_DPMS_3 3 | |
1450 | #define CRT_DISPLAY_CTRL_CLK 29:27 | |
1451 | #define CRT_DISPLAY_CTRL_CLK_PLL25 0 | |
1452 | #define CRT_DISPLAY_CTRL_CLK_PLL41 1 | |
1453 | #define CRT_DISPLAY_CTRL_CLK_PLL62 2 | |
1454 | #define CRT_DISPLAY_CTRL_CLK_PLL65 3 | |
1455 | #define CRT_DISPLAY_CTRL_CLK_PLL74 4 | |
1456 | #define CRT_DISPLAY_CTRL_CLK_PLL80 5 | |
1457 | #define CRT_DISPLAY_CTRL_CLK_PLL108 6 | |
1458 | #define CRT_DISPLAY_CTRL_CLK_RESERVED 7 | |
1459 | #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC 26:26 | |
1460 | #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_DISABLE 1 | |
1461 | #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_ENABLE 0 | |
1462 | ||
1463 | ||
78376535 JL |
1464 | #define CRT_DISPLAY_CTRL_RESERVED_2_MASK 25:24 |
1465 | #define CRT_DISPLAY_CTRL_RESERVED_2_MASK_ENABLE 3 | |
1466 | #define CRT_DISPLAY_CTRL_RESERVED_2_MASK_DISABLE 0 | |
81dee67e SM |
1467 | |
1468 | /* SM750LE definition */ | |
1469 | #define CRT_DISPLAY_CTRL_CRTSELECT 25:25 | |
1470 | #define CRT_DISPLAY_CTRL_CRTSELECT_VGA 0 | |
1471 | #define CRT_DISPLAY_CTRL_CRTSELECT_CRT 1 | |
1472 | #define CRT_DISPLAY_CTRL_RGBBIT 24:24 | |
1473 | #define CRT_DISPLAY_CTRL_RGBBIT_24BIT 0 | |
1474 | #define CRT_DISPLAY_CTRL_RGBBIT_12BIT 1 | |
1475 | ||
1476 | ||
78376535 | 1477 | #define CRT_DISPLAY_CTRL_RESERVED_3_MASK 15:15 |
81dee67e SM |
1478 | #define CRT_DISPLAY_CTRL_RESERVED_3_MASK_DISABLE 0 |
1479 | #define CRT_DISPLAY_CTRL_RESERVED_3_MASK_ENABLE 1 | |
1480 | ||
78376535 | 1481 | #define CRT_DISPLAY_CTRL_RESERVED_4_MASK 9:9 |
81dee67e SM |
1482 | #define CRT_DISPLAY_CTRL_RESERVED_4_MASK_DISABLE 0 |
1483 | #define CRT_DISPLAY_CTRL_RESERVED_4_MASK_ENABLE 1 | |
1484 | ||
1485 | #ifndef VALIDATION_CHIP | |
1486 | #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC 26:26 | |
1487 | #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_DISABLE 1 | |
1488 | #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_ENABLE 0 | |
1489 | #define CRT_DISPLAY_CTRL_CENTERING 24:24 | |
1490 | #define CRT_DISPLAY_CTRL_CENTERING_DISABLE 0 | |
1491 | #define CRT_DISPLAY_CTRL_CENTERING_ENABLE 1 | |
1492 | #endif | |
1493 | #define CRT_DISPLAY_CTRL_LOCK_TIMING 23:23 | |
1494 | #define CRT_DISPLAY_CTRL_LOCK_TIMING_DISABLE 0 | |
1495 | #define CRT_DISPLAY_CTRL_LOCK_TIMING_ENABLE 1 | |
1496 | #define CRT_DISPLAY_CTRL_EXPANSION 22:22 | |
1497 | #define CRT_DISPLAY_CTRL_EXPANSION_DISABLE 0 | |
1498 | #define CRT_DISPLAY_CTRL_EXPANSION_ENABLE 1 | |
1499 | #define CRT_DISPLAY_CTRL_VERTICAL_MODE 21:21 | |
1500 | #define CRT_DISPLAY_CTRL_VERTICAL_MODE_REPLICATE 0 | |
1501 | #define CRT_DISPLAY_CTRL_VERTICAL_MODE_INTERPOLATE 1 | |
1502 | #define CRT_DISPLAY_CTRL_HORIZONTAL_MODE 20:20 | |
1503 | #define CRT_DISPLAY_CTRL_HORIZONTAL_MODE_REPLICATE 0 | |
1504 | #define CRT_DISPLAY_CTRL_HORIZONTAL_MODE_INTERPOLATE 1 | |
1505 | #define CRT_DISPLAY_CTRL_SELECT 19:18 | |
1506 | #define CRT_DISPLAY_CTRL_SELECT_PANEL 0 | |
1507 | #define CRT_DISPLAY_CTRL_SELECT_VGA 1 | |
1508 | #define CRT_DISPLAY_CTRL_SELECT_CRT 2 | |
1509 | #define CRT_DISPLAY_CTRL_FIFO 17:16 | |
1510 | #define CRT_DISPLAY_CTRL_FIFO_1 0 | |
1511 | #define CRT_DISPLAY_CTRL_FIFO_3 1 | |
1512 | #define CRT_DISPLAY_CTRL_FIFO_7 2 | |
1513 | #define CRT_DISPLAY_CTRL_FIFO_11 3 | |
1514 | #define CRT_DISPLAY_CTRL_CLOCK_PHASE 14:14 | |
1515 | #define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0 | |
1516 | #define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1 | |
1517 | #define CRT_DISPLAY_CTRL_VSYNC_PHASE 13:13 | |
1518 | #define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0 | |
1519 | #define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1 | |
1520 | #define CRT_DISPLAY_CTRL_HSYNC_PHASE 12:12 | |
1521 | #define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0 | |
1522 | #define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1 | |
1523 | #define CRT_DISPLAY_CTRL_BLANK 10:10 | |
1524 | #define CRT_DISPLAY_CTRL_BLANK_OFF 0 | |
1525 | #define CRT_DISPLAY_CTRL_BLANK_ON 1 | |
1526 | #define CRT_DISPLAY_CTRL_TIMING 8:8 | |
1527 | #define CRT_DISPLAY_CTRL_TIMING_DISABLE 0 | |
1528 | #define CRT_DISPLAY_CTRL_TIMING_ENABLE 1 | |
1529 | #define CRT_DISPLAY_CTRL_PIXEL 7:4 | |
1530 | #define CRT_DISPLAY_CTRL_GAMMA 3:3 | |
1531 | #define CRT_DISPLAY_CTRL_GAMMA_DISABLE 0 | |
1532 | #define CRT_DISPLAY_CTRL_GAMMA_ENABLE 1 | |
1533 | #define CRT_DISPLAY_CTRL_PLANE 2:2 | |
1534 | #define CRT_DISPLAY_CTRL_PLANE_DISABLE 0 | |
1535 | #define CRT_DISPLAY_CTRL_PLANE_ENABLE 1 | |
1536 | #define CRT_DISPLAY_CTRL_FORMAT 1:0 | |
1537 | #define CRT_DISPLAY_CTRL_FORMAT_8 0 | |
1538 | #define CRT_DISPLAY_CTRL_FORMAT_16 1 | |
1539 | #define CRT_DISPLAY_CTRL_FORMAT_32 2 | |
1540 | #define CRT_DISPLAY_CTRL_RESERVED_BITS_MASK 0xFF000200 | |
1541 | ||
1542 | #define CRT_FB_ADDRESS 0x080204 | |
1543 | #define CRT_FB_ADDRESS_STATUS 31:31 | |
1544 | #define CRT_FB_ADDRESS_STATUS_CURRENT 0 | |
1545 | #define CRT_FB_ADDRESS_STATUS_PENDING 1 | |
1546 | #define CRT_FB_ADDRESS_EXT 27:27 | |
1547 | #define CRT_FB_ADDRESS_EXT_LOCAL 0 | |
1548 | #define CRT_FB_ADDRESS_EXT_EXTERNAL 1 | |
1549 | #define CRT_FB_ADDRESS_ADDRESS 25:0 | |
1550 | ||
1551 | #define CRT_FB_WIDTH 0x080208 | |
1552 | #define CRT_FB_WIDTH_WIDTH 29:16 | |
1553 | #define CRT_FB_WIDTH_OFFSET 13:0 | |
1554 | ||
1555 | #define CRT_HORIZONTAL_TOTAL 0x08020C | |
1556 | #define CRT_HORIZONTAL_TOTAL_TOTAL 27:16 | |
1557 | #define CRT_HORIZONTAL_TOTAL_DISPLAY_END 11:0 | |
1558 | ||
1559 | #define CRT_HORIZONTAL_SYNC 0x080210 | |
1560 | #define CRT_HORIZONTAL_SYNC_WIDTH 23:16 | |
1561 | #define CRT_HORIZONTAL_SYNC_START 11:0 | |
1562 | ||
1563 | #define CRT_VERTICAL_TOTAL 0x080214 | |
1564 | #define CRT_VERTICAL_TOTAL_TOTAL 26:16 | |
1565 | #define CRT_VERTICAL_TOTAL_DISPLAY_END 10:0 | |
1566 | ||
1567 | #define CRT_VERTICAL_SYNC 0x080218 | |
1568 | #define CRT_VERTICAL_SYNC_HEIGHT 21:16 | |
1569 | #define CRT_VERTICAL_SYNC_START 10:0 | |
1570 | ||
1571 | #define CRT_SIGNATURE_ANALYZER 0x08021C | |
1572 | #define CRT_SIGNATURE_ANALYZER_STATUS 31:16 | |
1573 | #define CRT_SIGNATURE_ANALYZER_ENABLE 3:3 | |
1574 | #define CRT_SIGNATURE_ANALYZER_ENABLE_DISABLE 0 | |
1575 | #define CRT_SIGNATURE_ANALYZER_ENABLE_ENABLE 1 | |
1576 | #define CRT_SIGNATURE_ANALYZER_RESET 2:2 | |
1577 | #define CRT_SIGNATURE_ANALYZER_RESET_NORMAL 0 | |
1578 | #define CRT_SIGNATURE_ANALYZER_RESET_RESET 1 | |
1579 | #define CRT_SIGNATURE_ANALYZER_SOURCE 1:0 | |
1580 | #define CRT_SIGNATURE_ANALYZER_SOURCE_RED 0 | |
1581 | #define CRT_SIGNATURE_ANALYZER_SOURCE_GREEN 1 | |
1582 | #define CRT_SIGNATURE_ANALYZER_SOURCE_BLUE 2 | |
1583 | ||
1584 | #define CRT_CURRENT_LINE 0x080220 | |
1585 | #define CRT_CURRENT_LINE_LINE 10:0 | |
1586 | ||
1587 | #define CRT_MONITOR_DETECT 0x080224 | |
1588 | #define CRT_MONITOR_DETECT_VALUE 25:25 | |
1589 | #define CRT_MONITOR_DETECT_VALUE_DISABLE 0 | |
1590 | #define CRT_MONITOR_DETECT_VALUE_ENABLE 1 | |
1591 | #define CRT_MONITOR_DETECT_ENABLE 24:24 | |
1592 | #define CRT_MONITOR_DETECT_ENABLE_DISABLE 0 | |
1593 | #define CRT_MONITOR_DETECT_ENABLE_ENABLE 1 | |
1594 | #define CRT_MONITOR_DETECT_RED 23:16 | |
1595 | #define CRT_MONITOR_DETECT_GREEN 15:8 | |
1596 | #define CRT_MONITOR_DETECT_BLUE 7:0 | |
1597 | ||
1598 | #define CRT_SCALE 0x080228 | |
1599 | #define CRT_SCALE_VERTICAL_MODE 31:31 | |
1600 | #define CRT_SCALE_VERTICAL_MODE_EXPAND 0 | |
1601 | #define CRT_SCALE_VERTICAL_MODE_SHRINK 1 | |
1602 | #define CRT_SCALE_VERTICAL_SCALE 27:16 | |
1603 | #define CRT_SCALE_HORIZONTAL_MODE 15:15 | |
1604 | #define CRT_SCALE_HORIZONTAL_MODE_EXPAND 0 | |
1605 | #define CRT_SCALE_HORIZONTAL_MODE_SHRINK 1 | |
1606 | #define CRT_SCALE_HORIZONTAL_SCALE 11:0 | |
1607 | ||
1608 | /* CRT Cursor Control */ | |
1609 | ||
1610 | #define CRT_HWC_ADDRESS 0x080230 | |
1611 | #define CRT_HWC_ADDRESS_ENABLE 31:31 | |
1612 | #define CRT_HWC_ADDRESS_ENABLE_DISABLE 0 | |
1613 | #define CRT_HWC_ADDRESS_ENABLE_ENABLE 1 | |
1614 | #define CRT_HWC_ADDRESS_EXT 27:27 | |
1615 | #define CRT_HWC_ADDRESS_EXT_LOCAL 0 | |
1616 | #define CRT_HWC_ADDRESS_EXT_EXTERNAL 1 | |
1617 | #define CRT_HWC_ADDRESS_ADDRESS 25:0 | |
1618 | ||
1619 | #define CRT_HWC_LOCATION 0x080234 | |
1620 | #define CRT_HWC_LOCATION_TOP 27:27 | |
1621 | #define CRT_HWC_LOCATION_TOP_INSIDE 0 | |
1622 | #define CRT_HWC_LOCATION_TOP_OUTSIDE 1 | |
1623 | #define CRT_HWC_LOCATION_Y 26:16 | |
1624 | #define CRT_HWC_LOCATION_LEFT 11:11 | |
1625 | #define CRT_HWC_LOCATION_LEFT_INSIDE 0 | |
1626 | #define CRT_HWC_LOCATION_LEFT_OUTSIDE 1 | |
1627 | #define CRT_HWC_LOCATION_X 10:0 | |
1628 | ||
1629 | #define CRT_HWC_COLOR_12 0x080238 | |
1630 | #define CRT_HWC_COLOR_12_2_RGB565 31:16 | |
1631 | #define CRT_HWC_COLOR_12_1_RGB565 15:0 | |
1632 | ||
1633 | #define CRT_HWC_COLOR_3 0x08023C | |
1634 | #define CRT_HWC_COLOR_3_RGB565 15:0 | |
1635 | ||
81dee67e SM |
1636 | /* This vertical expansion below start at 0x080240 ~ 0x080264 */ |
1637 | #define CRT_VERTICAL_EXPANSION 0x080240 | |
1638 | #ifndef VALIDATION_CHIP | |
1639 | #define CRT_VERTICAL_CENTERING_VALUE 31:24 | |
1640 | #endif | |
1641 | #define CRT_VERTICAL_EXPANSION_COMPARE_VALUE 23:16 | |
1642 | #define CRT_VERTICAL_EXPANSION_LINE_BUFFER 15:12 | |
1643 | #define CRT_VERTICAL_EXPANSION_SCALE_FACTOR 11:0 | |
1644 | ||
1645 | /* This horizontal expansion below start at 0x080268 ~ 0x08027C */ | |
1646 | #define CRT_HORIZONTAL_EXPANSION 0x080268 | |
1647 | #ifndef VALIDATION_CHIP | |
1648 | #define CRT_HORIZONTAL_CENTERING_VALUE 31:24 | |
1649 | #endif | |
1650 | #define CRT_HORIZONTAL_EXPANSION_COMPARE_VALUE 23:16 | |
1651 | #define CRT_HORIZONTAL_EXPANSION_SCALE_FACTOR 11:0 | |
1652 | ||
1653 | #ifndef VALIDATION_CHIP | |
1654 | /* Auto Centering */ | |
1655 | #define CRT_AUTO_CENTERING_TL 0x080280 | |
1656 | #define CRT_AUTO_CENTERING_TL_TOP 26:16 | |
1657 | #define CRT_AUTO_CENTERING_TL_LEFT 10:0 | |
1658 | ||
1659 | #define CRT_AUTO_CENTERING_BR 0x080284 | |
1660 | #define CRT_AUTO_CENTERING_BR_BOTTOM 26:16 | |
1661 | #define CRT_AUTO_CENTERING_BR_RIGHT 10:0 | |
1662 | #endif | |
1663 | ||
1664 | /* sm750le new register to control panel output */ | |
78376535 | 1665 | #define DISPLAY_CONTROL_750LE 0x80288 |
81dee67e SM |
1666 | /* Palette RAM */ |
1667 | ||
69e98df7 | 1668 | /* Panel Palette register starts at 0x080400 ~ 0x0807FC */ |
81dee67e SM |
1669 | #define PANEL_PALETTE_RAM 0x080400 |
1670 | ||
69e98df7 | 1671 | /* Panel Palette register starts at 0x080C00 ~ 0x080FFC */ |
81dee67e SM |
1672 | #define CRT_PALETTE_RAM 0x080C00 |
1673 | ||
81dee67e SM |
1674 | /* Color Space Conversion registers. */ |
1675 | ||
1676 | #define CSC_Y_SOURCE_BASE 0x1000C8 | |
1677 | #define CSC_Y_SOURCE_BASE_EXT 27:27 | |
1678 | #define CSC_Y_SOURCE_BASE_EXT_LOCAL 0 | |
1679 | #define CSC_Y_SOURCE_BASE_EXT_EXTERNAL 1 | |
1680 | #define CSC_Y_SOURCE_BASE_CS 26:26 | |
1681 | #define CSC_Y_SOURCE_BASE_CS_0 0 | |
1682 | #define CSC_Y_SOURCE_BASE_CS_1 1 | |
1683 | #define CSC_Y_SOURCE_BASE_ADDRESS 25:0 | |
1684 | ||
1685 | #define CSC_CONSTANTS 0x1000CC | |
1686 | #define CSC_CONSTANTS_Y 31:24 | |
1687 | #define CSC_CONSTANTS_R 23:16 | |
1688 | #define CSC_CONSTANTS_G 15:8 | |
1689 | #define CSC_CONSTANTS_B 7:0 | |
1690 | ||
1691 | #define CSC_Y_SOURCE_X 0x1000D0 | |
1692 | #define CSC_Y_SOURCE_X_INTEGER 26:16 | |
1693 | #define CSC_Y_SOURCE_X_FRACTION 15:3 | |
1694 | ||
1695 | #define CSC_Y_SOURCE_Y 0x1000D4 | |
1696 | #define CSC_Y_SOURCE_Y_INTEGER 27:16 | |
1697 | #define CSC_Y_SOURCE_Y_FRACTION 15:3 | |
1698 | ||
1699 | #define CSC_U_SOURCE_BASE 0x1000D8 | |
1700 | #define CSC_U_SOURCE_BASE_EXT 27:27 | |
1701 | #define CSC_U_SOURCE_BASE_EXT_LOCAL 0 | |
1702 | #define CSC_U_SOURCE_BASE_EXT_EXTERNAL 1 | |
1703 | #define CSC_U_SOURCE_BASE_CS 26:26 | |
1704 | #define CSC_U_SOURCE_BASE_CS_0 0 | |
1705 | #define CSC_U_SOURCE_BASE_CS_1 1 | |
1706 | #define CSC_U_SOURCE_BASE_ADDRESS 25:0 | |
1707 | ||
1708 | #define CSC_V_SOURCE_BASE 0x1000DC | |
1709 | #define CSC_V_SOURCE_BASE_EXT 27:27 | |
1710 | #define CSC_V_SOURCE_BASE_EXT_LOCAL 0 | |
1711 | #define CSC_V_SOURCE_BASE_EXT_EXTERNAL 1 | |
1712 | #define CSC_V_SOURCE_BASE_CS 26:26 | |
1713 | #define CSC_V_SOURCE_BASE_CS_0 0 | |
1714 | #define CSC_V_SOURCE_BASE_CS_1 1 | |
1715 | #define CSC_V_SOURCE_BASE_ADDRESS 25:0 | |
1716 | ||
1717 | #define CSC_SOURCE_DIMENSION 0x1000E0 | |
1718 | #define CSC_SOURCE_DIMENSION_X 31:16 | |
1719 | #define CSC_SOURCE_DIMENSION_Y 15:0 | |
1720 | ||
1721 | #define CSC_SOURCE_PITCH 0x1000E4 | |
1722 | #define CSC_SOURCE_PITCH_Y 31:16 | |
1723 | #define CSC_SOURCE_PITCH_UV 15:0 | |
1724 | ||
1725 | #define CSC_DESTINATION 0x1000E8 | |
1726 | #define CSC_DESTINATION_WRAP 31:31 | |
1727 | #define CSC_DESTINATION_WRAP_DISABLE 0 | |
1728 | #define CSC_DESTINATION_WRAP_ENABLE 1 | |
1729 | #define CSC_DESTINATION_X 27:16 | |
1730 | #define CSC_DESTINATION_Y 11:0 | |
1731 | ||
1732 | #define CSC_DESTINATION_DIMENSION 0x1000EC | |
1733 | #define CSC_DESTINATION_DIMENSION_X 31:16 | |
1734 | #define CSC_DESTINATION_DIMENSION_Y 15:0 | |
1735 | ||
1736 | #define CSC_DESTINATION_PITCH 0x1000F0 | |
1737 | #define CSC_DESTINATION_PITCH_X 31:16 | |
1738 | #define CSC_DESTINATION_PITCH_Y 15:0 | |
1739 | ||
1740 | #define CSC_SCALE_FACTOR 0x1000F4 | |
1741 | #define CSC_SCALE_FACTOR_HORIZONTAL 31:16 | |
1742 | #define CSC_SCALE_FACTOR_VERTICAL 15:0 | |
1743 | ||
1744 | #define CSC_DESTINATION_BASE 0x1000F8 | |
1745 | #define CSC_DESTINATION_BASE_EXT 27:27 | |
1746 | #define CSC_DESTINATION_BASE_EXT_LOCAL 0 | |
1747 | #define CSC_DESTINATION_BASE_EXT_EXTERNAL 1 | |
1748 | #define CSC_DESTINATION_BASE_CS 26:26 | |
1749 | #define CSC_DESTINATION_BASE_CS_0 0 | |
1750 | #define CSC_DESTINATION_BASE_CS_1 1 | |
1751 | #define CSC_DESTINATION_BASE_ADDRESS 25:0 | |
1752 | ||
1753 | #define CSC_CONTROL 0x1000FC | |
1754 | #define CSC_CONTROL_STATUS 31:31 | |
1755 | #define CSC_CONTROL_STATUS_STOP 0 | |
1756 | #define CSC_CONTROL_STATUS_START 1 | |
1757 | #define CSC_CONTROL_SOURCE_FORMAT 30:28 | |
1758 | #define CSC_CONTROL_SOURCE_FORMAT_YUV422 0 | |
1759 | #define CSC_CONTROL_SOURCE_FORMAT_YUV420I 1 | |
1760 | #define CSC_CONTROL_SOURCE_FORMAT_YUV420 2 | |
1761 | #define CSC_CONTROL_SOURCE_FORMAT_YVU9 3 | |
1762 | #define CSC_CONTROL_SOURCE_FORMAT_IYU1 4 | |
1763 | #define CSC_CONTROL_SOURCE_FORMAT_IYU2 5 | |
1764 | #define CSC_CONTROL_SOURCE_FORMAT_RGB565 6 | |
1765 | #define CSC_CONTROL_SOURCE_FORMAT_RGB8888 7 | |
1766 | #define CSC_CONTROL_DESTINATION_FORMAT 27:26 | |
1767 | #define CSC_CONTROL_DESTINATION_FORMAT_RGB565 0 | |
1768 | #define CSC_CONTROL_DESTINATION_FORMAT_RGB8888 1 | |
1769 | #define CSC_CONTROL_HORIZONTAL_FILTER 25:25 | |
1770 | #define CSC_CONTROL_HORIZONTAL_FILTER_DISABLE 0 | |
1771 | #define CSC_CONTROL_HORIZONTAL_FILTER_ENABLE 1 | |
1772 | #define CSC_CONTROL_VERTICAL_FILTER 24:24 | |
1773 | #define CSC_CONTROL_VERTICAL_FILTER_DISABLE 0 | |
1774 | #define CSC_CONTROL_VERTICAL_FILTER_ENABLE 1 | |
1775 | #define CSC_CONTROL_BYTE_ORDER 23:23 | |
1776 | #define CSC_CONTROL_BYTE_ORDER_YUYV 0 | |
1777 | #define CSC_CONTROL_BYTE_ORDER_UYVY 1 | |
1778 | ||
1779 | #define DE_DATA_PORT 0x110000 | |
1780 | ||
1781 | #define I2C_BYTE_COUNT 0x010040 | |
1782 | #define I2C_BYTE_COUNT_COUNT 3:0 | |
1783 | ||
1784 | #define I2C_CTRL 0x010041 | |
1785 | #define I2C_CTRL_INT 4:4 | |
1786 | #define I2C_CTRL_INT_DISABLE 0 | |
1787 | #define I2C_CTRL_INT_ENABLE 1 | |
1788 | #define I2C_CTRL_DIR 3:3 | |
1789 | #define I2C_CTRL_DIR_WR 0 | |
1790 | #define I2C_CTRL_DIR_RD 1 | |
1791 | #define I2C_CTRL_CTRL 2:2 | |
1792 | #define I2C_CTRL_CTRL_STOP 0 | |
1793 | #define I2C_CTRL_CTRL_START 1 | |
1794 | #define I2C_CTRL_MODE 1:1 | |
1795 | #define I2C_CTRL_MODE_STANDARD 0 | |
1796 | #define I2C_CTRL_MODE_FAST 1 | |
1797 | #define I2C_CTRL_EN 0:0 | |
1798 | #define I2C_CTRL_EN_DISABLE 0 | |
1799 | #define I2C_CTRL_EN_ENABLE 1 | |
1800 | ||
1801 | #define I2C_STATUS 0x010042 | |
1802 | #define I2C_STATUS_TX 3:3 | |
1803 | #define I2C_STATUS_TX_PROGRESS 0 | |
1804 | #define I2C_STATUS_TX_COMPLETED 1 | |
1805 | #define I2C_TX_DONE 0x08 | |
1806 | #define I2C_STATUS_ERR 2:2 | |
1807 | #define I2C_STATUS_ERR_NORMAL 0 | |
1808 | #define I2C_STATUS_ERR_ERROR 1 | |
1809 | #define I2C_STATUS_ERR_CLEAR 0 | |
1810 | #define I2C_STATUS_ACK 1:1 | |
1811 | #define I2C_STATUS_ACK_RECEIVED 0 | |
1812 | #define I2C_STATUS_ACK_NOT 1 | |
1813 | #define I2C_STATUS_BSY 0:0 | |
1814 | #define I2C_STATUS_BSY_IDLE 0 | |
1815 | #define I2C_STATUS_BSY_BUSY 1 | |
1816 | ||
1817 | #define I2C_RESET 0x010042 | |
1818 | #define I2C_RESET_BUS_ERROR 2:2 | |
1819 | #define I2C_RESET_BUS_ERROR_CLEAR 0 | |
1820 | ||
1821 | #define I2C_SLAVE_ADDRESS 0x010043 | |
1822 | #define I2C_SLAVE_ADDRESS_ADDRESS 7:1 | |
1823 | #define I2C_SLAVE_ADDRESS_RW 0:0 | |
1824 | #define I2C_SLAVE_ADDRESS_RW_W 0 | |
1825 | #define I2C_SLAVE_ADDRESS_RW_R 1 | |
1826 | ||
1827 | #define I2C_DATA0 0x010044 | |
1828 | #define I2C_DATA1 0x010045 | |
1829 | #define I2C_DATA2 0x010046 | |
1830 | #define I2C_DATA3 0x010047 | |
1831 | #define I2C_DATA4 0x010048 | |
1832 | #define I2C_DATA5 0x010049 | |
1833 | #define I2C_DATA6 0x01004A | |
1834 | #define I2C_DATA7 0x01004B | |
1835 | #define I2C_DATA8 0x01004C | |
1836 | #define I2C_DATA9 0x01004D | |
1837 | #define I2C_DATA10 0x01004E | |
1838 | #define I2C_DATA11 0x01004F | |
1839 | #define I2C_DATA12 0x010050 | |
1840 | #define I2C_DATA13 0x010051 | |
1841 | #define I2C_DATA14 0x010052 | |
1842 | #define I2C_DATA15 0x010053 | |
1843 | ||
1844 | ||
1845 | #define ZV0_CAPTURE_CTRL 0x090000 | |
1846 | #define ZV0_CAPTURE_CTRL_FIELD_INPUT 27:27 | |
1847 | #define ZV0_CAPTURE_CTRL_FIELD_INPUT_EVEN_FIELD 0 | |
1848 | #define ZV0_CAPTURE_CTRL_FIELD_INPUT_ODD_FIELD 1 | |
1849 | #define ZV0_CAPTURE_CTRL_SCAN 26:26 | |
1850 | #define ZV0_CAPTURE_CTRL_SCAN_PROGRESSIVE 0 | |
1851 | #define ZV0_CAPTURE_CTRL_SCAN_INTERLACE 1 | |
1852 | #define ZV0_CAPTURE_CTRL_CURRENT_BUFFER 25:25 | |
1853 | #define ZV0_CAPTURE_CTRL_CURRENT_BUFFER_0 0 | |
1854 | #define ZV0_CAPTURE_CTRL_CURRENT_BUFFER_1 1 | |
1855 | #define ZV0_CAPTURE_CTRL_VERTICAL_SYNC 24:24 | |
1856 | #define ZV0_CAPTURE_CTRL_VERTICAL_SYNC_INACTIVE 0 | |
1857 | #define ZV0_CAPTURE_CTRL_VERTICAL_SYNC_ACTIVE 1 | |
1858 | #define ZV0_CAPTURE_CTRL_ADJ 19:19 | |
1859 | #define ZV0_CAPTURE_CTRL_ADJ_NORMAL 0 | |
1860 | #define ZV0_CAPTURE_CTRL_ADJ_DELAY 1 | |
1861 | #define ZV0_CAPTURE_CTRL_HA 18:18 | |
1862 | #define ZV0_CAPTURE_CTRL_HA_DISABLE 0 | |
1863 | #define ZV0_CAPTURE_CTRL_HA_ENABLE 1 | |
1864 | #define ZV0_CAPTURE_CTRL_VSK 17:17 | |
1865 | #define ZV0_CAPTURE_CTRL_VSK_DISABLE 0 | |
1866 | #define ZV0_CAPTURE_CTRL_VSK_ENABLE 1 | |
1867 | #define ZV0_CAPTURE_CTRL_HSK 16:16 | |
1868 | #define ZV0_CAPTURE_CTRL_HSK_DISABLE 0 | |
1869 | #define ZV0_CAPTURE_CTRL_HSK_ENABLE 1 | |
1870 | #define ZV0_CAPTURE_CTRL_FD 15:15 | |
1871 | #define ZV0_CAPTURE_CTRL_FD_RISING 0 | |
1872 | #define ZV0_CAPTURE_CTRL_FD_FALLING 1 | |
1873 | #define ZV0_CAPTURE_CTRL_VP 14:14 | |
1874 | #define ZV0_CAPTURE_CTRL_VP_HIGH 0 | |
1875 | #define ZV0_CAPTURE_CTRL_VP_LOW 1 | |
1876 | #define ZV0_CAPTURE_CTRL_HP 13:13 | |
1877 | #define ZV0_CAPTURE_CTRL_HP_HIGH 0 | |
1878 | #define ZV0_CAPTURE_CTRL_HP_LOW 1 | |
1879 | #define ZV0_CAPTURE_CTRL_CP 12:12 | |
1880 | #define ZV0_CAPTURE_CTRL_CP_HIGH 0 | |
1881 | #define ZV0_CAPTURE_CTRL_CP_LOW 1 | |
1882 | #define ZV0_CAPTURE_CTRL_UVS 11:11 | |
1883 | #define ZV0_CAPTURE_CTRL_UVS_DISABLE 0 | |
1884 | #define ZV0_CAPTURE_CTRL_UVS_ENABLE 1 | |
1885 | #define ZV0_CAPTURE_CTRL_BS 10:10 | |
1886 | #define ZV0_CAPTURE_CTRL_BS_DISABLE 0 | |
1887 | #define ZV0_CAPTURE_CTRL_BS_ENABLE 1 | |
1888 | #define ZV0_CAPTURE_CTRL_CS 9:9 | |
1889 | #define ZV0_CAPTURE_CTRL_CS_16 0 | |
1890 | #define ZV0_CAPTURE_CTRL_CS_8 1 | |
1891 | #define ZV0_CAPTURE_CTRL_CF 8:8 | |
1892 | #define ZV0_CAPTURE_CTRL_CF_YUV 0 | |
1893 | #define ZV0_CAPTURE_CTRL_CF_RGB 1 | |
1894 | #define ZV0_CAPTURE_CTRL_FS 7:7 | |
1895 | #define ZV0_CAPTURE_CTRL_FS_DISABLE 0 | |
1896 | #define ZV0_CAPTURE_CTRL_FS_ENABLE 1 | |
1897 | #define ZV0_CAPTURE_CTRL_WEAVE 6:6 | |
1898 | #define ZV0_CAPTURE_CTRL_WEAVE_DISABLE 0 | |
1899 | #define ZV0_CAPTURE_CTRL_WEAVE_ENABLE 1 | |
1900 | #define ZV0_CAPTURE_CTRL_BOB 5:5 | |
1901 | #define ZV0_CAPTURE_CTRL_BOB_DISABLE 0 | |
1902 | #define ZV0_CAPTURE_CTRL_BOB_ENABLE 1 | |
1903 | #define ZV0_CAPTURE_CTRL_DB 4:4 | |
1904 | #define ZV0_CAPTURE_CTRL_DB_DISABLE 0 | |
1905 | #define ZV0_CAPTURE_CTRL_DB_ENABLE 1 | |
1906 | #define ZV0_CAPTURE_CTRL_CC 3:3 | |
1907 | #define ZV0_CAPTURE_CTRL_CC_CONTINUE 0 | |
1908 | #define ZV0_CAPTURE_CTRL_CC_CONDITION 1 | |
1909 | #define ZV0_CAPTURE_CTRL_RGB 2:2 | |
1910 | #define ZV0_CAPTURE_CTRL_RGB_DISABLE 0 | |
1911 | #define ZV0_CAPTURE_CTRL_RGB_ENABLE 1 | |
1912 | #define ZV0_CAPTURE_CTRL_656 1:1 | |
1913 | #define ZV0_CAPTURE_CTRL_656_DISABLE 0 | |
1914 | #define ZV0_CAPTURE_CTRL_656_ENABLE 1 | |
1915 | #define ZV0_CAPTURE_CTRL_CAP 0:0 | |
1916 | #define ZV0_CAPTURE_CTRL_CAP_DISABLE 0 | |
1917 | #define ZV0_CAPTURE_CTRL_CAP_ENABLE 1 | |
1918 | ||
1919 | #define ZV0_CAPTURE_CLIP 0x090004 | |
1920 | #define ZV0_CAPTURE_CLIP_YCLIP_EVEN_FIELD 25:16 | |
1921 | #define ZV0_CAPTURE_CLIP_YCLIP 25:16 | |
1922 | #define ZV0_CAPTURE_CLIP_XCLIP 9:0 | |
1923 | ||
1924 | #define ZV0_CAPTURE_SIZE 0x090008 | |
1925 | #define ZV0_CAPTURE_SIZE_HEIGHT 26:16 | |
1926 | #define ZV0_CAPTURE_SIZE_WIDTH 10:0 | |
1927 | ||
1928 | #define ZV0_CAPTURE_BUF0_ADDRESS 0x09000C | |
1929 | #define ZV0_CAPTURE_BUF0_ADDRESS_STATUS 31:31 | |
1930 | #define ZV0_CAPTURE_BUF0_ADDRESS_STATUS_CURRENT 0 | |
1931 | #define ZV0_CAPTURE_BUF0_ADDRESS_STATUS_PENDING 1 | |
1932 | #define ZV0_CAPTURE_BUF0_ADDRESS_EXT 27:27 | |
1933 | #define ZV0_CAPTURE_BUF0_ADDRESS_EXT_LOCAL 0 | |
1934 | #define ZV0_CAPTURE_BUF0_ADDRESS_EXT_EXTERNAL 1 | |
1935 | #define ZV0_CAPTURE_BUF0_ADDRESS_CS 26:26 | |
1936 | #define ZV0_CAPTURE_BUF0_ADDRESS_CS_0 0 | |
1937 | #define ZV0_CAPTURE_BUF0_ADDRESS_CS_1 1 | |
1938 | #define ZV0_CAPTURE_BUF0_ADDRESS_ADDRESS 25:0 | |
1939 | ||
1940 | #define ZV0_CAPTURE_BUF1_ADDRESS 0x090010 | |
1941 | #define ZV0_CAPTURE_BUF1_ADDRESS_STATUS 31:31 | |
1942 | #define ZV0_CAPTURE_BUF1_ADDRESS_STATUS_CURRENT 0 | |
1943 | #define ZV0_CAPTURE_BUF1_ADDRESS_STATUS_PENDING 1 | |
1944 | #define ZV0_CAPTURE_BUF1_ADDRESS_EXT 27:27 | |
1945 | #define ZV0_CAPTURE_BUF1_ADDRESS_EXT_LOCAL 0 | |
1946 | #define ZV0_CAPTURE_BUF1_ADDRESS_EXT_EXTERNAL 1 | |
1947 | #define ZV0_CAPTURE_BUF1_ADDRESS_CS 26:26 | |
1948 | #define ZV0_CAPTURE_BUF1_ADDRESS_CS_0 0 | |
1949 | #define ZV0_CAPTURE_BUF1_ADDRESS_CS_1 1 | |
1950 | #define ZV0_CAPTURE_BUF1_ADDRESS_ADDRESS 25:0 | |
1951 | ||
1952 | #define ZV0_CAPTURE_BUF_OFFSET 0x090014 | |
1953 | #ifndef VALIDATION_CHIP | |
1954 | #define ZV0_CAPTURE_BUF_OFFSET_YCLIP_ODD_FIELD 25:16 | |
1955 | #endif | |
1956 | #define ZV0_CAPTURE_BUF_OFFSET_OFFSET 15:0 | |
1957 | ||
1958 | #define ZV0_CAPTURE_FIFO_CTRL 0x090018 | |
1959 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO 2:0 | |
1960 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_0 0 | |
1961 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_1 1 | |
1962 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_2 2 | |
1963 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_3 3 | |
1964 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_4 4 | |
1965 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_5 5 | |
1966 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_6 6 | |
1967 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_7 7 | |
1968 | ||
1969 | #define ZV0_CAPTURE_YRGB_CONST 0x09001C | |
1970 | #define ZV0_CAPTURE_YRGB_CONST_Y 31:24 | |
1971 | #define ZV0_CAPTURE_YRGB_CONST_R 23:16 | |
1972 | #define ZV0_CAPTURE_YRGB_CONST_G 15:8 | |
1973 | #define ZV0_CAPTURE_YRGB_CONST_B 7:0 | |
1974 | ||
1975 | #define ZV0_CAPTURE_LINE_COMP 0x090020 | |
1976 | #define ZV0_CAPTURE_LINE_COMP_LC 10:0 | |
1977 | ||
1978 | /* ZV1 */ | |
1979 | ||
1980 | #define ZV1_CAPTURE_CTRL 0x098000 | |
1981 | #define ZV1_CAPTURE_CTRL_FIELD_INPUT 27:27 | |
1982 | #define ZV1_CAPTURE_CTRL_FIELD_INPUT_EVEN_FIELD 0 | |
1983 | #define ZV1_CAPTURE_CTRL_FIELD_INPUT_ODD_FIELD 0 | |
1984 | #define ZV1_CAPTURE_CTRL_SCAN 26:26 | |
1985 | #define ZV1_CAPTURE_CTRL_SCAN_PROGRESSIVE 0 | |
1986 | #define ZV1_CAPTURE_CTRL_SCAN_INTERLACE 1 | |
1987 | #define ZV1_CAPTURE_CTRL_CURRENT_BUFFER 25:25 | |
1988 | #define ZV1_CAPTURE_CTRL_CURRENT_BUFFER_0 0 | |
1989 | #define ZV1_CAPTURE_CTRL_CURRENT_BUFFER_1 1 | |
1990 | #define ZV1_CAPTURE_CTRL_VERTICAL_SYNC 24:24 | |
1991 | #define ZV1_CAPTURE_CTRL_VERTICAL_SYNC_INACTIVE 0 | |
1992 | #define ZV1_CAPTURE_CTRL_VERTICAL_SYNC_ACTIVE 1 | |
1993 | #define ZV1_CAPTURE_CTRL_PANEL 20:20 | |
1994 | #define ZV1_CAPTURE_CTRL_PANEL_DISABLE 0 | |
1995 | #define ZV1_CAPTURE_CTRL_PANEL_ENABLE 1 | |
1996 | #define ZV1_CAPTURE_CTRL_ADJ 19:19 | |
1997 | #define ZV1_CAPTURE_CTRL_ADJ_NORMAL 0 | |
1998 | #define ZV1_CAPTURE_CTRL_ADJ_DELAY 1 | |
1999 | #define ZV1_CAPTURE_CTRL_HA 18:18 | |
2000 | #define ZV1_CAPTURE_CTRL_HA_DISABLE 0 | |
2001 | #define ZV1_CAPTURE_CTRL_HA_ENABLE 1 | |
2002 | #define ZV1_CAPTURE_CTRL_VSK 17:17 | |
2003 | #define ZV1_CAPTURE_CTRL_VSK_DISABLE 0 | |
2004 | #define ZV1_CAPTURE_CTRL_VSK_ENABLE 1 | |
2005 | #define ZV1_CAPTURE_CTRL_HSK 16:16 | |
2006 | #define ZV1_CAPTURE_CTRL_HSK_DISABLE 0 | |
2007 | #define ZV1_CAPTURE_CTRL_HSK_ENABLE 1 | |
2008 | #define ZV1_CAPTURE_CTRL_FD 15:15 | |
2009 | #define ZV1_CAPTURE_CTRL_FD_RISING 0 | |
2010 | #define ZV1_CAPTURE_CTRL_FD_FALLING 1 | |
2011 | #define ZV1_CAPTURE_CTRL_VP 14:14 | |
2012 | #define ZV1_CAPTURE_CTRL_VP_HIGH 0 | |
2013 | #define ZV1_CAPTURE_CTRL_VP_LOW 1 | |
2014 | #define ZV1_CAPTURE_CTRL_HP 13:13 | |
2015 | #define ZV1_CAPTURE_CTRL_HP_HIGH 0 | |
2016 | #define ZV1_CAPTURE_CTRL_HP_LOW 1 | |
2017 | #define ZV1_CAPTURE_CTRL_CP 12:12 | |
2018 | #define ZV1_CAPTURE_CTRL_CP_HIGH 0 | |
2019 | #define ZV1_CAPTURE_CTRL_CP_LOW 1 | |
2020 | #define ZV1_CAPTURE_CTRL_UVS 11:11 | |
2021 | #define ZV1_CAPTURE_CTRL_UVS_DISABLE 0 | |
2022 | #define ZV1_CAPTURE_CTRL_UVS_ENABLE 1 | |
2023 | #define ZV1_CAPTURE_CTRL_BS 10:10 | |
2024 | #define ZV1_CAPTURE_CTRL_BS_DISABLE 0 | |
2025 | #define ZV1_CAPTURE_CTRL_BS_ENABLE 1 | |
2026 | #define ZV1_CAPTURE_CTRL_CS 9:9 | |
2027 | #define ZV1_CAPTURE_CTRL_CS_16 0 | |
2028 | #define ZV1_CAPTURE_CTRL_CS_8 1 | |
2029 | #define ZV1_CAPTURE_CTRL_CF 8:8 | |
2030 | #define ZV1_CAPTURE_CTRL_CF_YUV 0 | |
2031 | #define ZV1_CAPTURE_CTRL_CF_RGB 1 | |
2032 | #define ZV1_CAPTURE_CTRL_FS 7:7 | |
2033 | #define ZV1_CAPTURE_CTRL_FS_DISABLE 0 | |
2034 | #define ZV1_CAPTURE_CTRL_FS_ENABLE 1 | |
2035 | #define ZV1_CAPTURE_CTRL_WEAVE 6:6 | |
2036 | #define ZV1_CAPTURE_CTRL_WEAVE_DISABLE 0 | |
2037 | #define ZV1_CAPTURE_CTRL_WEAVE_ENABLE 1 | |
2038 | #define ZV1_CAPTURE_CTRL_BOB 5:5 | |
2039 | #define ZV1_CAPTURE_CTRL_BOB_DISABLE 0 | |
2040 | #define ZV1_CAPTURE_CTRL_BOB_ENABLE 1 | |
2041 | #define ZV1_CAPTURE_CTRL_DB 4:4 | |
2042 | #define ZV1_CAPTURE_CTRL_DB_DISABLE 0 | |
2043 | #define ZV1_CAPTURE_CTRL_DB_ENABLE 1 | |
2044 | #define ZV1_CAPTURE_CTRL_CC 3:3 | |
2045 | #define ZV1_CAPTURE_CTRL_CC_CONTINUE 0 | |
2046 | #define ZV1_CAPTURE_CTRL_CC_CONDITION 1 | |
2047 | #define ZV1_CAPTURE_CTRL_RGB 2:2 | |
2048 | #define ZV1_CAPTURE_CTRL_RGB_DISABLE 0 | |
2049 | #define ZV1_CAPTURE_CTRL_RGB_ENABLE 1 | |
2050 | #define ZV1_CAPTURE_CTRL_656 1:1 | |
2051 | #define ZV1_CAPTURE_CTRL_656_DISABLE 0 | |
2052 | #define ZV1_CAPTURE_CTRL_656_ENABLE 1 | |
2053 | #define ZV1_CAPTURE_CTRL_CAP 0:0 | |
2054 | #define ZV1_CAPTURE_CTRL_CAP_DISABLE 0 | |
2055 | #define ZV1_CAPTURE_CTRL_CAP_ENABLE 1 | |
2056 | ||
2057 | #define ZV1_CAPTURE_CLIP 0x098004 | |
2058 | #define ZV1_CAPTURE_CLIP_YCLIP 25:16 | |
2059 | #define ZV1_CAPTURE_CLIP_XCLIP 9:0 | |
2060 | ||
2061 | #define ZV1_CAPTURE_SIZE 0x098008 | |
2062 | #define ZV1_CAPTURE_SIZE_HEIGHT 26:16 | |
2063 | #define ZV1_CAPTURE_SIZE_WIDTH 10:0 | |
2064 | ||
2065 | #define ZV1_CAPTURE_BUF0_ADDRESS 0x09800C | |
2066 | #define ZV1_CAPTURE_BUF0_ADDRESS_STATUS 31:31 | |
2067 | #define ZV1_CAPTURE_BUF0_ADDRESS_STATUS_CURRENT 0 | |
2068 | #define ZV1_CAPTURE_BUF0_ADDRESS_STATUS_PENDING 1 | |
2069 | #define ZV1_CAPTURE_BUF0_ADDRESS_EXT 27:27 | |
2070 | #define ZV1_CAPTURE_BUF0_ADDRESS_EXT_LOCAL 0 | |
2071 | #define ZV1_CAPTURE_BUF0_ADDRESS_EXT_EXTERNAL 1 | |
2072 | #define ZV1_CAPTURE_BUF0_ADDRESS_CS 26:26 | |
2073 | #define ZV1_CAPTURE_BUF0_ADDRESS_CS_0 0 | |
2074 | #define ZV1_CAPTURE_BUF0_ADDRESS_CS_1 1 | |
2075 | #define ZV1_CAPTURE_BUF0_ADDRESS_ADDRESS 25:0 | |
2076 | ||
2077 | #define ZV1_CAPTURE_BUF1_ADDRESS 0x098010 | |
2078 | #define ZV1_CAPTURE_BUF1_ADDRESS_STATUS 31:31 | |
2079 | #define ZV1_CAPTURE_BUF1_ADDRESS_STATUS_CURRENT 0 | |
2080 | #define ZV1_CAPTURE_BUF1_ADDRESS_STATUS_PENDING 1 | |
2081 | #define ZV1_CAPTURE_BUF1_ADDRESS_EXT 27:27 | |
2082 | #define ZV1_CAPTURE_BUF1_ADDRESS_EXT_LOCAL 0 | |
2083 | #define ZV1_CAPTURE_BUF1_ADDRESS_EXT_EXTERNAL 1 | |
2084 | #define ZV1_CAPTURE_BUF1_ADDRESS_CS 26:26 | |
2085 | #define ZV1_CAPTURE_BUF1_ADDRESS_CS_0 0 | |
2086 | #define ZV1_CAPTURE_BUF1_ADDRESS_CS_1 1 | |
2087 | #define ZV1_CAPTURE_BUF1_ADDRESS_ADDRESS 25:0 | |
2088 | ||
2089 | #define ZV1_CAPTURE_BUF_OFFSET 0x098014 | |
2090 | #define ZV1_CAPTURE_BUF_OFFSET_OFFSET 15:0 | |
2091 | ||
2092 | #define ZV1_CAPTURE_FIFO_CTRL 0x098018 | |
2093 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO 2:0 | |
2094 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_0 0 | |
2095 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_1 1 | |
2096 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_2 2 | |
2097 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_3 3 | |
2098 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_4 4 | |
2099 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_5 5 | |
2100 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_6 6 | |
2101 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_7 7 | |
2102 | ||
2103 | #define ZV1_CAPTURE_YRGB_CONST 0x09801C | |
2104 | #define ZV1_CAPTURE_YRGB_CONST_Y 31:24 | |
2105 | #define ZV1_CAPTURE_YRGB_CONST_R 23:16 | |
2106 | #define ZV1_CAPTURE_YRGB_CONST_G 15:8 | |
2107 | #define ZV1_CAPTURE_YRGB_CONST_B 7:0 | |
2108 | ||
2109 | #define DMA_1_SOURCE 0x0D0010 | |
2110 | #define DMA_1_SOURCE_ADDRESS_EXT 27:27 | |
2111 | #define DMA_1_SOURCE_ADDRESS_EXT_LOCAL 0 | |
2112 | #define DMA_1_SOURCE_ADDRESS_EXT_EXTERNAL 1 | |
2113 | #define DMA_1_SOURCE_ADDRESS_CS 26:26 | |
2114 | #define DMA_1_SOURCE_ADDRESS_CS_0 0 | |
2115 | #define DMA_1_SOURCE_ADDRESS_CS_1 1 | |
2116 | #define DMA_1_SOURCE_ADDRESS 25:0 | |
2117 | ||
2118 | #define DMA_1_DESTINATION 0x0D0014 | |
2119 | #define DMA_1_DESTINATION_ADDRESS_EXT 27:27 | |
2120 | #define DMA_1_DESTINATION_ADDRESS_EXT_LOCAL 0 | |
2121 | #define DMA_1_DESTINATION_ADDRESS_EXT_EXTERNAL 1 | |
2122 | #define DMA_1_DESTINATION_ADDRESS_CS 26:26 | |
2123 | #define DMA_1_DESTINATION_ADDRESS_CS_0 0 | |
2124 | #define DMA_1_DESTINATION_ADDRESS_CS_1 1 | |
2125 | #define DMA_1_DESTINATION_ADDRESS 25:0 | |
2126 | ||
2127 | #define DMA_1_SIZE_CONTROL 0x0D0018 | |
2128 | #define DMA_1_SIZE_CONTROL_STATUS 31:31 | |
2129 | #define DMA_1_SIZE_CONTROL_STATUS_IDLE 0 | |
2130 | #define DMA_1_SIZE_CONTROL_STATUS_ACTIVE 1 | |
2131 | #define DMA_1_SIZE_CONTROL_SIZE 23:0 | |
2132 | ||
2133 | #define DMA_ABORT_INTERRUPT 0x0D0020 | |
2134 | #define DMA_ABORT_INTERRUPT_ABORT_1 5:5 | |
2135 | #define DMA_ABORT_INTERRUPT_ABORT_1_ENABLE 0 | |
2136 | #define DMA_ABORT_INTERRUPT_ABORT_1_ABORT 1 | |
2137 | #define DMA_ABORT_INTERRUPT_ABORT_0 4:4 | |
2138 | #define DMA_ABORT_INTERRUPT_ABORT_0_ENABLE 0 | |
2139 | #define DMA_ABORT_INTERRUPT_ABORT_0_ABORT 1 | |
2140 | #define DMA_ABORT_INTERRUPT_INT_1 1:1 | |
2141 | #define DMA_ABORT_INTERRUPT_INT_1_CLEAR 0 | |
2142 | #define DMA_ABORT_INTERRUPT_INT_1_FINISHED 1 | |
2143 | #define DMA_ABORT_INTERRUPT_INT_0 0:0 | |
2144 | #define DMA_ABORT_INTERRUPT_INT_0_CLEAR 0 | |
2145 | #define DMA_ABORT_INTERRUPT_INT_0_FINISHED 1 | |
2146 | ||
2147 | ||
2148 | ||
2149 | ||
2150 | ||
2151 | /* Default i2c CLK and Data GPIO. These are the default i2c pins */ | |
2152 | #define DEFAULT_I2C_SCL 30 | |
2153 | #define DEFAULT_I2C_SDA 31 | |
2154 | ||
2155 | ||
2156 | #define GPIO_DATA_SM750LE 0x020018 | |
2157 | #define GPIO_DATA_SM750LE_1 1:1 | |
2158 | #define GPIO_DATA_SM750LE_0 0:0 | |
2159 | ||
2160 | #define GPIO_DATA_DIRECTION_SM750LE 0x02001C | |
2161 | #define GPIO_DATA_DIRECTION_SM750LE_1 1:1 | |
2162 | #define GPIO_DATA_DIRECTION_SM750LE_1_INPUT 0 | |
2163 | #define GPIO_DATA_DIRECTION_SM750LE_1_OUTPUT 1 | |
2164 | #define GPIO_DATA_DIRECTION_SM750LE_0 0:0 | |
2165 | #define GPIO_DATA_DIRECTION_SM750LE_0_INPUT 0 | |
2166 | #define GPIO_DATA_DIRECTION_SM750LE_0_OUTPUT 1 | |
2167 | ||
2168 | ||
2169 | #endif |