projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 81dee67e SM |
1 | #ifndef DDK750_REG_H__ |
| 2 | #define DDK750_REG_H__ | |
| 3 | ||
| 4 | /* New register for SM750LE */ | |
| 5 | #define DE_STATE1 0x100054 | |
| c808d6ce | 6 | #define DE_STATE1_DE_ABORT BIT(0) |
| 81dee67e SM |
7 | |
| 8 | #define DE_STATE2 0x100058 | |
| ae6061db MR |
9 | #define DE_STATE2_DE_FIFO_EMPTY BIT(3) |
| 10 | #define DE_STATE2_DE_STATUS_BUSY BIT(2) | |
| 11 | #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1) | |
| 81dee67e SM |
12 | |
| 13 | #define SYSTEM_CTRL 0x000000 | |
| a8856ff8 MR |
14 | #define SYSTEM_CTRL_DPMS_MASK (0x3 << 30) |
| 15 | #define SYSTEM_CTRL_DPMS_VPHP (0x0 << 30) | |
| 16 | #define SYSTEM_CTRL_DPMS_VPHN (0x1 << 30) | |
| 17 | #define SYSTEM_CTRL_DPMS_VNHP (0x2 << 30) | |
| 18 | #define SYSTEM_CTRL_DPMS_VNHN (0x3 << 30) | |
| 410c756d MR |
19 | #define SYSTEM_CTRL_PCI_BURST BIT(29) |
| 20 | #define SYSTEM_CTRL_PCI_MASTER BIT(25) | |
| 21 | #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24) | |
| 22 | #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23) | |
| 23 | #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22) | |
| 24 | #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21) | |
| 25 | #define SYSTEM_CTRL_CSC_STATUS_BUSY BIT(20) | |
| 26 | #define SYSTEM_CTRL_CRT_VSYNC_ACTIVE BIT(19) | |
| 27 | #define SYSTEM_CTRL_PANEL_VSYNC_ACTIVE BIT(18) | |
| 28 | #define SYSTEM_CTRL_CURRENT_BUFFER_FLIP_PENDING BIT(17) | |
| 29 | #define SYSTEM_CTRL_DMA_STATUS_BUSY BIT(16) | |
| 30 | #define SYSTEM_CTRL_PCI_BURST_READ BIT(15) | |
| 31 | #define SYSTEM_CTRL_DE_ABORT BIT(13) | |
| 32 | #define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK BIT(11) | |
| 33 | #define SYSTEM_CTRL_PCI_RETRY_OFF BIT(7) | |
| a8856ff8 MR |
34 | #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_MASK (0x3 << 4) |
| 35 | #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1 (0x0 << 4) | |
| 36 | #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2 (0x1 << 4) | |
| 37 | #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4 (0x2 << 4) | |
| 38 | #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8 (0x3 << 4) | |
| 410c756d MR |
39 | #define SYSTEM_CTRL_CRT_TRISTATE BIT(3) |
| 40 | #define SYSTEM_CTRL_PCIMEM_TRISTATE BIT(2) | |
| 41 | #define SYSTEM_CTRL_LOCALMEM_TRISTATE BIT(1) | |
| 42 | #define SYSTEM_CTRL_PANEL_TRISTATE BIT(0) | |
| 81dee67e SM |
43 | |
| 44 | #define MISC_CTRL 0x000004 | |
| 5372350b | 45 | #define MISC_CTRL_DRAM_RERESH_COUNT BIT(27) |
| 5538d5c8 MR |
46 | #define MISC_CTRL_DRAM_REFRESH_TIME_MASK (0x3 << 25) |
| 47 | #define MISC_CTRL_DRAM_REFRESH_TIME_8 (0x0 << 25) | |
| 48 | #define MISC_CTRL_DRAM_REFRESH_TIME_16 (0x1 << 25) | |
| 49 | #define MISC_CTRL_DRAM_REFRESH_TIME_32 (0x2 << 25) | |
| 50 | #define MISC_CTRL_DRAM_REFRESH_TIME_64 (0x3 << 25) | |
| 5372350b MR |
51 | #define MISC_CTRL_INT_OUTPUT_INVERT BIT(24) |
| 52 | #define MISC_CTRL_PLL_CLK_COUNT BIT(23) | |
| 53 | #define MISC_CTRL_DAC_POWER_OFF BIT(20) | |
| 54 | #define MISC_CTRL_CLK_SELECT_TESTCLK BIT(16) | |
| 5538d5c8 MR |
55 | #define MISC_CTRL_DRAM_COLUMN_SIZE_MASK (0x3 << 14) |
| 56 | #define MISC_CTRL_DRAM_COLUMN_SIZE_256 (0x0 << 14) | |
| 57 | #define MISC_CTRL_DRAM_COLUMN_SIZE_512 (0x1 << 14) | |
| 58 | #define MISC_CTRL_DRAM_COLUMN_SIZE_1024 (0x2 << 14) | |
| 59 | #define MISC_CTRL_LOCALMEM_SIZE_MASK (0x3 << 12) | |
| 60 | #define MISC_CTRL_LOCALMEM_SIZE_8M (0x3 << 12) | |
| 61 | #define MISC_CTRL_LOCALMEM_SIZE_16M (0x0 << 12) | |
| 62 | #define MISC_CTRL_LOCALMEM_SIZE_32M (0x1 << 12) | |
| 63 | #define MISC_CTRL_LOCALMEM_SIZE_64M (0x2 << 12) | |
| 5372350b MR |
64 | #define MISC_CTRL_DRAM_TWTR BIT(11) |
| 65 | #define MISC_CTRL_DRAM_TWR BIT(10) | |
| 66 | #define MISC_CTRL_DRAM_TRP BIT(9) | |
| 67 | #define MISC_CTRL_DRAM_TRFC BIT(8) | |
| 68 | #define MISC_CTRL_DRAM_TRAS BIT(7) | |
| 69 | #define MISC_CTRL_LOCALMEM_RESET BIT(6) | |
| 70 | #define MISC_CTRL_LOCALMEM_STATE_INACTIVE BIT(5) | |
| 71 | #define MISC_CTRL_CPU_CAS_LATENCY BIT(4) | |
| 72 | #define MISC_CTRL_DLL_OFF BIT(3) | |
| 73 | #define MISC_CTRL_DRAM_OUTPUT_HIGH BIT(2) | |
| 74 | #define MISC_CTRL_LOCALMEM_BUS_SIZE BIT(1) | |
| 75 | #define MISC_CTRL_EMBEDDED_LOCALMEM_OFF BIT(0) | |
| 81dee67e SM |
76 | |
| 77 | #define GPIO_MUX 0x000008 | |
| 2a5149e0 MR |
78 | #define GPIO_MUX_31 BIT(31) |
| 79 | #define GPIO_MUX_30 BIT(30) | |
| 80 | #define GPIO_MUX_29 BIT(29) | |
| 81 | #define GPIO_MUX_28 BIT(28) | |
| 82 | #define GPIO_MUX_27 BIT(27) | |
| 83 | #define GPIO_MUX_26 BIT(26) | |
| 84 | #define GPIO_MUX_25 BIT(25) | |
| 85 | #define GPIO_MUX_24 BIT(24) | |
| 86 | #define GPIO_MUX_23 BIT(23) | |
| 87 | #define GPIO_MUX_22 BIT(22) | |
| 88 | #define GPIO_MUX_21 BIT(21) | |
| 89 | #define GPIO_MUX_20 BIT(20) | |
| 90 | #define GPIO_MUX_19 BIT(19) | |
| 91 | #define GPIO_MUX_18 BIT(18) | |
| 92 | #define GPIO_MUX_17 BIT(17) | |
| 93 | #define GPIO_MUX_16 BIT(16) | |
| 94 | #define GPIO_MUX_15 BIT(15) | |
| 95 | #define GPIO_MUX_14 BIT(14) | |
| 96 | #define GPIO_MUX_13 BIT(13) | |
| 97 | #define GPIO_MUX_12 BIT(12) | |
| 98 | #define GPIO_MUX_11 BIT(11) | |
| 99 | #define GPIO_MUX_10 BIT(10) | |
| 100 | #define GPIO_MUX_9 BIT(9) | |
| 101 | #define GPIO_MUX_8 BIT(8) | |
| 102 | #define GPIO_MUX_7 BIT(7) | |
| 103 | #define GPIO_MUX_6 BIT(6) | |
| 104 | #define GPIO_MUX_5 BIT(5) | |
| 105 | #define GPIO_MUX_4 BIT(4) | |
| 106 | #define GPIO_MUX_3 BIT(3) | |
| 107 | #define GPIO_MUX_2 BIT(2) | |
| 108 | #define GPIO_MUX_1 BIT(1) | |
| 109 | #define GPIO_MUX_0 BIT(0) | |
| 81dee67e SM |
110 | |
| 111 | #define LOCALMEM_ARBITRATION 0x00000C | |
| 10dfcb06 | 112 | #define LOCALMEM_ARBITRATION_ROTATE BIT(28) |
| 0d5d733b MR |
113 | #define LOCALMEM_ARBITRATION_VGA_MASK (0x7 << 24) |
| 114 | #define LOCALMEM_ARBITRATION_VGA_OFF (0x0 << 24) | |
| 115 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_1 (0x1 << 24) | |
| 116 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_2 (0x2 << 24) | |
| 117 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_3 (0x3 << 24) | |
| 118 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_4 (0x4 << 24) | |
| 119 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_5 (0x5 << 24) | |
| 120 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_6 (0x6 << 24) | |
| 121 | #define LOCALMEM_ARBITRATION_VGA_PRIORITY_7 (0x7 << 24) | |
| 122 | #define LOCALMEM_ARBITRATION_DMA_MASK (0x7 << 20) | |
| 123 | #define LOCALMEM_ARBITRATION_DMA_OFF (0x0 << 20) | |
| 124 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_1 (0x1 << 20) | |
| 125 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_2 (0x2 << 20) | |
| 126 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_3 (0x3 << 20) | |
| 127 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_4 (0x4 << 20) | |
| 128 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_5 (0x5 << 20) | |
| 129 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_6 (0x6 << 20) | |
| 130 | #define LOCALMEM_ARBITRATION_DMA_PRIORITY_7 (0x7 << 20) | |
| 131 | #define LOCALMEM_ARBITRATION_ZVPORT1_MASK (0x7 << 16) | |
| 132 | #define LOCALMEM_ARBITRATION_ZVPORT1_OFF (0x0 << 16) | |
| 133 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_1 (0x1 << 16) | |
| 134 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_2 (0x2 << 16) | |
| 135 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_3 (0x3 << 16) | |
| 136 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_4 (0x4 << 16) | |
| 137 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_5 (0x5 << 16) | |
| 138 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_6 (0x6 << 16) | |
| 139 | #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_7 (0x7 << 16) | |
| 140 | #define LOCALMEM_ARBITRATION_ZVPORT0_MASK (0x7 << 12) | |
| 141 | #define LOCALMEM_ARBITRATION_ZVPORT0_OFF (0x0 << 12) | |
| 142 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_1 (0x1 << 12) | |
| 143 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_2 (0x2 << 12) | |
| 144 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_3 (0x3 << 12) | |
| 145 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_4 (0x4 << 12) | |
| 146 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_5 (0x5 << 12) | |
| 147 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_6 (0x6 << 12) | |
| 148 | #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_7 (0x7 << 12) | |
| 149 | #define LOCALMEM_ARBITRATION_VIDEO_MASK (0x7 << 8) | |
| 150 | #define LOCALMEM_ARBITRATION_VIDEO_OFF (0x0 << 8) | |
| 151 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_1 (0x1 << 8) | |
| 152 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_2 (0x2 << 8) | |
| 153 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_3 (0x3 << 8) | |
| 154 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_4 (0x4 << 8) | |
| 155 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_5 (0x5 << 8) | |
| 156 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_6 (0x6 << 8) | |
| 157 | #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_7 (0x7 << 8) | |
| 158 | #define LOCALMEM_ARBITRATION_PANEL_MASK (0x7 << 4) | |
| 159 | #define LOCALMEM_ARBITRATION_PANEL_OFF (0x0 << 4) | |
| 160 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_1 (0x1 << 4) | |
| 161 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_2 (0x2 << 4) | |
| 162 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_3 (0x3 << 4) | |
| 163 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_4 (0x4 << 4) | |
| 164 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_5 (0x5 << 4) | |
| 165 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_6 (0x6 << 4) | |
| 166 | #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_7 (0x7 << 4) | |
| 167 | #define LOCALMEM_ARBITRATION_CRT_MASK 0x7 | |
| 168 | #define LOCALMEM_ARBITRATION_CRT_OFF 0x0 | |
| 169 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_1 0x1 | |
| 170 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_2 0x2 | |
| 171 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_3 0x3 | |
| 172 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_4 0x4 | |
| 173 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_5 0x5 | |
| 174 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_6 0x6 | |
| 175 | #define LOCALMEM_ARBITRATION_CRT_PRIORITY_7 0x7 | |
| 81dee67e SM |
176 | |
| 177 | #define PCIMEM_ARBITRATION 0x000010 | |
| 10dfcb06 | 178 | #define PCIMEM_ARBITRATION_ROTATE BIT(28) |
| 0d5d733b MR |
179 | #define PCIMEM_ARBITRATION_VGA_MASK (0x7 << 24) |
| 180 | #define PCIMEM_ARBITRATION_VGA_OFF (0x0 << 24) | |
| 181 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_1 (0x1 << 24) | |
| 182 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_2 (0x2 << 24) | |
| 183 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_3 (0x3 << 24) | |
| 184 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_4 (0x4 << 24) | |
| 185 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_5 (0x5 << 24) | |
| 186 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_6 (0x6 << 24) | |
| 187 | #define PCIMEM_ARBITRATION_VGA_PRIORITY_7 (0x7 << 24) | |
| 188 | #define PCIMEM_ARBITRATION_DMA_MASK (0x7 << 20) | |
| 189 | #define PCIMEM_ARBITRATION_DMA_OFF (0x0 << 20) | |
| 190 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_1 (0x1 << 20) | |
| 191 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_2 (0x2 << 20) | |
| 192 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_3 (0x3 << 20) | |
| 193 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_4 (0x4 << 20) | |
| 194 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_5 (0x5 << 20) | |
| 195 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_6 (0x6 << 20) | |
| 196 | #define PCIMEM_ARBITRATION_DMA_PRIORITY_7 (0x7 << 20) | |
| 197 | #define PCIMEM_ARBITRATION_ZVPORT1_MASK (0x7 << 16) | |
| 198 | #define PCIMEM_ARBITRATION_ZVPORT1_OFF (0x0 << 16) | |
| 199 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_1 (0x1 << 16) | |
| 200 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_2 (0x2 << 16) | |
| 201 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_3 (0x3 << 16) | |
| 202 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_4 (0x4 << 16) | |
| 203 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_5 (0x5 << 16) | |
| 204 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_6 (0x6 << 16) | |
| 205 | #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_7 (0x7 << 16) | |
| 206 | #define PCIMEM_ARBITRATION_ZVPORT0_MASK (0x7 << 12) | |
| 207 | #define PCIMEM_ARBITRATION_ZVPORT0_OFF (0x0 << 12) | |
| 208 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_1 (0x1 << 12) | |
| 209 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_2 (0x2 << 12) | |
| 210 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_3 (0x3 << 12) | |
| 211 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_4 (0x4 << 12) | |
| 212 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_5 (0x5 << 12) | |
| 213 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_6 (0x6 << 12) | |
| 214 | #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_7 (0x7 << 12) | |
| 215 | #define PCIMEM_ARBITRATION_VIDEO_MASK (0x7 << 8) | |
| 216 | #define PCIMEM_ARBITRATION_VIDEO_OFF (0x0 << 8) | |
| 217 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_1 (0x1 << 8) | |
| 218 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_2 (0x2 << 8) | |
| 219 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_3 (0x3 << 8) | |
| 220 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_4 (0x4 << 8) | |
| 221 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_5 (0x5 << 8) | |
| 222 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_6 (0x6 << 8) | |
| 223 | #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_7 (0x7 << 8) | |
| 224 | #define PCIMEM_ARBITRATION_PANEL_MASK (0x7 << 4) | |
| 225 | #define PCIMEM_ARBITRATION_PANEL_OFF (0x0 << 4) | |
| 226 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_1 (0x1 << 4) | |
| 227 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_2 (0x2 << 4) | |
| 228 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_3 (0x3 << 4) | |
| 229 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_4 (0x4 << 4) | |
| 230 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_5 (0x5 << 4) | |
| 231 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_6 (0x6 << 4) | |
| 232 | #define PCIMEM_ARBITRATION_PANEL_PRIORITY_7 (0x7 << 4) | |
| 233 | #define PCIMEM_ARBITRATION_CRT_MASK 0x7 | |
| 234 | #define PCIMEM_ARBITRATION_CRT_OFF 0x0 | |
| 235 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_1 0x1 | |
| 236 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_2 0x2 | |
| 237 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_3 0x3 | |
| 238 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_4 0x4 | |
| 239 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_5 0x5 | |
| 240 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_6 0x6 | |
| 241 | #define PCIMEM_ARBITRATION_CRT_PRIORITY_7 0x7 | |
| 81dee67e SM |
242 | |
| 243 | #define RAW_INT 0x000020 | |
| 10dfcb06 MR |
244 | #define RAW_INT_ZVPORT1_VSYNC BIT(4) |
| 245 | #define RAW_INT_ZVPORT0_VSYNC BIT(3) | |
| 246 | #define RAW_INT_CRT_VSYNC BIT(2) | |
| 247 | #define RAW_INT_PANEL_VSYNC BIT(1) | |
| 248 | #define RAW_INT_VGA_VSYNC BIT(0) | |
| 81dee67e SM |
249 | |
| 250 | #define INT_STATUS 0x000024 | |
| 10dfcb06 MR |
251 | #define INT_STATUS_GPIO31 BIT(31) |
| 252 | #define INT_STATUS_GPIO30 BIT(30) | |
| 253 | #define INT_STATUS_GPIO29 BIT(29) | |
| 254 | #define INT_STATUS_GPIO28 BIT(28) | |
| 255 | #define INT_STATUS_GPIO27 BIT(27) | |
| 256 | #define INT_STATUS_GPIO26 BIT(26) | |
| 257 | #define INT_STATUS_GPIO25 BIT(25) | |
| 258 | #define INT_STATUS_I2C BIT(12) | |
| 259 | #define INT_STATUS_PWM BIT(11) | |
| 260 | #define INT_STATUS_DMA1 BIT(10) | |
| 261 | #define INT_STATUS_DMA0 BIT(9) | |
| 262 | #define INT_STATUS_PCI BIT(8) | |
| 263 | #define INT_STATUS_SSP1 BIT(7) | |
| 264 | #define INT_STATUS_SSP0 BIT(6) | |
| 265 | #define INT_STATUS_DE BIT(5) | |
| 266 | #define INT_STATUS_ZVPORT1_VSYNC BIT(4) | |
| 267 | #define INT_STATUS_ZVPORT0_VSYNC BIT(3) | |
| 268 | #define INT_STATUS_CRT_VSYNC BIT(2) | |
| 269 | #define INT_STATUS_PANEL_VSYNC BIT(1) | |
| 270 | #define INT_STATUS_VGA_VSYNC BIT(0) | |
| 81dee67e SM |
271 | |
| 272 | #define INT_MASK 0x000028 | |
| 10dfcb06 MR |
273 | #define INT_MASK_GPIO31 BIT(31) |
| 274 | #define INT_MASK_GPIO30 BIT(30) | |
| 275 | #define INT_MASK_GPIO29 BIT(29) | |
| 276 | #define INT_MASK_GPIO28 BIT(28) | |
| 277 | #define INT_MASK_GPIO27 BIT(27) | |
| 278 | #define INT_MASK_GPIO26 BIT(26) | |
| 279 | #define INT_MASK_GPIO25 BIT(25) | |
| 280 | #define INT_MASK_I2C BIT(12) | |
| 281 | #define INT_MASK_PWM BIT(11) | |
| 282 | #define INT_MASK_DMA1 BIT(10) | |
| 283 | #define INT_MASK_DMA BIT(9) | |
| 284 | #define INT_MASK_PCI BIT(8) | |
| 285 | #define INT_MASK_SSP1 BIT(7) | |
| 286 | #define INT_MASK_SSP0 BIT(6) | |
| 287 | #define INT_MASK_DE BIT(5) | |
| 288 | #define INT_MASK_ZVPORT1_VSYNC BIT(4) | |
| 289 | #define INT_MASK_ZVPORT0_VSYNC BIT(3) | |
| 290 | #define INT_MASK_CRT_VSYNC BIT(2) | |
| 291 | #define INT_MASK_PANEL_VSYNC BIT(1) | |
| 292 | #define INT_MASK_VGA_VSYNC BIT(0) | |
| 81dee67e SM |
293 | |
| 294 | #define CURRENT_GATE 0x000040 | |
| 6e8aa4a1 | 295 | #define CURRENT_GATE_MCLK_MASK (0x3 << 14) |
| 81dee67e | 296 | #ifdef VALIDATION_CHIP |
| 6e8aa4a1 MR |
297 | #define CURRENT_GATE_MCLK_112MHZ (0x0 << 14) |
| 298 | #define CURRENT_GATE_MCLK_84MHZ (0x1 << 14) | |
| 299 | #define CURRENT_GATE_MCLK_56MHZ (0x2 << 14) | |
| 300 | #define CURRENT_GATE_MCLK_42MHZ (0x3 << 14) | |
| 81dee67e | 301 | #else |
| 6e8aa4a1 MR |
302 | #define CURRENT_GATE_MCLK_DIV_3 (0x0 << 14) |
| 303 | #define CURRENT_GATE_MCLK_DIV_4 (0x1 << 14) | |
| 304 | #define CURRENT_GATE_MCLK_DIV_6 (0x2 << 14) | |
| 305 | #define CURRENT_GATE_MCLK_DIV_8 (0x3 << 14) | |
| 81dee67e | 306 | #endif |
| 6e8aa4a1 | 307 | #define CURRENT_GATE_M2XCLK_MASK (0x3 << 12) |
| 81dee67e | 308 | #ifdef VALIDATION_CHIP |
| 6e8aa4a1 MR |
309 | #define CURRENT_GATE_M2XCLK_336MHZ (0x0 << 12) |
| 310 | #define CURRENT_GATE_M2XCLK_168MHZ (0x1 << 12) | |
| 311 | #define CURRENT_GATE_M2XCLK_112MHZ (0x2 << 12) | |
| 312 | #define CURRENT_GATE_M2XCLK_84MHZ (0x3 << 12) | |
| 81dee67e | 313 | #else |
| 6e8aa4a1 MR |
314 | #define CURRENT_GATE_M2XCLK_DIV_1 (0x0 << 12) |
| 315 | #define CURRENT_GATE_M2XCLK_DIV_2 (0x1 << 12) | |
| 316 | #define CURRENT_GATE_M2XCLK_DIV_3 (0x2 << 12) | |
| 317 | #define CURRENT_GATE_M2XCLK_DIV_4 (0x3 << 12) | |
| 81dee67e | 318 | #endif |
| 90946e52 MR |
319 | #define CURRENT_GATE_VGA BIT(10) |
| 320 | #define CURRENT_GATE_PWM BIT(9) | |
| 321 | #define CURRENT_GATE_I2C BIT(8) | |
| 322 | #define CURRENT_GATE_SSP BIT(7) | |
| 323 | #define CURRENT_GATE_GPIO BIT(6) | |
| 324 | #define CURRENT_GATE_ZVPORT BIT(5) | |
| 325 | #define CURRENT_GATE_CSC BIT(4) | |
| 326 | #define CURRENT_GATE_DE BIT(3) | |
| 327 | #define CURRENT_GATE_DISPLAY BIT(2) | |
| 328 | #define CURRENT_GATE_LOCALMEM BIT(1) | |
| 329 | #define CURRENT_GATE_DMA BIT(0) | |
| 81dee67e SM |
330 | |
| 331 | #define MODE0_GATE 0x000044 | |
| a9412451 MR |
332 | #define MODE0_GATE_MCLK_MASK (0x3 << 14) |
| 333 | #define MODE0_GATE_MCLK_112MHZ (0x0 << 14) | |
| 334 | #define MODE0_GATE_MCLK_84MHZ (0x1 << 14) | |
| 335 | #define MODE0_GATE_MCLK_56MHZ (0x2 << 14) | |
| 336 | #define MODE0_GATE_MCLK_42MHZ (0x3 << 14) | |
| 337 | #define MODE0_GATE_M2XCLK_MASK (0x3 << 12) | |
| 338 | #define MODE0_GATE_M2XCLK_336MHZ (0x0 << 12) | |
| 339 | #define MODE0_GATE_M2XCLK_168MHZ (0x1 << 12) | |
| 340 | #define MODE0_GATE_M2XCLK_112MHZ (0x2 << 12) | |
| 341 | #define MODE0_GATE_M2XCLK_84MHZ (0x3 << 12) | |
| 05e9d9ea MR |
342 | #define MODE0_GATE_VGA BIT(10) |
| 343 | #define MODE0_GATE_PWM BIT(9) | |
| 344 | #define MODE0_GATE_I2C BIT(8) | |
| 345 | #define MODE0_GATE_SSP BIT(7) | |
| 346 | #define MODE0_GATE_GPIO BIT(6) | |
| 347 | #define MODE0_GATE_ZVPORT BIT(5) | |
| 348 | #define MODE0_GATE_CSC BIT(4) | |
| 349 | #define MODE0_GATE_DE BIT(3) | |
| 350 | #define MODE0_GATE_DISPLAY BIT(2) | |
| 351 | #define MODE0_GATE_LOCALMEM BIT(1) | |
| 352 | #define MODE0_GATE_DMA BIT(0) | |
| 81dee67e SM |
353 | |
| 354 | #define MODE1_GATE 0x000048 | |
| 0d5d733b MR |
355 | #define MODE1_GATE_MCLK_MASK (0x3 << 14) |
| 356 | #define MODE1_GATE_MCLK_112MHZ (0x0 << 14) | |
| 357 | #define MODE1_GATE_MCLK_84MHZ (0x1 << 14) | |
| 358 | #define MODE1_GATE_MCLK_56MHZ (0x2 << 14) | |
| 359 | #define MODE1_GATE_MCLK_42MHZ (0x3 << 14) | |
| 360 | #define MODE1_GATE_M2XCLK_MASK (0x3 << 12) | |
| 361 | #define MODE1_GATE_M2XCLK_336MHZ (0x0 << 12) | |
| 362 | #define MODE1_GATE_M2XCLK_168MHZ (0x1 << 12) | |
| 363 | #define MODE1_GATE_M2XCLK_112MHZ (0x2 << 12) | |
| 364 | #define MODE1_GATE_M2XCLK_84MHZ (0x3 << 12) | |
| 10dfcb06 MR |
365 | #define MODE1_GATE_VGA BIT(10) |
| 366 | #define MODE1_GATE_PWM BIT(9) | |
| 367 | #define MODE1_GATE_I2C BIT(8) | |
| 368 | #define MODE1_GATE_SSP BIT(7) | |
| 369 | #define MODE1_GATE_GPIO BIT(6) | |
| 370 | #define MODE1_GATE_ZVPORT BIT(5) | |
| 371 | #define MODE1_GATE_CSC BIT(4) | |
| 372 | #define MODE1_GATE_DE BIT(3) | |
| 373 | #define MODE1_GATE_DISPLAY BIT(2) | |
| 374 | #define MODE1_GATE_LOCALMEM BIT(1) | |
| 375 | #define MODE1_GATE_DMA BIT(0) | |
| 81dee67e SM |
376 | |
| 377 | #define POWER_MODE_CTRL 0x00004C | |
| 378 | #ifdef VALIDATION_CHIP | |
| 776980cf | 379 | #define POWER_MODE_CTRL_336CLK BIT(4) |
| 81dee67e | 380 | #endif |
| 776980cf MR |
381 | #define POWER_MODE_CTRL_OSC_INPUT BIT(3) |
| 382 | #define POWER_MODE_CTRL_ACPI BIT(2) | |
| f41b17fc MR |
383 | #define POWER_MODE_CTRL_MODE_MASK (0x3 << 0) |
| 384 | #define POWER_MODE_CTRL_MODE_MODE0 (0x0 << 0) | |
| 385 | #define POWER_MODE_CTRL_MODE_MODE1 (0x1 << 0) | |
| 386 | #define POWER_MODE_CTRL_MODE_SLEEP (0x2 << 0) | |
| 81dee67e SM |
387 | |
| 388 | #define PCI_MASTER_BASE 0x000050 | |
| 0d5d733b | 389 | #define PCI_MASTER_BASE_ADDRESS_MASK 0xff |
| 81dee67e SM |
390 | |
| 391 | #define DEVICE_ID 0x000054 | |
| 0d5d733b MR |
392 | #define DEVICE_ID_DEVICE_ID_MASK (0xffff << 16) |
| 393 | #define DEVICE_ID_REVISION_ID_MASK 0xff | |
| 81dee67e SM |
394 | |
| 395 | #define PLL_CLK_COUNT 0x000058 | |
| 0d5d733b | 396 | #define PLL_CLK_COUNT_COUNTER_MASK 0xffff |
| 81dee67e SM |
397 | |
| 398 | #define PANEL_PLL_CTRL 0x00005C | |
| 5557eb17 MR |
399 | #define PLL_CTRL_BYPASS BIT(18) |
| 400 | #define PLL_CTRL_POWER BIT(17) | |
| 401 | #define PLL_CTRL_INPUT BIT(16) | |
| 81dee67e | 402 | #ifdef VALIDATION_CHIP |
| cdd5df64 MR |
403 | #define PLL_CTRL_OD_SHIFT 14 |
| 404 | #define PLL_CTRL_OD_MASK (0x3 << 14) | |
| 81dee67e | 405 | #else |
| cdd5df64 MR |
406 | #define PLL_CTRL_POD_SHIFT 14 |
| 407 | #define PLL_CTRL_POD_MASK (0x3 << 14) | |
| 408 | #define PLL_CTRL_OD_SHIFT 12 | |
| 409 | #define PLL_CTRL_OD_MASK (0x3 << 12) | |
| 81dee67e | 410 | #endif |
| cdd5df64 MR |
411 | #define PLL_CTRL_N_SHIFT 8 |
| 412 | #define PLL_CTRL_N_MASK (0xf << 8) | |
| 413 | #define PLL_CTRL_M_SHIFT 0 | |
| 414 | #define PLL_CTRL_M_MASK 0xff | |
| 81dee67e SM |
415 | |
| 416 | #define CRT_PLL_CTRL 0x000060 | |
| 81dee67e SM |
417 | |
| 418 | #define VGA_PLL0_CTRL 0x000064 | |
| 81dee67e SM |
419 | |
| 420 | #define VGA_PLL1_CTRL 0x000068 | |
| 81dee67e SM |
421 | |
| 422 | #define SCRATCH_DATA 0x00006c | |
| 423 | ||
| 424 | #ifndef VALIDATION_CHIP | |
| 425 | ||
| 426 | #define MXCLK_PLL_CTRL 0x000070 | |
| 81dee67e SM |
427 | |
| 428 | #define VGA_CONFIGURATION 0x000088 | |
| e6f10d28 | 429 | #define VGA_CONFIGURATION_USER_DEFINE_MASK (0x3 << 4) |
| d9798143 MR |
430 | #define VGA_CONFIGURATION_PLL BIT(2) |
| 431 | #define VGA_CONFIGURATION_MODE BIT(1) | |
| 81dee67e SM |
432 | |
| 433 | #endif | |
| 434 | ||
| 435 | #define GPIO_DATA 0x010000 | |
| 10dfcb06 MR |
436 | #define GPIO_DATA_31 BIT(31) |
| 437 | #define GPIO_DATA_30 BIT(30) | |
| 438 | #define GPIO_DATA_29 BIT(29) | |
| 439 | #define GPIO_DATA_28 BIT(28) | |
| 440 | #define GPIO_DATA_27 BIT(27) | |
| 441 | #define GPIO_DATA_26 BIT(26) | |
| 442 | #define GPIO_DATA_25 BIT(25) | |
| 443 | #define GPIO_DATA_24 BIT(24) | |
| 444 | #define GPIO_DATA_23 BIT(23) | |
| 445 | #define GPIO_DATA_22 BIT(22) | |
| 446 | #define GPIO_DATA_21 BIT(21) | |
| 447 | #define GPIO_DATA_20 BIT(20) | |
| 448 | #define GPIO_DATA_19 BIT(19) | |
| 449 | #define GPIO_DATA_18 BIT(18) | |
| 450 | #define GPIO_DATA_17 BIT(17) | |
| 451 | #define GPIO_DATA_16 BIT(16) | |
| 452 | #define GPIO_DATA_15 BIT(15) | |
| 453 | #define GPIO_DATA_14 BIT(14) | |
| 454 | #define GPIO_DATA_13 BIT(13) | |
| 455 | #define GPIO_DATA_12 BIT(12) | |
| 456 | #define GPIO_DATA_11 BIT(11) | |
| 457 | #define GPIO_DATA_10 BIT(10) | |
| 458 | #define GPIO_DATA_9 BIT(9) | |
| 459 | #define GPIO_DATA_8 BIT(8) | |
| 460 | #define GPIO_DATA_7 BIT(7) | |
| 461 | #define GPIO_DATA_6 BIT(6) | |
| 462 | #define GPIO_DATA_5 BIT(5) | |
| 463 | #define GPIO_DATA_4 BIT(4) | |
| 464 | #define GPIO_DATA_3 BIT(3) | |
| 465 | #define GPIO_DATA_2 BIT(2) | |
| 466 | #define GPIO_DATA_1 BIT(1) | |
| 467 | #define GPIO_DATA_0 BIT(0) | |
| 81dee67e SM |
468 | |
| 469 | #define GPIO_DATA_DIRECTION 0x010004 | |
| 10dfcb06 MR |
470 | #define GPIO_DATA_DIRECTION_31 BIT(31) |
| 471 | #define GPIO_DATA_DIRECTION_30 BIT(30) | |
| 472 | #define GPIO_DATA_DIRECTION_29 BIT(29) | |
| 473 | #define GPIO_DATA_DIRECTION_28 BIT(28) | |
| 474 | #define GPIO_DATA_DIRECTION_27 BIT(27) | |
| 475 | #define GPIO_DATA_DIRECTION_26 BIT(26) | |
| 476 | #define GPIO_DATA_DIRECTION_25 BIT(25) | |
| 477 | #define GPIO_DATA_DIRECTION_24 BIT(24) | |
| 478 | #define GPIO_DATA_DIRECTION_23 BIT(23) | |
| 479 | #define GPIO_DATA_DIRECTION_22 BIT(22) | |
| 480 | #define GPIO_DATA_DIRECTION_21 BIT(21) | |
| 481 | #define GPIO_DATA_DIRECTION_20 BIT(20) | |
| 482 | #define GPIO_DATA_DIRECTION_19 BIT(19) | |
| 483 | #define GPIO_DATA_DIRECTION_18 BIT(18) | |
| 484 | #define GPIO_DATA_DIRECTION_17 BIT(17) | |
| 485 | #define GPIO_DATA_DIRECTION_16 BIT(16) | |
| 486 | #define GPIO_DATA_DIRECTION_15 BIT(15) | |
| 487 | #define GPIO_DATA_DIRECTION_14 BIT(14) | |
| 488 | #define GPIO_DATA_DIRECTION_13 BIT(13) | |
| 489 | #define GPIO_DATA_DIRECTION_12 BIT(12) | |
| 490 | #define GPIO_DATA_DIRECTION_11 BIT(11) | |
| 491 | #define GPIO_DATA_DIRECTION_10 BIT(10) | |
| 492 | #define GPIO_DATA_DIRECTION_9 BIT(9) | |
| 493 | #define GPIO_DATA_DIRECTION_8 BIT(8) | |
| 494 | #define GPIO_DATA_DIRECTION_7 BIT(7) | |
| 495 | #define GPIO_DATA_DIRECTION_6 BIT(6) | |
| 496 | #define GPIO_DATA_DIRECTION_5 BIT(5) | |
| 497 | #define GPIO_DATA_DIRECTION_4 BIT(4) | |
| 498 | #define GPIO_DATA_DIRECTION_3 BIT(3) | |
| 499 | #define GPIO_DATA_DIRECTION_2 BIT(2) | |
| 500 | #define GPIO_DATA_DIRECTION_1 BIT(1) | |
| 501 | #define GPIO_DATA_DIRECTION_0 BIT(0) | |
| 81dee67e SM |
502 | |
| 503 | #define GPIO_INTERRUPT_SETUP 0x010008 | |
| 10dfcb06 MR |
504 | #define GPIO_INTERRUPT_SETUP_TRIGGER_31 BIT(22) |
| 505 | #define GPIO_INTERRUPT_SETUP_TRIGGER_30 BIT(21) | |
| 506 | #define GPIO_INTERRUPT_SETUP_TRIGGER_29 BIT(20) | |
| 507 | #define GPIO_INTERRUPT_SETUP_TRIGGER_28 BIT(19) | |
| 508 | #define GPIO_INTERRUPT_SETUP_TRIGGER_27 BIT(18) | |
| 509 | #define GPIO_INTERRUPT_SETUP_TRIGGER_26 BIT(17) | |
| 510 | #define GPIO_INTERRUPT_SETUP_TRIGGER_25 BIT(16) | |
| 511 | #define GPIO_INTERRUPT_SETUP_ACTIVE_31 BIT(14) | |
| 512 | #define GPIO_INTERRUPT_SETUP_ACTIVE_30 BIT(13) | |
| 513 | #define GPIO_INTERRUPT_SETUP_ACTIVE_29 BIT(12) | |
| 514 | #define GPIO_INTERRUPT_SETUP_ACTIVE_28 BIT(11) | |
| 515 | #define GPIO_INTERRUPT_SETUP_ACTIVE_27 BIT(10) | |
| 516 | #define GPIO_INTERRUPT_SETUP_ACTIVE_26 BIT(9) | |
| 517 | #define GPIO_INTERRUPT_SETUP_ACTIVE_25 BIT(8) | |
| 518 | #define GPIO_INTERRUPT_SETUP_ENABLE_31 BIT(6) | |
| 519 | #define GPIO_INTERRUPT_SETUP_ENABLE_30 BIT(5) | |
| 520 | #define GPIO_INTERRUPT_SETUP_ENABLE_29 BIT(4) | |
| 521 | #define GPIO_INTERRUPT_SETUP_ENABLE_28 BIT(3) | |
| 522 | #define GPIO_INTERRUPT_SETUP_ENABLE_27 BIT(2) | |
| 523 | #define GPIO_INTERRUPT_SETUP_ENABLE_26 BIT(1) | |
| 524 | #define GPIO_INTERRUPT_SETUP_ENABLE_25 BIT(0) | |
| 81dee67e SM |
525 | |
| 526 | #define GPIO_INTERRUPT_STATUS 0x01000C | |
| 10dfcb06 MR |
527 | #define GPIO_INTERRUPT_STATUS_31 BIT(22) |
| 528 | #define GPIO_INTERRUPT_STATUS_30 BIT(21) | |
| 529 | #define GPIO_INTERRUPT_STATUS_29 BIT(20) | |
| 530 | #define GPIO_INTERRUPT_STATUS_28 BIT(19) | |
| 531 | #define GPIO_INTERRUPT_STATUS_27 BIT(18) | |
| 532 | #define GPIO_INTERRUPT_STATUS_26 BIT(17) | |
| 533 | #define GPIO_INTERRUPT_STATUS_25 BIT(16) | |
| 81dee67e SM |
534 | |
| 535 | ||
| 536 | #define PANEL_DISPLAY_CTRL 0x080000 | |
| 9bd2c86b | 537 | #define PANEL_DISPLAY_CTRL_RESERVED_MASK 0xc0f08000 |
| c4e893b7 MR |
538 | #define PANEL_DISPLAY_CTRL_SELECT_SHIFT 28 |
| 539 | #define PANEL_DISPLAY_CTRL_SELECT_MASK (0x3 << 28) | |
| 540 | #define PANEL_DISPLAY_CTRL_SELECT_PANEL (0x0 << 28) | |
| 541 | #define PANEL_DISPLAY_CTRL_SELECT_VGA (0x1 << 28) | |
| 542 | #define PANEL_DISPLAY_CTRL_SELECT_CRT (0x2 << 28) | |
| 6fba39cf MR |
543 | #define PANEL_DISPLAY_CTRL_FPEN BIT(27) |
| 544 | #define PANEL_DISPLAY_CTRL_VBIASEN BIT(26) | |
| 545 | #define PANEL_DISPLAY_CTRL_DATA BIT(25) | |
| 546 | #define PANEL_DISPLAY_CTRL_FPVDDEN BIT(24) | |
| 6fba39cf MR |
547 | #define PANEL_DISPLAY_CTRL_DUAL_DISPLAY BIT(19) |
| 548 | #define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL BIT(18) | |
| c4e893b7 MR |
549 | #define PANEL_DISPLAY_CTRL_FIFO (0x3 << 16) |
| 550 | #define PANEL_DISPLAY_CTRL_FIFO_1 (0x0 << 16) | |
| 551 | #define PANEL_DISPLAY_CTRL_FIFO_3 (0x1 << 16) | |
| 552 | #define PANEL_DISPLAY_CTRL_FIFO_7 (0x2 << 16) | |
| 553 | #define PANEL_DISPLAY_CTRL_FIFO_11 (0x3 << 16) | |
| 6fba39cf MR |
554 | #define DISPLAY_CTRL_CLOCK_PHASE BIT(14) |
| 555 | #define DISPLAY_CTRL_VSYNC_PHASE BIT(13) | |
| 556 | #define DISPLAY_CTRL_HSYNC_PHASE BIT(12) | |
| 557 | #define PANEL_DISPLAY_CTRL_VSYNC BIT(11) | |
| 558 | #define PANEL_DISPLAY_CTRL_CAPTURE_TIMING BIT(10) | |
| 559 | #define PANEL_DISPLAY_CTRL_COLOR_KEY BIT(9) | |
| 560 | #define DISPLAY_CTRL_TIMING BIT(8) | |
| 561 | #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR BIT(7) | |
| 562 | #define PANEL_DISPLAY_CTRL_VERTICAL_PAN BIT(6) | |
| 563 | #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR BIT(5) | |
| 564 | #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN BIT(4) | |
| 565 | #define DISPLAY_CTRL_GAMMA BIT(3) | |
| 566 | #define DISPLAY_CTRL_PLANE BIT(2) | |
| c4e893b7 MR |
567 | #define PANEL_DISPLAY_CTRL_FORMAT (0x3 << 0) |
| 568 | #define PANEL_DISPLAY_CTRL_FORMAT_8 (0x0 << 0) | |
| 569 | #define PANEL_DISPLAY_CTRL_FORMAT_16 (0x1 << 0) | |
| 570 | #define PANEL_DISPLAY_CTRL_FORMAT_32 (0x2 << 0) | |
| 81dee67e SM |
571 | |
| 572 | #define PANEL_PAN_CTRL 0x080004 | |
| 0d5d733b MR |
573 | #define PANEL_PAN_CTRL_VERTICAL_PAN_MASK (0xff << 24) |
| 574 | #define PANEL_PAN_CTRL_VERTICAL_VSYNC_MASK (0x3f << 16) | |
| 575 | #define PANEL_PAN_CTRL_HORIZONTAL_PAN_MASK (0xff << 8) | |
| 576 | #define PANEL_PAN_CTRL_HORIZONTAL_VSYNC_MASK 0x3f | |
| 81dee67e SM |
577 | |
| 578 | #define PANEL_COLOR_KEY 0x080008 | |
| 0d5d733b MR |
579 | #define PANEL_COLOR_KEY_MASK_MASK (0xffff << 16) |
| 580 | #define PANEL_COLOR_KEY_VALUE_MASK 0xffff | |
| 81dee67e SM |
581 | |
| 582 | #define PANEL_FB_ADDRESS 0x08000C | |
| 4463690a MR |
583 | #define PANEL_FB_ADDRESS_STATUS BIT(31) |
| 584 | #define PANEL_FB_ADDRESS_EXT BIT(27) | |
| 585 | #define PANEL_FB_ADDRESS_ADDRESS_MASK 0x1ffffff | |
| 81dee67e SM |
586 | |
| 587 | #define PANEL_FB_WIDTH 0x080010 | |
| 26a3cc90 MR |
588 | #define PANEL_FB_WIDTH_WIDTH_SHIFT 16 |
| 589 | #define PANEL_FB_WIDTH_WIDTH_MASK (0x3fff << 16) | |
| 590 | #define PANEL_FB_WIDTH_OFFSET_MASK 0x3fff | |
| 81dee67e SM |
591 | |
| 592 | #define PANEL_WINDOW_WIDTH 0x080014 | |
| 4c221d82 MR |
593 | #define PANEL_WINDOW_WIDTH_WIDTH_SHIFT 16 |
| 594 | #define PANEL_WINDOW_WIDTH_WIDTH_MASK (0xfff << 16) | |
| 595 | #define PANEL_WINDOW_WIDTH_X_MASK 0xfff | |
| 81dee67e SM |
596 | |
| 597 | #define PANEL_WINDOW_HEIGHT 0x080018 | |
| f91969f7 MR |
598 | #define PANEL_WINDOW_HEIGHT_HEIGHT_SHIFT 16 |
| 599 | #define PANEL_WINDOW_HEIGHT_HEIGHT_MASK (0xfff << 16) | |
| 600 | #define PANEL_WINDOW_HEIGHT_Y_MASK 0xfff | |
| 81dee67e SM |
601 | |
| 602 | #define PANEL_PLANE_TL 0x08001C | |
| 30ca5cb6 MR |
603 | #define PANEL_PLANE_TL_TOP_SHIFT 16 |
| 604 | #define PANEL_PLANE_TL_TOP_MASK (0xeff << 16) | |
| 605 | #define PANEL_PLANE_TL_LEFT_MASK 0xeff | |
| 81dee67e SM |
606 | |
| 607 | #define PANEL_PLANE_BR 0x080020 | |
| 27b047bb MR |
608 | #define PANEL_PLANE_BR_BOTTOM_SHIFT 16 |
| 609 | #define PANEL_PLANE_BR_BOTTOM_MASK (0xeff << 16) | |
| 610 | #define PANEL_PLANE_BR_RIGHT_MASK 0xeff | |
| 81dee67e SM |
611 | |
| 612 | #define PANEL_HORIZONTAL_TOTAL 0x080024 | |
| 60112069 MR |
613 | #define PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT 16 |
| 614 | #define PANEL_HORIZONTAL_TOTAL_TOTAL_MASK (0xfff << 16) | |
| 615 | #define PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK 0xfff | |
| 81dee67e SM |
616 | |
| 617 | #define PANEL_HORIZONTAL_SYNC 0x080028 | |
| a6f17bc4 MR |
618 | #define PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT 16 |
| 619 | #define PANEL_HORIZONTAL_SYNC_WIDTH_MASK (0xff << 16) | |
| 620 | #define PANEL_HORIZONTAL_SYNC_START_MASK 0xfff | |
| 81dee67e SM |
621 | |
| 622 | #define PANEL_VERTICAL_TOTAL 0x08002C | |
| 6014a31d MR |
623 | #define PANEL_VERTICAL_TOTAL_TOTAL_SHIFT 16 |
| 624 | #define PANEL_VERTICAL_TOTAL_TOTAL_MASK (0x7ff << 16) | |
| 625 | #define PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK 0x7ff | |
| 81dee67e SM |
626 | |
| 627 | #define PANEL_VERTICAL_SYNC 0x080030 | |
| 8ffe4610 MR |
628 | #define PANEL_VERTICAL_SYNC_HEIGHT_SHIFT 16 |
| 629 | #define PANEL_VERTICAL_SYNC_HEIGHT_MASK (0x3f << 16) | |
| 630 | #define PANEL_VERTICAL_SYNC_START_MASK 0x7ff | |
| 81dee67e SM |
631 | |
| 632 | #define PANEL_CURRENT_LINE 0x080034 | |
| 0d5d733b | 633 | #define PANEL_CURRENT_LINE_LINE_MASK 0x7ff |
| 81dee67e SM |
634 | |
| 635 | /* Video Control */ | |
| 636 | ||
| 637 | #define VIDEO_DISPLAY_CTRL 0x080040 | |
| 10dfcb06 | 638 | #define VIDEO_DISPLAY_CTRL_LINE_BUFFER BIT(18) |
| 0d5d733b MR |
639 | #define VIDEO_DISPLAY_CTRL_FIFO_MASK (0x3 << 16) |
| 640 | #define VIDEO_DISPLAY_CTRL_FIFO_1 (0x0 << 16) | |
| 641 | #define VIDEO_DISPLAY_CTRL_FIFO_3 (0x1 << 16) | |
| 642 | #define VIDEO_DISPLAY_CTRL_FIFO_7 (0x2 << 16) | |
| 643 | #define VIDEO_DISPLAY_CTRL_FIFO_11 (0x3 << 16) | |
| 10dfcb06 MR |
644 | #define VIDEO_DISPLAY_CTRL_BUFFER BIT(15) |
| 645 | #define VIDEO_DISPLAY_CTRL_CAPTURE BIT(14) | |
| 646 | #define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER BIT(13) | |
| 647 | #define VIDEO_DISPLAY_CTRL_BYTE_SWAP BIT(12) | |
| 648 | #define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE BIT(11) | |
| 649 | #define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE BIT(10) | |
| 650 | #define VIDEO_DISPLAY_CTRL_VERTICAL_MODE BIT(9) | |
| 651 | #define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE BIT(8) | |
| 0d5d733b | 652 | #define VIDEO_DISPLAY_CTRL_PIXEL_MASK (0xf << 4) |
| 10dfcb06 | 653 | #define VIDEO_DISPLAY_CTRL_GAMMA BIT(3) |
| 0d5d733b MR |
654 | #define VIDEO_DISPLAY_CTRL_FORMAT_MASK 0x3 |
| 655 | #define VIDEO_DISPLAY_CTRL_FORMAT_8 0x0 | |
| 656 | #define VIDEO_DISPLAY_CTRL_FORMAT_16 0x1 | |
| 657 | #define VIDEO_DISPLAY_CTRL_FORMAT_32 0x2 | |
| 658 | #define VIDEO_DISPLAY_CTRL_FORMAT_YUV 0x3 | |
| 81dee67e SM |
659 | |
| 660 | #define VIDEO_FB_0_ADDRESS 0x080044 | |
| 10dfcb06 MR |
661 | #define VIDEO_FB_0_ADDRESS_STATUS BIT(31) |
| 662 | #define VIDEO_FB_0_ADDRESS_EXT BIT(27) | |
| 0d5d733b | 663 | #define VIDEO_FB_0_ADDRESS_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
664 | |
| 665 | #define VIDEO_FB_WIDTH 0x080048 | |
| 0d5d733b MR |
666 | #define VIDEO_FB_WIDTH_WIDTH_MASK (0x3fff << 16) |
| 667 | #define VIDEO_FB_WIDTH_OFFSET_MASK 0x3fff | |
| 81dee67e SM |
668 | |
| 669 | #define VIDEO_FB_0_LAST_ADDRESS 0x08004C | |
| 10dfcb06 | 670 | #define VIDEO_FB_0_LAST_ADDRESS_EXT BIT(27) |
| 0d5d733b | 671 | #define VIDEO_FB_0_LAST_ADDRESS_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
672 | |
| 673 | #define VIDEO_PLANE_TL 0x080050 | |
| 0d5d733b MR |
674 | #define VIDEO_PLANE_TL_TOP_MASK (0x7ff << 16) |
| 675 | #define VIDEO_PLANE_TL_LEFT_MASK 0x7ff | |
| 81dee67e SM |
676 | |
| 677 | #define VIDEO_PLANE_BR 0x080054 | |
| 0d5d733b MR |
678 | #define VIDEO_PLANE_BR_BOTTOM_MASK (0x7ff << 16) |
| 679 | #define VIDEO_PLANE_BR_RIGHT_MASK 0x7ff | |
| 81dee67e SM |
680 | |
| 681 | #define VIDEO_SCALE 0x080058 | |
| 10dfcb06 | 682 | #define VIDEO_SCALE_VERTICAL_MODE BIT(31) |
| 0d5d733b | 683 | #define VIDEO_SCALE_VERTICAL_SCALE_MASK (0xfff << 16) |
| 10dfcb06 | 684 | #define VIDEO_SCALE_HORIZONTAL_MODE BIT(15) |
| 0d5d733b | 685 | #define VIDEO_SCALE_HORIZONTAL_SCALE_MASK 0xfff |
| 81dee67e SM |
686 | |
| 687 | #define VIDEO_INITIAL_SCALE 0x08005C | |
| 0d5d733b MR |
688 | #define VIDEO_INITIAL_SCALE_FB_1_MASK (0xfff << 16) |
| 689 | #define VIDEO_INITIAL_SCALE_FB_0_MASK 0xfff | |
| 81dee67e SM |
690 | |
| 691 | #define VIDEO_YUV_CONSTANTS 0x080060 | |
| 0d5d733b MR |
692 | #define VIDEO_YUV_CONSTANTS_Y_MASK (0xff << 24) |
| 693 | #define VIDEO_YUV_CONSTANTS_R_MASK (0xff << 16) | |
| 694 | #define VIDEO_YUV_CONSTANTS_G_MASK (0xff << 8) | |
| 695 | #define VIDEO_YUV_CONSTANTS_B_MASK 0xff | |
| 81dee67e SM |
696 | |
| 697 | #define VIDEO_FB_1_ADDRESS 0x080064 | |
| 10dfcb06 MR |
698 | #define VIDEO_FB_1_ADDRESS_STATUS BIT(31) |
| 699 | #define VIDEO_FB_1_ADDRESS_EXT BIT(27) | |
| 0d5d733b | 700 | #define VIDEO_FB_1_ADDRESS_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
701 | |
| 702 | #define VIDEO_FB_1_LAST_ADDRESS 0x080068 | |
| 10dfcb06 | 703 | #define VIDEO_FB_1_LAST_ADDRESS_EXT BIT(27) |
| 0d5d733b | 704 | #define VIDEO_FB_1_LAST_ADDRESS_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
705 | |
| 706 | /* Video Alpha Control */ | |
| 707 | ||
| 708 | #define VIDEO_ALPHA_DISPLAY_CTRL 0x080080 | |
| 10dfcb06 | 709 | #define VIDEO_ALPHA_DISPLAY_CTRL_SELECT BIT(28) |
| 0d5d733b MR |
710 | #define VIDEO_ALPHA_DISPLAY_CTRL_ALPHA_MASK (0xf << 24) |
| 711 | #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_MASK (0x3 << 16) | |
| 712 | #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_1 (0x0 << 16) | |
| 713 | #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_3 (0x1 << 16) | |
| 714 | #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_7 (0x2 << 16) | |
| 715 | #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_11 (0x3 << 16) | |
| 10dfcb06 MR |
716 | #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE BIT(11) |
| 717 | #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE BIT(10) | |
| 718 | #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE BIT(9) | |
| 719 | #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE BIT(8) | |
| 0d5d733b | 720 | #define VIDEO_ALPHA_DISPLAY_CTRL_PIXEL_MASK (0xf << 4) |
| 10dfcb06 | 721 | #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY BIT(3) |
| 0d5d733b MR |
722 | #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_MASK 0x3 |
| 723 | #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_8 0x0 | |
| 724 | #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_16 0x1 | |
| 725 | #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 0x2 | |
| 726 | #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4 0x3 | |
| 81dee67e SM |
727 | |
| 728 | #define VIDEO_ALPHA_FB_ADDRESS 0x080084 | |
| 10dfcb06 MR |
729 | #define VIDEO_ALPHA_FB_ADDRESS_STATUS BIT(31) |
| 730 | #define VIDEO_ALPHA_FB_ADDRESS_EXT BIT(27) | |
| 0d5d733b | 731 | #define VIDEO_ALPHA_FB_ADDRESS_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
732 | |
| 733 | #define VIDEO_ALPHA_FB_WIDTH 0x080088 | |
| 0d5d733b MR |
734 | #define VIDEO_ALPHA_FB_WIDTH_WIDTH_MASK (0x3fff << 16) |
| 735 | #define VIDEO_ALPHA_FB_WIDTH_OFFSET_MASK 0x3fff | |
| 81dee67e SM |
736 | |
| 737 | #define VIDEO_ALPHA_FB_LAST_ADDRESS 0x08008C | |
| 10dfcb06 | 738 | #define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT BIT(27) |
| 0d5d733b | 739 | #define VIDEO_ALPHA_FB_LAST_ADDRESS_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
740 | |
| 741 | #define VIDEO_ALPHA_PLANE_TL 0x080090 | |
| 0d5d733b MR |
742 | #define VIDEO_ALPHA_PLANE_TL_TOP_MASK (0x7ff << 16) |
| 743 | #define VIDEO_ALPHA_PLANE_TL_LEFT_MASK 0x7ff | |
| 81dee67e SM |
744 | |
| 745 | #define VIDEO_ALPHA_PLANE_BR 0x080094 | |
| 0d5d733b MR |
746 | #define VIDEO_ALPHA_PLANE_BR_BOTTOM_MASK (0x7ff << 16) |
| 747 | #define VIDEO_ALPHA_PLANE_BR_RIGHT_MASK 0x7ff | |
| 81dee67e SM |
748 | |
| 749 | #define VIDEO_ALPHA_SCALE 0x080098 | |
| 10dfcb06 | 750 | #define VIDEO_ALPHA_SCALE_VERTICAL_MODE BIT(31) |
| 0d5d733b | 751 | #define VIDEO_ALPHA_SCALE_VERTICAL_SCALE_MASK (0xfff << 16) |
| 10dfcb06 | 752 | #define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE BIT(15) |
| 0d5d733b | 753 | #define VIDEO_ALPHA_SCALE_HORIZONTAL_SCALE_MASK 0xfff |
| 81dee67e SM |
754 | |
| 755 | #define VIDEO_ALPHA_INITIAL_SCALE 0x08009C | |
| 0d5d733b MR |
756 | #define VIDEO_ALPHA_INITIAL_SCALE_VERTICAL_MASK (0xfff << 16) |
| 757 | #define VIDEO_ALPHA_INITIAL_SCALE_HORIZONTAL_MASK 0xfff | |
| 81dee67e SM |
758 | |
| 759 | #define VIDEO_ALPHA_CHROMA_KEY 0x0800A0 | |
| 0d5d733b MR |
760 | #define VIDEO_ALPHA_CHROMA_KEY_MASK_MASK (0xffff << 16) |
| 761 | #define VIDEO_ALPHA_CHROMA_KEY_VALUE_MASK 0xffff | |
| 81dee67e SM |
762 | |
| 763 | #define VIDEO_ALPHA_COLOR_LOOKUP_01 0x0800A4 | |
| 0d5d733b MR |
764 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_MASK (0xffff << 16) |
| 765 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_RED_MASK (0x1f << 27) | |
| 766 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_GREEN_MASK (0x3f << 21) | |
| 767 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_BLUE_MASK (0x1f << 16) | |
| 768 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_MASK 0xffff | |
| 769 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_RED_MASK (0x1f << 11) | |
| 770 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_GREEN_MASK (0x3f << 5) | |
| 771 | #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_BLUE_MASK 0x1f | |
| 81dee67e SM |
772 | |
| 773 | #define VIDEO_ALPHA_COLOR_LOOKUP_23 0x0800A8 | |
| 0d5d733b MR |
774 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_MASK (0xffff << 16) |
| 775 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_RED_MASK (0x1f << 27) | |
| 776 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_GREEN_MASK (0x3f << 21) | |
| 777 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_BLUE_MASK (0x1f << 16) | |
| 778 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_MASK 0xffff | |
| 779 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_RED_MASK (0x1f << 11) | |
| 780 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_GREEN_MASK (0x3f << 5) | |
| 781 | #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_BLUE_MASK 0x1f | |
| 81dee67e SM |
782 | |
| 783 | #define VIDEO_ALPHA_COLOR_LOOKUP_45 0x0800AC | |
| 0d5d733b MR |
784 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_MASK (0xffff << 16) |
| 785 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_RED_MASK (0x1f << 27) | |
| 786 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_GREEN_MASK (0x3f << 21) | |
| 787 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_BLUE_MASK (0x1f << 16) | |
| 788 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_MASK 0xffff | |
| 789 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_RED_MASK (0x1f << 11) | |
| 790 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_GREEN_MASK (0x3f << 5) | |
| 791 | #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_BLUE_MASK 0x1f | |
| 81dee67e SM |
792 | |
| 793 | #define VIDEO_ALPHA_COLOR_LOOKUP_67 0x0800B0 | |
| 0d5d733b MR |
794 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_MASK (0xffff << 16) |
| 795 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_RED_MASK (0x1f << 27) | |
| 796 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_GREEN_MASK (0x3f << 21) | |
| 797 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_BLUE_MASK (0x1f << 16) | |
| 798 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_MASK 0xffff | |
| 799 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_RED_MASK (0x1f << 11) | |
| 800 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_GREEN_MASK (0x3f << 5) | |
| 801 | #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_BLUE_MASK 0x1f | |
| 81dee67e SM |
802 | |
| 803 | #define VIDEO_ALPHA_COLOR_LOOKUP_89 0x0800B4 | |
| 0d5d733b MR |
804 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_MASK (0xffff << 16) |
| 805 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_RED_MASK (0x1f << 27) | |
| 806 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_GREEN_MASK (0x3f << 21) | |
| 807 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_BLUE_MASK (0x1f << 16) | |
| 808 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_MASK 0xffff | |
| 809 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_RED_MASK (0x1f << 11) | |
| 810 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_GREEN_MASK (0x3f << 5) | |
| 811 | #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_BLUE_MASK 0x1f | |
| 81dee67e SM |
812 | |
| 813 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB 0x0800B8 | |
| 0d5d733b MR |
814 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_MASK (0xffff << 16) |
| 815 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_RED_MASK (0x1f << 27) | |
| 816 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_GREEN_MASK (0x3f << 21) | |
| 817 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_BLUE_MASK (0x1f << 16) | |
| 818 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_MASK 0xffff | |
| 819 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_RED_MASK (0x1f << 11) | |
| 820 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_GREEN_MASK (0x3f << 5) | |
| 821 | #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_BLUE_MASK 0x1f | |
| 81dee67e SM |
822 | |
| 823 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD 0x0800BC | |
| 0d5d733b MR |
824 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_MASK (0xffff << 16) |
| 825 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_RED_MASK (0x1f << 27) | |
| 826 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_GREEN_MASK (0x3f << 21) | |
| 827 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_BLUE_MASK (0x1f << 16) | |
| 828 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_MASK 0xffff | |
| 829 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_RED_MASK (0x1f << 11) | |
| 830 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_GREEN_MASK (0x3f << 5) | |
| 831 | #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_BLUE_MASK 0x1f | |
| 81dee67e SM |
832 | |
| 833 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF 0x0800C0 | |
| 0d5d733b MR |
834 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_MASK (0xffff << 16) |
| 835 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_RED_MASK (0x1f << 27) | |
| 836 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_GREEN_MASK (0x3f << 21) | |
| 837 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_BLUE_MASK (0x1f << 16) | |
| 838 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_MASK 0xffff | |
| 839 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_RED_MASK (0x1f << 11) | |
| 840 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_GREEN_MASK (0x3f << 5) | |
| 841 | #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_BLUE_MASK 0x1f | |
| 81dee67e SM |
842 | |
| 843 | /* Panel Cursor Control */ | |
| 844 | ||
| 845 | #define PANEL_HWC_ADDRESS 0x0800F0 | |
| 10dfcb06 MR |
846 | #define PANEL_HWC_ADDRESS_ENABLE BIT(31) |
| 847 | #define PANEL_HWC_ADDRESS_EXT BIT(27) | |
| 0d5d733b | 848 | #define PANEL_HWC_ADDRESS_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
849 | |
| 850 | #define PANEL_HWC_LOCATION 0x0800F4 | |
| 10dfcb06 | 851 | #define PANEL_HWC_LOCATION_TOP BIT(27) |
| 0d5d733b | 852 | #define PANEL_HWC_LOCATION_Y_MASK (0x7ff << 16) |
| 10dfcb06 | 853 | #define PANEL_HWC_LOCATION_LEFT BIT(11) |
| 0d5d733b | 854 | #define PANEL_HWC_LOCATION_X_MASK 0x7ff |
| 81dee67e SM |
855 | |
| 856 | #define PANEL_HWC_COLOR_12 0x0800F8 | |
| 0d5d733b MR |
857 | #define PANEL_HWC_COLOR_12_2_RGB565_MASK (0xffff << 16) |
| 858 | #define PANEL_HWC_COLOR_12_1_RGB565_MASK 0xffff | |
| 81dee67e SM |
859 | |
| 860 | #define PANEL_HWC_COLOR_3 0x0800FC | |
| 0d5d733b | 861 | #define PANEL_HWC_COLOR_3_RGB565_MASK 0xffff |
| 81dee67e SM |
862 | |
| 863 | /* Old Definitions +++ */ | |
| 864 | #define PANEL_HWC_COLOR_01 0x0800F8 | |
| 0d5d733b MR |
865 | #define PANEL_HWC_COLOR_01_1_RED_MASK (0x1f << 27) |
| 866 | #define PANEL_HWC_COLOR_01_1_GREEN_MASK (0x3f << 21) | |
| 867 | #define PANEL_HWC_COLOR_01_1_BLUE_MASK (0x1f << 16) | |
| 868 | #define PANEL_HWC_COLOR_01_0_RED_MASK (0x1f << 11) | |
| 869 | #define PANEL_HWC_COLOR_01_0_GREEN_MASK (0x3f << 5) | |
| 870 | #define PANEL_HWC_COLOR_01_0_BLUE_MASK 0x1f | |
| 81dee67e SM |
871 | |
| 872 | #define PANEL_HWC_COLOR_2 0x0800FC | |
| 0d5d733b MR |
873 | #define PANEL_HWC_COLOR_2_RED_MASK (0x1f << 11) |
| 874 | #define PANEL_HWC_COLOR_2_GREEN_MASK (0x3f << 5) | |
| 875 | #define PANEL_HWC_COLOR_2_BLUE_MASK 0x1f | |
| 81dee67e SM |
876 | /* Old Definitions --- */ |
| 877 | ||
| 878 | /* Alpha Control */ | |
| 879 | ||
| 880 | #define ALPHA_DISPLAY_CTRL 0x080100 | |
| 10dfcb06 | 881 | #define ALPHA_DISPLAY_CTRL_SELECT BIT(28) |
| 0d5d733b MR |
882 | #define ALPHA_DISPLAY_CTRL_ALPHA_MASK (0xf << 24) |
| 883 | #define ALPHA_DISPLAY_CTRL_FIFO_MASK (0x3 << 16) | |
| 884 | #define ALPHA_DISPLAY_CTRL_FIFO_1 (0x0 << 16) | |
| 885 | #define ALPHA_DISPLAY_CTRL_FIFO_3 (0x1 << 16) | |
| 886 | #define ALPHA_DISPLAY_CTRL_FIFO_7 (0x2 << 16) | |
| 887 | #define ALPHA_DISPLAY_CTRL_FIFO_11 (0x3 << 16) | |
| 888 | #define ALPHA_DISPLAY_CTRL_PIXEL_MASK (0xf << 4) | |
| 10dfcb06 | 889 | #define ALPHA_DISPLAY_CTRL_CHROMA_KEY BIT(3) |
| 0d5d733b MR |
890 | #define ALPHA_DISPLAY_CTRL_FORMAT_MASK 0x3 |
| 891 | #define ALPHA_DISPLAY_CTRL_FORMAT_16 0x1 | |
| 892 | #define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 0x2 | |
| 893 | #define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4 0x3 | |
| 81dee67e SM |
894 | |
| 895 | #define ALPHA_FB_ADDRESS 0x080104 | |
| 10dfcb06 MR |
896 | #define ALPHA_FB_ADDRESS_STATUS BIT(31) |
| 897 | #define ALPHA_FB_ADDRESS_EXT BIT(27) | |
| 0d5d733b | 898 | #define ALPHA_FB_ADDRESS_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
899 | |
| 900 | #define ALPHA_FB_WIDTH 0x080108 | |
| 0d5d733b MR |
901 | #define ALPHA_FB_WIDTH_WIDTH_MASK (0x3fff << 16) |
| 902 | #define ALPHA_FB_WIDTH_OFFSET_MASK 0x3fff | |
| 81dee67e SM |
903 | |
| 904 | #define ALPHA_PLANE_TL 0x08010C | |
| 0d5d733b MR |
905 | #define ALPHA_PLANE_TL_TOP_MASK (0x7ff << 16) |
| 906 | #define ALPHA_PLANE_TL_LEFT_MASK 0x7ff | |
| 81dee67e SM |
907 | |
| 908 | #define ALPHA_PLANE_BR 0x080110 | |
| 0d5d733b MR |
909 | #define ALPHA_PLANE_BR_BOTTOM_MASK (0x7ff << 16) |
| 910 | #define ALPHA_PLANE_BR_RIGHT_MASK 0x7ff | |
| 81dee67e SM |
911 | |
| 912 | #define ALPHA_CHROMA_KEY 0x080114 | |
| 0d5d733b MR |
913 | #define ALPHA_CHROMA_KEY_MASK_MASK (0xffff << 16) |
| 914 | #define ALPHA_CHROMA_KEY_VALUE_MASK 0xffff | |
| 81dee67e SM |
915 | |
| 916 | #define ALPHA_COLOR_LOOKUP_01 0x080118 | |
| 0d5d733b MR |
917 | #define ALPHA_COLOR_LOOKUP_01_1_MASK (0xffff << 16) |
| 918 | #define ALPHA_COLOR_LOOKUP_01_1_RED_MASK (0x1f << 27) | |
| 919 | #define ALPHA_COLOR_LOOKUP_01_1_GREEN_MASK (0x3f << 21) | |
| 920 | #define ALPHA_COLOR_LOOKUP_01_1_BLUE_MASK (0x1f << 16) | |
| 921 | #define ALPHA_COLOR_LOOKUP_01_0_MASK 0xffff | |
| 922 | #define ALPHA_COLOR_LOOKUP_01_0_RED_MASK (0x1f << 11) | |
| 923 | #define ALPHA_COLOR_LOOKUP_01_0_GREEN_MASK (0x3f << 5) | |
| 924 | #define ALPHA_COLOR_LOOKUP_01_0_BLUE_MASK 0x1f | |
| 81dee67e SM |
925 | |
| 926 | #define ALPHA_COLOR_LOOKUP_23 0x08011C | |
| 0d5d733b MR |
927 | #define ALPHA_COLOR_LOOKUP_23_3_MASK (0xffff << 16) |
| 928 | #define ALPHA_COLOR_LOOKUP_23_3_RED_MASK (0x1f << 27) | |
| 929 | #define ALPHA_COLOR_LOOKUP_23_3_GREEN_MASK (0x3f << 21) | |
| 930 | #define ALPHA_COLOR_LOOKUP_23_3_BLUE_MASK (0x1f << 16) | |
| 931 | #define ALPHA_COLOR_LOOKUP_23_2_MASK 0xffff | |
| 932 | #define ALPHA_COLOR_LOOKUP_23_2_RED_MASK (0x1f << 11) | |
| 933 | #define ALPHA_COLOR_LOOKUP_23_2_GREEN_MASK (0x3f << 5) | |
| 934 | #define ALPHA_COLOR_LOOKUP_23_2_BLUE_MASK 0x1f | |
| 81dee67e SM |
935 | |
| 936 | #define ALPHA_COLOR_LOOKUP_45 0x080120 | |
| 0d5d733b MR |
937 | #define ALPHA_COLOR_LOOKUP_45_5_MASK (0xffff << 16) |
| 938 | #define ALPHA_COLOR_LOOKUP_45_5_RED_MASK (0x1f << 27) | |
| 939 | #define ALPHA_COLOR_LOOKUP_45_5_GREEN_MASK (0x3f << 21) | |
| 940 | #define ALPHA_COLOR_LOOKUP_45_5_BLUE_MASK (0x1f << 16) | |
| 941 | #define ALPHA_COLOR_LOOKUP_45_4_MASK 0xffff | |
| 942 | #define ALPHA_COLOR_LOOKUP_45_4_RED_MASK (0x1f << 11) | |
| 943 | #define ALPHA_COLOR_LOOKUP_45_4_GREEN_MASK (0x3f << 5) | |
| 944 | #define ALPHA_COLOR_LOOKUP_45_4_BLUE_MASK 0x1f | |
| 81dee67e SM |
945 | |
| 946 | #define ALPHA_COLOR_LOOKUP_67 0x080124 | |
| 0d5d733b MR |
947 | #define ALPHA_COLOR_LOOKUP_67_7_MASK (0xffff << 16) |
| 948 | #define ALPHA_COLOR_LOOKUP_67_7_RED_MASK (0x1f << 27) | |
| 949 | #define ALPHA_COLOR_LOOKUP_67_7_GREEN_MASK (0x3f << 21) | |
| 950 | #define ALPHA_COLOR_LOOKUP_67_7_BLUE_MASK (0x1f << 16) | |
| 951 | #define ALPHA_COLOR_LOOKUP_67_6_MASK 0xffff | |
| 952 | #define ALPHA_COLOR_LOOKUP_67_6_RED_MASK (0x1f << 11) | |
| 953 | #define ALPHA_COLOR_LOOKUP_67_6_GREEN_MASK (0x3f << 5) | |
| 954 | #define ALPHA_COLOR_LOOKUP_67_6_BLUE_MASK 0x1f | |
| 81dee67e SM |
955 | |
| 956 | #define ALPHA_COLOR_LOOKUP_89 0x080128 | |
| 0d5d733b MR |
957 | #define ALPHA_COLOR_LOOKUP_89_9_MASK (0xffff << 16) |
| 958 | #define ALPHA_COLOR_LOOKUP_89_9_RED_MASK (0x1f << 27) | |
| 959 | #define ALPHA_COLOR_LOOKUP_89_9_GREEN_MASK (0x3f << 21) | |
| 960 | #define ALPHA_COLOR_LOOKUP_89_9_BLUE_MASK (0x1f << 16) | |
| 961 | #define ALPHA_COLOR_LOOKUP_89_8_MASK 0xffff | |
| 962 | #define ALPHA_COLOR_LOOKUP_89_8_RED_MASK (0x1f << 11) | |
| 963 | #define ALPHA_COLOR_LOOKUP_89_8_GREEN_MASK (0x3f << 5) | |
| 964 | #define ALPHA_COLOR_LOOKUP_89_8_BLUE_MASK 0x1f | |
| 81dee67e SM |
965 | |
| 966 | #define ALPHA_COLOR_LOOKUP_AB 0x08012C | |
| 0d5d733b MR |
967 | #define ALPHA_COLOR_LOOKUP_AB_B_MASK (0xffff << 16) |
| 968 | #define ALPHA_COLOR_LOOKUP_AB_B_RED_MASK (0x1f << 27) | |
| 969 | #define ALPHA_COLOR_LOOKUP_AB_B_GREEN_MASK (0x3f << 21) | |
| 970 | #define ALPHA_COLOR_LOOKUP_AB_B_BLUE_MASK (0x1f << 16) | |
| 971 | #define ALPHA_COLOR_LOOKUP_AB_A_MASK 0xffff | |
| 972 | #define ALPHA_COLOR_LOOKUP_AB_A_RED_MASK (0x1f << 11) | |
| 973 | #define ALPHA_COLOR_LOOKUP_AB_A_GREEN_MASK (0x3f << 5) | |
| 974 | #define ALPHA_COLOR_LOOKUP_AB_A_BLUE_MASK 0x1f | |
| 81dee67e SM |
975 | |
| 976 | #define ALPHA_COLOR_LOOKUP_CD 0x080130 | |
| 0d5d733b MR |
977 | #define ALPHA_COLOR_LOOKUP_CD_D_MASK (0xffff << 16) |
| 978 | #define ALPHA_COLOR_LOOKUP_CD_D_RED_MASK (0x1f << 27) | |
| 979 | #define ALPHA_COLOR_LOOKUP_CD_D_GREEN_MASK (0x3f << 21) | |
| 980 | #define ALPHA_COLOR_LOOKUP_CD_D_BLUE_MASK (0x1f << 16) | |
| 981 | #define ALPHA_COLOR_LOOKUP_CD_C_MASK 0xffff | |
| 982 | #define ALPHA_COLOR_LOOKUP_CD_C_RED_MASK (0x1f << 11) | |
| 983 | #define ALPHA_COLOR_LOOKUP_CD_C_GREEN_MASK (0x3f << 5) | |
| 984 | #define ALPHA_COLOR_LOOKUP_CD_C_BLUE_MASK 0x1f | |
| 81dee67e SM |
985 | |
| 986 | #define ALPHA_COLOR_LOOKUP_EF 0x080134 | |
| 0d5d733b MR |
987 | #define ALPHA_COLOR_LOOKUP_EF_F_MASK (0xffff << 16) |
| 988 | #define ALPHA_COLOR_LOOKUP_EF_F_RED_MASK (0x1f << 27) | |
| 989 | #define ALPHA_COLOR_LOOKUP_EF_F_GREEN_MASK (0x3f << 21) | |
| 990 | #define ALPHA_COLOR_LOOKUP_EF_F_BLUE_MASK (0x1f << 16) | |
| 991 | #define ALPHA_COLOR_LOOKUP_EF_E_MASK 0xffff | |
| 992 | #define ALPHA_COLOR_LOOKUP_EF_E_RED_MASK (0x1f << 11) | |
| 993 | #define ALPHA_COLOR_LOOKUP_EF_E_GREEN_MASK (0x3f << 5) | |
| 994 | #define ALPHA_COLOR_LOOKUP_EF_E_BLUE_MASK 0x1f | |
| 81dee67e SM |
995 | |
| 996 | /* CRT Graphics Control */ | |
| 997 | ||
| 998 | #define CRT_DISPLAY_CTRL 0x080200 | |
| 9bd2c86b | 999 | #define CRT_DISPLAY_CTRL_RESERVED_MASK 0xfb008200 |
| 81dee67e SM |
1000 | |
| 1001 | /* SM750LE definition */ | |
| cdce1f18 MR |
1002 | #define CRT_DISPLAY_CTRL_DPMS_SHIFT 30 |
| 1003 | #define CRT_DISPLAY_CTRL_DPMS_MASK (0x3 << 30) | |
| 1004 | #define CRT_DISPLAY_CTRL_DPMS_0 (0x0 << 30) | |
| 1005 | #define CRT_DISPLAY_CTRL_DPMS_1 (0x1 << 30) | |
| 1006 | #define CRT_DISPLAY_CTRL_DPMS_2 (0x2 << 30) | |
| 1007 | #define CRT_DISPLAY_CTRL_DPMS_3 (0x3 << 30) | |
| 1008 | #define CRT_DISPLAY_CTRL_CLK_MASK (0x7 << 27) | |
| 1009 | #define CRT_DISPLAY_CTRL_CLK_PLL25 (0x0 << 27) | |
| 1010 | #define CRT_DISPLAY_CTRL_CLK_PLL41 (0x1 << 27) | |
| 1011 | #define CRT_DISPLAY_CTRL_CLK_PLL62 (0x2 << 27) | |
| 1012 | #define CRT_DISPLAY_CTRL_CLK_PLL65 (0x3 << 27) | |
| 1013 | #define CRT_DISPLAY_CTRL_CLK_PLL74 (0x4 << 27) | |
| 1014 | #define CRT_DISPLAY_CTRL_CLK_PLL80 (0x5 << 27) | |
| 1015 | #define CRT_DISPLAY_CTRL_CLK_PLL108 (0x6 << 27) | |
| 1016 | #define CRT_DISPLAY_CTRL_CLK_RESERVED (0x7 << 27) | |
| d8264edf | 1017 | #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC BIT(26) |
| 81dee67e | 1018 | |
| 81dee67e | 1019 | /* SM750LE definition */ |
| d8264edf MR |
1020 | #define CRT_DISPLAY_CTRL_CRTSELECT BIT(25) |
| 1021 | #define CRT_DISPLAY_CTRL_RGBBIT BIT(24) | |
| 81dee67e | 1022 | |
| 81dee67e | 1023 | #ifndef VALIDATION_CHIP |
| d8264edf | 1024 | #define CRT_DISPLAY_CTRL_CENTERING BIT(24) |
| 81dee67e | 1025 | #endif |
| d8264edf MR |
1026 | #define CRT_DISPLAY_CTRL_LOCK_TIMING BIT(23) |
| 1027 | #define CRT_DISPLAY_CTRL_EXPANSION BIT(22) | |
| 1028 | #define CRT_DISPLAY_CTRL_VERTICAL_MODE BIT(21) | |
| 1029 | #define CRT_DISPLAY_CTRL_HORIZONTAL_MODE BIT(20) | |
| cdce1f18 MR |
1030 | #define CRT_DISPLAY_CTRL_SELECT_SHIFT 18 |
| 1031 | #define CRT_DISPLAY_CTRL_SELECT_MASK (0x3 << 18) | |
| 1032 | #define CRT_DISPLAY_CTRL_SELECT_PANEL (0x0 << 18) | |
| 1033 | #define CRT_DISPLAY_CTRL_SELECT_VGA (0x1 << 18) | |
| 1034 | #define CRT_DISPLAY_CTRL_SELECT_CRT (0x2 << 18) | |
| 1035 | #define CRT_DISPLAY_CTRL_FIFO_MASK (0x3 << 16) | |
| 1036 | #define CRT_DISPLAY_CTRL_FIFO_1 (0x0 << 16) | |
| 1037 | #define CRT_DISPLAY_CTRL_FIFO_3 (0x1 << 16) | |
| 1038 | #define CRT_DISPLAY_CTRL_FIFO_7 (0x2 << 16) | |
| 1039 | #define CRT_DISPLAY_CTRL_FIFO_11 (0x3 << 16) | |
| d8264edf | 1040 | #define CRT_DISPLAY_CTRL_BLANK BIT(10) |
| cdce1f18 MR |
1041 | #define CRT_DISPLAY_CTRL_PIXEL_MASK (0xf << 4) |
| 1042 | #define CRT_DISPLAY_CTRL_FORMAT_MASK (0x3 << 0) | |
| 1043 | #define CRT_DISPLAY_CTRL_FORMAT_8 (0x0 << 0) | |
| 1044 | #define CRT_DISPLAY_CTRL_FORMAT_16 (0x1 << 0) | |
| 1045 | #define CRT_DISPLAY_CTRL_FORMAT_32 (0x2 << 0) | |
| 81dee67e SM |
1046 | |
| 1047 | #define CRT_FB_ADDRESS 0x080204 | |
| 7ea833df MR |
1048 | #define CRT_FB_ADDRESS_STATUS BIT(31) |
| 1049 | #define CRT_FB_ADDRESS_EXT BIT(27) | |
| 1050 | #define CRT_FB_ADDRESS_ADDRESS_MASK 0x3ffffff | |
| 81dee67e SM |
1051 | |
| 1052 | #define CRT_FB_WIDTH 0x080208 | |
| d6a4cba7 MR |
1053 | #define CRT_FB_WIDTH_WIDTH_SHIFT 16 |
| 1054 | #define CRT_FB_WIDTH_WIDTH_MASK (0x3fff << 16) | |
| 1055 | #define CRT_FB_WIDTH_OFFSET_MASK 0x3fff | |
| 81dee67e SM |
1056 | |
| 1057 | #define CRT_HORIZONTAL_TOTAL 0x08020C | |
| 32849f85 MR |
1058 | #define CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT 16 |
| 1059 | #define CRT_HORIZONTAL_TOTAL_TOTAL_MASK (0xfff << 16) | |
| 1060 | #define CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK 0xfff | |
| 81dee67e SM |
1061 | |
| 1062 | #define CRT_HORIZONTAL_SYNC 0x080210 | |
| 1adb3c23 MR |
1063 | #define CRT_HORIZONTAL_SYNC_WIDTH_SHIFT 16 |
| 1064 | #define CRT_HORIZONTAL_SYNC_WIDTH_MASK (0xff << 16) | |
| 1065 | #define CRT_HORIZONTAL_SYNC_START_MASK 0xfff | |
| 81dee67e SM |
1066 | |
| 1067 | #define CRT_VERTICAL_TOTAL 0x080214 | |
| 3d5158d3 MR |
1068 | #define CRT_VERTICAL_TOTAL_TOTAL_SHIFT 16 |
| 1069 | #define CRT_VERTICAL_TOTAL_TOTAL_MASK (0x7ff << 16) | |
| 1070 | #define CRT_VERTICAL_TOTAL_DISPLAY_END_MASK (0x7ff) | |
| 81dee67e SM |
1071 | |
| 1072 | #define CRT_VERTICAL_SYNC 0x080218 | |
| 620c3912 MR |
1073 | #define CRT_VERTICAL_SYNC_HEIGHT_SHIFT 16 |
| 1074 | #define CRT_VERTICAL_SYNC_HEIGHT_MASK (0x3f << 16) | |
| 1075 | #define CRT_VERTICAL_SYNC_START_MASK 0x7ff | |
| 81dee67e SM |
1076 | |
| 1077 | #define CRT_SIGNATURE_ANALYZER 0x08021C | |
| 0d5d733b | 1078 | #define CRT_SIGNATURE_ANALYZER_STATUS_MASK (0xffff << 16) |
| 10dfcb06 MR |
1079 | #define CRT_SIGNATURE_ANALYZER_ENABLE BIT(3) |
| 1080 | #define CRT_SIGNATURE_ANALYZER_RESET BIT(2) | |
| 0d5d733b | 1081 | #define CRT_SIGNATURE_ANALYZER_SOURCE_MASK 0x3 |
| 81dee67e SM |
1082 | #define CRT_SIGNATURE_ANALYZER_SOURCE_RED 0 |
| 1083 | #define CRT_SIGNATURE_ANALYZER_SOURCE_GREEN 1 | |
| 1084 | #define CRT_SIGNATURE_ANALYZER_SOURCE_BLUE 2 | |
| 1085 | ||
| 1086 | #define CRT_CURRENT_LINE 0x080220 | |
| 0d5d733b | 1087 | #define CRT_CURRENT_LINE_LINE_MASK 0x7ff |
| 81dee67e SM |
1088 | |
| 1089 | #define CRT_MONITOR_DETECT 0x080224 | |
| 10dfcb06 MR |
1090 | #define CRT_MONITOR_DETECT_VALUE BIT(25) |
| 1091 | #define CRT_MONITOR_DETECT_ENABLE BIT(24) | |
| 0d5d733b MR |
1092 | #define CRT_MONITOR_DETECT_RED_MASK (0xff << 16) |
| 1093 | #define CRT_MONITOR_DETECT_GREEN_MASK (0xff << 8) | |
| 1094 | #define CRT_MONITOR_DETECT_BLUE_MASK 0xff | |
| 81dee67e SM |
1095 | |
| 1096 | #define CRT_SCALE 0x080228 | |
| 10dfcb06 | 1097 | #define CRT_SCALE_VERTICAL_MODE BIT(31) |
| 0d5d733b | 1098 | #define CRT_SCALE_VERTICAL_SCALE_MASK (0xfff << 16) |
| 10dfcb06 | 1099 | #define CRT_SCALE_HORIZONTAL_MODE BIT(15) |
| 0d5d733b | 1100 | #define CRT_SCALE_HORIZONTAL_SCALE_MASK 0xfff |
| 81dee67e SM |
1101 | |
| 1102 | /* CRT Cursor Control */ | |
| 1103 | ||
| 1104 | #define CRT_HWC_ADDRESS 0x080230 | |
| 10dfcb06 MR |
1105 | #define CRT_HWC_ADDRESS_ENABLE BIT(31) |
| 1106 | #define CRT_HWC_ADDRESS_EXT BIT(27) | |
| 0d5d733b | 1107 | #define CRT_HWC_ADDRESS_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
1108 | |
| 1109 | #define CRT_HWC_LOCATION 0x080234 | |
| 10dfcb06 | 1110 | #define CRT_HWC_LOCATION_TOP BIT(27) |
| 0d5d733b | 1111 | #define CRT_HWC_LOCATION_Y_MASK (0x7ff << 16) |
| 10dfcb06 | 1112 | #define CRT_HWC_LOCATION_LEFT BIT(11) |
| 0d5d733b | 1113 | #define CRT_HWC_LOCATION_X_MASK 0x7ff |
| 81dee67e SM |
1114 | |
| 1115 | #define CRT_HWC_COLOR_12 0x080238 | |
| 0d5d733b MR |
1116 | #define CRT_HWC_COLOR_12_2_RGB565_MASK (0xffff << 16) |
| 1117 | #define CRT_HWC_COLOR_12_1_RGB565_MASK 0xffff | |
| 81dee67e SM |
1118 | |
| 1119 | #define CRT_HWC_COLOR_3 0x08023C | |
| 0d5d733b | 1120 | #define CRT_HWC_COLOR_3_RGB565_MASK 0xffff |
| 81dee67e | 1121 | |
| 81dee67e SM |
1122 | /* This vertical expansion below start at 0x080240 ~ 0x080264 */ |
| 1123 | #define CRT_VERTICAL_EXPANSION 0x080240 | |
| 1124 | #ifndef VALIDATION_CHIP | |
| 0d5d733b | 1125 | #define CRT_VERTICAL_CENTERING_VALUE_MASK (0xff << 24) |
| 81dee67e | 1126 | #endif |
| 0d5d733b MR |
1127 | #define CRT_VERTICAL_EXPANSION_COMPARE_VALUE_MASK (0xff << 16) |
| 1128 | #define CRT_VERTICAL_EXPANSION_LINE_BUFFER_MASK (0xf << 12) | |
| 1129 | #define CRT_VERTICAL_EXPANSION_SCALE_FACTOR_MASK 0xfff | |
| 81dee67e SM |
1130 | |
| 1131 | /* This horizontal expansion below start at 0x080268 ~ 0x08027C */ | |
| 1132 | #define CRT_HORIZONTAL_EXPANSION 0x080268 | |
| 1133 | #ifndef VALIDATION_CHIP | |
| 0d5d733b | 1134 | #define CRT_HORIZONTAL_CENTERING_VALUE_MASK (0xff << 24) |
| 81dee67e | 1135 | #endif |
| 0d5d733b MR |
1136 | #define CRT_HORIZONTAL_EXPANSION_COMPARE_VALUE_MASK (0xff << 16) |
| 1137 | #define CRT_HORIZONTAL_EXPANSION_SCALE_FACTOR_MASK 0xfff | |
| 81dee67e SM |
1138 | |
| 1139 | #ifndef VALIDATION_CHIP | |
| 1140 | /* Auto Centering */ | |
| 1141 | #define CRT_AUTO_CENTERING_TL 0x080280 | |
| 85943dae MR |
1142 | #define CRT_AUTO_CENTERING_TL_TOP_MASK (0x7ff << 16) |
| 1143 | #define CRT_AUTO_CENTERING_TL_LEFT_MASK 0x7ff | |
| 81dee67e SM |
1144 | |
| 1145 | #define CRT_AUTO_CENTERING_BR 0x080284 | |
| aed4b787 MR |
1146 | #define CRT_AUTO_CENTERING_BR_BOTTOM_MASK (0x7ff << 16) |
| 1147 | #define CRT_AUTO_CENTERING_BR_BOTTOM_SHIFT 16 | |
| 1148 | #define CRT_AUTO_CENTERING_BR_RIGHT_MASK 0x7ff | |
| 81dee67e SM |
1149 | #endif |
| 1150 | ||
| 1151 | /* sm750le new register to control panel output */ | |
| 78376535 | 1152 | #define DISPLAY_CONTROL_750LE 0x80288 |
| 81dee67e SM |
1153 | /* Palette RAM */ |
| 1154 | ||
| 69e98df7 | 1155 | /* Panel Palette register starts at 0x080400 ~ 0x0807FC */ |
| 81dee67e SM |
1156 | #define PANEL_PALETTE_RAM 0x080400 |
| 1157 | ||
| 69e98df7 | 1158 | /* Panel Palette register starts at 0x080C00 ~ 0x080FFC */ |
| 81dee67e SM |
1159 | #define CRT_PALETTE_RAM 0x080C00 |
| 1160 | ||
| 81dee67e SM |
1161 | /* Color Space Conversion registers. */ |
| 1162 | ||
| 1163 | #define CSC_Y_SOURCE_BASE 0x1000C8 | |
| 10dfcb06 MR |
1164 | #define CSC_Y_SOURCE_BASE_EXT BIT(27) |
| 1165 | #define CSC_Y_SOURCE_BASE_CS BIT(26) | |
| 0d5d733b | 1166 | #define CSC_Y_SOURCE_BASE_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
1167 | |
| 1168 | #define CSC_CONSTANTS 0x1000CC | |
| 0d5d733b MR |
1169 | #define CSC_CONSTANTS_Y_MASK (0xff << 24) |
| 1170 | #define CSC_CONSTANTS_R_MASK (0xff << 16) | |
| 1171 | #define CSC_CONSTANTS_G_MASK (0xff << 8) | |
| 1172 | #define CSC_CONSTANTS_B_MASK 0xff | |
| 81dee67e SM |
1173 | |
| 1174 | #define CSC_Y_SOURCE_X 0x1000D0 | |
| 0d5d733b MR |
1175 | #define CSC_Y_SOURCE_X_INTEGER_MASK (0x7ff << 16) |
| 1176 | #define CSC_Y_SOURCE_X_FRACTION_MASK (0x1fff << 3) | |
| 81dee67e SM |
1177 | |
| 1178 | #define CSC_Y_SOURCE_Y 0x1000D4 | |
| 0d5d733b MR |
1179 | #define CSC_Y_SOURCE_Y_INTEGER_MASK (0xfff << 16) |
| 1180 | #define CSC_Y_SOURCE_Y_FRACTION_MASK (0x1fff << 3) | |
| 81dee67e SM |
1181 | |
| 1182 | #define CSC_U_SOURCE_BASE 0x1000D8 | |
| 10dfcb06 MR |
1183 | #define CSC_U_SOURCE_BASE_EXT BIT(27) |
| 1184 | #define CSC_U_SOURCE_BASE_CS BIT(26) | |
| 0d5d733b | 1185 | #define CSC_U_SOURCE_BASE_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
1186 | |
| 1187 | #define CSC_V_SOURCE_BASE 0x1000DC | |
| 10dfcb06 MR |
1188 | #define CSC_V_SOURCE_BASE_EXT BIT(27) |
| 1189 | #define CSC_V_SOURCE_BASE_CS BIT(26) | |
| 0d5d733b | 1190 | #define CSC_V_SOURCE_BASE_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
1191 | |
| 1192 | #define CSC_SOURCE_DIMENSION 0x1000E0 | |
| 0d5d733b MR |
1193 | #define CSC_SOURCE_DIMENSION_X_MASK (0xffff << 16) |
| 1194 | #define CSC_SOURCE_DIMENSION_Y_MASK 0xffff | |
| 81dee67e SM |
1195 | |
| 1196 | #define CSC_SOURCE_PITCH 0x1000E4 | |
| 0d5d733b MR |
1197 | #define CSC_SOURCE_PITCH_Y_MASK (0xffff << 16) |
| 1198 | #define CSC_SOURCE_PITCH_UV_MASK 0xffff | |
| 81dee67e SM |
1199 | |
| 1200 | #define CSC_DESTINATION 0x1000E8 | |
| 10dfcb06 | 1201 | #define CSC_DESTINATION_WRAP BIT(31) |
| 0d5d733b MR |
1202 | #define CSC_DESTINATION_X_MASK (0xfff << 16) |
| 1203 | #define CSC_DESTINATION_Y_MASK 0xfff | |
| 81dee67e SM |
1204 | |
| 1205 | #define CSC_DESTINATION_DIMENSION 0x1000EC | |
| 0d5d733b MR |
1206 | #define CSC_DESTINATION_DIMENSION_X_MASK (0xffff << 16) |
| 1207 | #define CSC_DESTINATION_DIMENSION_Y_MASK 0xffff | |
| 81dee67e SM |
1208 | |
| 1209 | #define CSC_DESTINATION_PITCH 0x1000F0 | |
| 0d5d733b MR |
1210 | #define CSC_DESTINATION_PITCH_X_MASK (0xffff << 16) |
| 1211 | #define CSC_DESTINATION_PITCH_Y_MASK 0xffff | |
| 81dee67e SM |
1212 | |
| 1213 | #define CSC_SCALE_FACTOR 0x1000F4 | |
| 0d5d733b MR |
1214 | #define CSC_SCALE_FACTOR_HORIZONTAL_MASK (0xffff << 16) |
| 1215 | #define CSC_SCALE_FACTOR_VERTICAL_MASK 0xffff | |
| 81dee67e SM |
1216 | |
| 1217 | #define CSC_DESTINATION_BASE 0x1000F8 | |
| 10dfcb06 MR |
1218 | #define CSC_DESTINATION_BASE_EXT BIT(27) |
| 1219 | #define CSC_DESTINATION_BASE_CS BIT(26) | |
| 0d5d733b | 1220 | #define CSC_DESTINATION_BASE_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
1221 | |
| 1222 | #define CSC_CONTROL 0x1000FC | |
| 10dfcb06 | 1223 | #define CSC_CONTROL_STATUS BIT(31) |
| 0d5d733b MR |
1224 | #define CSC_CONTROL_SOURCE_FORMAT_MASK (0x7 << 28) |
| 1225 | #define CSC_CONTROL_SOURCE_FORMAT_YUV422 (0x0 << 28) | |
| 1226 | #define CSC_CONTROL_SOURCE_FORMAT_YUV420I (0x1 << 28) | |
| 1227 | #define CSC_CONTROL_SOURCE_FORMAT_YUV420 (0x2 << 28) | |
| 1228 | #define CSC_CONTROL_SOURCE_FORMAT_YVU9 (0x3 << 28) | |
| 1229 | #define CSC_CONTROL_SOURCE_FORMAT_IYU1 (0x4 << 28) | |
| 1230 | #define CSC_CONTROL_SOURCE_FORMAT_IYU2 (0x5 << 28) | |
| 1231 | #define CSC_CONTROL_SOURCE_FORMAT_RGB565 (0x6 << 28) | |
| 1232 | #define CSC_CONTROL_SOURCE_FORMAT_RGB8888 (0x7 << 28) | |
| 1233 | #define CSC_CONTROL_DESTINATION_FORMAT_MASK (0x3 << 26) | |
| 1234 | #define CSC_CONTROL_DESTINATION_FORMAT_RGB565 (0x0 << 26) | |
| 1235 | #define CSC_CONTROL_DESTINATION_FORMAT_RGB8888 (0x1 << 26) | |
| 10dfcb06 MR |
1236 | #define CSC_CONTROL_HORIZONTAL_FILTER BIT(25) |
| 1237 | #define CSC_CONTROL_VERTICAL_FILTER BIT(24) | |
| 1238 | #define CSC_CONTROL_BYTE_ORDER BIT(23) | |
| 81dee67e SM |
1239 | |
| 1240 | #define DE_DATA_PORT 0x110000 | |
| 1241 | ||
| 1242 | #define I2C_BYTE_COUNT 0x010040 | |
| 0d5d733b | 1243 | #define I2C_BYTE_COUNT_COUNT_MASK 0xf |
| 81dee67e SM |
1244 | |
| 1245 | #define I2C_CTRL 0x010041 | |
| b71413e0 MR |
1246 | #define I2C_CTRL_INT BIT(4) |
| 1247 | #define I2C_CTRL_DIR BIT(3) | |
| 1248 | #define I2C_CTRL_CTRL BIT(2) | |
| 1249 | #define I2C_CTRL_MODE BIT(1) | |
| 1250 | #define I2C_CTRL_EN BIT(0) | |
| 81dee67e SM |
1251 | |
| 1252 | #define I2C_STATUS 0x010042 | |
| 3e155b81 MR |
1253 | #define I2C_STATUS_TX BIT(3) |
| 1254 | #define I2C_STATUS_ERR BIT(2) | |
| 1255 | #define I2C_STATUS_ACK BIT(1) | |
| 1256 | #define I2C_STATUS_BSY BIT(0) | |
| 81dee67e SM |
1257 | |
| 1258 | #define I2C_RESET 0x010042 | |
| 10dfcb06 | 1259 | #define I2C_RESET_BUS_ERROR BIT(2) |
| 81dee67e SM |
1260 | |
| 1261 | #define I2C_SLAVE_ADDRESS 0x010043 | |
| 0d5d733b | 1262 | #define I2C_SLAVE_ADDRESS_ADDRESS_MASK (0x7f << 1) |
| 10dfcb06 | 1263 | #define I2C_SLAVE_ADDRESS_RW BIT(0) |
| 81dee67e SM |
1264 | |
| 1265 | #define I2C_DATA0 0x010044 | |
| 1266 | #define I2C_DATA1 0x010045 | |
| 1267 | #define I2C_DATA2 0x010046 | |
| 1268 | #define I2C_DATA3 0x010047 | |
| 1269 | #define I2C_DATA4 0x010048 | |
| 1270 | #define I2C_DATA5 0x010049 | |
| 1271 | #define I2C_DATA6 0x01004A | |
| 1272 | #define I2C_DATA7 0x01004B | |
| 1273 | #define I2C_DATA8 0x01004C | |
| 1274 | #define I2C_DATA9 0x01004D | |
| 1275 | #define I2C_DATA10 0x01004E | |
| 1276 | #define I2C_DATA11 0x01004F | |
| 1277 | #define I2C_DATA12 0x010050 | |
| 1278 | #define I2C_DATA13 0x010051 | |
| 1279 | #define I2C_DATA14 0x010052 | |
| 1280 | #define I2C_DATA15 0x010053 | |
| 1281 | ||
| 1282 | ||
| 1283 | #define ZV0_CAPTURE_CTRL 0x090000 | |
| 10dfcb06 MR |
1284 | #define ZV0_CAPTURE_CTRL_FIELD_INPUT BIT(27) |
| 1285 | #define ZV0_CAPTURE_CTRL_SCAN BIT(26) | |
| 1286 | #define ZV0_CAPTURE_CTRL_CURRENT_BUFFER BIT(25) | |
| 1287 | #define ZV0_CAPTURE_CTRL_VERTICAL_SYNC BIT(24) | |
| 1288 | #define ZV0_CAPTURE_CTRL_ADJ BIT(19) | |
| 1289 | #define ZV0_CAPTURE_CTRL_HA BIT(18) | |
| 1290 | #define ZV0_CAPTURE_CTRL_VSK BIT(17) | |
| 1291 | #define ZV0_CAPTURE_CTRL_HSK BIT(16) | |
| 1292 | #define ZV0_CAPTURE_CTRL_FD BIT(15) | |
| 1293 | #define ZV0_CAPTURE_CTRL_VP BIT(14) | |
| 1294 | #define ZV0_CAPTURE_CTRL_HP BIT(13) | |
| 1295 | #define ZV0_CAPTURE_CTRL_CP BIT(12) | |
| 1296 | #define ZV0_CAPTURE_CTRL_UVS BIT(11) | |
| 1297 | #define ZV0_CAPTURE_CTRL_BS BIT(10) | |
| 1298 | #define ZV0_CAPTURE_CTRL_CS BIT(9) | |
| 1299 | #define ZV0_CAPTURE_CTRL_CF BIT(8) | |
| 1300 | #define ZV0_CAPTURE_CTRL_FS BIT(7) | |
| 1301 | #define ZV0_CAPTURE_CTRL_WEAVE BIT(6) | |
| 1302 | #define ZV0_CAPTURE_CTRL_BOB BIT(5) | |
| 1303 | #define ZV0_CAPTURE_CTRL_DB BIT(4) | |
| 1304 | #define ZV0_CAPTURE_CTRL_CC BIT(3) | |
| 1305 | #define ZV0_CAPTURE_CTRL_RGB BIT(2) | |
| 1306 | #define ZV0_CAPTURE_CTRL_656 BIT(1) | |
| 1307 | #define ZV0_CAPTURE_CTRL_CAP BIT(0) | |
| 81dee67e SM |
1308 | |
| 1309 | #define ZV0_CAPTURE_CLIP 0x090004 | |
| 0d5d733b MR |
1310 | #define ZV0_CAPTURE_CLIP_EYCLIP_MASK (0x3ff << 16) |
| 1311 | #define ZV0_CAPTURE_CLIP_XCLIP_MASK 0x3ff | |
| 81dee67e SM |
1312 | |
| 1313 | #define ZV0_CAPTURE_SIZE 0x090008 | |
| 0d5d733b MR |
1314 | #define ZV0_CAPTURE_SIZE_HEIGHT_MASK (0x7ff << 16) |
| 1315 | #define ZV0_CAPTURE_SIZE_WIDTH_MASK 0x7ff | |
| 81dee67e SM |
1316 | |
| 1317 | #define ZV0_CAPTURE_BUF0_ADDRESS 0x09000C | |
| 10dfcb06 MR |
1318 | #define ZV0_CAPTURE_BUF0_ADDRESS_STATUS BIT(31) |
| 1319 | #define ZV0_CAPTURE_BUF0_ADDRESS_EXT BIT(27) | |
| 1320 | #define ZV0_CAPTURE_BUF0_ADDRESS_CS BIT(26) | |
| 0d5d733b | 1321 | #define ZV0_CAPTURE_BUF0_ADDRESS_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
1322 | |
| 1323 | #define ZV0_CAPTURE_BUF1_ADDRESS 0x090010 | |
| 10dfcb06 MR |
1324 | #define ZV0_CAPTURE_BUF1_ADDRESS_STATUS BIT(31) |
| 1325 | #define ZV0_CAPTURE_BUF1_ADDRESS_EXT BIT(27) | |
| 1326 | #define ZV0_CAPTURE_BUF1_ADDRESS_CS BIT(26) | |
| 0d5d733b | 1327 | #define ZV0_CAPTURE_BUF1_ADDRESS_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
1328 | |
| 1329 | #define ZV0_CAPTURE_BUF_OFFSET 0x090014 | |
| 1330 | #ifndef VALIDATION_CHIP | |
| 0d5d733b | 1331 | #define ZV0_CAPTURE_BUF_OFFSET_YCLIP_ODD_FIELD (0x3ff << 16) |
| 81dee67e | 1332 | #endif |
| 0d5d733b | 1333 | #define ZV0_CAPTURE_BUF_OFFSET_OFFSET_MASK 0xffff |
| 81dee67e SM |
1334 | |
| 1335 | #define ZV0_CAPTURE_FIFO_CTRL 0x090018 | |
| 0d5d733b | 1336 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_MASK 0x7 |
| 81dee67e SM |
1337 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_0 0 |
| 1338 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_1 1 | |
| 1339 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_2 2 | |
| 1340 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_3 3 | |
| 1341 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_4 4 | |
| 1342 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_5 5 | |
| 1343 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_6 6 | |
| 1344 | #define ZV0_CAPTURE_FIFO_CTRL_FIFO_7 7 | |
| 1345 | ||
| 1346 | #define ZV0_CAPTURE_YRGB_CONST 0x09001C | |
| 0d5d733b MR |
1347 | #define ZV0_CAPTURE_YRGB_CONST_Y_MASK (0xff << 24) |
| 1348 | #define ZV0_CAPTURE_YRGB_CONST_R_MASK (0xff << 16) | |
| 1349 | #define ZV0_CAPTURE_YRGB_CONST_G_MASK (0xff << 8) | |
| 1350 | #define ZV0_CAPTURE_YRGB_CONST_B_MASK 0xff | |
| 81dee67e SM |
1351 | |
| 1352 | #define ZV0_CAPTURE_LINE_COMP 0x090020 | |
| 0d5d733b | 1353 | #define ZV0_CAPTURE_LINE_COMP_LC_MASK 0x7ff |
| 81dee67e SM |
1354 | |
| 1355 | /* ZV1 */ | |
| 1356 | ||
| 1357 | #define ZV1_CAPTURE_CTRL 0x098000 | |
| 10dfcb06 MR |
1358 | #define ZV1_CAPTURE_CTRL_FIELD_INPUT BIT(27) |
| 1359 | #define ZV1_CAPTURE_CTRL_SCAN BIT(26) | |
| 1360 | #define ZV1_CAPTURE_CTRL_CURRENT_BUFFER BIT(25) | |
| 1361 | #define ZV1_CAPTURE_CTRL_VERTICAL_SYNC BIT(24) | |
| 1362 | #define ZV1_CAPTURE_CTRL_PANEL BIT(20) | |
| 1363 | #define ZV1_CAPTURE_CTRL_ADJ BIT(19) | |
| 1364 | #define ZV1_CAPTURE_CTRL_HA BIT(18) | |
| 1365 | #define ZV1_CAPTURE_CTRL_VSK BIT(17) | |
| 1366 | #define ZV1_CAPTURE_CTRL_HSK BIT(16) | |
| 1367 | #define ZV1_CAPTURE_CTRL_FD BIT(15) | |
| 1368 | #define ZV1_CAPTURE_CTRL_VP BIT(14) | |
| 1369 | #define ZV1_CAPTURE_CTRL_HP BIT(13) | |
| 1370 | #define ZV1_CAPTURE_CTRL_CP BIT(12) | |
| 1371 | #define ZV1_CAPTURE_CTRL_UVS BIT(11) | |
| 1372 | #define ZV1_CAPTURE_CTRL_BS BIT(10) | |
| 1373 | #define ZV1_CAPTURE_CTRL_CS BIT(9) | |
| 1374 | #define ZV1_CAPTURE_CTRL_CF BIT(8) | |
| 1375 | #define ZV1_CAPTURE_CTRL_FS BIT(7) | |
| 1376 | #define ZV1_CAPTURE_CTRL_WEAVE BIT(6) | |
| 1377 | #define ZV1_CAPTURE_CTRL_BOB BIT(5) | |
| 1378 | #define ZV1_CAPTURE_CTRL_DB BIT(4) | |
| 1379 | #define ZV1_CAPTURE_CTRL_CC BIT(3) | |
| 1380 | #define ZV1_CAPTURE_CTRL_RGB BIT(2) | |
| 1381 | #define ZV1_CAPTURE_CTRL_656 BIT(1) | |
| 1382 | #define ZV1_CAPTURE_CTRL_CAP BIT(0) | |
| 81dee67e SM |
1383 | |
| 1384 | #define ZV1_CAPTURE_CLIP 0x098004 | |
| 0d5d733b MR |
1385 | #define ZV1_CAPTURE_CLIP_YCLIP_MASK (0x3ff << 16) |
| 1386 | #define ZV1_CAPTURE_CLIP_XCLIP_MASK 0x3ff | |
| 81dee67e SM |
1387 | |
| 1388 | #define ZV1_CAPTURE_SIZE 0x098008 | |
| 0d5d733b MR |
1389 | #define ZV1_CAPTURE_SIZE_HEIGHT_MASK (0x7ff << 16) |
| 1390 | #define ZV1_CAPTURE_SIZE_WIDTH_MASK 0x7ff | |
| 81dee67e SM |
1391 | |
| 1392 | #define ZV1_CAPTURE_BUF0_ADDRESS 0x09800C | |
| 10dfcb06 MR |
1393 | #define ZV1_CAPTURE_BUF0_ADDRESS_STATUS BIT(31) |
| 1394 | #define ZV1_CAPTURE_BUF0_ADDRESS_EXT BIT(27) | |
| 1395 | #define ZV1_CAPTURE_BUF0_ADDRESS_CS BIT(26) | |
| 0d5d733b | 1396 | #define ZV1_CAPTURE_BUF0_ADDRESS_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
1397 | |
| 1398 | #define ZV1_CAPTURE_BUF1_ADDRESS 0x098010 | |
| 10dfcb06 MR |
1399 | #define ZV1_CAPTURE_BUF1_ADDRESS_STATUS BIT(31) |
| 1400 | #define ZV1_CAPTURE_BUF1_ADDRESS_EXT BIT(27) | |
| 1401 | #define ZV1_CAPTURE_BUF1_ADDRESS_CS BIT(26) | |
| 0d5d733b | 1402 | #define ZV1_CAPTURE_BUF1_ADDRESS_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
1403 | |
| 1404 | #define ZV1_CAPTURE_BUF_OFFSET 0x098014 | |
| 0d5d733b | 1405 | #define ZV1_CAPTURE_BUF_OFFSET_OFFSET_MASK 0xffff |
| 81dee67e SM |
1406 | |
| 1407 | #define ZV1_CAPTURE_FIFO_CTRL 0x098018 | |
| 0d5d733b | 1408 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_MASK 0x7 |
| 81dee67e SM |
1409 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_0 0 |
| 1410 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_1 1 | |
| 1411 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_2 2 | |
| 1412 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_3 3 | |
| 1413 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_4 4 | |
| 1414 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_5 5 | |
| 1415 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_6 6 | |
| 1416 | #define ZV1_CAPTURE_FIFO_CTRL_FIFO_7 7 | |
| 1417 | ||
| 1418 | #define ZV1_CAPTURE_YRGB_CONST 0x09801C | |
| 0d5d733b MR |
1419 | #define ZV1_CAPTURE_YRGB_CONST_Y_MASK (0xff << 24) |
| 1420 | #define ZV1_CAPTURE_YRGB_CONST_R_MASK (0xff << 16) | |
| 1421 | #define ZV1_CAPTURE_YRGB_CONST_G_MASK (0xff << 8) | |
| 1422 | #define ZV1_CAPTURE_YRGB_CONST_B_MASK 0xff | |
| 81dee67e SM |
1423 | |
| 1424 | #define DMA_1_SOURCE 0x0D0010 | |
| 10dfcb06 MR |
1425 | #define DMA_1_SOURCE_ADDRESS_EXT BIT(27) |
| 1426 | #define DMA_1_SOURCE_ADDRESS_CS BIT(26) | |
| 0d5d733b | 1427 | #define DMA_1_SOURCE_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
1428 | |
| 1429 | #define DMA_1_DESTINATION 0x0D0014 | |
| 10dfcb06 MR |
1430 | #define DMA_1_DESTINATION_ADDRESS_EXT BIT(27) |
| 1431 | #define DMA_1_DESTINATION_ADDRESS_CS BIT(26) | |
| 0d5d733b | 1432 | #define DMA_1_DESTINATION_ADDRESS_MASK 0x3ffffff |
| 81dee67e SM |
1433 | |
| 1434 | #define DMA_1_SIZE_CONTROL 0x0D0018 | |
| 10dfcb06 | 1435 | #define DMA_1_SIZE_CONTROL_STATUS BIT(31) |
| 0d5d733b | 1436 | #define DMA_1_SIZE_CONTROL_SIZE_MASK 0xffffff |
| 81dee67e SM |
1437 | |
| 1438 | #define DMA_ABORT_INTERRUPT 0x0D0020 | |
| 0f23be70 MR |
1439 | #define DMA_ABORT_INTERRUPT_ABORT_1 BIT(5) |
| 1440 | #define DMA_ABORT_INTERRUPT_ABORT_0 BIT(4) | |
| 1441 | #define DMA_ABORT_INTERRUPT_INT_1 BIT(1) | |
| 1442 | #define DMA_ABORT_INTERRUPT_INT_0 BIT(0) | |
| 81dee67e SM |
1443 | |
| 1444 | /* Default i2c CLK and Data GPIO. These are the default i2c pins */ | |
| 1445 | #define DEFAULT_I2C_SCL 30 | |
| 1446 | #define DEFAULT_I2C_SDA 31 | |
| 1447 | ||
| 1448 | ||
| 1449 | #define GPIO_DATA_SM750LE 0x020018 | |
| 10dfcb06 MR |
1450 | #define GPIO_DATA_SM750LE_1 BIT(1) |
| 1451 | #define GPIO_DATA_SM750LE_0 BIT(0) | |
| 81dee67e SM |
1452 | |
| 1453 | #define GPIO_DATA_DIRECTION_SM750LE 0x02001C | |
| 10dfcb06 MR |
1454 | #define GPIO_DATA_DIRECTION_SM750LE_1 BIT(1) |
| 1455 | #define GPIO_DATA_DIRECTION_SM750LE_0 BIT(0) | |
| 81dee67e SM |
1456 | |
| 1457 | ||
| 1458 | #endif |