Commit | Line | Data |
---|---|---|
efe9bc08 | 1 | #include "ddk750_chip.h" |
81dee67e SM |
2 | #include "ddk750_reg.h" |
3 | #include "ddk750_power.h" | |
4 | ||
03140dab | 5 | void ddk750_set_dpms(DPMS_t state) |
81dee67e SM |
6 | { |
7 | unsigned int value; | |
40403c1b | 8 | |
06a4f429 | 9 | if (sm750_get_chip_type() == SM750LE) { |
c075b6f2 | 10 | value = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_DPMS_MASK; |
cdce1f18 | 11 | value |= (state << CRT_DISPLAY_CTRL_DPMS_SHIFT); |
c075b6f2 | 12 | poke32(CRT_DISPLAY_CTRL, value); |
6338a781 | 13 | } else { |
c075b6f2 | 14 | value = peek32(SYSTEM_CTRL); |
a8856ff8 | 15 | value = (value & ~SYSTEM_CTRL_DPMS_MASK) | state; |
c075b6f2 | 16 | poke32(SYSTEM_CTRL, value); |
81dee67e SM |
17 | } |
18 | } | |
19 | ||
03140dab | 20 | static unsigned int get_power_mode(void) |
81dee67e | 21 | { |
06a4f429 | 22 | if (sm750_get_chip_type() == SM750LE) |
81dee67e | 23 | return 0; |
c075b6f2 | 24 | return peek32(POWER_MODE_CTRL) & POWER_MODE_CTRL_MODE_MASK; |
81dee67e SM |
25 | } |
26 | ||
81dee67e SM |
27 | /* |
28 | * SM50x can operate in one of three modes: 0, 1 or Sleep. | |
29 | * On hardware reset, power mode 0 is default. | |
30 | */ | |
52d0744d | 31 | void sm750_set_power_mode(unsigned int mode) |
81dee67e | 32 | { |
c2b6028f | 33 | unsigned int ctrl = 0; |
81dee67e | 34 | |
c075b6f2 | 35 | ctrl = peek32(POWER_MODE_CTRL) & ~POWER_MODE_CTRL_MODE_MASK; |
81dee67e | 36 | |
06a4f429 | 37 | if (sm750_get_chip_type() == SM750LE) |
81dee67e SM |
38 | return; |
39 | ||
c2b6028f | 40 | switch (mode) { |
78376535 | 41 | case POWER_MODE_CTRL_MODE_MODE0: |
c2b6028f | 42 | ctrl |= POWER_MODE_CTRL_MODE_MODE0; |
78376535 | 43 | break; |
81dee67e | 44 | |
78376535 | 45 | case POWER_MODE_CTRL_MODE_MODE1: |
c2b6028f | 46 | ctrl |= POWER_MODE_CTRL_MODE_MODE1; |
78376535 | 47 | break; |
81dee67e | 48 | |
78376535 | 49 | case POWER_MODE_CTRL_MODE_SLEEP: |
c2b6028f | 50 | ctrl |= POWER_MODE_CTRL_MODE_SLEEP; |
78376535 | 51 | break; |
81dee67e | 52 | |
78376535 JL |
53 | default: |
54 | break; | |
55 | } | |
81dee67e | 56 | |
78376535 | 57 | /* Set up other fields in Power Control Register */ |
c2b6028f EL |
58 | if (mode == POWER_MODE_CTRL_MODE_SLEEP) { |
59 | ctrl &= ~POWER_MODE_CTRL_OSC_INPUT; | |
81dee67e | 60 | #ifdef VALIDATION_CHIP |
c2b6028f | 61 | ctrl &= ~POWER_MODE_CTRL_336CLK; |
81dee67e | 62 | #endif |
259fef35 | 63 | } else { |
c2b6028f | 64 | ctrl |= POWER_MODE_CTRL_OSC_INPUT; |
81dee67e | 65 | #ifdef VALIDATION_CHIP |
c2b6028f | 66 | ctrl |= POWER_MODE_CTRL_336CLK; |
81dee67e | 67 | #endif |
78376535 | 68 | } |
81dee67e | 69 | |
78376535 | 70 | /* Program new power mode. */ |
c075b6f2 | 71 | poke32(POWER_MODE_CTRL, ctrl); |
81dee67e SM |
72 | } |
73 | ||
52d0744d | 74 | void sm750_set_current_gate(unsigned int gate) |
81dee67e | 75 | { |
03140dab | 76 | if (get_power_mode() == POWER_MODE_CTRL_MODE_MODE1) |
c075b6f2 | 77 | poke32(MODE1_GATE, gate); |
cefc2fc6 | 78 | else |
c075b6f2 | 79 | poke32(MODE0_GATE, gate); |
81dee67e SM |
80 | } |
81 | ||
81dee67e SM |
82 | /* |
83 | * This function enable/disable the 2D engine. | |
84 | */ | |
52d0744d | 85 | void sm750_enable_2d_engine(unsigned int enable) |
81dee67e | 86 | { |
f741554e | 87 | u32 gate; |
78376535 | 88 | |
c075b6f2 | 89 | gate = peek32(CURRENT_GATE); |
69988ba2 | 90 | if (enable) |
90946e52 | 91 | gate |= (CURRENT_GATE_DE | CURRENT_GATE_CSC); |
69988ba2 | 92 | else |
90946e52 | 93 | gate &= ~(CURRENT_GATE_DE | CURRENT_GATE_CSC); |
78376535 | 94 | |
52d0744d | 95 | sm750_set_current_gate(gate); |
81dee67e SM |
96 | } |
97 | ||
52d0744d | 98 | void sm750_enable_dma(unsigned int enable) |
81dee67e | 99 | { |
f741554e | 100 | u32 gate; |
81dee67e | 101 | |
78376535 | 102 | /* Enable DMA Gate */ |
c075b6f2 | 103 | gate = peek32(CURRENT_GATE); |
78376535 | 104 | if (enable) |
90946e52 | 105 | gate |= CURRENT_GATE_DMA; |
78376535 | 106 | else |
90946e52 | 107 | gate &= ~CURRENT_GATE_DMA; |
81dee67e | 108 | |
52d0744d | 109 | sm750_set_current_gate(gate); |
81dee67e SM |
110 | } |
111 | ||
112 | /* | |
113 | * This function enable/disable the GPIO Engine | |
114 | */ | |
52d0744d | 115 | void sm750_enable_gpio(unsigned int enable) |
81dee67e | 116 | { |
f741554e | 117 | u32 gate; |
81dee67e | 118 | |
78376535 | 119 | /* Enable GPIO Gate */ |
c075b6f2 | 120 | gate = peek32(CURRENT_GATE); |
78376535 | 121 | if (enable) |
90946e52 | 122 | gate |= CURRENT_GATE_GPIO; |
78376535 | 123 | else |
90946e52 | 124 | gate &= ~CURRENT_GATE_GPIO; |
81dee67e | 125 | |
52d0744d | 126 | sm750_set_current_gate(gate); |
81dee67e SM |
127 | } |
128 | ||
81dee67e SM |
129 | /* |
130 | * This function enable/disable the I2C Engine | |
131 | */ | |
52d0744d | 132 | void sm750_enable_i2c(unsigned int enable) |
81dee67e | 133 | { |
f741554e | 134 | u32 gate; |
81dee67e | 135 | |
78376535 | 136 | /* Enable I2C Gate */ |
c075b6f2 | 137 | gate = peek32(CURRENT_GATE); |
78376535 | 138 | if (enable) |
90946e52 | 139 | gate |= CURRENT_GATE_I2C; |
78376535 | 140 | else |
90946e52 | 141 | gate &= ~CURRENT_GATE_I2C; |
81dee67e | 142 | |
52d0744d | 143 | sm750_set_current_gate(gate); |
81dee67e | 144 | } |