projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 81dee67e SM |
2 | #ifndef DDK750_CHIP_H__ |
| 3 | #define DDK750_CHIP_H__ | |
| 4 | #define DEFAULT_INPUT_CLOCK 14318181 /* Default reference clock */ | |
| 62fa8e10 SM |
5 | #ifndef SM750LE_REVISION_ID |
| 6 | #define SM750LE_REVISION_ID ((unsigned char)0xfe) | |
| 7 | #endif | |
| 81dee67e | 8 | |
| f8b0dced | 9 | #include <linux/io.h> |
| efe9bc08 EL |
10 | #include <linux/ioport.h> |
| 11 | #include <linux/uaccess.h> | |
| 12 | ||
| c075b6f2 MS |
13 | extern void __iomem *mmio750; |
| 14 | ||
| efe9bc08 | 15 | /* software control endianness */ |
| c075b6f2 MS |
16 | static inline u32 peek32(u32 addr) |
| 17 | { | |
| 18 | return readl(addr + mmio750); | |
| 19 | } | |
| efe9bc08 | 20 | |
| 16808dcf | 21 | static inline void poke32(u32 addr, u32 data) |
| c075b6f2 MS |
22 | { |
| 23 | writel(data, addr + mmio750); | |
| 24 | } | |
| f8b0dced | 25 | |
| 81dee67e | 26 | /* This is all the chips recognized by this library */ |
| 17eb0b29 | 27 | enum logical_chip_type { |
| 63de0eb0 IA |
28 | SM_UNKNOWN, |
| 29 | SM718, | |
| 30 | SM750, | |
| 31 | SM750LE, | |
| 17eb0b29 | 32 | }; |
| 81dee67e | 33 | |
| 17eb0b29 | 34 | enum clock_type { |
| 81dee67e SM |
35 | MXCLK_PLL, |
| 36 | PRIMARY_PLL, | |
| 37 | SECONDARY_PLL, | |
| 38 | VGA0_PLL, | |
| 39 | VGA1_PLL, | |
| 17eb0b29 | 40 | }; |
| 81dee67e | 41 | |
| 9872fa75 | 42 | struct pll_value { |
| 8635b4c4 IT |
43 | enum clock_type clock_type; |
| 44 | unsigned long input_freq; /* Input clock frequency to the PLL */ | |
| 81dee67e | 45 | |
| 63de0eb0 IA |
46 | /* Use this when clockType = PANEL_PLL */ |
| 47 | unsigned long M; | |
| 48 | unsigned long N; | |
| 49 | unsigned long OD; | |
| 50 | unsigned long POD; | |
| 9872fa75 | 51 | }; |
| 81dee67e SM |
52 | |
| 53 | /* input struct to initChipParam() function */ | |
| 9872fa75 | 54 | struct initchip_param { |
| f5016082 | 55 | /* Use power mode 0 or 1 */ |
| 8635b4c4 | 56 | unsigned short power_mode; |
| f5016082 ES |
57 | |
| 58 | /* | |
| 59 | * Speed of main chip clock in MHz unit | |
| 60 | * 0 = keep the current clock setting | |
| 61 | * Others = the new main chip clock | |
| 62 | */ | |
| 8635b4c4 | 63 | unsigned short chip_clock; |
| f5016082 ES |
64 | |
| 65 | /* | |
| 66 | * Speed of memory clock in MHz unit | |
| 67 | * 0 = keep the current clock setting | |
| 68 | * Others = the new memory clock | |
| 69 | */ | |
| 8635b4c4 | 70 | unsigned short mem_clock; |
| f5016082 ES |
71 | |
| 72 | /* | |
| 73 | * Speed of master clock in MHz unit | |
| 74 | * 0 = keep the current clock setting | |
| 75 | * Others = the new master clock | |
| 76 | */ | |
| 8635b4c4 | 77 | unsigned short master_clock; |
| f5016082 ES |
78 | |
| 79 | /* | |
| 80 | * 0 = leave all engine state untouched. | |
| 81 | * 1 = make sure they are off: 2D, Overlay, | |
| 82 | * video alpha, alpha, hardware cursors | |
| 83 | */ | |
| 8635b4c4 | 84 | unsigned short set_all_eng_off; |
| f5016082 ES |
85 | |
| 86 | /* | |
| 87 | * 0 = Do not reset the memory controller | |
| 88 | * 1 = Reset the memory controller | |
| 89 | */ | |
| 8635b4c4 | 90 | unsigned char reset_memory; |
| 81dee67e | 91 | |
| 63de0eb0 | 92 | /* More initialization parameter can be added if needed */ |
| 9872fa75 | 93 | }; |
| 81dee67e | 94 | |
| 17eb0b29 | 95 | enum logical_chip_type sm750_get_chip_type(void); |
| de5e4aea | 96 | void sm750_set_chip_type(unsigned short dev_id, u8 rev_id); |
| 52d0744d | 97 | unsigned int sm750_calc_pll_value(unsigned int request, struct pll_value *pll); |
| 8635b4c4 | 98 | unsigned int sm750_format_pll_reg(struct pll_value *p_PLL); |
| 3fcb465f | 99 | unsigned int ddk750_get_vm_size(void); |
| 47c565ea | 100 | int ddk750_init_hw(struct initchip_param *pinit_param); |
| 81dee67e | 101 | |
| 81dee67e | 102 | #endif |