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staging: rts_pstor: delete a function
[linux-2.6-block.git] / drivers / staging / rts_pstor / sd.c
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77d89b08 1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/blkdev.h>
24#include <linux/kthread.h>
25#include <linux/sched.h>
26
27#include "rtsx.h"
28#include "rtsx_transport.h"
29#include "rtsx_scsi.h"
30#include "rtsx_card.h"
31#include "sd.h"
32
33#define SD_MAX_RETRY_COUNT 3
34
35u16 REG_SD_CFG1;
36u16 REG_SD_CFG2;
37u16 REG_SD_CFG3;
38u16 REG_SD_STAT1;
39u16 REG_SD_STAT2;
40u16 REG_SD_BUS_STAT;
41u16 REG_SD_PAD_CTL;
42u16 REG_SD_SAMPLE_POINT_CTL;
43u16 REG_SD_PUSH_POINT_CTL;
44u16 REG_SD_CMD0;
45u16 REG_SD_CMD1;
46u16 REG_SD_CMD2;
47u16 REG_SD_CMD3;
48u16 REG_SD_CMD4;
49u16 REG_SD_CMD5;
50u16 REG_SD_BYTE_CNT_L;
51u16 REG_SD_BYTE_CNT_H;
52u16 REG_SD_BLOCK_CNT_L;
53u16 REG_SD_BLOCK_CNT_H;
54u16 REG_SD_TRANSFER;
55u16 REG_SD_VPCLK0_CTL;
56u16 REG_SD_VPCLK1_CTL;
57u16 REG_SD_DCMPS0_CTL;
58u16 REG_SD_DCMPS1_CTL;
59
60static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code)
61{
62 struct sd_info *sd_card = &(chip->sd_card);
63
64 sd_card->err_code |= err_code;
65}
66
67static inline void sd_clr_err_code(struct rtsx_chip *chip)
68{
69 struct sd_info *sd_card = &(chip->sd_card);
70
71 sd_card->err_code = 0;
72}
73
74static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code)
75{
76 struct sd_info *sd_card = &(chip->sd_card);
77
78 return sd_card->err_code & err_code;
79}
80
81static void sd_init_reg_addr(struct rtsx_chip *chip)
82{
83 if (CHECK_PID(chip, 0x5209)) {
84 REG_SD_CFG1 = SD_CFG1;
85 REG_SD_CFG2 = SD_CFG2;
86 REG_SD_CFG3 = SD_CFG3;
87 REG_SD_STAT1 = SD_STAT1;
88 REG_SD_STAT2 = SD_STAT2;
89 REG_SD_BUS_STAT = SD_BUS_STAT;
90 REG_SD_PAD_CTL = SD_PAD_CTL;
91 REG_SD_SAMPLE_POINT_CTL = SD_SAMPLE_POINT_CTL;
92 REG_SD_PUSH_POINT_CTL = SD_PUSH_POINT_CTL;
93 REG_SD_CMD0 = SD_CMD0;
94 REG_SD_CMD1 = SD_CMD1;
95 REG_SD_CMD2 = SD_CMD2;
96 REG_SD_CMD3 = SD_CMD3;
97 REG_SD_CMD4 = SD_CMD4;
98 REG_SD_CMD5 = SD_CMD5;
99 REG_SD_BYTE_CNT_L = SD_BYTE_CNT_L;
100 REG_SD_BYTE_CNT_H = SD_BYTE_CNT_H;
101 REG_SD_BLOCK_CNT_L = SD_BLOCK_CNT_L;
102 REG_SD_BLOCK_CNT_H = SD_BLOCK_CNT_H;
103 REG_SD_TRANSFER = SD_TRANSFER;
104 REG_SD_VPCLK0_CTL = SD_VPCLK0_CTL;
105 REG_SD_VPCLK1_CTL = SD_VPCLK1_CTL;
106 REG_SD_DCMPS0_CTL = SD_DCMPS0_CTL;
107 REG_SD_DCMPS1_CTL = SD_DCMPS1_CTL;
108 } else {
109 REG_SD_CFG1 = 0xFD31;
110 REG_SD_CFG2 = 0xFD33;
111 REG_SD_CFG3 = 0xFD3E;
112 REG_SD_STAT1 = 0xFD30;
113 REG_SD_STAT2 = 0;
114 REG_SD_BUS_STAT = 0;
115 REG_SD_PAD_CTL = 0;
116 REG_SD_SAMPLE_POINT_CTL = 0;
117 REG_SD_PUSH_POINT_CTL = 0;
118 REG_SD_CMD0 = 0xFD34;
119 REG_SD_CMD1 = 0xFD35;
120 REG_SD_CMD2 = 0xFD36;
121 REG_SD_CMD3 = 0xFD37;
122 REG_SD_CMD4 = 0xFD38;
123 REG_SD_CMD5 = 0xFD5A;
124 REG_SD_BYTE_CNT_L = 0xFD39;
125 REG_SD_BYTE_CNT_H = 0xFD3A;
126 REG_SD_BLOCK_CNT_L = 0xFD3B;
127 REG_SD_BLOCK_CNT_H = 0xFD3C;
128 REG_SD_TRANSFER = 0xFD32;
129 REG_SD_VPCLK0_CTL = 0;
130 REG_SD_VPCLK1_CTL = 0;
131 REG_SD_DCMPS0_CTL = 0;
132 REG_SD_DCMPS1_CTL = 0;
133 }
134}
135
136static int sd_check_data0_status(struct rtsx_chip *chip)
137{
138 u8 stat;
139
140 if (CHECK_PID(chip, 0x5209)) {
141 RTSX_READ_REG(chip, REG_SD_BUS_STAT, &stat);
142 } else {
143 RTSX_READ_REG(chip, REG_SD_STAT1, &stat);
144 }
145
146 if (!(stat & SD_DAT0_STATUS)) {
147 sd_set_err_code(chip, SD_BUSY);
148 TRACE_RET(chip, STATUS_FAIL);
149 }
150
151 return STATUS_SUCCESS;
152}
153
154static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
155 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
156{
157 struct sd_info *sd_card = &(chip->sd_card);
158 int retval;
159 int timeout = 100;
160 u16 reg_addr;
161 u8 *ptr;
162 int stat_idx = 0;
163 int rty_cnt = 0;
164
165 sd_clr_err_code(chip);
166
167 RTSX_DEBUGP("SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg);
168
169 if (rsp_type == SD_RSP_TYPE_R1b)
170 timeout = 3000;
171
172RTY_SEND_CMD:
173
174 rtsx_init_cmd(chip);
175
176 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
177 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
178 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
179 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
180 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
181
182 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
183 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
184 0x01, PINGPONG_BUFFER);
185 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
186 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
187 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
188 SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END | SD_STAT_IDLE);
189
190 if (rsp_type == SD_RSP_TYPE_R2) {
191 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) {
192 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
193 }
194 stat_idx = 16;
195 } else if (rsp_type != SD_RSP_TYPE_R0) {
196 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++) {
197 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
198 }
199 stat_idx = 5;
200 }
201
202 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
203
204 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
205 if (retval < 0) {
206 u8 val;
207
208 rtsx_read_register(chip, REG_SD_STAT1, &val);
209 RTSX_DEBUGP("SD_STAT1: 0x%x\n", val);
210
211 if (CHECK_PID(chip, 0x5209)) {
212 rtsx_read_register(chip, REG_SD_STAT2, &val);
213 RTSX_DEBUGP("SD_STAT2: 0x%x\n", val);
214
215 if (val & SD_RSP_80CLK_TIMEOUT) {
216 rtsx_clear_sd_error(chip);
217 sd_set_err_code(chip, SD_RSP_TIMEOUT);
218 TRACE_RET(chip, STATUS_FAIL);
219 }
220
221 rtsx_read_register(chip, REG_SD_BUS_STAT, &val);
222 RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", val);
223 } else {
224 rtsx_read_register(chip, REG_SD_CFG3, &val);
225 RTSX_DEBUGP("SD_CFG3: 0x%x\n", val);
226 }
227
228 if (retval == -ETIMEDOUT) {
229 if (rsp_type & SD_WAIT_BUSY_END) {
230 retval = sd_check_data0_status(chip);
231 if (retval != STATUS_SUCCESS) {
232 rtsx_clear_sd_error(chip);
233 TRACE_RET(chip, retval);
234 }
235 } else {
236 sd_set_err_code(chip, SD_TO_ERR);
237 }
238 retval = STATUS_TIMEDOUT;
239 } else {
240 retval = STATUS_FAIL;
241 }
242 rtsx_clear_sd_error(chip);
243
244 TRACE_RET(chip, retval);
245 }
246
247 if (rsp_type == SD_RSP_TYPE_R0)
248 return STATUS_SUCCESS;
249
250 ptr = rtsx_get_cmd_data(chip) + 1;
251
252 if ((ptr[0] & 0xC0) != 0) {
253 sd_set_err_code(chip, SD_STS_ERR);
254 TRACE_RET(chip, STATUS_FAIL);
255 }
256
257 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
258 if (ptr[stat_idx] & SD_CRC7_ERR) {
259 if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
260 sd_set_err_code(chip, SD_CRC_ERR);
261 TRACE_RET(chip, STATUS_FAIL);
262 }
263 if (rty_cnt < SD_MAX_RETRY_COUNT) {
264 wait_timeout(20);
265 rty_cnt++;
266 goto RTY_SEND_CMD;
267 } else {
268 sd_set_err_code(chip, SD_CRC_ERR);
269 TRACE_RET(chip, STATUS_FAIL);
270 }
271 }
272 }
273
274 if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) {
275 if ((cmd_idx != SEND_RELATIVE_ADDR) && (cmd_idx != SEND_IF_COND)) {
276 if (cmd_idx != STOP_TRANSMISSION) {
277 if (ptr[1] & 0x80) {
278 TRACE_RET(chip, STATUS_FAIL);
279 }
280 }
281#ifdef SUPPORT_SD_LOCK
282 if (ptr[1] & 0x7D)
283#else
284 if (ptr[1] & 0x7F)
285#endif
286 {
287 RTSX_DEBUGP("ptr[1]: 0x%02x\n", ptr[1]);
288 TRACE_RET(chip, STATUS_FAIL);
289 }
290 if (ptr[2] & 0xFF) {
291 RTSX_DEBUGP("ptr[2]: 0x%02x\n", ptr[2]);
292 TRACE_RET(chip, STATUS_FAIL);
293 }
294 if (ptr[3] & 0x80) {
295 RTSX_DEBUGP("ptr[3]: 0x%02x\n", ptr[3]);
296 TRACE_RET(chip, STATUS_FAIL);
297 }
298 if (ptr[3] & 0x01) {
299 sd_card->sd_data_buf_ready = 1;
300 } else {
301 sd_card->sd_data_buf_ready = 0;
302 }
303 }
304 }
305
306 if (rsp && rsp_len)
307 memcpy(rsp, ptr, rsp_len);
308
309 return STATUS_SUCCESS;
310}
311
312static int sd_read_data(struct rtsx_chip *chip,
313 u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt,
314 u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len,
315 int timeout)
316{
317 struct sd_info *sd_card = &(chip->sd_card);
318 int retval;
319 int i;
320
321 sd_clr_err_code(chip);
322
323 if (!buf)
324 buf_len = 0;
325
326 if (buf_len > 512) {
327 TRACE_RET(chip, STATUS_FAIL);
328 }
329
330 rtsx_init_cmd(chip);
331
332 if (cmd_len) {
333 RTSX_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
334 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
335 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i, 0xFF, cmd[i]);
336 }
337 }
338 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
339 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8));
340 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)blk_cnt);
341 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(blk_cnt >> 8));
342
343 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
344
345 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
346 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
347 SD_CHECK_CRC7 | SD_RSP_LEN_6);
348 if (trans_mode != SD_TM_AUTO_TUNING) {
349 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
350 }
351 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START);
352 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
353
354 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
355 if (retval < 0) {
356 if (retval == -ETIMEDOUT) {
357 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
358 SD_RSP_TYPE_R1, NULL, 0);
359 }
360
361 TRACE_RET(chip, STATUS_FAIL);
362 }
363
364 if (buf && buf_len) {
365 retval = rtsx_read_ppbuf(chip, buf, buf_len);
366 if (retval != STATUS_SUCCESS) {
367 TRACE_RET(chip, STATUS_FAIL);
368 }
369 }
370
371 return STATUS_SUCCESS;
372}
373
374static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode,
375 u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt, u8 bus_width,
376 u8 *buf, int buf_len, int timeout)
377{
378 struct sd_info *sd_card = &(chip->sd_card);
379 int retval;
380 int i;
381
382 sd_clr_err_code(chip);
383
384 if (!buf)
385 buf_len = 0;
386
387 if (buf_len > 512) {
388 /* This function can't write data more than one page */
389 TRACE_RET(chip, STATUS_FAIL);
390 }
391
392 if (buf && buf_len) {
393 retval = rtsx_write_ppbuf(chip, buf, buf_len);
394 if (retval != STATUS_SUCCESS) {
395 TRACE_RET(chip, STATUS_FAIL);
396 }
397 }
398
399 rtsx_init_cmd(chip);
400
401 if (cmd_len) {
402 RTSX_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
403 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
404 rtsx_add_cmd(chip, WRITE_REG_CMD,
405 REG_SD_CMD0 + i, 0xFF, cmd[i]);
406 }
407 }
408 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
409 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8));
410 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)blk_cnt);
411 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(blk_cnt >> 8));
412
413 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
414
415 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
416 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
417 SD_CHECK_CRC7 | SD_RSP_LEN_6);
418
419 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START);
420 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
421
422 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
423 if (retval < 0) {
424 if (retval == -ETIMEDOUT) {
425 sd_send_cmd_get_rsp(chip, SEND_STATUS,
426 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
427 }
428
429 TRACE_RET(chip, STATUS_FAIL);
430 }
431
432 return STATUS_SUCCESS;
433}
434
435static int sd_check_csd(struct rtsx_chip *chip, char check_wp)
436{
437 struct sd_info *sd_card = &(chip->sd_card);
438 int retval;
439 int i;
440 u8 csd_ver, trans_speed;
441 u8 rsp[16];
442
443 for (i = 0; i < 6; i++) {
444 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
445 sd_set_err_code(chip, SD_NO_CARD);
446 TRACE_RET(chip, STATUS_FAIL);
447 }
448
449 retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr, SD_RSP_TYPE_R2, rsp, 16);
450 if (retval == STATUS_SUCCESS)
451 break;
452 }
453
454 if (i == 6) {
455 TRACE_RET(chip, STATUS_FAIL);
456 }
457
458 memcpy(sd_card->raw_csd, rsp + 1, 15);
459
460 if (CHECK_PID(chip, 0x5209)) {
461 RTSX_READ_REG(chip, REG_SD_CMD5, sd_card->raw_csd + 15);
462 }
463
464 RTSX_DEBUGP("CSD Response:\n");
465 RTSX_DUMP(sd_card->raw_csd, 16);
466
467 csd_ver = (rsp[1] & 0xc0) >> 6;
468 RTSX_DEBUGP("csd_ver = %d\n", csd_ver);
469
470 trans_speed = rsp[4];
471 if ((trans_speed & 0x07) == 0x02) {
472 if ((trans_speed & 0xf8) >= 0x30) {
473 if (chip->asic_code) {
474 sd_card->sd_clock = 47;
475 } else {
476 sd_card->sd_clock = CLK_50;
477 }
478 } else if ((trans_speed & 0xf8) == 0x28) {
479 if (chip->asic_code) {
480 sd_card->sd_clock = 39;
481 } else {
482 sd_card->sd_clock = CLK_40;
483 }
484 } else if ((trans_speed & 0xf8) == 0x20) {
485 if (chip->asic_code) {
486 sd_card->sd_clock = 29;
487 } else {
488 sd_card->sd_clock = CLK_30;
489 }
490 } else if ((trans_speed & 0xf8) >= 0x10) {
491 if (chip->asic_code) {
492 sd_card->sd_clock = 23;
493 } else {
494 sd_card->sd_clock = CLK_20;
495 }
496 } else if ((trans_speed & 0x08) >= 0x08) {
497 if (chip->asic_code) {
498 sd_card->sd_clock = 19;
499 } else {
500 sd_card->sd_clock = CLK_20;
501 }
502 } else {
503 TRACE_RET(chip, STATUS_FAIL);
504 }
505 } else {
506 TRACE_RET(chip, STATUS_FAIL);
507 }
508
509 if (CHK_MMC_SECTOR_MODE(sd_card)) {
510 sd_card->capacity = 0;
511 } else {
512 if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) {
513 u8 blk_size, c_size_mult;
514 u16 c_size;
515 blk_size = rsp[6] & 0x0F;
516 c_size = ((u16)(rsp[7] & 0x03) << 10)
517 + ((u16)rsp[8] << 2)
518 + ((u16)(rsp[9] & 0xC0) >> 6);
519 c_size_mult = (u8)((rsp[10] & 0x03) << 1);
520 c_size_mult += (rsp[11] & 0x80) >> 7;
521 sd_card->capacity = (((u32)(c_size + 1)) * (1 << (c_size_mult + 2))) << (blk_size - 9);
522 } else {
523 u32 total_sector = 0;
524 total_sector = (((u32)rsp[8] & 0x3f) << 16) |
525 ((u32)rsp[9] << 8) | (u32)rsp[10];
526 sd_card->capacity = (total_sector + 1) << 10;
527 }
528 }
529
530 if (check_wp) {
531 if (rsp[15] & 0x30) {
532 chip->card_wp |= SD_CARD;
533 }
534 RTSX_DEBUGP("CSD WP Status: 0x%x\n", rsp[15]);
535 }
536
537 return STATUS_SUCCESS;
538}
539
540static int sd_set_sample_push_timing(struct rtsx_chip *chip)
541{
542 struct sd_info *sd_card = &(chip->sd_card);
543
544 if (CHECK_PID(chip, 0x5209)) {
545 if (CHK_SD_SDR104(sd_card) || CHK_SD_SDR50(sd_card)) {
546 RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST,
547 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
548 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
549 RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
550 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
551 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
552 } else if (CHK_SD_DDR50(sd_card) || CHK_MMC_DDR52(sd_card)) {
553 RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST,
554 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
555 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
556 RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
557 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
558 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
559 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, DDR_VAR_TX_CMD_DAT,
560 DDR_VAR_TX_CMD_DAT);
561 RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
562 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
563 } else {
564 u8 val = 0;
565
566 RTSX_WRITE_REG(chip, SD_CFG1, 0x0C, SD_20_MODE);
567 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
568 RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
569 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
570 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
571
572 if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_AUTO) {
573 val = SD20_TX_NEG_EDGE;
574 } else if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY) {
575 val = SD20_TX_14_AHEAD;
576 } else {
577 val = SD20_TX_NEG_EDGE;
578 }
579 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, SD20_TX_SEL_MASK, val);
580
581 if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
582 if (chip->asic_code) {
583 if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
584 val = SD20_RX_14_DELAY;
585 } else {
586 val = SD20_RX_POS_EDGE;
587 }
588 } else {
589 val = SD20_RX_14_DELAY;
590 }
591 } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_DELAY) {
592 val = SD20_RX_14_DELAY;
593 } else {
594 val = SD20_RX_POS_EDGE;
595 }
596 RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, SD20_RX_SEL_MASK, val);
597 }
598 } else {
599 u8 val = 0;
600
601 if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY) {
602 val |= 0x10;
603 }
604
605 if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
606 if (chip->asic_code) {
607 if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
608 if (val & 0x10) {
609 val |= 0x04;
610 } else {
611 val |= 0x08;
612 }
613 }
614 } else {
615 if (val & 0x10) {
616 val |= 0x04;
617 } else {
618 val |= 0x08;
619 }
620 }
621 } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_DELAY) {
622 if (val & 0x10) {
623 val |= 0x04;
624 } else {
625 val |= 0x08;
626 }
627 }
628
629 RTSX_WRITE_REG(chip, REG_SD_CFG1, 0x1C, val);
630 }
631
632 return STATUS_SUCCESS;
633}
634
635static void sd_choose_proper_clock(struct rtsx_chip *chip)
636{
637 struct sd_info *sd_card = &(chip->sd_card);
638
639 if (CHK_SD_SDR104(sd_card)) {
640 if (chip->asic_code) {
641 sd_card->sd_clock = chip->asic_sd_sdr104_clk;
642 } else {
643 sd_card->sd_clock = chip->fpga_sd_sdr104_clk;
644 }
645 } else if (CHK_SD_DDR50(sd_card)) {
646 if (chip->asic_code) {
647 sd_card->sd_clock = chip->asic_sd_ddr50_clk;
648 } else {
649 sd_card->sd_clock = chip->fpga_sd_ddr50_clk;
650 }
651 } else if (CHK_SD_SDR50(sd_card)) {
652 if (chip->asic_code) {
653 sd_card->sd_clock = chip->asic_sd_sdr50_clk;
654 } else {
655 sd_card->sd_clock = chip->fpga_sd_sdr50_clk;
656 }
657 } else if (CHK_SD_HS(sd_card)) {
658 if (chip->asic_code) {
659 sd_card->sd_clock = chip->asic_sd_hs_clk;
660 } else {
661 sd_card->sd_clock = chip->fpga_sd_hs_clk;
662 }
663 } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
664 if (chip->asic_code) {
665 sd_card->sd_clock = chip->asic_mmc_52m_clk;
666 } else {
667 sd_card->sd_clock = chip->fpga_mmc_52m_clk;
668 }
669 } else if (CHK_MMC_26M(sd_card)) {
670 if (chip->asic_code) {
671 sd_card->sd_clock = 48;
672 } else {
673 sd_card->sd_clock = CLK_50;
674 }
675 }
676}
677
678static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div)
679{
680 u8 mask = 0, val = 0;
681
682 if (CHECK_PID(chip, 0x5209)) {
683 mask = SD_CLK_DIVIDE_MASK;
684 val = clk_div;
685 } else {
686 mask = 0x60;
687 if (clk_div == SD_CLK_DIVIDE_0) {
688 val = 0x00;
689 } else if (clk_div == SD_CLK_DIVIDE_128) {
690 val = 0x40;
691 } else if (clk_div == SD_CLK_DIVIDE_256) {
692 val = 0x20;
693 }
694 }
695
696 RTSX_WRITE_REG(chip, REG_SD_CFG1, mask, val);
697
698 return STATUS_SUCCESS;
699}
700
701static int sd_set_init_para(struct rtsx_chip *chip)
702{
703 struct sd_info *sd_card = &(chip->sd_card);
704 int retval;
705
706 retval = sd_set_sample_push_timing(chip);
707 if (retval != STATUS_SUCCESS) {
708 TRACE_RET(chip, STATUS_FAIL);
709 }
710
711 sd_choose_proper_clock(chip);
712
713 retval = switch_clock(chip, sd_card->sd_clock);
714 if (retval != STATUS_SUCCESS) {
715 TRACE_RET(chip, STATUS_FAIL);
716 }
717
718 return STATUS_SUCCESS;
719}
720
721int sd_select_card(struct rtsx_chip *chip, int select)
722{
723 struct sd_info *sd_card = &(chip->sd_card);
724 int retval;
725 u8 cmd_idx, cmd_type;
726 u32 addr;
727
728 if (select) {
729 cmd_idx = SELECT_CARD;
730 cmd_type = SD_RSP_TYPE_R1;
731 addr = sd_card->sd_addr;
732 } else {
733 cmd_idx = DESELECT_CARD;
734 cmd_type = SD_RSP_TYPE_R0;
735 addr = 0;
736 }
737
738 retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
739 if (retval != STATUS_SUCCESS) {
740 TRACE_RET(chip, STATUS_FAIL);
741 }
742
743 return STATUS_SUCCESS;
744}
745
746#ifdef SUPPORT_SD_LOCK
747static int sd_update_lock_status(struct rtsx_chip *chip)
748{
749 struct sd_info *sd_card = &(chip->sd_card);
750 int retval;
751 u8 rsp[5];
752
753 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, 5);
754 if (retval != STATUS_SUCCESS) {
755 TRACE_RET(chip, STATUS_FAIL);
756 }
757
758 if (rsp[1] & 0x02) {
759 sd_card->sd_lock_status |= SD_LOCKED;
760 } else {
761 sd_card->sd_lock_status &= ~SD_LOCKED;
762 }
763
764 RTSX_DEBUGP("sd_card->sd_lock_status = 0x%x\n", sd_card->sd_lock_status);
765
766 if (rsp[1] & 0x01) {
767 TRACE_RET(chip, STATUS_FAIL);
768 }
769
770 return STATUS_SUCCESS;
771}
772#endif
773
774static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state, u8 data_ready, int polling_cnt)
775{
776 struct sd_info *sd_card = &(chip->sd_card);
777 int retval, i;
778 u8 rsp[5];
779
780 for (i = 0; i < polling_cnt; i++) {
781 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
782 sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, 5);
783 if (retval != STATUS_SUCCESS) {
784 TRACE_RET(chip, STATUS_FAIL);
785 }
786
787 if (((rsp[3] & 0x1E) == state) && ((rsp[3] & 0x01) == data_ready)) {
788 return STATUS_SUCCESS;
789 }
790 }
791
792 TRACE_RET(chip, STATUS_FAIL);
793}
794
795static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage)
796{
797 int retval;
798
799 if (voltage == SD_IO_3V3) {
800 if (chip->asic_code) {
801 retval = rtsx_write_phy_register(chip, 0x08, 0x4FC0 | chip->phy_voltage);
802 if (retval != STATUS_SUCCESS) {
803 TRACE_RET(chip, STATUS_FAIL);
804 }
805 } else {
806 RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, 0);
807 }
808 } else if (voltage == SD_IO_1V8) {
809 if (chip->asic_code) {
810 retval = rtsx_write_phy_register(chip, 0x08, 0x4C40 | chip->phy_voltage);
811 if (retval != STATUS_SUCCESS) {
812 TRACE_RET(chip, STATUS_FAIL);
813 }
814 } else {
815 RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, SD_IO_USING_1V8);
816 }
817 } else {
818 TRACE_RET(chip, STATUS_FAIL);
819 }
820
821 return STATUS_SUCCESS;
822}
823
824static int sd_voltage_switch(struct rtsx_chip *chip)
825{
826 int retval;
827 u8 stat;
828
829 RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, SD_CLK_TOGGLE_EN);
830
831 retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1, NULL, 0);
832 if (retval != STATUS_SUCCESS) {
833 TRACE_RET(chip, STATUS_FAIL);
834 }
835
836 udelay(chip->sd_voltage_switch_delay);
837
838 RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
839 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
840 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
841 TRACE_RET(chip, STATUS_FAIL);
842 }
843
844 RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_FORCE_STOP);
845 retval = sd_change_bank_voltage(chip, SD_IO_1V8);
846 if (retval != STATUS_SUCCESS) {
847 TRACE_RET(chip, STATUS_FAIL);
848 }
849 wait_timeout(50);
850
851 RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
852 wait_timeout(10);
853
854 RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
855 if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
856 SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
857 (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
858 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
859 RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", stat);
860 rtsx_write_register(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
861 rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0);
862 TRACE_RET(chip, STATUS_FAIL);
863 }
864
865 RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
866
867 return STATUS_SUCCESS;
868}
869
870static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir)
871{
872 if (tune_dir == TUNE_RX) {
873 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_RX);
874 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RX);
875 } else {
876 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_TX);
877 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_TX);
878 }
879
880 return STATUS_SUCCESS;
881}
882
883static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
884{
885 struct sd_info *sd_card = &(chip->sd_card);
886 u16 SD_VP_CTL, SD_DCMPS_CTL;
887 u8 val;
888 int retval;
889 int ddr_rx = 0;
890
891 RTSX_DEBUGP("sd_change_phase (sample_point = %d, tune_dir = %d)\n",
892 sample_point, tune_dir);
893
894 if (tune_dir == TUNE_RX) {
895 SD_VP_CTL = SD_VPRX_CTL;
896 SD_DCMPS_CTL = SD_DCMPS_RX_CTL;
897 if (CHK_SD_DDR50(sd_card)) {
898 ddr_rx = 1;
899 }
900 } else {
901 SD_VP_CTL = SD_VPTX_CTL;
902 SD_DCMPS_CTL = SD_DCMPS_TX_CTL;
903 }
904
905 if (chip->asic_code) {
906 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
907 RTSX_WRITE_REG(chip, SD_VP_CTL, 0x1F, sample_point);
908 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
909 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET);
910 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
911 } else {
912#if CONFIG_RTS_PSTOR_DEBUG
913 rtsx_read_register(chip, SD_VP_CTL, &val);
914 RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val);
915 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
916 RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
917#endif
918
919 if (ddr_rx) {
920 RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, PHASE_CHANGE);
921 udelay(50);
922 RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
923 PHASE_CHANGE | PHASE_NOT_RESET | sample_point);
924 } else {
925 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
926 udelay(50);
927 RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
928 PHASE_NOT_RESET | sample_point);
929 }
930 udelay(100);
931
932 rtsx_init_cmd(chip);
933 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE, DCMPS_CHANGE);
934 rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
935 retval = rtsx_send_cmd(chip, SD_CARD, 100);
936 if (retval != STATUS_SUCCESS) {
937 TRACE_GOTO(chip, Fail);
938 }
939
940 val = *rtsx_get_cmd_data(chip);
941 if (val & DCMPS_ERROR) {
942 TRACE_GOTO(chip, Fail);
943 }
944 if ((val & DCMPS_CURRENT_PHASE) != sample_point) {
945 TRACE_GOTO(chip, Fail);
946 }
947 RTSX_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
948 if (ddr_rx) {
949 RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, 0);
950 } else {
951 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
952 }
953 udelay(50);
954 }
955
956 RTSX_WRITE_REG(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
957
958 return STATUS_SUCCESS;
959
960Fail:
961#if CONFIG_RTS_PSTOR_DEBUG
962 rtsx_read_register(chip, SD_VP_CTL, &val);
963 RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val);
964 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
965 RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
966#endif
967
968 rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
969 rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0);
970 wait_timeout(10);
971 sd_reset_dcm(chip, tune_dir);
972 return STATUS_FAIL;
973}
974
975static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width)
976{
977 struct sd_info *sd_card = &(chip->sd_card);
978 int retval;
979 u8 cmd[5], buf[8];
980
981 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
982 if (retval != STATUS_SUCCESS) {
983 TRACE_RET(chip, STATUS_FAIL);
984 }
985
986 cmd[0] = 0x40 | SEND_SCR;
987 cmd[1] = 0;
988 cmd[2] = 0;
989 cmd[3] = 0;
990 cmd[4] = 0;
991
992 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width, buf, 8, 250);
993 if (retval != STATUS_SUCCESS) {
994 rtsx_clear_sd_error(chip);
995 TRACE_RET(chip, STATUS_FAIL);
996 }
997
998 memcpy(sd_card->raw_scr, buf, 8);
999
1000 if ((buf[0] & 0x0F) == 0) {
1001 TRACE_RET(chip, STATUS_FAIL);
1002 }
1003
1004 return STATUS_SUCCESS;
1005}
1006
1007static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group, u8 func_to_switch,
1008 u8 *buf, int buf_len)
1009{
1010 u8 support_mask = 0, query_switch = 0, switch_busy = 0;
1011 int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
1012
1013 if (func_group == SD_FUNC_GROUP_1) {
1014 support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
1015 query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
1016 check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
1017
1018 switch (func_to_switch) {
1019 case HS_SUPPORT:
1020 support_mask = HS_SUPPORT_MASK;
1021 query_switch = HS_QUERY_SWITCH_OK;
1022 switch_busy = HS_SWITCH_BUSY;
1023 break;
1024
1025 case SDR50_SUPPORT:
1026 support_mask = SDR50_SUPPORT_MASK;
1027 query_switch = SDR50_QUERY_SWITCH_OK;
1028 switch_busy = SDR50_SWITCH_BUSY;
1029 break;
1030
1031 case SDR104_SUPPORT:
1032 support_mask = SDR104_SUPPORT_MASK;
1033 query_switch = SDR104_QUERY_SWITCH_OK;
1034 switch_busy = SDR104_SWITCH_BUSY;
1035 break;
1036
1037 case DDR50_SUPPORT:
1038 support_mask = DDR50_SUPPORT_MASK;
1039 query_switch = DDR50_QUERY_SWITCH_OK;
1040 switch_busy = DDR50_SWITCH_BUSY;
1041 break;
1042
1043 default:
1044 TRACE_RET(chip, STATUS_FAIL);
1045 }
1046 } else if (func_group == SD_FUNC_GROUP_3) {
1047 support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
1048 query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
1049 check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
1050
1051 switch (func_to_switch) {
1052 case DRIVING_TYPE_A:
1053 support_mask = DRIVING_TYPE_A_MASK;
1054 query_switch = TYPE_A_QUERY_SWITCH_OK;
1055 switch_busy = TYPE_A_SWITCH_BUSY;
1056 break;
1057
1058 case DRIVING_TYPE_C:
1059 support_mask = DRIVING_TYPE_C_MASK;
1060 query_switch = TYPE_C_QUERY_SWITCH_OK;
1061 switch_busy = TYPE_C_SWITCH_BUSY;
1062 break;
1063
1064 case DRIVING_TYPE_D:
1065 support_mask = DRIVING_TYPE_D_MASK;
1066 query_switch = TYPE_D_QUERY_SWITCH_OK;
1067 switch_busy = TYPE_D_SWITCH_BUSY;
1068 break;
1069
1070 default:
1071 TRACE_RET(chip, STATUS_FAIL);
1072 }
1073 } else if (func_group == SD_FUNC_GROUP_4) {
1074 support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
1075 query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
1076 check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
1077
1078 switch (func_to_switch) {
1079 case CURRENT_LIMIT_400:
1080 support_mask = CURRENT_LIMIT_400_MASK;
1081 query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
1082 switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
1083 break;
1084
1085 case CURRENT_LIMIT_600:
1086 support_mask = CURRENT_LIMIT_600_MASK;
1087 query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
1088 switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
1089 break;
1090
1091 case CURRENT_LIMIT_800:
1092 support_mask = CURRENT_LIMIT_800_MASK;
1093 query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
1094 switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
1095 break;
1096
1097 default:
1098 TRACE_RET(chip, STATUS_FAIL);
1099 }
1100 } else {
1101 TRACE_RET(chip, STATUS_FAIL);
1102 }
1103
1104 if (func_group == SD_FUNC_GROUP_1) {
1105 if (!(buf[support_offset] & support_mask) ||
1106 ((buf[query_switch_offset] & 0x0F) != query_switch)) {
1107 TRACE_RET(chip, STATUS_FAIL);
1108 }
1109 }
1110
1111 /* Check 'Busy Status' */
1112 if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) &&
1113 ((buf[check_busy_offset] & switch_busy) == switch_busy)) {
1114 TRACE_RET(chip, STATUS_FAIL);
1115 }
1116
1117 return STATUS_SUCCESS;
1118}
1119
1120static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode,
1121 u8 func_group, u8 func_to_switch, u8 bus_width)
1122{
1123 struct sd_info *sd_card = &(chip->sd_card);
1124 int retval;
1125 u8 cmd[5], buf[64];
1126
1127 RTSX_DEBUGP("sd_check_switch_mode (mode = %d, func_group = %d, func_to_switch = %d)\n",
1128 mode, func_group, func_to_switch);
1129
1130 cmd[0] = 0x40 | SWITCH;
1131 cmd[1] = mode;
1132
1133 if (func_group == SD_FUNC_GROUP_1) {
1134 cmd[2] = 0xFF;
1135 cmd[3] = 0xFF;
1136 cmd[4] = 0xF0 + func_to_switch;
1137 } else if (func_group == SD_FUNC_GROUP_3) {
1138 cmd[2] = 0xFF;
1139 cmd[3] = 0xF0 + func_to_switch;
1140 cmd[4] = 0xFF;
1141 } else if (func_group == SD_FUNC_GROUP_4) {
1142 cmd[2] = 0xFF;
1143 cmd[3] = 0x0F + (func_to_switch << 4);
1144 cmd[4] = 0xFF;
1145 } else {
1146 cmd[1] = SD_CHECK_MODE;
1147 cmd[2] = 0xFF;
1148 cmd[3] = 0xFF;
1149 cmd[4] = 0xFF;
1150 }
1151
1152 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width, buf, 64, 250);
1153 if (retval != STATUS_SUCCESS) {
1154 rtsx_clear_sd_error(chip);
1155 TRACE_RET(chip, STATUS_FAIL);
1156 }
1157
1158 RTSX_DUMP(buf, 64);
1159
1160 if (func_group == NO_ARGUMENT) {
1161 sd_card->func_group1_mask = buf[0x0D];
1162 sd_card->func_group2_mask = buf[0x0B];
1163 sd_card->func_group3_mask = buf[0x09];
1164 sd_card->func_group4_mask = buf[0x07];
1165
1166 RTSX_DEBUGP("func_group1_mask = 0x%02x\n", buf[0x0D]);
1167 RTSX_DEBUGP("func_group2_mask = 0x%02x\n", buf[0x0B]);
1168 RTSX_DEBUGP("func_group3_mask = 0x%02x\n", buf[0x09]);
1169 RTSX_DEBUGP("func_group4_mask = 0x%02x\n", buf[0x07]);
1170 } else {
1171 /* Maximum current consumption, check whether current is acceptable;
1172 * bit[511:496] = 0x0000 means some error happaned.
1173 */
1174 u16 cc = ((u16)buf[0] << 8) | buf[1];
1175 RTSX_DEBUGP("Maximum current consumption: %dmA\n", cc);
1176 if ((cc == 0) || (cc > 800)) {
1177 TRACE_RET(chip, STATUS_FAIL);
1178 }
1179 retval = sd_query_switch_result(chip, func_group, func_to_switch, buf, 64);
1180 if (retval != STATUS_SUCCESS) {
1181 TRACE_RET(chip, STATUS_FAIL);
1182 }
1183
1184 if ((cc > 400) || (func_to_switch > CURRENT_LIMIT_400)) {
1185 RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK, chip->sd_800mA_ocp_thd);
1186 RTSX_WRITE_REG(chip, CARD_PWR_CTL, PMOS_STRG_MASK, PMOS_STRG_800mA);
1187 }
1188 }
1189
1190 return STATUS_SUCCESS;
1191}
1192
1193static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch)
1194{
1195 if (func_group == SD_FUNC_GROUP_1) {
1196 if (func_to_switch > HS_SUPPORT) {
1197 func_to_switch--;
1198 }
1199 } else if (func_group == SD_FUNC_GROUP_4) {
1200 if (func_to_switch > CURRENT_LIMIT_200) {
1201 func_to_switch--;
1202 }
1203 }
1204
1205 return func_to_switch;
1206}
1207
1208static int sd_check_switch(struct rtsx_chip *chip,
1209 u8 func_group, u8 func_to_switch, u8 bus_width)
1210{
1211 int retval;
1212 int i;
1213 int switch_good = 0;
1214
1215 for (i = 0; i < 3; i++) {
1216 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1217 sd_set_err_code(chip, SD_NO_CARD);
1218 TRACE_RET(chip, STATUS_FAIL);
1219 }
1220
1221 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group,
1222 func_to_switch, bus_width);
1223 if (retval == STATUS_SUCCESS) {
1224 u8 stat;
1225
1226 retval = sd_check_switch_mode(chip, SD_SWITCH_MODE,
1227 func_group, func_to_switch, bus_width);
1228 if (retval == STATUS_SUCCESS) {
1229 switch_good = 1;
1230 break;
1231 }
1232
1233 RTSX_READ_REG(chip, SD_STAT1, &stat);
1234 if (stat & SD_CRC16_ERR) {
1235 RTSX_DEBUGP("SD CRC16 error when switching mode\n");
1236 TRACE_RET(chip, STATUS_FAIL);
1237 }
1238 }
1239
1240 func_to_switch = downgrade_switch_mode(func_group, func_to_switch);
1241
1242 wait_timeout(20);
1243 }
1244
1245 if (!switch_good) {
1246 TRACE_RET(chip, STATUS_FAIL);
1247 }
1248
1249 return STATUS_SUCCESS;
1250}
1251
1252static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width)
1253{
1254 struct sd_info *sd_card = &(chip->sd_card);
1255 int retval;
1256 int i;
1257 u8 func_to_switch = 0;
1258
1259 /* Get supported functions */
1260 retval = sd_check_switch_mode(chip, SD_CHECK_MODE,
1261 NO_ARGUMENT, NO_ARGUMENT, bus_width);
1262 if (retval != STATUS_SUCCESS) {
1263 TRACE_RET(chip, STATUS_FAIL);
1264 }
1265
1266 sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail);
1267
1268 for (i = 0; i < 4; i++) {
1269 switch ((u8)(chip->sd_speed_prior >> (i*8))) {
1270 case SDR104_SUPPORT:
1271 if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK)
1272 && chip->sdr104_en) {
1273 func_to_switch = SDR104_SUPPORT;
1274 }
1275 break;
1276
1277 case DDR50_SUPPORT:
1278 if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK)
1279 && chip->ddr50_en) {
1280 func_to_switch = DDR50_SUPPORT;
1281 }
1282 break;
1283
1284 case SDR50_SUPPORT:
1285 if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK)
1286 && chip->sdr50_en) {
1287 func_to_switch = SDR50_SUPPORT;
1288 }
1289 break;
1290
1291 case HS_SUPPORT:
1292 if (sd_card->func_group1_mask & HS_SUPPORT_MASK) {
1293 func_to_switch = HS_SUPPORT;
1294 }
1295 break;
1296
1297 default:
1298 continue;
1299 }
1300
1301
1302 if (func_to_switch) {
1303 break;
1304 }
1305 }
1306 RTSX_DEBUGP("SD_FUNC_GROUP_1: func_to_switch = 0x%02x", func_to_switch);
1307
1308#ifdef SUPPORT_SD_LOCK
1309 if ((sd_card->sd_lock_status & SD_SDR_RST)
1310 && (DDR50_SUPPORT == func_to_switch)
1311 && (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) {
1312 func_to_switch = SDR50_SUPPORT;
1313 RTSX_DEBUGP("Using SDR50 instead of DDR50 for SD Lock\n");
1314 }
1315#endif
1316
1317 if (func_to_switch) {
1318 retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch, bus_width);
1319 if (retval != STATUS_SUCCESS) {
1320 if (func_to_switch == SDR104_SUPPORT) {
1321 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK;
1322 } else if (func_to_switch == DDR50_SUPPORT) {
1323 sd_card->sd_switch_fail =
1324 SDR104_SUPPORT_MASK | DDR50_SUPPORT_MASK;
1325 } else if (func_to_switch == SDR50_SUPPORT) {
1326 sd_card->sd_switch_fail =
1327 SDR104_SUPPORT_MASK | DDR50_SUPPORT_MASK |
1328 SDR50_SUPPORT_MASK;
1329 }
1330 TRACE_RET(chip, STATUS_FAIL);
1331 }
1332
1333 if (func_to_switch == SDR104_SUPPORT) {
1334 SET_SD_SDR104(sd_card);
1335 } else if (func_to_switch == DDR50_SUPPORT) {
1336 SET_SD_DDR50(sd_card);
1337 } else if (func_to_switch == SDR50_SUPPORT) {
1338 SET_SD_SDR50(sd_card);
1339 } else {
1340 SET_SD_HS(sd_card);
1341 }
1342 }
1343
1344 if (CHK_SD_DDR50(sd_card)) {
1345 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0x04);
1346 retval = sd_set_sample_push_timing(chip);
1347 if (retval != STATUS_SUCCESS) {
1348 TRACE_RET(chip, STATUS_FAIL);
1349 }
1350 }
1351
1352 func_to_switch = 0xFF;
1353
1354 for (i = 0; i < 4; i++) {
1355 switch ((u8)(chip->sd_current_prior >> (i*8))) {
1356 case CURRENT_LIMIT_800:
1357 if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK) {
1358 func_to_switch = CURRENT_LIMIT_800;
1359 }
1360 break;
1361
1362 case CURRENT_LIMIT_600:
1363 if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK) {
1364 func_to_switch = CURRENT_LIMIT_600;
1365 }
1366 break;
1367
1368 case CURRENT_LIMIT_400:
1369 if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK) {
1370 func_to_switch = CURRENT_LIMIT_400;
1371 }
1372 break;
1373
1374 case CURRENT_LIMIT_200:
1375 if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK) {
1376 func_to_switch = CURRENT_LIMIT_200;
1377 }
1378 break;
1379
1380 default:
1381 continue;
1382 }
1383
1384 if (func_to_switch != 0xFF) {
1385 break;
1386 }
1387 }
1388
1389 RTSX_DEBUGP("SD_FUNC_GROUP_4: func_to_switch = 0x%02x", func_to_switch);
1390
1391 if (func_to_switch <= CURRENT_LIMIT_800) {
1392 retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch, bus_width);
1393 if (retval != STATUS_SUCCESS) {
1394 if (sd_check_err_code(chip, SD_NO_CARD)) {
1395 TRACE_RET(chip, STATUS_FAIL);
1396 }
1397 }
1398 RTSX_DEBUGP("Switch current limit finished! (%d)\n", retval);
1399 }
1400
1401 if (CHK_SD_DDR50(sd_card)) {
1402 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0);
1403 }
1404
1405 return STATUS_SUCCESS;
1406}
1407
1408static int sd_wait_data_idle(struct rtsx_chip *chip)
1409{
1410 int retval = STATUS_TIMEDOUT;
1411 int i;
1412 u8 val = 0;
1413
1414 for (i = 0; i < 100; i++) {
1415 RTSX_READ_REG(chip, SD_DATA_STATE, &val);
1416 if (val & SD_DATA_IDLE) {
1417 retval = STATUS_SUCCESS;
1418 break;
1419 }
1420 udelay(100);
1421 }
1422 RTSX_DEBUGP("SD_DATA_STATE: 0x%02x\n", val);
1423
1424 return retval;
1425}
1426
1427static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1428{
1429 int retval;
1430 u8 cmd[5];
1431
1432 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1433 if (retval != STATUS_SUCCESS) {
1434 TRACE_RET(chip, STATUS_FAIL);
1435 }
1436
1437 cmd[0] = 0x40 | SEND_TUNING_PATTERN;
1438 cmd[1] = 0;
1439 cmd[2] = 0;
1440 cmd[3] = 0;
1441 cmd[4] = 0;
1442
1443 retval = sd_read_data(chip, SD_TM_AUTO_TUNING,
1444 cmd, 5, 0x40, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1445 if (retval != STATUS_SUCCESS) {
1446 (void)sd_wait_data_idle(chip);
1447
1448 rtsx_clear_sd_error(chip);
1449 TRACE_RET(chip, STATUS_FAIL);
1450 }
1451
1452 return STATUS_SUCCESS;
1453}
1454
1455static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1456{
1457 struct sd_info *sd_card = &(chip->sd_card);
1458 int retval;
1459 u8 cmd[5];
1460
1461 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1462 if (retval != STATUS_SUCCESS) {
1463 TRACE_RET(chip, STATUS_FAIL);
1464 }
1465
1466 RTSX_DEBUGP("sd ddr tuning rx\n");
1467
1468 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
1469 if (retval != STATUS_SUCCESS) {
1470 TRACE_RET(chip, STATUS_FAIL);
1471 }
1472
1473 cmd[0] = 0x40 | SD_STATUS;
1474 cmd[1] = 0;
1475 cmd[2] = 0;
1476 cmd[3] = 0;
1477 cmd[4] = 0;
1478
1479 retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1480 cmd, 5, 64, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1481 if (retval != STATUS_SUCCESS) {
1482 (void)sd_wait_data_idle(chip);
1483
1484 rtsx_clear_sd_error(chip);
1485 TRACE_RET(chip, STATUS_FAIL);
1486 }
1487
1488 return STATUS_SUCCESS;
1489}
1490
1491static int mmc_ddr_tunning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1492{
1493 struct sd_info *sd_card = &(chip->sd_card);
1494 int retval;
1495 u8 cmd[5], bus_width;
1496
1497 if (CHK_MMC_8BIT(sd_card)) {
1498 bus_width = SD_BUS_WIDTH_8;
1499 } else if (CHK_MMC_4BIT(sd_card)) {
1500 bus_width = SD_BUS_WIDTH_4;
1501 } else {
1502 bus_width = SD_BUS_WIDTH_1;
1503 }
1504
1505 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1506 if (retval != STATUS_SUCCESS) {
1507 TRACE_RET(chip, STATUS_FAIL);
1508 }
1509
1510 RTSX_DEBUGP("mmc ddr tuning rx\n");
1511
1512 cmd[0] = 0x40 | SEND_EXT_CSD;
1513 cmd[1] = 0;
1514 cmd[2] = 0;
1515 cmd[3] = 0;
1516 cmd[4] = 0;
1517
1518 retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1519 cmd, 5, 0x200, 1, bus_width, NULL, 0, 100);
1520 if (retval != STATUS_SUCCESS) {
1521 (void)sd_wait_data_idle(chip);
1522
1523 rtsx_clear_sd_error(chip);
1524 TRACE_RET(chip, STATUS_FAIL);
1525 }
1526
1527 return STATUS_SUCCESS;
1528}
1529
1530static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1531{
1532 struct sd_info *sd_card = &(chip->sd_card);
1533 int retval;
1534
1535 retval = sd_change_phase(chip, sample_point, TUNE_TX);
1536 if (retval != STATUS_SUCCESS) {
1537 TRACE_RET(chip, STATUS_FAIL);
1538 }
1539
1540 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN);
1541
1542 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1543 SD_RSP_TYPE_R1, NULL, 0);
1544 if (retval != STATUS_SUCCESS) {
1545 if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1546 rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1547 TRACE_RET(chip, STATUS_FAIL);
1548 }
1549 }
1550
1551 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1552
1553 return STATUS_SUCCESS;
1554}
1555
1556static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1557{
1558 struct sd_info *sd_card = &(chip->sd_card);
1559 int retval;
1560 u8 cmd[5], bus_width;
1561
1562 retval = sd_change_phase(chip, sample_point, TUNE_TX);
1563 if (retval != STATUS_SUCCESS) {
1564 TRACE_RET(chip, STATUS_FAIL);
1565 }
1566
1567 if (CHK_SD(sd_card)) {
1568 bus_width = SD_BUS_WIDTH_4;
1569 } else {
1570 if (CHK_MMC_8BIT(sd_card)) {
1571 bus_width = SD_BUS_WIDTH_8;
1572 } else if (CHK_MMC_4BIT(sd_card)) {
1573 bus_width = SD_BUS_WIDTH_4;
1574 } else {
1575 bus_width = SD_BUS_WIDTH_1;
1576 }
1577 }
1578
1579 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
1580 if (retval != STATUS_SUCCESS) {
1581 TRACE_RET(chip, STATUS_FAIL);
1582 }
1583
1584 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN);
1585
1586 cmd[0] = 0x40 | PROGRAM_CSD;
1587 cmd[1] = 0;
1588 cmd[2] = 0;
1589 cmd[3] = 0;
1590 cmd[4] = 0;
1591
1592 retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2,
1593 cmd, 5, 16, 1, bus_width, sd_card->raw_csd, 16, 100);
1594 if (retval != STATUS_SUCCESS) {
1595 rtsx_clear_sd_error(chip);
1596 rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1597 TRACE_RET(chip, STATUS_FAIL);
1598 }
1599
1600 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1601
1602 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
1603
1604 return STATUS_SUCCESS;
1605}
1606
1607static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map, u8 tune_dir)
1608{
1609 struct sd_info *sd_card = &(chip->sd_card);
1610 struct timing_phase_path path[MAX_PHASE + 1];
1611 int i, j, cont_path_cnt;
1612 int new_block, max_len, final_path_idx;
1613 u8 final_phase = 0xFF;
1614
1615 if (phase_map == 0xFFFFFFFF) {
1616 if (tune_dir == TUNE_RX) {
1617 final_phase = (u8)chip->sd_default_rx_phase;
1618 } else {
1619 final_phase = (u8)chip->sd_default_tx_phase;
1620 }
1621
1622 goto Search_Finish;
1623 }
1624
1625 cont_path_cnt = 0;
1626 new_block = 1;
1627 j = 0;
1628 for (i = 0; i < MAX_PHASE + 1; i++) {
1629 if (phase_map & (1 << i)) {
1630 if (new_block) {
1631 new_block = 0;
1632 j = cont_path_cnt++;
1633 path[j].start = i;
1634 path[j].end = i;
1635 } else {
1636 path[j].end = i;
1637 }
1638 } else {
1639 new_block = 1;
1640 if (cont_path_cnt) {
1641 int idx = cont_path_cnt - 1;
1642 path[idx].len = path[idx].end - path[idx].start + 1;
1643 path[idx].mid = path[idx].start + path[idx].len / 2;
1644 }
1645 }
1646 }
1647
1648 if (cont_path_cnt == 0) {
1649 RTSX_DEBUGP("No continuous phase path\n");
1650 goto Search_Finish;
1651 } else {
1652 int idx = cont_path_cnt - 1;
1653 path[idx].len = path[idx].end - path[idx].start + 1;
1654 path[idx].mid = path[idx].start + path[idx].len / 2;
1655 }
1656
1657 if ((path[0].start == 0) && (path[cont_path_cnt - 1].end == MAX_PHASE)) {
1658 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1659 path[0].len += path[cont_path_cnt - 1].len;
1660 path[0].mid = path[0].start + path[0].len / 2;
1661 if (path[0].mid < 0) {
1662 path[0].mid += MAX_PHASE + 1;
1663 }
1664 cont_path_cnt--;
1665 }
1666
1667 max_len = 0;
1668 final_phase = 0;
1669 final_path_idx = 0;
1670 for (i = 0; i < cont_path_cnt; i++) {
1671 if (path[i].len > max_len) {
1672 max_len = path[i].len;
1673 final_phase = (u8)path[i].mid;
1674 final_path_idx = i;
1675 }
1676
1677 RTSX_DEBUGP("path[%d].start = %d\n", i, path[i].start);
1678 RTSX_DEBUGP("path[%d].end = %d\n", i, path[i].end);
1679 RTSX_DEBUGP("path[%d].len = %d\n", i, path[i].len);
1680 RTSX_DEBUGP("path[%d].mid = %d\n", i, path[i].mid);
1681 RTSX_DEBUGP("\n");
1682 }
1683
1684 if (tune_dir == TUNE_TX) {
1685 if (CHK_SD_SDR104(sd_card)) {
1686 if (max_len > 15) {
1687 int temp_mid = (max_len - 16) / 2;
1688 int temp_final_phase =
1689 path[final_path_idx].end - (max_len - (6 + temp_mid));
1690
1691 if (temp_final_phase < 0) {
1692 final_phase = (u8)(temp_final_phase + MAX_PHASE + 1);
1693 } else {
1694 final_phase = (u8)temp_final_phase;
1695 }
1696 }
1697 } else if (CHK_SD_SDR50(sd_card)) {
1698 if (max_len > 12) {
1699 int temp_mid = (max_len - 13) / 2;
1700 int temp_final_phase =
1701 path[final_path_idx].end - (max_len - (3 + temp_mid));
1702
1703 if (temp_final_phase < 0) {
1704 final_phase = (u8)(temp_final_phase + MAX_PHASE + 1);
1705 } else {
1706 final_phase = (u8)temp_final_phase;
1707 }
1708 }
1709 }
1710 }
1711
1712Search_Finish:
1713 RTSX_DEBUGP("Final choosen phase: %d\n", final_phase);
1714 return final_phase;
1715}
1716
1717static int sd_tuning_rx(struct rtsx_chip *chip)
1718{
1719 struct sd_info *sd_card = &(chip->sd_card);
1720 int retval;
1721 int i, j;
1722 u32 raw_phase_map[3], phase_map;
1723 u8 final_phase;
1724 int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1725
1726 if (CHK_SD(sd_card)) {
1727 if (CHK_SD_DDR50(sd_card)) {
1728 tuning_cmd = sd_ddr_tuning_rx_cmd;
1729 } else {
1730 tuning_cmd = sd_sdr_tuning_rx_cmd;
1731 }
1732 } else {
1733 if (CHK_MMC_DDR52(sd_card)) {
1734 tuning_cmd = mmc_ddr_tunning_rx_cmd;
1735 } else {
1736 TRACE_RET(chip, STATUS_FAIL);
1737 }
1738 }
1739
1740 for (i = 0; i < 3; i++) {
1741 raw_phase_map[i] = 0;
1742 for (j = MAX_PHASE; j >= 0; j--) {
1743 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1744 sd_set_err_code(chip, SD_NO_CARD);
1745 TRACE_RET(chip, STATUS_FAIL);
1746 }
1747
1748 retval = tuning_cmd(chip, (u8)j);
1749 if (retval == STATUS_SUCCESS) {
1750 raw_phase_map[i] |= 1 << j;
1751 }
1752 }
1753 }
1754
1755 phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1756 for (i = 0; i < 3; i++) {
1757 RTSX_DEBUGP("RX raw_phase_map[%d] = 0x%08x\n", i, raw_phase_map[i]);
1758 }
1759 RTSX_DEBUGP("RX phase_map = 0x%08x\n", phase_map);
1760
1761 final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX);
1762 if (final_phase == 0xFF) {
1763 TRACE_RET(chip, STATUS_FAIL);
1764 }
1765
1766 retval = sd_change_phase(chip, final_phase, TUNE_RX);
1767 if (retval != STATUS_SUCCESS) {
1768 TRACE_RET(chip, STATUS_FAIL);
1769 }
1770
1771 return STATUS_SUCCESS;
1772}
1773
1774static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip)
1775{
1776 struct sd_info *sd_card = &(chip->sd_card);
1777 int retval;
1778 int i;
1779 u32 phase_map;
1780 u8 final_phase;
1781
1782 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN);
1783
1784 phase_map = 0;
1785 for (i = MAX_PHASE; i >= 0; i--) {
1786 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1787 sd_set_err_code(chip, SD_NO_CARD);
1788 rtsx_write_register(chip, SD_CFG3,
1789 SD_RSP_80CLK_TIMEOUT_EN, 0);
1790 TRACE_RET(chip, STATUS_FAIL);
1791 }
1792
1793 retval = sd_change_phase(chip, (u8)i, TUNE_TX);
1794 if (retval != STATUS_SUCCESS) {
1795 continue;
1796 }
1797
1798 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1799 SD_RSP_TYPE_R1, NULL, 0);
1800 if ((retval == STATUS_SUCCESS) || !sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1801 phase_map |= 1 << i;
1802 }
1803 }
1804
1805 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1806
1807 RTSX_DEBUGP("DDR TX pre tune phase_map = 0x%08x\n", phase_map);
1808
1809 final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1810 if (final_phase == 0xFF) {
1811 TRACE_RET(chip, STATUS_FAIL);
1812 }
1813
1814 retval = sd_change_phase(chip, final_phase, TUNE_TX);
1815 if (retval != STATUS_SUCCESS) {
1816 TRACE_RET(chip, STATUS_FAIL);
1817 }
1818
1819 RTSX_DEBUGP("DDR TX pre tune phase: %d\n", (int)final_phase);
1820
1821 return STATUS_SUCCESS;
1822}
1823
1824static int sd_tuning_tx(struct rtsx_chip *chip)
1825{
1826 struct sd_info *sd_card = &(chip->sd_card);
1827 int retval;
1828 int i, j;
1829 u32 raw_phase_map[3], phase_map;
1830 u8 final_phase;
1831 int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1832
1833 if (CHK_SD(sd_card)) {
1834 if (CHK_SD_DDR50(sd_card)) {
1835 tuning_cmd = sd_ddr_tuning_tx_cmd;
1836 } else {
1837 tuning_cmd = sd_sdr_tuning_tx_cmd;
1838 }
1839 } else {
1840 if (CHK_MMC_DDR52(sd_card)) {
1841 tuning_cmd = sd_ddr_tuning_tx_cmd;
1842 } else {
1843 TRACE_RET(chip, STATUS_FAIL);
1844 }
1845 }
1846
1847 for (i = 0; i < 3; i++) {
1848 raw_phase_map[i] = 0;
1849 for (j = MAX_PHASE; j >= 0; j--) {
1850 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1851 sd_set_err_code(chip, SD_NO_CARD);
1852 rtsx_write_register(chip, SD_CFG3,
1853 SD_RSP_80CLK_TIMEOUT_EN, 0);
1854 TRACE_RET(chip, STATUS_FAIL);
1855 }
1856
1857 retval = tuning_cmd(chip, (u8)j);
1858 if (retval == STATUS_SUCCESS) {
1859 raw_phase_map[i] |= 1 << j;
1860 }
1861 }
1862 }
1863
1864 phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1865 for (i = 0; i < 3; i++) {
1866 RTSX_DEBUGP("TX raw_phase_map[%d] = 0x%08x\n", i, raw_phase_map[i]);
1867 }
1868 RTSX_DEBUGP("TX phase_map = 0x%08x\n", phase_map);
1869
1870 final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1871 if (final_phase == 0xFF) {
1872 TRACE_RET(chip, STATUS_FAIL);
1873 }
1874
1875 retval = sd_change_phase(chip, final_phase, TUNE_TX);
1876 if (retval != STATUS_SUCCESS) {
1877 TRACE_RET(chip, STATUS_FAIL);
1878 }
1879
1880 return STATUS_SUCCESS;
1881}
1882
1883static int sd_sdr_tuning(struct rtsx_chip *chip)
1884{
1885 int retval;
1886
1887 retval = sd_tuning_tx(chip);
1888 if (retval != STATUS_SUCCESS) {
1889 TRACE_RET(chip, STATUS_FAIL);
1890 }
1891
1892 retval = sd_tuning_rx(chip);
1893 if (retval != STATUS_SUCCESS) {
1894 TRACE_RET(chip, STATUS_FAIL);
1895 }
1896
1897 return STATUS_SUCCESS;
1898}
1899
1900static int sd_ddr_tuning(struct rtsx_chip *chip)
1901{
1902 int retval;
1903
1904 if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1905 retval = sd_ddr_pre_tuning_tx(chip);
1906 if (retval != STATUS_SUCCESS) {
1907 TRACE_RET(chip, STATUS_FAIL);
1908 }
1909 } else {
1910 retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase, TUNE_TX);
1911 if (retval != STATUS_SUCCESS) {
1912 TRACE_RET(chip, STATUS_FAIL);
1913 }
1914 }
1915
1916 retval = sd_tuning_rx(chip);
1917 if (retval != STATUS_SUCCESS) {
1918 TRACE_RET(chip, STATUS_FAIL);
1919 }
1920
1921 if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1922 retval = sd_tuning_tx(chip);
1923 if (retval != STATUS_SUCCESS) {
1924 TRACE_RET(chip, STATUS_FAIL);
1925 }
1926 }
1927
1928 return STATUS_SUCCESS;
1929}
1930
1931static int mmc_ddr_tuning(struct rtsx_chip *chip)
1932{
1933 int retval;
1934
1935 if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1936 retval = sd_ddr_pre_tuning_tx(chip);
1937 if (retval != STATUS_SUCCESS) {
1938 TRACE_RET(chip, STATUS_FAIL);
1939 }
1940 } else {
1941 retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase, TUNE_TX);
1942 if (retval != STATUS_SUCCESS) {
1943 TRACE_RET(chip, STATUS_FAIL);
1944 }
1945 }
1946
1947 retval = sd_tuning_rx(chip);
1948 if (retval != STATUS_SUCCESS) {
1949 TRACE_RET(chip, STATUS_FAIL);
1950 }
1951
1952 if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1953 retval = sd_tuning_tx(chip);
1954 if (retval != STATUS_SUCCESS) {
1955 TRACE_RET(chip, STATUS_FAIL);
1956 }
1957 }
1958
1959 return STATUS_SUCCESS;
1960}
1961
1962int sd_switch_clock(struct rtsx_chip *chip)
1963{
1964 struct sd_info *sd_card = &(chip->sd_card);
1965 int retval;
1966 int re_tuning = 0;
1967
1968 retval = select_card(chip, SD_CARD);
1969 if (retval != STATUS_SUCCESS) {
1970 TRACE_RET(chip, STATUS_FAIL);
1971 }
1972
1973 if (CHECK_PID(chip, 0x5209) &&
1974 (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))) {
1975 if (sd_card->need_retune && (sd_card->sd_clock != chip->cur_clk)) {
1976 re_tuning = 1;
1977 sd_card->need_retune = 0;
1978 }
1979 }
1980
1981 retval = switch_clock(chip, sd_card->sd_clock);
1982 if (retval != STATUS_SUCCESS) {
1983 TRACE_RET(chip, STATUS_FAIL);
1984 }
1985
1986 if (re_tuning) {
1987 if (CHK_SD(sd_card)) {
1988 if (CHK_SD_DDR50(sd_card)) {
1989 retval = sd_ddr_tuning(chip);
1990 } else {
1991 retval = sd_sdr_tuning(chip);
1992 }
1993 } else {
1994 if (CHK_MMC_DDR52(sd_card)) {
1995 retval = mmc_ddr_tuning(chip);
1996 }
1997 }
1998
1999 if (retval != STATUS_SUCCESS) {
2000 TRACE_RET(chip, STATUS_FAIL);
2001 }
2002 }
2003
2004 return STATUS_SUCCESS;
2005}
2006
2007static int sd_prepare_reset(struct rtsx_chip *chip)
2008{
2009 struct sd_info *sd_card = &(chip->sd_card);
2010 int retval;
2011
2012 if (chip->asic_code) {
2013 sd_card->sd_clock = 29;
2014 } else {
2015 sd_card->sd_clock = CLK_30;
2016 }
2017
2018 chip->sd_io = 0;
2019
2020 retval = sd_set_init_para(chip);
2021 if (retval != STATUS_SUCCESS) {
2022 TRACE_RET(chip, retval);
2023 }
2024
2025 if (CHECK_PID(chip, 0x5209)) {
2026 RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF,
2027 SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1);
2028 RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, 0xFF, SD20_RX_POS_EDGE);
2029 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0xFF, 0);
2030 } else {
2031 RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF, 0x40);
2032 }
2033
2034 RTSX_WRITE_REG(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
2035
2036 retval = select_card(chip, SD_CARD);
2037 if (retval != STATUS_SUCCESS) {
2038 TRACE_RET(chip, STATUS_FAIL);
2039 }
2040
2041 return STATUS_SUCCESS;
2042}
2043
2044static int sd_pull_ctl_disable(struct rtsx_chip *chip)
2045{
2046 if (CHECK_PID(chip, 0x5209)) {
2047 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
2048 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
2049 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0xD5);
2050 } else if (CHECK_PID(chip, 0x5208)) {
2051 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
2052 XD_D3_PD | SD_D7_PD | SD_CLK_PD | SD_D5_PD);
2053 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
2054 SD_D6_PD | SD_D0_PD | SD_D1_PD | XD_D5_PD);
2055 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
2056 SD_D4_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
2057 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
2058 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
2059 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
2060 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
2061 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
2062 } else if (CHECK_PID(chip, 0x5288)) {
2063 if (CHECK_BARO_PKG(chip, QFN)) {
2064 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
2065 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
2066 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
2067 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
2068 }
2069 }
2070
2071 return STATUS_SUCCESS;
2072}
2073
2074int sd_pull_ctl_enable(struct rtsx_chip *chip)
2075{
2076 int retval;
2077
2078 rtsx_init_cmd(chip);
2079
2080 if (CHECK_PID(chip, 0x5209)) {
2081 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA);
2082 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0xAA);
2083 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xE9);
2084 } else if (CHECK_PID(chip, 0x5208)) {
2085 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
2086 XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU);
2087 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
2088 SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD);
2089 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
2090 SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
2091 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
2092 XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD);
2093 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
2094 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
2095 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
2096 } else if (CHECK_PID(chip, 0x5288)) {
2097 if (CHECK_BARO_PKG(chip, QFN)) {
2098 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xA8);
2099 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x5A);
2100 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
2101 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0xAA);
2102 }
2103 }
2104
2105 retval = rtsx_send_cmd(chip, SD_CARD, 100);
2106 if (retval < 0) {
2107 TRACE_RET(chip, STATUS_FAIL);
2108 }
2109
2110 return STATUS_SUCCESS;
2111}
2112
2113static int sd_init_power(struct rtsx_chip *chip)
2114{
2115 int retval;
2116
2117 if (CHECK_PID(chip, 0x5209)) {
2118 RTSX_WRITE_REG(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_OFF);
2119 }
2120
2121 retval = sd_power_off_card3v3(chip);
2122 if (retval != STATUS_SUCCESS) {
2123 TRACE_RET(chip, STATUS_FAIL);
2124 }
2125
2126 if (!chip->ft2_fast_mode) {
2127 wait_timeout(250);
2128 }
2129
2130 retval = enable_card_clock(chip, SD_CARD);
2131 if (retval != STATUS_SUCCESS) {
2132 TRACE_RET(chip, STATUS_FAIL);
2133 }
2134
2135 if (chip->asic_code) {
2136 retval = sd_pull_ctl_enable(chip);
2137 if (retval != STATUS_SUCCESS) {
2138 TRACE_RET(chip, STATUS_FAIL);
2139 }
2140 } else {
2141 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_SD_PULL_CTL_BIT | 0x20, 0);
2142 }
2143
2144 if (chip->ft2_fast_mode) {
2145 if (CHECK_PID(chip, 0x5209)) {
2146 RTSX_WRITE_REG(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_ON);
2147 }
2148 } else {
2149 retval = card_power_on(chip, SD_CARD);
2150 if (retval != STATUS_SUCCESS) {
2151 TRACE_RET(chip, STATUS_FAIL);
2152 }
2153 wait_timeout(260);
2154
2155#ifdef SUPPORT_OCP
2156 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
2157 RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat);
2158 TRACE_RET(chip, STATUS_FAIL);
2159 }
2160#endif
2161 }
2162
2163 RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
2164
2165 return STATUS_SUCCESS;
2166}
2167
2168static int sd_dummy_clock(struct rtsx_chip *chip)
2169{
2170 if (CHECK_PID(chip, 0x5209)) {
2171 RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
2172 wait_timeout(5);
2173 RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0x00);
2174 } else {
2175 RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0x01);
2176 wait_timeout(5);
2177 RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0);
2178 }
2179
2180 return STATUS_SUCCESS;
2181}
2182
2183static int sd_read_lba0(struct rtsx_chip *chip)
2184{
2185 struct sd_info *sd_card = &(chip->sd_card);
2186 int retval;
2187 u8 cmd[5], bus_width;
2188
2189 cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2190 cmd[1] = 0;
2191 cmd[2] = 0;
2192 cmd[3] = 0;
2193 cmd[4] = 0;
2194
2195 if (CHK_SD(sd_card)) {
2196 bus_width = SD_BUS_WIDTH_4;
2197 } else {
2198 if (CHK_MMC_8BIT(sd_card)) {
2199 bus_width = SD_BUS_WIDTH_8;
2200 } else if (CHK_MMC_4BIT(sd_card)) {
2201 bus_width = SD_BUS_WIDTH_4;
2202 } else {
2203 bus_width = SD_BUS_WIDTH_1;
2204 }
2205 }
2206
2207 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd,
2208 5, 512, 1, bus_width, NULL, 0, 100);
2209 if (retval != STATUS_SUCCESS) {
2210 TRACE_RET(chip, STATUS_FAIL);
2211 }
2212
2213 return STATUS_SUCCESS;
2214}
2215
2216static int sd_check_wp_state(struct rtsx_chip *chip)
2217{
2218 struct sd_info *sd_card = &(chip->sd_card);
2219 int retval;
2220 u32 val;
2221 u16 sd_card_type;
2222 u8 cmd[5], buf[64];
2223
2224 retval = sd_send_cmd_get_rsp(chip, APP_CMD,
2225 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2226 if (retval != STATUS_SUCCESS) {
2227 TRACE_RET(chip, STATUS_FAIL);
2228 }
2229
2230 cmd[0] = 0x40 | SD_STATUS;
2231 cmd[1] = 0;
2232 cmd[2] = 0;
2233 cmd[3] = 0;
2234 cmd[4] = 0;
2235
2236 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, SD_BUS_WIDTH_4, buf, 64, 250);
2237 if (retval != STATUS_SUCCESS) {
2238 rtsx_clear_sd_error(chip);
2239
2240 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2241 TRACE_RET(chip, STATUS_FAIL);
2242 }
2243
2244 RTSX_DEBUGP("ACMD13:\n");
2245 RTSX_DUMP(buf, 64);
2246
2247 sd_card_type = ((u16)buf[2] << 8) | buf[3];
2248 RTSX_DEBUGP("sd_card_type = 0x%04x\n", sd_card_type);
2249 if ((sd_card_type == 0x0001) || (sd_card_type == 0x0002)) {
2250 /* ROM card or OTP */
2251 chip->card_wp |= SD_CARD;
2252 }
2253
2254 /* Check SD Machanical Write-Protect Switch */
2255 val = rtsx_readl(chip, RTSX_BIPR);
2256 if (val & SD_WRITE_PROTECT) {
2257 chip->card_wp |= SD_CARD;
2258 }
2259
2260 return STATUS_SUCCESS;
2261}
2262
2263static int reset_sd(struct rtsx_chip *chip)
2264{
2265 struct sd_info *sd_card = &(chip->sd_card);
2266 int retval, i = 0, j = 0, k = 0, hi_cap_flow = 0;
2267 int sd_dont_switch = 0;
2268 int support_1v8 = 0;
2269 int try_sdio = 1;
2270 u8 rsp[16];
2271 u8 switch_bus_width;
2272 u32 voltage = 0;
2273 int sd20_mode = 0;
2274
2275 SET_SD(sd_card);
2276
2277Switch_Fail:
2278
2279 i = 0;
2280 j = 0;
2281 k = 0;
2282 hi_cap_flow = 0;
2283
2284#ifdef SUPPORT_SD_LOCK
2285 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2286 goto SD_UNLOCK_ENTRY;
2287#endif
2288
2289 retval = sd_prepare_reset(chip);
2290 if (retval != STATUS_SUCCESS) {
2291 TRACE_RET(chip, STATUS_FAIL);
2292 }
2293
2294 retval = sd_dummy_clock(chip);
2295 if (retval != STATUS_SUCCESS) {
2296 TRACE_RET(chip, STATUS_FAIL);
2297 }
2298
2299 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) {
2300 int rty_cnt = 0;
2301
2302 for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) {
2303 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2304 sd_set_err_code(chip, SD_NO_CARD);
2305 TRACE_RET(chip, STATUS_FAIL);
2306 }
2307
2308 retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0, SD_RSP_TYPE_R4, rsp, 5);
2309 if (retval == STATUS_SUCCESS) {
2310 int func_num = (rsp[1] >> 4) && 0x07;
2311 if (func_num) {
2312 RTSX_DEBUGP("SD_IO card (Function number: %d)!\n", func_num);
2313 chip->sd_io = 1;
2314 TRACE_RET(chip, STATUS_FAIL);
2315 }
2316
2317 break;
2318 }
2319
2320 sd_init_power(chip);
2321
2322 sd_dummy_clock(chip);
2323 }
2324
2325 RTSX_DEBUGP("Normal card!\n");
2326 }
2327
2328 /* Start Initialization Process of SD Card */
2329RTY_SD_RST:
2330 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0);
2331 if (retval != STATUS_SUCCESS) {
2332 TRACE_RET(chip, STATUS_FAIL);
2333 }
2334
2335 wait_timeout(20);
2336
2337 retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA, SD_RSP_TYPE_R7, rsp, 5);
2338 if (retval == STATUS_SUCCESS) {
2339 if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) {
2340 hi_cap_flow = 1;
2341 if (CHECK_PID(chip, 0x5209)) {
2342 if (sd20_mode) {
2343 voltage = SUPPORT_VOLTAGE |
2344 SUPPORT_HIGH_AND_EXTENDED_CAPACITY;
2345 } else {
2346 voltage = SUPPORT_VOLTAGE |
2347 SUPPORT_HIGH_AND_EXTENDED_CAPACITY |
2348 SUPPORT_MAX_POWER_PERMANCE | SUPPORT_1V8;
2349 }
2350 } else {
2351 voltage = SUPPORT_VOLTAGE | 0x40000000;
2352 }
2353 }
2354 }
2355
2356 if (!hi_cap_flow) {
2357 voltage = SUPPORT_VOLTAGE;
2358
2359 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0);
2360 if (retval != STATUS_SUCCESS) {
2361 TRACE_RET(chip, STATUS_FAIL);
2362 }
2363
2364 wait_timeout(20);
2365 }
2366
2367 do {
2368 retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1, NULL, 0);
2369 if (retval != STATUS_SUCCESS) {
2370 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2371 sd_set_err_code(chip, SD_NO_CARD);
2372 TRACE_RET(chip, STATUS_FAIL);
2373 }
2374
2375 j++;
2376 if (j < 3) {
2377 goto RTY_SD_RST;
2378 } else {
2379 TRACE_RET(chip, STATUS_FAIL);
2380 }
2381 }
2382
2383 retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage, SD_RSP_TYPE_R3, rsp, 5);
2384 if (retval != STATUS_SUCCESS) {
2385 k++;
2386 if (k < 3) {
2387 goto RTY_SD_RST;
2388 } else {
2389 TRACE_RET(chip, STATUS_FAIL);
2390 }
2391 }
2392
2393 i++;
2394 wait_timeout(20);
2395 } while (!(rsp[1] & 0x80) && (i < 255));
2396
2397 if (i == 255) {
2398 TRACE_RET(chip, STATUS_FAIL);
2399 }
2400
2401 if (hi_cap_flow) {
2402 if (rsp[1] & 0x40) {
2403 SET_SD_HCXC(sd_card);
2404 } else {
2405 CLR_SD_HCXC(sd_card);
2406 }
2407 if (CHECK_PID(chip, 0x5209) && CHK_SD_HCXC(sd_card) && !sd20_mode) {
2408 support_1v8 = (rsp[1] & 0x01) ? 1 : 0;
2409 } else {
2410 support_1v8 = 0;
2411 }
2412 } else {
2413 CLR_SD_HCXC(sd_card);
2414 support_1v8 = 0;
2415 }
2416 RTSX_DEBUGP("support_1v8 = %d\n", support_1v8);
2417
2418 if (support_1v8) {
2419 retval = sd_voltage_switch(chip);
2420 if (retval != STATUS_SUCCESS) {
2421 TRACE_RET(chip, STATUS_FAIL);
2422 }
2423 }
2424
2425 retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0);
2426 if (retval != STATUS_SUCCESS) {
2427 TRACE_RET(chip, STATUS_FAIL);
2428 }
2429
2430 for (i = 0; i < 3; i++) {
2431 retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0, SD_RSP_TYPE_R6, rsp, 5);
2432 if (retval != STATUS_SUCCESS) {
2433 TRACE_RET(chip, STATUS_FAIL);
2434 }
2435
2436 sd_card->sd_addr = (u32)rsp[1] << 24;
2437 sd_card->sd_addr += (u32)rsp[2] << 16;
2438
2439 if (sd_card->sd_addr) {
2440 break;
2441 }
2442 }
2443
2444 retval = sd_check_csd(chip, 1);
2445 if (retval != STATUS_SUCCESS) {
2446 TRACE_RET(chip, STATUS_FAIL);
2447 }
2448
2449 retval = sd_select_card(chip, 1);
2450 if (retval != STATUS_SUCCESS) {
2451 TRACE_RET(chip, STATUS_FAIL);
2452 }
2453
2454#ifdef SUPPORT_SD_LOCK
2455SD_UNLOCK_ENTRY:
2456 retval = sd_update_lock_status(chip);
2457 if (retval != STATUS_SUCCESS) {
2458 TRACE_RET(chip, STATUS_FAIL);
2459 }
2460
2461 if (sd_card->sd_lock_status & SD_LOCKED) {
2462 sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST);
2463 return STATUS_SUCCESS;
2464 } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) {
2465 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
2466 }
2467#endif
2468
2469 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2470 if (retval != STATUS_SUCCESS) {
2471 TRACE_RET(chip, STATUS_FAIL);
2472 }
2473 retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0, SD_RSP_TYPE_R1, NULL, 0);
2474 if (retval != STATUS_SUCCESS) {
2475 TRACE_RET(chip, STATUS_FAIL);
2476 }
2477
2478 if (support_1v8) {
2479 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2480 if (retval != STATUS_SUCCESS) {
2481 TRACE_RET(chip, STATUS_FAIL);
2482 }
2483 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1, NULL, 0);
2484 if (retval != STATUS_SUCCESS) {
2485 TRACE_RET(chip, STATUS_FAIL);
2486 }
2487
2488 switch_bus_width = SD_BUS_WIDTH_4;
2489 } else {
2490 switch_bus_width = SD_BUS_WIDTH_1;
2491 }
2492
2493 retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, NULL, 0);
2494 if (retval != STATUS_SUCCESS) {
2495 TRACE_RET(chip, STATUS_FAIL);
2496 }
2497
2498 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2499 if (retval != STATUS_SUCCESS) {
2500 TRACE_RET(chip, STATUS_FAIL);
2501 }
2502
2503 if (!(sd_card->raw_csd[4] & 0x40))
2504 sd_dont_switch = 1;
2505
2506 if (!sd_dont_switch) {
2507 retval = sd_check_spec(chip, switch_bus_width);
2508 if (retval == STATUS_SUCCESS) {
2509 retval = sd_switch_function(chip, switch_bus_width);
2510 if (retval != STATUS_SUCCESS) {
2511 if (CHECK_PID(chip, 0x5209)) {
2512 sd_change_bank_voltage(chip, SD_IO_3V3);
2513 }
2514 sd_init_power(chip);
2515 sd_dont_switch = 1;
2516 try_sdio = 0;
2517
2518 goto Switch_Fail;
2519 }
2520 } else {
2521 if (support_1v8) {
2522 if (CHECK_PID(chip, 0x5209)) {
2523 sd_change_bank_voltage(chip, SD_IO_3V3);
2524 }
2525 sd_init_power(chip);
2526 sd_dont_switch = 1;
2527 try_sdio = 0;
2528
2529 goto Switch_Fail;
2530 }
2531 }
2532 }
2533
2534 if (!support_1v8) {
2535 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2536 if (retval != STATUS_SUCCESS) {
2537 TRACE_RET(chip, STATUS_FAIL);
2538 }
2539 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1, NULL, 0);
2540 if (retval != STATUS_SUCCESS) {
2541 TRACE_RET(chip, STATUS_FAIL);
2542 }
2543 }
2544
2545#ifdef SUPPORT_SD_LOCK
2546 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2547#endif
2548
2549 if (CHK_SD30_SPEED(sd_card)) {
2550 int read_lba0 = 1;
2551
2552 RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_1v8);
2553
2554 retval = sd_set_init_para(chip);
2555 if (retval != STATUS_SUCCESS) {
2556 TRACE_RET(chip, STATUS_FAIL);
2557 }
2558
2559 if (CHK_SD_DDR50(sd_card)) {
2560 retval = sd_ddr_tuning(chip);
2561 } else {
2562 retval = sd_sdr_tuning(chip);
2563 }
2564
2565 if (retval != STATUS_SUCCESS) {
2566 if (sd20_mode) {
2567 TRACE_RET(chip, STATUS_FAIL);
2568 } else {
2569 retval = sd_init_power(chip);
2570 if (retval != STATUS_SUCCESS) {
2571 TRACE_RET(chip, STATUS_FAIL);
2572 }
2573 try_sdio = 0;
2574 sd20_mode = 1;
2575 goto Switch_Fail;
2576 }
2577 }
2578
2579 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2580
2581 if (CHK_SD_DDR50(sd_card)) {
2582 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
2583 if (retval != STATUS_SUCCESS) {
2584 read_lba0 = 0;
2585 }
2586 }
2587
2588 if (read_lba0) {
2589 retval = sd_read_lba0(chip);
2590 if (retval != STATUS_SUCCESS) {
2591 if (sd20_mode) {
2592 TRACE_RET(chip, STATUS_FAIL);
2593 } else {
2594 retval = sd_init_power(chip);
2595 if (retval != STATUS_SUCCESS) {
2596 TRACE_RET(chip, STATUS_FAIL);
2597 }
2598 try_sdio = 0;
2599 sd20_mode = 1;
2600 goto Switch_Fail;
2601 }
2602 }
2603 }
2604 }
2605
2606 retval = sd_check_wp_state(chip);
2607 if (retval != STATUS_SUCCESS) {
2608 TRACE_RET(chip, STATUS_FAIL);
2609 }
2610
2611 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2612
2613#ifdef SUPPORT_SD_LOCK
2614 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2615 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02);
2616 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00);
2617 }
2618#endif
2619
2620 return STATUS_SUCCESS;
2621}
2622
2623
2624static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width)
2625{
2626 struct sd_info *sd_card = &(chip->sd_card);
2627 int retval;
2628 u8 buf[8] = {0}, bus_width, *ptr;
2629 u16 byte_cnt;
2630 int len;
2631
2632 retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL, 0);
2633 if (retval != STATUS_SUCCESS) {
2634 TRACE_RET(chip, STATUS_FAIL);
2635 }
2636
2637 if (width == MMC_8BIT_BUS) {
2638 buf[0] = 0x55;
2639 buf[1] = 0xAA;
2640 len = 8;
2641 byte_cnt = 8;
2642 bus_width = SD_BUS_WIDTH_8;
2643 } else {
2644 buf[0] = 0x5A;
2645 len = 4;
2646 byte_cnt = 4;
2647 bus_width = SD_BUS_WIDTH_4;
2648 }
2649
2650 if (!CHECK_PID(chip, 0x5209)) {
2651 RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x02, 0x02);
2652 }
2653
2654 retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3,
2655 NULL, 0, byte_cnt, 1, bus_width, buf, len, 100);
2656 if (retval != STATUS_SUCCESS) {
2657 if (CHECK_PID(chip, 0x5209)) {
2658 u8 val1 = 0, val2 = 0;
2659 rtsx_read_register(chip, REG_SD_STAT1, &val1);
2660 rtsx_read_register(chip, REG_SD_STAT2, &val2);
2661 rtsx_clear_sd_error(chip);
2662 if ((val1 & 0xE0) || val2) {
2663 TRACE_RET(chip, STATUS_FAIL);
2664 }
2665 } else {
2666 rtsx_clear_sd_error(chip);
2667 rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2668 TRACE_RET(chip, STATUS_FAIL);
2669 }
2670 }
2671
2672 if (!CHECK_PID(chip, 0x5209)) {
2673 RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x02, 0);
2674 }
2675
2676 RTSX_DEBUGP("SD/MMC CMD %d\n", BUSTEST_R);
2677
2678 rtsx_init_cmd(chip);
2679
2680 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R);
2681
2682 if (width == MMC_8BIT_BUS) {
2683 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x08);
2684 } else {
2685 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x04);
2686 }
2687
2688 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2689 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2690
2691 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2692 SD_CALCULATE_CRC7 | SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2693 SD_CHECK_CRC7 | SD_RSP_LEN_6);
2694 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
2695 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_NORMAL_READ | SD_TRANSFER_START);
2696 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
2697
2698 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0);
2699 if (width == MMC_8BIT_BUS) {
2700 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0);
2701 }
2702
2703 retval = rtsx_send_cmd(chip, SD_CARD, 100);
2704 if (retval < 0) {
2705 rtsx_clear_sd_error(chip);
2706 TRACE_RET(chip, STATUS_FAIL);
2707 }
2708
2709 ptr = rtsx_get_cmd_data(chip) + 1;
2710
2711 if (width == MMC_8BIT_BUS) {
2712 RTSX_DEBUGP("BUSTEST_R [8bits]: 0x%02x 0x%02x\n", ptr[0], ptr[1]);
2713 if ((ptr[0] == 0xAA) && (ptr[1] == 0x55)) {
2714 u8 rsp[5];
2715 u32 arg;
2716
2717 if (CHK_MMC_DDR52(sd_card)) {
2718 arg = 0x03B70600;
2719 } else {
2720 arg = 0x03B70200;
2721 }
2722 retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, SD_RSP_TYPE_R1b, rsp, 5);
2723 if ((retval == STATUS_SUCCESS) && !(rsp[4] & MMC_SWITCH_ERR)) {
2724 return STATUS_SUCCESS;
2725 }
2726 }
2727 } else {
2728 RTSX_DEBUGP("BUSTEST_R [4bits]: 0x%02x\n", ptr[0]);
2729 if (ptr[0] == 0xA5) {
2730 u8 rsp[5];
2731 u32 arg;
2732
2733 if (CHK_MMC_DDR52(sd_card)) {
2734 arg = 0x03B70500;
2735 } else {
2736 arg = 0x03B70100;
2737 }
2738 retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, SD_RSP_TYPE_R1b, rsp, 5);
2739 if ((retval == STATUS_SUCCESS) && !(rsp[4] & MMC_SWITCH_ERR)) {
2740 return STATUS_SUCCESS;
2741 }
2742 }
2743 }
2744
2745 TRACE_RET(chip, STATUS_FAIL);
2746}
2747
2748
2749static int mmc_switch_timing_bus(struct rtsx_chip *chip, int switch_ddr)
2750{
2751 struct sd_info *sd_card = &(chip->sd_card);
2752 int retval;
2753 u8 *ptr, card_type, card_type_mask = 0;
2754
2755 CLR_MMC_HS(sd_card);
2756
2757 RTSX_DEBUGP("SD/MMC CMD %d\n", SEND_EXT_CSD);
2758
2759 rtsx_init_cmd(chip);
2760
2761 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | SEND_EXT_CSD);
2762 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0);
2763 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0);
2764 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0);
2765 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0);
2766
2767 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0);
2768 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2);
2769 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2770 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2771
2772 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2773 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2774 SD_CHECK_CRC7 | SD_RSP_LEN_6);
2775 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
2776 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_NORMAL_READ | SD_TRANSFER_START);
2777 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
2778
2779 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0);
2780 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0);
2781 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0);
2782 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0);
2783 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0);
2784
2785 retval = rtsx_send_cmd(chip, SD_CARD, 1000);
2786 if (retval < 0) {
2787 if (retval == -ETIMEDOUT) {
2788 rtsx_clear_sd_error(chip);
2789 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2790 SD_RSP_TYPE_R1, NULL, 0);
2791 }
2792 TRACE_RET(chip, STATUS_FAIL);
2793 }
2794
2795 ptr = rtsx_get_cmd_data(chip);
2796 if (ptr[0] & SD_TRANSFER_ERR) {
2797 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2798 TRACE_RET(chip, STATUS_FAIL);
2799 }
2800
2801 if (CHK_MMC_SECTOR_MODE(sd_card)) {
2802 sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) |
2803 ((u32)ptr[3] << 8) | ((u32)ptr[2]);
2804 }
2805
2806 if (CHECK_PID(chip, 0x5209)) {
2807#ifdef SUPPORT_SD_LOCK
2808 if (!(sd_card->sd_lock_status & SD_SDR_RST) &&
2809 (chip->sd_ctl & SUPPORT_MMC_DDR_MODE)) {
2810 card_type_mask = 0x07;
2811 } else {
2812 card_type_mask = 0x03;
2813 }
2814#else
2815 if (chip->sd_ctl & SUPPORT_MMC_DDR_MODE) {
2816 card_type_mask = 0x07;
2817 } else {
2818 card_type_mask = 0x03;
2819 }
2820#endif
2821 } else {
2822 card_type_mask = 0x03;
2823 }
2824 card_type = ptr[1] & card_type_mask;
2825 if (card_type) {
2826 u8 rsp[5];
2827
2828 if (card_type & 0x04) {
2829 if (switch_ddr) {
2830 SET_MMC_DDR52(sd_card);
2831 } else {
2832 SET_MMC_52M(sd_card);
2833 }
2834 } else if (card_type & 0x02) {
2835 SET_MMC_52M(sd_card);
2836 } else {
2837 SET_MMC_26M(sd_card);
2838 }
2839
2840 retval = sd_send_cmd_get_rsp(chip, SWITCH,
2841 0x03B90100, SD_RSP_TYPE_R1b, rsp, 5);
2842 if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR)) {
2843 CLR_MMC_HS(sd_card);
2844 }
2845 }
2846
2847 sd_choose_proper_clock(chip);
2848 retval = switch_clock(chip, sd_card->sd_clock);
2849 if (retval != STATUS_SUCCESS) {
2850 TRACE_RET(chip, STATUS_FAIL);
2851 }
2852
2853 if (mmc_test_switch_bus(chip, MMC_8BIT_BUS) == STATUS_SUCCESS) {
2854 SET_MMC_8BIT(sd_card);
2855 chip->card_bus_width[chip->card2lun[SD_CARD]] = 8;
2856#ifdef SUPPORT_SD_LOCK
2857 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2858#endif
2859 } else if (mmc_test_switch_bus(chip, MMC_4BIT_BUS) == STATUS_SUCCESS) {
2860 SET_MMC_4BIT(sd_card);
2861 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2862#ifdef SUPPORT_SD_LOCK
2863 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2864#endif
2865 } else {
2866 CLR_MMC_8BIT(sd_card);
2867 CLR_MMC_4BIT(sd_card);
2868 }
2869
2870 return STATUS_SUCCESS;
2871}
2872
2873
2874static int reset_mmc(struct rtsx_chip *chip)
2875{
2876 struct sd_info *sd_card = &(chip->sd_card);
2877 int retval, i = 0, j = 0, k = 0;
2878 int switch_ddr = 1;
2879 u8 rsp[16];
2880 u8 spec_ver = 0;
2881 u32 temp;
2882
2883#ifdef SUPPORT_SD_LOCK
2884 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2885 goto MMC_UNLOCK_ENTRY;
2886#endif
2887
2888DDR_TUNING_FAIL:
2889
2890 retval = sd_prepare_reset(chip);
2891 if (retval != STATUS_SUCCESS) {
2892 TRACE_RET(chip, retval);
2893 }
2894
2895 SET_MMC(sd_card);
2896
2897RTY_MMC_RST:
2898 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0);
2899 if (retval != STATUS_SUCCESS) {
2900 TRACE_RET(chip, STATUS_FAIL);
2901 }
2902
2903 do {
2904 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2905 sd_set_err_code(chip, SD_NO_CARD);
2906 TRACE_RET(chip, STATUS_FAIL);
2907 }
2908
2909 retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND,
2910 (SUPPORT_VOLTAGE|0x40000000), SD_RSP_TYPE_R3, rsp, 5);
2911 if (retval != STATUS_SUCCESS) {
2912 if (sd_check_err_code(chip, SD_BUSY) || sd_check_err_code(chip, SD_TO_ERR)) {
2913 k++;
2914 if (k < 20) {
2915 sd_clr_err_code(chip);
2916 goto RTY_MMC_RST;
2917 } else {
2918 TRACE_RET(chip, STATUS_FAIL);
2919 }
2920 } else {
2921 j++;
2922 if (j < 100) {
2923 sd_clr_err_code(chip);
2924 goto RTY_MMC_RST;
2925 } else {
2926 TRACE_RET(chip, STATUS_FAIL);
2927 }
2928 }
2929 }
2930
2931 wait_timeout(20);
2932 i++;
2933 } while (!(rsp[1] & 0x80) && (i < 255));
2934
2935 if (i == 255) {
2936 TRACE_RET(chip, STATUS_FAIL);
2937 }
2938
2939 if ((rsp[1] & 0x60) == 0x40) {
2940 SET_MMC_SECTOR_MODE(sd_card);
2941 } else {
2942 CLR_MMC_SECTOR_MODE(sd_card);
2943 }
2944
2945 retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0);
2946 if (retval != STATUS_SUCCESS) {
2947 TRACE_RET(chip, STATUS_FAIL);
2948 }
2949
2950 sd_card->sd_addr = 0x00100000;
2951 retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr, SD_RSP_TYPE_R6, rsp, 5);
2952 if (retval != STATUS_SUCCESS) {
2953 TRACE_RET(chip, STATUS_FAIL);
2954 }
2955
2956 retval = sd_check_csd(chip, 1);
2957 if (retval != STATUS_SUCCESS) {
2958 TRACE_RET(chip, STATUS_FAIL);
2959 }
2960
2961 spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2;
2962
2963 retval = sd_select_card(chip, 1);
2964 if (retval != STATUS_SUCCESS) {
2965 TRACE_RET(chip, STATUS_FAIL);
2966 }
2967
2968 retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, NULL, 0);
2969 if (retval != STATUS_SUCCESS) {
2970 TRACE_RET(chip, STATUS_FAIL);
2971 }
2972
2973#ifdef SUPPORT_SD_LOCK
2974MMC_UNLOCK_ENTRY:
2975 retval = sd_update_lock_status(chip);
2976 if (retval != STATUS_SUCCESS) {
2977 TRACE_RET(chip, STATUS_FAIL);
2978 }
2979#endif
2980
2981 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2982 if (retval != STATUS_SUCCESS) {
2983 TRACE_RET(chip, STATUS_FAIL);
2984 }
2985
2986 chip->card_bus_width[chip->card2lun[SD_CARD]] = 1;
2987
2988 if (!sd_card->mmc_dont_switch_bus) {
2989 if (spec_ver == 4) {
2990 (void)mmc_switch_timing_bus(chip, switch_ddr);
2991 }
2992
2993 if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0)) {
2994 TRACE_RET(chip, STATUS_FAIL);
2995 }
2996
2997 if (switch_ddr && CHK_MMC_DDR52(sd_card)) {
2998 retval = sd_set_init_para(chip);
2999 if (retval != STATUS_SUCCESS) {
3000 TRACE_RET(chip, STATUS_FAIL);
3001 }
3002
3003 retval = mmc_ddr_tuning(chip);
3004 if (retval != STATUS_SUCCESS) {
3005 retval = sd_init_power(chip);
3006 if (retval != STATUS_SUCCESS) {
3007 TRACE_RET(chip, STATUS_FAIL);
3008 }
3009 switch_ddr = 0;
3010 goto DDR_TUNING_FAIL;
3011 }
3012
3013 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3014 if (retval == STATUS_SUCCESS) {
3015 retval = sd_read_lba0(chip);
3016 if (retval != STATUS_SUCCESS) {
3017 retval = sd_init_power(chip);
3018 if (retval != STATUS_SUCCESS) {
3019 TRACE_RET(chip, STATUS_FAIL);
3020 }
3021 switch_ddr = 0;
3022 goto DDR_TUNING_FAIL;
3023 }
3024 }
3025 }
3026 }
3027
3028#ifdef SUPPORT_SD_LOCK
3029 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
3030 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02);
3031 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00);
3032 }
3033#endif
3034
3035 temp = rtsx_readl(chip, RTSX_BIPR);
3036 if (temp & SD_WRITE_PROTECT) {
3037 chip->card_wp |= SD_CARD;
3038 }
3039
3040 return STATUS_SUCCESS;
3041}
3042
3043static void sd_init_type(struct rtsx_chip *chip)
3044{
3045 struct sd_info *sd_card = &(chip->sd_card);
3046
3047 memset(sd_card, 0, sizeof(struct sd_info));
3048
3049 sd_card->sd_type = 0;
3050 sd_card->seq_mode = 0;
3051 sd_card->sd_data_buf_ready = 0;
3052 sd_card->capacity = 0;
3053 sd_card->sd_switch_fail = 0;
3054 sd_card->mmc_dont_switch_bus = 0;
3055 sd_card->need_retune = 0;
3056
3057#ifdef SUPPORT_SD_LOCK
3058 sd_card->sd_lock_status = 0;
3059 sd_card->sd_erase_status = 0;
3060#endif
3061
3062 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0;
3063}
3064
3065int reset_sd_card(struct rtsx_chip *chip)
3066{
3067 struct sd_info *sd_card = &(chip->sd_card);
3068 int retval;
3069
3070 sd_init_reg_addr(chip);
3071
3072 sd_init_type(chip);
3073
3074 retval = enable_card_clock(chip, SD_CARD);
3075 if (retval != STATUS_SUCCESS) {
3076 TRACE_RET(chip, STATUS_FAIL);
3077 }
3078
3079 if (chip->ignore_sd && CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
3080 if (chip->asic_code) {
3081 retval = sd_pull_ctl_enable(chip);
3082 if (retval != STATUS_SUCCESS) {
3083 TRACE_RET(chip, STATUS_FAIL);
3084 }
3085 } else {
3086 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
3087 FPGA_SD_PULL_CTL_BIT | 0x20, 0);
3088 if (retval != STATUS_SUCCESS) {
3089 TRACE_RET(chip, STATUS_FAIL);
3090 }
3091 }
3092 retval = card_share_mode(chip, SD_CARD);
3093 if (retval != STATUS_SUCCESS) {
3094 TRACE_RET(chip, STATUS_FAIL);
3095 }
3096
3097 chip->sd_io = 1;
3098 TRACE_RET(chip, STATUS_FAIL);
3099 }
3100
3101 retval = sd_init_power(chip);
3102 if (retval != STATUS_SUCCESS) {
3103 TRACE_RET(chip, STATUS_FAIL);
3104 }
3105
3106 if (chip->sd_ctl & RESET_MMC_FIRST) {
3107 retval = reset_mmc(chip);
3108 if ((retval != STATUS_SUCCESS) && !sd_check_err_code(chip, SD_NO_CARD)) {
3109 retval = reset_sd(chip);
3110 if (retval != STATUS_SUCCESS) {
3111 if (CHECK_PID(chip, 0x5209)) {
3112 retval = sd_change_bank_voltage(chip, SD_IO_3V3);
3113 if (retval != STATUS_SUCCESS) {
3114 TRACE_RET(chip, STATUS_FAIL);
3115 }
3116 }
3117 }
3118 }
3119 } else {
3120 retval = reset_sd(chip);
3121 if (retval != STATUS_SUCCESS) {
3122 if (sd_check_err_code(chip, SD_NO_CARD)) {
3123 TRACE_RET(chip, STATUS_FAIL);
3124 }
3125
3126 if (CHECK_PID(chip, 0x5209)) {
3127 retval = sd_change_bank_voltage(chip, SD_IO_3V3);
3128 if (retval != STATUS_SUCCESS) {
3129 TRACE_RET(chip, STATUS_FAIL);
3130 }
3131 }
3132
3133 if (!chip->sd_io) {
3134 retval = reset_mmc(chip);
3135 }
3136 }
3137 }
3138
3139 if (retval != STATUS_SUCCESS) {
3140 TRACE_RET(chip, STATUS_FAIL);
3141 }
3142
3143 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3144 if (retval != STATUS_SUCCESS) {
3145 TRACE_RET(chip, STATUS_FAIL);
3146 }
3147 RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3148 RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3149
3150 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3151
3152 retval = sd_set_init_para(chip);
3153 if (retval != STATUS_SUCCESS) {
3154 TRACE_RET(chip, STATUS_FAIL);
3155 }
3156
3157 RTSX_DEBUGP("sd_card->sd_type = 0x%x\n", sd_card->sd_type);
3158
3159 return STATUS_SUCCESS;
3160}
3161
3162static int reset_mmc_only(struct rtsx_chip *chip)
3163{
3164 struct sd_info *sd_card = &(chip->sd_card);
3165 int retval;
3166
3167 sd_card->sd_type = 0;
3168 sd_card->seq_mode = 0;
3169 sd_card->sd_data_buf_ready = 0;
3170 sd_card->capacity = 0;
3171 sd_card->sd_switch_fail = 0;
3172
3173#ifdef SUPPORT_SD_LOCK
3174 sd_card->sd_lock_status = 0;
3175 sd_card->sd_erase_status = 0;
3176#endif
3177
3178 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0;
3179
3180 retval = enable_card_clock(chip, SD_CARD);
3181 if (retval != STATUS_SUCCESS) {
3182 TRACE_RET(chip, STATUS_FAIL);
3183 }
3184
3185 retval = sd_init_power(chip);
3186 if (retval != STATUS_SUCCESS) {
3187 TRACE_RET(chip, STATUS_FAIL);
3188 }
3189
3190 retval = reset_mmc(chip);
3191 if (retval != STATUS_SUCCESS) {
3192 TRACE_RET(chip, STATUS_FAIL);
3193 }
3194
3195 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3196 if (retval != STATUS_SUCCESS) {
3197 TRACE_RET(chip, STATUS_FAIL);
3198 }
3199 RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3200 RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3201
3202 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3203
3204 retval = sd_set_init_para(chip);
3205 if (retval != STATUS_SUCCESS) {
3206 TRACE_RET(chip, STATUS_FAIL);
3207 }
3208
3209 RTSX_DEBUGP("In reset_mmc_only, sd_card->sd_type = 0x%x\n", sd_card->sd_type);
3210
3211 return STATUS_SUCCESS;
3212}
3213
3214#define WAIT_DATA_READY_RTY_CNT 255
3215
3216static int wait_data_buf_ready(struct rtsx_chip *chip)
3217{
3218 struct sd_info *sd_card = &(chip->sd_card);
3219 int i, retval;
3220
3221 for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) {
3222 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3223 sd_set_err_code(chip, SD_NO_CARD);
3224 TRACE_RET(chip, STATUS_FAIL);
3225 }
3226
3227 sd_card->sd_data_buf_ready = 0;
3228
3229 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
3230 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3231 if (retval != STATUS_SUCCESS) {
3232 TRACE_RET(chip, STATUS_FAIL);
3233 }
3234
3235 if (sd_card->sd_data_buf_ready) {
3236 return sd_send_cmd_get_rsp(chip, SEND_STATUS,
3237 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3238 }
3239 }
3240
3241 sd_set_err_code(chip, SD_TO_ERR);
3242
3243 TRACE_RET(chip, STATUS_FAIL);
3244}
3245
3246void sd_stop_seq_mode(struct rtsx_chip *chip)
3247{
3248 struct sd_info *sd_card = &(chip->sd_card);
3249 int retval;
3250
3251 if (sd_card->seq_mode) {
3252 retval = sd_switch_clock(chip);
3253 if (retval != STATUS_SUCCESS) {
3254 return;
3255 }
3256
3257 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3258 SD_RSP_TYPE_R1b, NULL, 0);
3259 if (retval != STATUS_SUCCESS) {
3260 sd_set_err_code(chip, SD_STS_ERR);
3261 }
3262 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3263 if (retval != STATUS_SUCCESS) {
3264 sd_set_err_code(chip, SD_STS_ERR);
3265 }
3266 sd_card->seq_mode = 0;
3267
3268 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3269 }
3270}
3271
3272static inline int sd_auto_tune_clock(struct rtsx_chip *chip)
3273{
3274 struct sd_info *sd_card = &(chip->sd_card);
3275 int retval;
3276
3277 if (chip->asic_code) {
3278 if (sd_card->sd_clock > 30) {
3279 sd_card->sd_clock -= 20;
3280 }
3281 } else {
3282 switch (sd_card->sd_clock) {
3283 case CLK_200:
3284 sd_card->sd_clock = CLK_150;
3285 break;
3286
3287 case CLK_150:
3288 sd_card->sd_clock = CLK_120;
3289 break;
3290
3291 case CLK_120:
3292 sd_card->sd_clock = CLK_100;
3293 break;
3294
3295 case CLK_100:
3296 sd_card->sd_clock = CLK_80;
3297 break;
3298
3299 case CLK_80:
3300 sd_card->sd_clock = CLK_60;
3301 break;
3302
3303 case CLK_60:
3304 sd_card->sd_clock = CLK_50;
3305 break;
3306
3307 default:
3308 break;
3309 }
3310 }
3311
3312 retval = sd_switch_clock(chip);
3313 if (retval != STATUS_SUCCESS) {
3314 TRACE_RET(chip, STATUS_FAIL);
3315 }
3316
3317 return STATUS_SUCCESS;
3318}
3319
3320int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt)
3321{
3322 struct sd_info *sd_card = &(chip->sd_card);
3323 u32 data_addr;
3324 u8 cfg2;
3325 int retval;
3326
3327 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3328 RTSX_DEBUGP("sd_rw: Read %d %s from 0x%x\n", sector_cnt,
3329 (sector_cnt > 1) ? "sectors" : "sector", start_sector);
3330 } else {
3331 RTSX_DEBUGP("sd_rw: Write %d %s to 0x%x\n", sector_cnt,
3332 (sector_cnt > 1) ? "sectors" : "sector", start_sector);
3333 }
3334
3335 sd_card->cleanup_counter = 0;
3336
3337 if (!(chip->card_ready & SD_CARD)) {
3338 sd_card->seq_mode = 0;
3339
3340 retval = reset_sd_card(chip);
3341 if (retval == STATUS_SUCCESS) {
3342 chip->card_ready |= SD_CARD;
3343 chip->card_fail &= ~SD_CARD;
3344 } else {
3345 chip->card_ready &= ~SD_CARD;
3346 chip->card_fail |= SD_CARD;
3347 chip->capacity[chip->card2lun[SD_CARD]] = 0;
3348 chip->rw_need_retry = 1;
3349 TRACE_RET(chip, STATUS_FAIL);
3350 }
3351 }
3352
3353 if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card)) {
3354 data_addr = start_sector << 9;
3355 } else {
3356 data_addr = start_sector;
3357 }
3358
3359 sd_clr_err_code(chip);
3360
3361 retval = sd_switch_clock(chip);
3362 if (retval != STATUS_SUCCESS) {
3363 sd_set_err_code(chip, SD_IO_ERR);
3364 TRACE_GOTO(chip, RW_FAIL);
3365 }
3366
3367 if (sd_card->seq_mode && ((sd_card->pre_dir != srb->sc_data_direction)
3368 || ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) != start_sector))) {
3369 if ((sd_card->pre_sec_cnt < 0x80)
3370 && (sd_card->pre_dir == DMA_FROM_DEVICE)
3371 && !CHK_SD30_SPEED(sd_card)
3372 && !CHK_SD_HS(sd_card)
3373 && !CHK_MMC_HS(sd_card)) {
3374 sd_send_cmd_get_rsp(chip, SEND_STATUS,
3375 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3376 }
3377
3378 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
3379 0, SD_RSP_TYPE_R1b, NULL, 0);
3380 if (retval != STATUS_SUCCESS) {
3381 chip->rw_need_retry = 1;
3382 sd_set_err_code(chip, SD_STS_ERR);
3383 TRACE_GOTO(chip, RW_FAIL);
3384 }
3385
3386 sd_card->seq_mode = 0;
3387
3388 retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3389 if (retval != STATUS_SUCCESS) {
3390 sd_set_err_code(chip, SD_IO_ERR);
3391 TRACE_GOTO(chip, RW_FAIL);
3392 }
3393
3394 if ((sd_card->pre_sec_cnt < 0x80)
3395 && !CHK_SD30_SPEED(sd_card)
3396 && !CHK_SD_HS(sd_card)
3397 && !CHK_MMC_HS(sd_card)) {
3398 sd_send_cmd_get_rsp(chip, SEND_STATUS,
3399 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3400 }
3401 }
3402
3403 rtsx_init_cmd(chip);
3404
3405 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
3406 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
3407 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)sector_cnt);
3408 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(sector_cnt >> 8));
3409
3410 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3411
3412 if (CHK_MMC_8BIT(sd_card)) {
3413 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8);
3414 } else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card)) {
3415 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3416 } else {
3417 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_1);
3418 }
3419
3420 if (sd_card->seq_mode) {
3421 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3422 SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3423 if (CHECK_PID(chip, 0x5209)) {
3424 if (!CHK_SD30_SPEED(sd_card)) {
3425 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
3426 }
3427 }
3428 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3429
3430 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512);
3431
3432 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3433 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3434 SD_TM_AUTO_READ_3 | SD_TRANSFER_START);
3435 } else {
3436 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3437 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3438 }
3439
3440 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
3441
3442 rtsx_send_cmd_no_wait(chip);
3443 } else {
3444 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3445 RTSX_DEBUGP("SD/MMC CMD %d\n", READ_MULTIPLE_BLOCK);
3446 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3447 0x40 | READ_MULTIPLE_BLOCK);
3448 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(data_addr >> 24));
3449 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(data_addr >> 16));
3450 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(data_addr >> 8));
3451 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)data_addr);
3452
3453 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3454 SD_CHECK_CRC7 | SD_RSP_LEN_6;
3455 if (CHECK_PID(chip, 0x5209)) {
3456 if (!CHK_SD30_SPEED(sd_card)) {
3457 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
3458 }
3459 }
3460 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3461
3462 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512);
3463
3464 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3465 SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3466 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3467 SD_TRANSFER_END, SD_TRANSFER_END);
3468
3469 rtsx_send_cmd_no_wait(chip);
3470 } else {
3471 retval = rtsx_send_cmd(chip, SD_CARD, 50);
3472 if (retval < 0) {
3473 rtsx_clear_sd_error(chip);
3474
3475 chip->rw_need_retry = 1;
3476 sd_set_err_code(chip, SD_TO_ERR);
3477 TRACE_GOTO(chip, RW_FAIL);
3478 }
3479
3480 retval = wait_data_buf_ready(chip);
3481 if (retval != STATUS_SUCCESS) {
3482 chip->rw_need_retry = 1;
3483 sd_set_err_code(chip, SD_TO_ERR);
3484 TRACE_GOTO(chip, RW_FAIL);
3485 }
3486
3487 retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK,
3488 data_addr, SD_RSP_TYPE_R1, NULL, 0);
3489 if (retval != STATUS_SUCCESS) {
3490 chip->rw_need_retry = 1;
3491 TRACE_GOTO(chip, RW_FAIL);
3492 }
3493
3494 rtsx_init_cmd(chip);
3495
3496 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3497 SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3498 if (CHECK_PID(chip, 0x5209)) {
3499 if (!CHK_SD30_SPEED(sd_card)) {
3500 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
3501 }
3502 }
3503 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3504
3505 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512);
3506
3507 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3508 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3509 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3510 SD_TRANSFER_END, SD_TRANSFER_END);
3511
3512 rtsx_send_cmd_no_wait(chip);
3513 }
3514
3515 sd_card->seq_mode = 1;
3516 }
3517
3518 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb),
3519 scsi_sg_count(srb), srb->sc_data_direction, chip->sd_timeout);
3520 if (retval < 0) {
3521 u8 stat = 0;
3522 int err;
3523
3524 sd_card->seq_mode = 0;
3525
3526 if (retval == -ETIMEDOUT) {
3527 err = STATUS_TIMEDOUT;
3528 } else {
3529 err = STATUS_FAIL;
3530 }
3531
3532 rtsx_read_register(chip, REG_SD_STAT1, &stat);
3533 rtsx_clear_sd_error(chip);
3534 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3535 chip->rw_need_retry = 0;
3536 RTSX_DEBUGP("No card exist, exit sd_rw\n");
3537 TRACE_RET(chip, STATUS_FAIL);
3538 }
3539
3540 chip->rw_need_retry = 1;
3541
3542 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, SD_RSP_TYPE_R1b, NULL, 0);
3543 if (retval != STATUS_SUCCESS) {
3544 sd_set_err_code(chip, SD_STS_ERR);
3545 TRACE_GOTO(chip, RW_FAIL);
3546 }
3547
3548 if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) {
3549 RTSX_DEBUGP("SD CRC error, tune clock!\n");
3550 sd_set_err_code(chip, SD_CRC_ERR);
3551 TRACE_GOTO(chip, RW_FAIL);
3552 }
3553
3554 if (err == STATUS_TIMEDOUT) {
3555 sd_set_err_code(chip, SD_TO_ERR);
3556 TRACE_GOTO(chip, RW_FAIL);
3557 }
3558
3559 TRACE_RET(chip, err);
3560 }
3561
3562 sd_card->pre_sec_addr = start_sector;
3563 sd_card->pre_sec_cnt = sector_cnt;
3564 sd_card->pre_dir = srb->sc_data_direction;
3565
3566 return STATUS_SUCCESS;
3567
3568RW_FAIL:
3569 sd_card->seq_mode = 0;
3570
3571 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3572 chip->rw_need_retry = 0;
3573 RTSX_DEBUGP("No card exist, exit sd_rw\n");
3574 TRACE_RET(chip, STATUS_FAIL);
3575 }
3576
3577 if (sd_check_err_code(chip, SD_CRC_ERR)) {
3578 if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) {
3579 sd_card->mmc_dont_switch_bus = 1;
3580 reset_mmc_only(chip);
3581 sd_card->mmc_dont_switch_bus = 0;
3582 } else {
3583 sd_card->need_retune = 1;
3584 sd_auto_tune_clock(chip);
3585 }
3586 } else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) {
3587 retval = reset_sd_card(chip);
3588 if (retval != STATUS_SUCCESS) {
3589 chip->card_ready &= ~SD_CARD;
3590 chip->card_fail |= SD_CARD;
3591 chip->capacity[chip->card2lun[SD_CARD]] = 0;
3592 }
3593 }
3594
3595 TRACE_RET(chip, STATUS_FAIL);
3596}
3597
3598#ifdef SUPPORT_CPRM
3599int soft_reset_sd_card(struct rtsx_chip *chip)
3600{
3601 return reset_sd(chip);
3602}
3603
3604int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
3605 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, int special_check)
3606{
3607 int retval;
3608 int timeout = 100;
3609 u16 reg_addr;
3610 u8 *ptr;
3611 int stat_idx = 0;
3612 int rty_cnt = 0;
3613
3614 RTSX_DEBUGP("EXT SD/MMC CMD %d\n", cmd_idx);
3615
3616 if (rsp_type == SD_RSP_TYPE_R1b) {
3617 timeout = 3000;
3618 }
3619
3620RTY_SEND_CMD:
3621
3622 rtsx_init_cmd(chip);
3623
3624 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
3625 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
3626 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
3627 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
3628 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
3629
3630 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
3631 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3632 0x01, PINGPONG_BUFFER);
3633 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
3634 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
3635 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
3636
3637 if (rsp_type == SD_RSP_TYPE_R2) {
3638 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) {
3639 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3640 }
3641 stat_idx = 17;
3642 } else if (rsp_type != SD_RSP_TYPE_R0) {
3643 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++) {
3644 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3645 }
3646 stat_idx = 6;
3647 }
3648 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0);
3649
3650 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
3651
3652 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
3653 if (retval < 0) {
3654 if (retval == -ETIMEDOUT) {
3655 rtsx_clear_sd_error(chip);
3656
3657 if (rsp_type & SD_WAIT_BUSY_END) {
3658 retval = sd_check_data0_status(chip);
3659 if (retval != STATUS_SUCCESS) {
3660 TRACE_RET(chip, retval);
3661 }
3662 } else {
3663 sd_set_err_code(chip, SD_TO_ERR);
3664 }
3665 }
3666 TRACE_RET(chip, STATUS_FAIL);
3667 }
3668
3669 if (rsp_type == SD_RSP_TYPE_R0) {
3670 return STATUS_SUCCESS;
3671 }
3672
3673 ptr = rtsx_get_cmd_data(chip) + 1;
3674
3675 if ((ptr[0] & 0xC0) != 0) {
3676 sd_set_err_code(chip, SD_STS_ERR);
3677 TRACE_RET(chip, STATUS_FAIL);
3678 }
3679
3680 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
3681 if (ptr[stat_idx] & SD_CRC7_ERR) {
3682 if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
3683 sd_set_err_code(chip, SD_CRC_ERR);
3684 TRACE_RET(chip, STATUS_FAIL);
3685 }
3686 if (rty_cnt < SD_MAX_RETRY_COUNT) {
3687 wait_timeout(20);
3688 rty_cnt++;
3689 goto RTY_SEND_CMD;
3690 } else {
3691 sd_set_err_code(chip, SD_CRC_ERR);
3692 TRACE_RET(chip, STATUS_FAIL);
3693 }
3694 }
3695 }
3696
3697 if ((cmd_idx == SELECT_CARD) || (cmd_idx == APP_CMD) ||
3698 (cmd_idx == SEND_STATUS) || (cmd_idx == STOP_TRANSMISSION)) {
3699 if ((cmd_idx != STOP_TRANSMISSION) && (special_check == 0)) {
3700 if (ptr[1] & 0x80) {
3701 TRACE_RET(chip, STATUS_FAIL);
3702 }
3703 }
3704#ifdef SUPPORT_SD_LOCK
3705 if (ptr[1] & 0x7D)
3706#else
3707 if (ptr[1] & 0x7F)
3708#endif
3709 {
3710 TRACE_RET(chip, STATUS_FAIL);
3711 }
3712 if (ptr[2] & 0xF8) {
3713 TRACE_RET(chip, STATUS_FAIL);
3714 }
3715
3716 if (cmd_idx == SELECT_CARD) {
3717 if (rsp_type == SD_RSP_TYPE_R2) {
3718 if ((ptr[3] & 0x1E) != 0x04) {
3719 TRACE_RET(chip, STATUS_FAIL);
3720 }
3721 } else if (rsp_type == SD_RSP_TYPE_R2) {
3722 if ((ptr[3] & 0x1E) != 0x03) {
3723 TRACE_RET(chip, STATUS_FAIL);
3724 }
3725 }
3726 }
3727 }
3728
3729 if (rsp && rsp_len) {
3730 memcpy(rsp, ptr, rsp_len);
3731 }
3732
3733 return STATUS_SUCCESS;
3734}
3735
3736int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type)
3737{
3738 int retval, rsp_len;
3739 u16 reg_addr;
3740
3741 if (rsp_type == SD_RSP_TYPE_R0) {
3742 return STATUS_SUCCESS;
3743 }
3744
3745 rtsx_init_cmd(chip);
3746
3747 if (rsp_type == SD_RSP_TYPE_R2) {
3748 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) {
3749 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3750 }
3751 rsp_len = 17;
3752 } else if (rsp_type != SD_RSP_TYPE_R0) {
3753 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++) {
3754 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3755 }
3756 rsp_len = 6;
3757 }
3758 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0);
3759
3760 retval = rtsx_send_cmd(chip, SD_CARD, 100);
3761 if (retval != STATUS_SUCCESS) {
3762 TRACE_RET(chip, STATUS_FAIL);
3763 }
3764
3765 if (rsp) {
3766 int min_len = (rsp_len < len) ? rsp_len : len;
3767
3768 memcpy(rsp, rtsx_get_cmd_data(chip), min_len);
3769
3770 RTSX_DEBUGP("min_len = %d\n", min_len);
3771 RTSX_DEBUGP("Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n",
3772 rsp[0], rsp[1], rsp[2], rsp[3]);
3773 }
3774
3775 return STATUS_SUCCESS;
3776}
3777
3778int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3779{
3780 struct sd_info *sd_card = &(chip->sd_card);
3781 unsigned int lun = SCSI_LUN(srb);
3782 int len;
3783 u8 buf[18] = {
3784 0x00,
3785 0x00,
3786 0x00,
3787 0x0E,
3788 0x00,
3789 0x00,
3790 0x00,
3791 0x00,
3792 0x53,
3793 0x44,
3794 0x20,
3795 0x43,
3796 0x61,
3797 0x72,
3798 0x64,
3799 0x00,
3800 0x00,
3801 0x00,
3802 };
3803
3804 sd_card->pre_cmd_err = 0;
3805
3806 if (!(CHK_BIT(chip->lun_mc, lun))) {
3807 SET_BIT(chip->lun_mc, lun);
3808 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3809 TRACE_RET(chip, TRANSPORT_FAILED);
3810 }
3811
3812 if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) || (0x20 != srb->cmnd[4]) ||
3813 (0x43 != srb->cmnd[5]) || (0x61 != srb->cmnd[6]) ||
3814 (0x72 != srb->cmnd[7]) || (0x64 != srb->cmnd[8])) {
3815 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3816 TRACE_RET(chip, TRANSPORT_FAILED);
3817 }
3818
3819 switch (srb->cmnd[1] & 0x0F) {
3820 case 0:
3821 sd_card->sd_pass_thru_en = 0;
3822 break;
3823
3824 case 1:
3825 sd_card->sd_pass_thru_en = 1;
3826 break;
3827
3828 default:
3829 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3830 TRACE_RET(chip, TRANSPORT_FAILED);
3831 }
3832
3833 buf[5] = (1 == CHK_SD(sd_card)) ? 0x01 : 0x02;
3834 if (chip->card_wp & SD_CARD) {
3835 buf[5] |= 0x80;
3836 }
3837
3838 buf[6] = (u8)(sd_card->sd_addr >> 16);
3839 buf[7] = (u8)(sd_card->sd_addr >> 24);
3840
3841 buf[15] = chip->max_lun;
3842
3843 len = min(18, (int)scsi_bufflen(srb));
3844 rtsx_stor_set_xfer_buf(buf, len, srb);
3845
3846 return TRANSPORT_GOOD;
3847}
3848
3849static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type, int *rsp_len)
3850{
3851 if (!rsp_type || !rsp_len) {
3852 return STATUS_FAIL;
3853 }
3854
3855 switch (srb->cmnd[10]) {
3856 case 0x03:
3857 *rsp_type = SD_RSP_TYPE_R0;
3858 *rsp_len = 0;
3859 break;
3860
3861 case 0x04:
3862 *rsp_type = SD_RSP_TYPE_R1;
3863 *rsp_len = 6;
3864 break;
3865
3866 case 0x05:
3867 *rsp_type = SD_RSP_TYPE_R1b;
3868 *rsp_len = 6;
3869 break;
3870
3871 case 0x06:
3872 *rsp_type = SD_RSP_TYPE_R2;
3873 *rsp_len = 17;
3874 break;
3875
3876 case 0x07:
3877 *rsp_type = SD_RSP_TYPE_R3;
3878 *rsp_len = 6;
3879 break;
3880
3881 default:
3882 return STATUS_FAIL;
3883 }
3884
3885 return STATUS_SUCCESS;
3886}
3887
3888int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3889{
3890 struct sd_info *sd_card = &(chip->sd_card);
3891 unsigned int lun = SCSI_LUN(srb);
3892 int retval, rsp_len;
3893 u8 cmd_idx, rsp_type;
3894 u8 standby = 0, acmd = 0;
3895 u32 arg;
3896
3897 if (!sd_card->sd_pass_thru_en) {
3898 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3899 TRACE_RET(chip, TRANSPORT_FAILED);
3900 }
3901
3902 retval = sd_switch_clock(chip);
3903 if (retval != STATUS_SUCCESS) {
3904 TRACE_RET(chip, TRANSPORT_FAILED);
3905 }
3906
3907 if (sd_card->pre_cmd_err) {
3908 sd_card->pre_cmd_err = 0;
3909 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3910 TRACE_RET(chip, TRANSPORT_FAILED);
3911 }
3912
3913 cmd_idx = srb->cmnd[2] & 0x3F;
3914 if (srb->cmnd[1] & 0x02) {
3915 standby = 1;
3916 }
3917 if (srb->cmnd[1] & 0x01) {
3918 acmd = 1;
3919 }
3920
3921 arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
3922 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
3923
3924 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
3925 if (retval != STATUS_SUCCESS) {
3926 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3927 TRACE_RET(chip, TRANSPORT_FAILED);
3928 }
3929 sd_card->last_rsp_type = rsp_type;
3930
3931 retval = sd_switch_clock(chip);
3932 if (retval != STATUS_SUCCESS) {
3933 TRACE_RET(chip, TRANSPORT_FAILED);
3934 }
3935
3936#ifdef SUPPORT_SD_LOCK
3937 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
3938 if (CHK_MMC_8BIT(sd_card)) {
3939 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8);
3940 if (retval != STATUS_SUCCESS) {
3941 TRACE_RET(chip, TRANSPORT_FAILED);
3942 }
3943 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
3944 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3945 if (retval != STATUS_SUCCESS) {
3946 TRACE_RET(chip, TRANSPORT_FAILED);
3947 }
3948 }
3949 }
3950#else
3951 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3952 if (retval != STATUS_SUCCESS) {
3953 TRACE_RET(chip, TRANSPORT_FAILED);
3954 }
3955#endif
3956
3957 if (standby) {
3958 retval = sd_select_card(chip, 0);
3959 if (retval != STATUS_SUCCESS) {
3960 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3961 }
3962 }
3963
3964 if (acmd) {
3965 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
3966 SD_RSP_TYPE_R1, NULL, 0, 0);
3967 if (retval != STATUS_SUCCESS) {
3968 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3969 }
3970 }
3971
3972 retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
3973 sd_card->rsp, rsp_len, 0);
3974 if (retval != STATUS_SUCCESS) {
3975 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3976 }
3977
3978 if (standby) {
3979 retval = sd_select_card(chip, 1);
3980 if (retval != STATUS_SUCCESS) {
3981 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3982 }
3983 }
3984
3985#ifdef SUPPORT_SD_LOCK
3986 retval = sd_update_lock_status(chip);
3987 if (retval != STATUS_SUCCESS) {
3988 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3989 }
3990#endif
3991
3992 scsi_set_resid(srb, 0);
3993 return TRANSPORT_GOOD;
3994
3995SD_Execute_Cmd_Failed:
3996 sd_card->pre_cmd_err = 1;
3997 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
3998 release_sd_card(chip);
3999 do_reset_sd_card(chip);
4000 if (!(chip->card_ready & SD_CARD)) {
4001 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4002 }
4003
4004 TRACE_RET(chip, TRANSPORT_FAILED);
4005}
4006
4007int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4008{
4009 struct sd_info *sd_card = &(chip->sd_card);
4010 unsigned int lun = SCSI_LUN(srb);
4011 int retval, rsp_len, i;
4012 int cmd13_checkbit = 0, read_err = 0;
4013 u8 cmd_idx, rsp_type, bus_width;
4014 u8 send_cmd12 = 0, standby = 0, acmd = 0;
4015 u32 data_len;
4016
4017 if (!sd_card->sd_pass_thru_en) {
4018 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4019 TRACE_RET(chip, TRANSPORT_FAILED);
4020 }
4021
4022 if (sd_card->pre_cmd_err) {
4023 sd_card->pre_cmd_err = 0;
4024 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4025 TRACE_RET(chip, TRANSPORT_FAILED);
4026 }
4027
4028 retval = sd_switch_clock(chip);
4029 if (retval != STATUS_SUCCESS) {
4030 TRACE_RET(chip, TRANSPORT_FAILED);
4031 }
4032
4033 cmd_idx = srb->cmnd[2] & 0x3F;
4034 if (srb->cmnd[1] & 0x04) {
4035 send_cmd12 = 1;
4036 }
4037 if (srb->cmnd[1] & 0x02) {
4038 standby = 1;
4039 }
4040 if (srb->cmnd[1] & 0x01) {
4041 acmd = 1;
4042 }
4043
4044 data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] << 8) | srb->cmnd[9];
4045
4046 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4047 if (retval != STATUS_SUCCESS) {
4048 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4049 TRACE_RET(chip, TRANSPORT_FAILED);
4050 }
4051 sd_card->last_rsp_type = rsp_type;
4052
4053 retval = sd_switch_clock(chip);
4054 if (retval != STATUS_SUCCESS) {
4055 TRACE_RET(chip, TRANSPORT_FAILED);
4056 }
4057
4058#ifdef SUPPORT_SD_LOCK
4059 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4060 if (CHK_MMC_8BIT(sd_card)) {
4061 bus_width = SD_BUS_WIDTH_8;
4062 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4063 bus_width = SD_BUS_WIDTH_4;
4064 } else {
4065 bus_width = SD_BUS_WIDTH_1;
4066 }
4067 } else {
4068 bus_width = SD_BUS_WIDTH_4;
4069 }
4070 RTSX_DEBUGP("bus_width = %d\n", bus_width);
4071#else
4072 bus_width = SD_BUS_WIDTH_4;
4073#endif
4074
4075 if (data_len < 512) {
4076 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4077 SD_RSP_TYPE_R1, NULL, 0, 0);
4078 if (retval != STATUS_SUCCESS) {
4079 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4080 }
4081 }
4082
4083 if (standby) {
4084 retval = sd_select_card(chip, 0);
4085 if (retval != STATUS_SUCCESS) {
4086 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4087 }
4088 }
4089
4090 if (acmd) {
4091 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
4092 SD_RSP_TYPE_R1, NULL, 0, 0);
4093 if (retval != STATUS_SUCCESS) {
4094 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4095 }
4096 }
4097
4098 if (data_len <= 512) {
4099 int min_len;
4100 u8 *buf;
4101 u16 byte_cnt, blk_cnt;
4102 u8 cmd[5];
4103
4104 byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9];
4105 blk_cnt = 1;
4106
4107 cmd[0] = 0x40 | cmd_idx;
4108 cmd[1] = srb->cmnd[3];
4109 cmd[2] = srb->cmnd[4];
4110 cmd[3] = srb->cmnd[5];
4111 cmd[4] = srb->cmnd[6];
4112
4113 buf = (u8 *)kmalloc(data_len, GFP_KERNEL);
4114 if (buf == NULL) {
4115 TRACE_RET(chip, TRANSPORT_ERROR);
4116 }
4117
4118 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt,
4119 blk_cnt, bus_width, buf, data_len, 2000);
4120 if (retval != STATUS_SUCCESS) {
4121 read_err = 1;
4122 kfree(buf);
4123 rtsx_clear_sd_error(chip);
4124 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4125 }
4126
4127 min_len = min(data_len, scsi_bufflen(srb));
4128 rtsx_stor_set_xfer_buf(buf, min_len, srb);
4129
4130 kfree(buf);
4131 } else if (!(data_len & 0x1FF)) {
4132 rtsx_init_cmd(chip);
4133
4134 trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512);
4135
4136 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
4137 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
4138 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4139 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4140 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4141 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4142
4143 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
4144 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, srb->cmnd[3]);
4145 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, srb->cmnd[4]);
4146 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, srb->cmnd[5]);
4147 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, srb->cmnd[6]);
4148
4149 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
4150 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
4151
4152 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
4153 0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
4154 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
4155
4156 rtsx_send_cmd_no_wait(chip);
4157
4158 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb),
4159 scsi_sg_count(srb), DMA_FROM_DEVICE, 10000);
4160 if (retval < 0) {
4161 read_err = 1;
4162 rtsx_clear_sd_error(chip);
4163 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4164 }
4165
4166 } else {
4167 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4168 }
4169
4170 retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type);
4171 if (retval != STATUS_SUCCESS) {
4172 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4173 }
4174
4175 if (standby) {
4176 retval = sd_select_card(chip, 1);
4177 if (retval != STATUS_SUCCESS) {
4178 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4179 }
4180 }
4181
4182 if (send_cmd12) {
4183 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
4184 0, SD_RSP_TYPE_R1b, NULL, 0, 0);
4185 if (retval != STATUS_SUCCESS) {
4186 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4187 }
4188 }
4189
4190 if (data_len < 512) {
4191 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4192 SD_RSP_TYPE_R1, NULL, 0, 0);
4193 if (retval != STATUS_SUCCESS) {
4194 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4195 }
4196
4197 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4198 if (retval != STATUS_SUCCESS) {
4199 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4200 }
4201 retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4202 if (retval != STATUS_SUCCESS) {
4203 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4204 }
4205 }
4206
4207 if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) {
4208 cmd13_checkbit = 1;
4209 }
4210
4211 for (i = 0; i < 3; i++) {
4212 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
4213 SD_RSP_TYPE_R1, NULL, 0, cmd13_checkbit);
4214 if (retval == STATUS_SUCCESS) {
4215 break;
4216 }
4217 }
4218 if (retval != STATUS_SUCCESS) {
4219 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4220 }
4221
4222 scsi_set_resid(srb, 0);
4223 return TRANSPORT_GOOD;
4224
4225SD_Execute_Read_Cmd_Failed:
4226 sd_card->pre_cmd_err = 1;
4227 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4228 if (read_err) {
4229 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4230 }
4231 release_sd_card(chip);
4232 do_reset_sd_card(chip);
4233 if (!(chip->card_ready & SD_CARD)) {
4234 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4235 }
4236
4237 TRACE_RET(chip, TRANSPORT_FAILED);
4238}
4239
4240int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4241{
4242 struct sd_info *sd_card = &(chip->sd_card);
4243 unsigned int lun = SCSI_LUN(srb);
4244 int retval, rsp_len, i;
4245 int cmd13_checkbit = 0, write_err = 0;
4246 u8 cmd_idx, rsp_type;
4247 u8 send_cmd12 = 0, standby = 0, acmd = 0;
4248 u32 data_len, arg;
4249#ifdef SUPPORT_SD_LOCK
4250 int lock_cmd_fail = 0;
4251 u8 sd_lock_state = 0;
4252 u8 lock_cmd_type = 0;
4253#endif
4254
4255 if (!sd_card->sd_pass_thru_en) {
4256 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4257 TRACE_RET(chip, TRANSPORT_FAILED);
4258 }
4259
4260 if (sd_card->pre_cmd_err) {
4261 sd_card->pre_cmd_err = 0;
4262 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4263 TRACE_RET(chip, TRANSPORT_FAILED);
4264 }
4265
4266 retval = sd_switch_clock(chip);
4267 if (retval != STATUS_SUCCESS) {
4268 TRACE_RET(chip, TRANSPORT_FAILED);
4269 }
4270
4271 cmd_idx = srb->cmnd[2] & 0x3F;
4272 if (srb->cmnd[1] & 0x04) {
4273 send_cmd12 = 1;
4274 }
4275 if (srb->cmnd[1] & 0x02) {
4276 standby = 1;
4277 }
4278 if (srb->cmnd[1] & 0x01) {
4279 acmd = 1;
4280 }
4281
4282 data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] << 8) | srb->cmnd[9];
4283 arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
4284 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
4285
4286#ifdef SUPPORT_SD_LOCK
4287 if (cmd_idx == LOCK_UNLOCK) {
4288 sd_lock_state = sd_card->sd_lock_status;
4289 sd_lock_state &= SD_LOCKED;
4290 }
4291#endif
4292
4293 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4294 if (retval != STATUS_SUCCESS) {
4295 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4296 TRACE_RET(chip, TRANSPORT_FAILED);
4297 }
4298 sd_card->last_rsp_type = rsp_type;
4299
4300 retval = sd_switch_clock(chip);
4301 if (retval != STATUS_SUCCESS) {
4302 TRACE_RET(chip, TRANSPORT_FAILED);
4303 }
4304
4305#ifdef SUPPORT_SD_LOCK
4306 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4307 if (CHK_MMC_8BIT(sd_card)) {
4308 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8);
4309 if (retval != STATUS_SUCCESS) {
4310 TRACE_RET(chip, TRANSPORT_FAILED);
4311 }
4312 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4313 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4314 if (retval != STATUS_SUCCESS) {
4315 TRACE_RET(chip, TRANSPORT_FAILED);
4316 }
4317 }
4318 }
4319#else
4320 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4321 if (retval != STATUS_SUCCESS) {
4322 TRACE_RET(chip, TRANSPORT_FAILED);
4323 }
4324#endif
4325
4326 if (data_len < 512) {
4327 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4328 SD_RSP_TYPE_R1, NULL, 0, 0);
4329 if (retval != STATUS_SUCCESS) {
4330 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4331 }
4332 }
4333
4334 if (standby) {
4335 retval = sd_select_card(chip, 0);
4336 if (retval != STATUS_SUCCESS) {
4337 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4338 }
4339 }
4340
4341 if (acmd) {
4342 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
4343 SD_RSP_TYPE_R1, NULL, 0, 0);
4344 if (retval != STATUS_SUCCESS) {
4345 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4346 }
4347 }
4348
4349 retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
4350 sd_card->rsp, rsp_len, 0);
4351 if (retval != STATUS_SUCCESS) {
4352 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4353 }
4354
4355 if (data_len <= 512) {
4356 u16 i;
4357 u8 *buf;
4358
4359 buf = (u8 *)kmalloc(data_len, GFP_KERNEL);
4360 if (buf == NULL) {
4361 TRACE_RET(chip, TRANSPORT_ERROR);
4362 }
4363
4364 rtsx_stor_get_xfer_buf(buf, data_len, srb);
4365
4366#ifdef SUPPORT_SD_LOCK
4367 if (cmd_idx == LOCK_UNLOCK) {
4368 lock_cmd_type = buf[0] & 0x0F;
4369 }
4370#endif
4371
4372 if (data_len > 256) {
4373 rtsx_init_cmd(chip);
4374 for (i = 0; i < 256; i++) {
4375 rtsx_add_cmd(chip, WRITE_REG_CMD,
4376 PPBUF_BASE2 + i, 0xFF, buf[i]);
4377 }
4378 retval = rtsx_send_cmd(chip, 0, 250);
4379 if (retval != STATUS_SUCCESS) {
4380 kfree(buf);
4381 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4382 }
4383
4384 rtsx_init_cmd(chip);
4385 for (i = 256; i < data_len; i++) {
4386 rtsx_add_cmd(chip, WRITE_REG_CMD,
4387 PPBUF_BASE2 + i, 0xFF, buf[i]);
4388 }
4389 retval = rtsx_send_cmd(chip, 0, 250);
4390 if (retval != STATUS_SUCCESS) {
4391 kfree(buf);
4392 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4393 }
4394 } else {
4395 rtsx_init_cmd(chip);
4396 for (i = 0; i < data_len; i++) {
4397 rtsx_add_cmd(chip, WRITE_REG_CMD,
4398 PPBUF_BASE2 + i, 0xFF, buf[i]);
4399 }
4400 retval = rtsx_send_cmd(chip, 0, 250);
4401 if (retval != STATUS_SUCCESS) {
4402 kfree(buf);
4403 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4404 }
4405 }
4406
4407 kfree(buf);
4408
4409 rtsx_init_cmd(chip);
4410
4411 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, srb->cmnd[8] & 0x03);
4412 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, srb->cmnd[9]);
4413 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0x00);
4414 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 0x01);
4415 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
4416
4417 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4418 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4419 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
4420
4421 retval = rtsx_send_cmd(chip, SD_CARD, 250);
4422 } else if (!(data_len & 0x1FF)) {
4423 rtsx_init_cmd(chip);
4424
4425 trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512);
4426
4427 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
4428 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
4429 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4430 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4431 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4432 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4433
4434 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4435 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
4436
4437 rtsx_send_cmd_no_wait(chip);
4438
4439 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb),
4440 scsi_sg_count(srb), DMA_TO_DEVICE, 10000);
4441
4442 } else {
4443 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4444 }
4445
4446 if (retval < 0) {
4447 write_err = 1;
4448 rtsx_clear_sd_error(chip);
4449 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4450 }
4451
4452#ifdef SUPPORT_SD_LOCK
4453 if (cmd_idx == LOCK_UNLOCK) {
4454 if (lock_cmd_type == SD_ERASE) {
4455 sd_card->sd_erase_status = SD_UNDER_ERASING;
4456 scsi_set_resid(srb, 0);
4457 return TRANSPORT_GOOD;
4458 }
4459
4460 rtsx_init_cmd(chip);
4461 if (CHECK_PID(chip, 0x5209)) {
4462 rtsx_add_cmd(chip, CHECK_REG_CMD, SD_BUS_STAT, SD_DAT0_STATUS, SD_DAT0_STATUS);
4463 } else {
4464 rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02);
4465 }
4466 rtsx_send_cmd(chip, SD_CARD, 250);
4467
4468 retval = sd_update_lock_status(chip);
4469 if (retval != STATUS_SUCCESS) {
4470 RTSX_DEBUGP("Lock command fail!\n");
4471 lock_cmd_fail = 1;
4472 }
4473 }
4474#endif /* SUPPORT_SD_LOCK */
4475
4476 if (standby) {
4477 retval = sd_select_card(chip, 1);
4478 if (retval != STATUS_SUCCESS) {
4479 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4480 }
4481 }
4482
4483 if (send_cmd12) {
4484 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
4485 0, SD_RSP_TYPE_R1b, NULL, 0, 0);
4486 if (retval != STATUS_SUCCESS) {
4487 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4488 }
4489 }
4490
4491 if (data_len < 512) {
4492 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4493 SD_RSP_TYPE_R1, NULL, 0, 0);
4494 if (retval != STATUS_SUCCESS) {
4495 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4496 }
4497
4498 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4499 if (retval != STATUS_SUCCESS) {
4500 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4501 }
4502 rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4503 if (retval != STATUS_SUCCESS) {
4504 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4505 }
4506 }
4507
4508 if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) {
4509 cmd13_checkbit = 1;
4510 }
4511
4512 for (i = 0; i < 3; i++) {
4513 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
4514 SD_RSP_TYPE_R1, NULL, 0, cmd13_checkbit);
4515 if (retval == STATUS_SUCCESS) {
4516 break;
4517 }
4518 }
4519 if (retval != STATUS_SUCCESS) {
4520 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4521 }
4522
4523#ifdef SUPPORT_SD_LOCK
4524 if (cmd_idx == LOCK_UNLOCK) {
4525 if (!lock_cmd_fail) {
4526 RTSX_DEBUGP("lock_cmd_type = 0x%x\n", lock_cmd_type);
4527 if (lock_cmd_type & SD_CLR_PWD) {
4528 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
4529 }
4530 if (lock_cmd_type & SD_SET_PWD) {
4531 sd_card->sd_lock_status |= SD_PWD_EXIST;
4532 }
4533 }
4534
4535 RTSX_DEBUGP("sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n",
4536 sd_lock_state, sd_card->sd_lock_status);
4537 if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) {
4538 sd_card->sd_lock_notify = 1;
4539 if (sd_lock_state) {
4540 if (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) {
4541 sd_card->sd_lock_status |= (SD_UNLOCK_POW_ON | SD_SDR_RST);
4542 if (CHK_SD(sd_card)) {
4543 retval = reset_sd(chip);
4544 if (retval != STATUS_SUCCESS) {
4545 sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4546 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4547 }
4548 }
4549
4550 sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4551 }
4552 }
4553 }
4554 }
4555
4556 if (lock_cmd_fail) {
4557 scsi_set_resid(srb, 0);
4558 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4559 TRACE_RET(chip, TRANSPORT_FAILED);
4560 }
4561#endif /* SUPPORT_SD_LOCK */
4562
4563 scsi_set_resid(srb, 0);
4564 return TRANSPORT_GOOD;
4565
4566SD_Execute_Write_Cmd_Failed:
4567 sd_card->pre_cmd_err = 1;
4568 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4569 if (write_err) {
4570 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
4571 }
4572 release_sd_card(chip);
4573 do_reset_sd_card(chip);
4574 if (!(chip->card_ready & SD_CARD)) {
4575 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4576 }
4577
4578 TRACE_RET(chip, TRANSPORT_FAILED);
4579}
4580
4581int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4582{
4583 struct sd_info *sd_card = &(chip->sd_card);
4584 unsigned int lun = SCSI_LUN(srb);
4585 int count;
4586 u16 data_len;
4587
4588 if (!sd_card->sd_pass_thru_en) {
4589 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4590 TRACE_RET(chip, TRANSPORT_FAILED);
4591 }
4592
4593 if (sd_card->pre_cmd_err) {
4594 sd_card->pre_cmd_err = 0;
4595 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4596 TRACE_RET(chip, TRANSPORT_FAILED);
4597 }
4598
4599 data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8];
4600
4601 if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) {
4602 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4603 TRACE_RET(chip, TRANSPORT_FAILED);
4604 } else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) {
4605 count = (data_len < 17) ? data_len : 17;
4606 } else {
4607 count = (data_len < 6) ? data_len : 6;
4608 }
4609 rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb);
4610
4611 RTSX_DEBUGP("Response length: %d\n", data_len);
4612 RTSX_DEBUGP("Response: 0x%x 0x%x 0x%x 0x%x\n",
4613 sd_card->rsp[0], sd_card->rsp[1], sd_card->rsp[2], sd_card->rsp[3]);
4614
4615 scsi_set_resid(srb, 0);
4616 return TRANSPORT_GOOD;
4617}
4618
4619int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4620{
4621 struct sd_info *sd_card = &(chip->sd_card);
4622 unsigned int lun = SCSI_LUN(srb);
4623 int retval;
4624
4625 if (!sd_card->sd_pass_thru_en) {
4626 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4627 TRACE_RET(chip, TRANSPORT_FAILED);
4628 }
4629
4630 if (sd_card->pre_cmd_err) {
4631 sd_card->pre_cmd_err = 0;
4632 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4633 TRACE_RET(chip, TRANSPORT_FAILED);
4634 }
4635
4636 if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) || (0x20 != srb->cmnd[4]) ||
4637 (0x43 != srb->cmnd[5]) || (0x61 != srb->cmnd[6]) ||
4638 (0x72 != srb->cmnd[7]) || (0x64 != srb->cmnd[8])) {
4639 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4640 TRACE_RET(chip, TRANSPORT_FAILED);
4641 }
4642
4643 switch (srb->cmnd[1] & 0x0F) {
4644 case 0:
4645#ifdef SUPPORT_SD_LOCK
4646 if (0x64 == srb->cmnd[9]) {
4647 sd_card->sd_lock_status |= SD_SDR_RST;
4648 }
4649#endif
4650 retval = reset_sd_card(chip);
4651 if (retval != STATUS_SUCCESS) {
4652#ifdef SUPPORT_SD_LOCK
4653 sd_card->sd_lock_status &= ~SD_SDR_RST;
4654#endif
4655 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4656 sd_card->pre_cmd_err = 1;
4657 TRACE_RET(chip, TRANSPORT_FAILED);
4658 }
4659#ifdef SUPPORT_SD_LOCK
4660 sd_card->sd_lock_status &= ~SD_SDR_RST;
4661#endif
4662 break;
4663
4664 case 1:
4665 retval = soft_reset_sd_card(chip);
4666 if (retval != STATUS_SUCCESS) {
4667 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4668 sd_card->pre_cmd_err = 1;
4669 TRACE_RET(chip, TRANSPORT_FAILED);
4670 }
4671 break;
4672
4673 default:
4674 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4675 TRACE_RET(chip, TRANSPORT_FAILED);
4676 }
4677
4678 scsi_set_resid(srb, 0);
4679 return TRANSPORT_GOOD;
4680}
4681#endif
4682
4683void sd_cleanup_work(struct rtsx_chip *chip)
4684{
4685 struct sd_info *sd_card = &(chip->sd_card);
4686
4687 if (sd_card->seq_mode) {
4688 RTSX_DEBUGP("SD: stop transmission\n");
4689 sd_stop_seq_mode(chip);
4690 sd_card->cleanup_counter = 0;
4691 }
4692}
4693
4694int sd_power_off_card3v3(struct rtsx_chip *chip)
4695{
4696 int retval;
4697
4698 retval = disable_card_clock(chip, SD_CARD);
4699 if (retval != STATUS_SUCCESS) {
4700 TRACE_RET(chip, STATUS_FAIL);
4701 }
4702
4703 RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, 0);
4704
4705 if (!chip->ft2_fast_mode) {
4706 retval = card_power_off(chip, SD_CARD);
4707 if (retval != STATUS_SUCCESS) {
4708 TRACE_RET(chip, STATUS_FAIL);
4709 }
4710
4711 wait_timeout(50);
4712 }
4713
4714 if (chip->asic_code) {
4715 retval = sd_pull_ctl_disable(chip);
4716 if (retval != STATUS_SUCCESS) {
4717 TRACE_RET(chip, STATUS_FAIL);
4718 }
4719 } else {
4720 RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
4721 FPGA_SD_PULL_CTL_BIT | 0x20, FPGA_SD_PULL_CTL_BIT);
4722 }
4723
4724 return STATUS_SUCCESS;
4725}
4726
4727int release_sd_card(struct rtsx_chip *chip)
4728{
4729 struct sd_info *sd_card = &(chip->sd_card);
4730 int retval;
4731
4732 RTSX_DEBUGP("release_sd_card\n");
4733
4734 chip->card_ready &= ~SD_CARD;
4735 chip->card_fail &= ~SD_CARD;
4736 chip->card_wp &= ~SD_CARD;
4737
4738 chip->sd_io = 0;
4739 chip->sd_int = 0;
4740
4741#ifdef SUPPORT_SD_LOCK
4742 sd_card->sd_lock_status = 0;
4743 sd_card->sd_erase_status = 0;
4744#endif
4745
4746 memset(sd_card->raw_csd, 0, 16);
4747 memset(sd_card->raw_scr, 0, 8);
4748
4749 retval = sd_power_off_card3v3(chip);
4750 if (retval != STATUS_SUCCESS) {
4751 TRACE_RET(chip, STATUS_FAIL);
4752 }
4753
4754 if (CHECK_PID(chip, 0x5209)) {
4755 retval = sd_change_bank_voltage(chip, SD_IO_3V3);
4756 if (retval != STATUS_SUCCESS) {
4757 TRACE_RET(chip, STATUS_FAIL);
4758 }
4759
4760 if (CHK_SD30_SPEED(sd_card)) {
4761 RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_3v3);
4762 }
4763
4764 RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK, chip->sd_400mA_ocp_thd);
4765 }
4766
4767 return STATUS_SUCCESS;
4768}
Linux 6.x block layer and io_uring tree(s)