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1dac4186 | 1 | /* Driver for Realtek RTS51xx USB card reader |
2 | * Header file | |
3 | * | |
4 | * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2, or (at your option) any | |
9 | * later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along | |
17 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | * | |
19 | * Author: | |
20 | * wwang (wei_wang@realsil.com.cn) | |
21 | * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China | |
22 | * Maintainer: | |
23 | * Edwin Rong (edwin_rong@realsil.com.cn) | |
24 | * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China | |
25 | */ | |
26 | ||
27 | #ifndef __RTS51X_CARD_H | |
28 | #define __RTS51X_CARD_H | |
29 | ||
30 | #include "rts51x_chip.h" | |
31 | ||
32 | /* Register bit definition */ | |
33 | ||
34 | /* Card Power Control Register */ | |
35 | #define POWER_OFF 0x03 | |
36 | #define PARTIAL_POWER_ON 0x02 | |
37 | #define POWER_ON 0x00 | |
38 | #define POWER_MASK 0x03 | |
39 | #define LDO3318_PWR_MASK 0x0C | |
40 | #define LDO_ON 0x00 | |
41 | #define LDO_SUSPEND 0x08 | |
42 | #define LDO_OFF 0x0C | |
43 | #define DV3318_AUTO_PWR_OFF 0x10 | |
44 | #define FORCE_LDO_POWERB 0x60 | |
45 | ||
46 | /* Card Output Enable Register */ | |
47 | #define XD_OUTPUT_EN 0x02 | |
48 | #define SD_OUTPUT_EN 0x04 | |
49 | #define MS_OUTPUT_EN 0x08 | |
50 | ||
51 | /* System Clock Control Register */ | |
52 | ||
53 | /* System Clock Divider Register */ | |
54 | #define CLK_CHANGE 0x80 | |
55 | #define CLK_DIV_1 0x00 | |
56 | #define CLK_DIV_2 0x01 | |
57 | #define CLK_DIV_4 0x02 | |
58 | #define CLK_DIV_8 0x03 | |
59 | ||
60 | /* System Clock Select Register */ | |
61 | #define SSC_60 0 | |
62 | #define SSC_80 1 | |
63 | #define SSC_100 2 | |
64 | #define SSC_120 3 | |
65 | #define SSC_150 4 | |
66 | ||
67 | /* Card Clock Enable Register */ | |
68 | #define XD_CLK_EN 0x02 | |
69 | #define SD_CLK_EN 0x04 | |
70 | #define MS_CLK_EN 0x08 | |
71 | ||
72 | /* Card Select Register */ | |
73 | #define XD_MOD_SEL 1 | |
74 | #define SD_MOD_SEL 2 | |
75 | #define MS_MOD_SEL 3 | |
76 | ||
77 | /* Card Transfer Reset Register */ | |
78 | #define XD_STOP 0x02 | |
79 | #define SD_STOP 0x04 | |
80 | #define MS_STOP 0x08 | |
81 | #define XD_CLR_ERR 0x20 | |
82 | #define SD_CLR_ERR 0x40 | |
83 | #define MS_CLR_ERR 0x80 | |
84 | ||
85 | /* SD30_drive_sel */ | |
86 | #define SD30_DRIVE_MASK 0x07 | |
87 | ||
88 | /* CARD_DRIVE_SEL */ | |
89 | #define SD20_DRIVE_MASK 0x03 | |
90 | #define DRIVE_4mA 0x00 | |
91 | #define DRIVE_8mA 0x01 | |
92 | #define DRIVE_12mA 0x02 | |
93 | ||
94 | /* FPGA_PULL_CTL */ | |
95 | #define FPGA_MS_PULL_CTL_EN 0xEF | |
96 | #define FPGA_SD_PULL_CTL_EN 0xF7 | |
97 | #define FPGA_XD_PULL_CTL_EN1 0xFE | |
98 | #define FPGA_XD_PULL_CTL_EN2 0xFD | |
99 | #define FPGA_XD_PULL_CTL_EN3 0xFB | |
100 | ||
101 | #define FPGA_MS_PULL_CTL_BIT 0x10 | |
102 | #define FPGA_SD_PULL_CTL_BIT 0x08 | |
103 | ||
104 | /* Card Data Source Register */ | |
105 | #define PINGPONG_BUFFER 0x01 | |
106 | #define RING_BUFFER 0x00 | |
107 | ||
108 | /* SFSM_ED */ | |
109 | #define HW_CMD_STOP 0x80 | |
110 | #define CLR_STAGE_STALL 0x08 | |
111 | #define CARD_ERR 0x10 | |
112 | ||
113 | /* CARD_SHARE_MODE */ | |
114 | #define CARD_SHARE_LQFP48 0x04 | |
115 | #define CARD_SHARE_QFN24 0x00 | |
116 | #define CARD_SHARE_LQFP_SEL 0x04 | |
117 | #define CARD_SHARE_XD 0x00 | |
118 | #define CARD_SHARE_SD 0x01 | |
119 | #define CARD_SHARE_MS 0x02 | |
120 | #define CARD_SHARE_MASK 0x03 | |
121 | ||
122 | /* CARD_AUTO_BLINK */ | |
123 | #define BLINK_ENABLE 0x08 | |
124 | #define BLINK_SPEED_MASK 0x07 | |
125 | ||
126 | /* CARD_GPIO */ | |
127 | #define GPIO_OE 0x02 | |
128 | #define GPIO_OUTPUT 0x01 | |
129 | ||
130 | /* CARD_CLK_SOURCE */ | |
131 | #define CRC_FIX_CLK (0x00 << 0) | |
132 | #define CRC_VAR_CLK0 (0x01 << 0) | |
133 | #define CRC_VAR_CLK1 (0x02 << 0) | |
134 | #define SD30_FIX_CLK (0x00 << 2) | |
135 | #define SD30_VAR_CLK0 (0x01 << 2) | |
136 | #define SD30_VAR_CLK1 (0x02 << 2) | |
137 | #define SAMPLE_FIX_CLK (0x00 << 4) | |
138 | #define SAMPLE_VAR_CLK0 (0x01 << 4) | |
139 | #define SAMPLE_VAR_CLK1 (0x02 << 4) | |
140 | ||
141 | /* DCM_DRP_CTL */ | |
142 | #define DCM_RESET 0x08 | |
143 | #define DCM_LOCKED 0x04 | |
144 | #define DCM_208M 0x00 | |
145 | #define DCM_TX 0x01 | |
146 | #define DCM_RX 0x02 | |
147 | ||
148 | /* DCM_DRP_TRIG */ | |
149 | #define DRP_START 0x80 | |
150 | #define DRP_DONE 0x40 | |
151 | ||
152 | /* DCM_DRP_CFG */ | |
153 | #define DRP_WRITE 0x80 | |
154 | #define DRP_READ 0x00 | |
155 | #define DCM_WRITE_ADDRESS_50 0x50 | |
156 | #define DCM_WRITE_ADDRESS_51 0x51 | |
157 | #define DCM_READ_ADDRESS_00 0x00 | |
158 | #define DCM_READ_ADDRESS_51 0x51 | |
159 | ||
160 | /* HW_VERSION */ | |
161 | #define FPGA_VER 0x80 | |
162 | #define HW_VER_MASK 0x0F | |
163 | ||
164 | /* CD_DEGLITCH_EN */ | |
165 | #define DISABLE_SD_CD 0x08 | |
166 | #define DISABLE_MS_CD 0x10 | |
167 | #define DISABLE_XD_CD 0x20 | |
168 | #define SD_CD_DEGLITCH_EN 0x01 | |
169 | #define MS_CD_DEGLITCH_EN 0x02 | |
170 | #define XD_CD_DEGLITCH_EN 0x04 | |
171 | ||
172 | /* OCPCTL */ | |
173 | #define CARD_OC_DETECT_EN 0x08 | |
174 | #define CARD_OC_CLR 0x01 | |
175 | ||
176 | /* CARD_DMA1_CTL */ | |
177 | #define EXTEND_DMA1_ASYNC_SIGNAL 0x02 | |
178 | ||
179 | /* HS_USB_STAT */ | |
180 | #define USB_HI_SPEED 0x01 | |
181 | ||
182 | /* CFG_MODE_1 */ | |
183 | #define RTS5179 0x02 | |
184 | ||
185 | /* SYS_DUMMY0 */ | |
186 | #define NYET_EN 0x01 | |
187 | #define NYET_MSAK 0x01 | |
188 | ||
189 | /* SSC_CTL1 */ | |
190 | #define SSC_RSTB 0x80 | |
191 | #define SSC_8X_EN 0x40 | |
192 | #define SSC_FIX_FRAC 0x20 | |
193 | #define SSC_SEL_1M 0x00 | |
194 | #define SSC_SEL_2M 0x08 | |
195 | #define SSC_SEL_4M 0x10 | |
196 | #define SSC_SEL_8M 0x18 | |
197 | ||
198 | /* SSC_CTL2 */ | |
199 | #define SSC_DEPTH_MASK 0x03 | |
200 | #define SSC_DEPTH_DISALBE 0x00 | |
201 | #define SSC_DEPTH_2M 0x01 | |
202 | #define SSC_DEPTH_1M 0x02 | |
203 | #define SSC_DEPTH_512K 0x03 | |
204 | ||
205 | /* LDO_POWER_CFG */ | |
206 | #define TUNE_SD18_MASK 0x1C | |
1dac4186 | 207 | #define TUNE_SD18_1V8 (0x01 << 2) |
1dac4186 | 208 | #define TUNE_SD18_3V3 (0x07 << 2) |
209 | ||
210 | /* XD_CP_WAITTIME */ | |
211 | #define WAIT_1F 0x00 | |
212 | #define WAIT_3F 0x01 | |
213 | #define WAIT_7F 0x02 | |
214 | #define WAIT_FF 0x03 | |
215 | ||
216 | /* XD_INIT */ | |
217 | #define XD_PWR_OFF_DELAY0 0x00 | |
218 | #define XD_PWR_OFF_DELAY1 0x02 | |
219 | #define XD_PWR_OFF_DELAY2 0x04 | |
220 | #define XD_PWR_OFF_DELAY3 0x06 | |
221 | #define XD_AUTO_PWR_OFF_EN 0xF7 | |
222 | #define XD_NO_AUTO_PWR_OFF 0x08 | |
223 | ||
224 | /* XD_DTCTL */ | |
225 | /* XD_CATCTL */ | |
226 | #define XD_TIME_RWN_1 0x00 | |
227 | #define XD_TIME_RWN_STEP 0x20 | |
228 | #define XD_TIME_RW_1 0x00 | |
229 | #define XD_TIME_RW_STEP 0x04 | |
230 | #define XD_TIME_SETUP_1 0x00 | |
231 | #define XD_TIME_SETUP_STEP 0x01 | |
232 | ||
233 | /* XD_CTL */ | |
234 | #define XD_ECC2_UNCORRECTABLE 0x80 | |
235 | #define XD_ECC2_ERROR 0x40 | |
236 | #define XD_ECC1_UNCORRECTABLE 0x20 | |
237 | #define XD_ECC1_ERROR 0x10 | |
238 | #define XD_RDY 0x04 | |
239 | #define XD_CE_EN 0xFD | |
240 | #define XD_CE_DISEN 0x02 | |
241 | #define XD_WP_EN 0xFE | |
242 | #define XD_WP_DISEN 0x01 | |
243 | ||
244 | /* XD_TRANSFER */ | |
245 | #define XD_TRANSFER_START 0x80 | |
246 | #define XD_TRANSFER_END 0x40 | |
247 | #define XD_PPB_EMPTY 0x20 | |
248 | #define XD_ERR 0x10 | |
249 | #define XD_RESET 0x00 | |
250 | #define XD_ERASE 0x01 | |
251 | #define XD_READ_STATUS 0x02 | |
252 | #define XD_READ_ID 0x03 | |
253 | #define XD_READ_REDUNDANT 0x04 | |
254 | #define XD_READ_PAGES 0x05 | |
255 | #define XD_SET_CMD 0x06 | |
256 | #define XD_NORMAL_READ 0x07 | |
257 | #define XD_WRITE_PAGES 0x08 | |
258 | #define XD_NORMAL_WRITE 0x09 | |
259 | #define XD_WRITE_REDUNDANT 0x0A | |
260 | #define XD_SET_ADDR 0x0B | |
261 | #define XD_COPY_PAGES 0x0C | |
262 | ||
263 | /* XD_CFG */ | |
264 | #define XD_PPB_TO_SIE 0x80 | |
265 | #define XD_TO_PPB_ONLY 0x00 | |
266 | #define XD_BA_TRANSFORM 0x40 | |
267 | #define XD_BA_NO_TRANSFORM 0x00 | |
268 | #define XD_NO_CALC_ECC 0x20 | |
269 | #define XD_CALC_ECC 0x00 | |
270 | #define XD_IGNORE_ECC 0x10 | |
271 | #define XD_CHECK_ECC 0x00 | |
272 | #define XD_DIRECT_TO_RB 0x08 | |
273 | #define XD_ADDR_MASK 0x07 | |
274 | #define XD_ADDR_LENGTH_0 0x00 | |
275 | #define XD_ADDR_LENGTH_1 0x01 | |
276 | #define XD_ADDR_LENGTH_2 0x02 | |
277 | #define XD_ADDR_LENGTH_3 0x03 | |
278 | #define XD_ADDR_LENGTH_4 0x04 | |
279 | ||
280 | /* XD_PAGE_STATUS */ | |
281 | #define XD_GPG 0xFF | |
282 | #define XD_BPG 0x00 | |
283 | ||
284 | /* XD_BLOCK_STATUS */ | |
285 | #define XD_GBLK 0xFF | |
286 | #define XD_LATER_BBLK 0xF0 | |
287 | ||
288 | /* XD_PARITY */ | |
289 | #define XD_ECC2_ALL1 0x80 | |
290 | #define XD_ECC1_ALL1 0x40 | |
291 | #define XD_BA2_ALL0 0x20 | |
292 | #define XD_BA1_ALL0 0x10 | |
293 | #define XD_BA1_BA2_EQL 0x04 | |
294 | #define XD_BA2_VALID 0x02 | |
295 | #define XD_BA1_VALID 0x01 | |
296 | ||
297 | /* XD_CHK_DATA_STATUS */ | |
298 | #define XD_PGSTS_ZEROBIT_OVER4 0x00 | |
299 | #define XD_PGSTS_NOT_FF 0x02 | |
300 | #define XD_AUTO_CHK_DATA_STATUS 0x01 | |
301 | ||
302 | /* SD_CFG1 */ | |
303 | #define SD_CLK_DIVIDE_0 0x00 | |
304 | #define SD_CLK_DIVIDE_256 0xC0 | |
305 | #define SD_CLK_DIVIDE_128 0x80 | |
306 | #define SD_CLK_DIVIDE_MASK 0xC0 | |
307 | #define SD_BUS_WIDTH_1 0x00 | |
308 | #define SD_BUS_WIDTH_4 0x01 | |
309 | #define SD_BUS_WIDTH_8 0x02 | |
310 | #define SD_ASYNC_FIFO_RST 0x10 | |
311 | #define SD_20_MODE 0x00 | |
312 | #define SD_DDR_MODE 0x04 | |
313 | #define SD_30_MODE 0x08 | |
314 | ||
315 | /* SD_CFG2 */ | |
316 | #define SD_CALCULATE_CRC7 0x00 | |
317 | #define SD_NO_CALCULATE_CRC7 0x80 | |
318 | #define SD_CHECK_CRC16 0x00 | |
319 | #define SD_NO_CHECK_CRC16 0x40 | |
320 | #define SD_WAIT_CRC_TO_EN 0x20 | |
321 | #define SD_WAIT_BUSY_END 0x08 | |
322 | #define SD_NO_WAIT_BUSY_END 0x00 | |
323 | #define SD_CHECK_CRC7 0x00 | |
324 | #define SD_NO_CHECK_CRC7 0x04 | |
325 | #define SD_RSP_LEN_0 0x00 | |
326 | #define SD_RSP_LEN_6 0x01 | |
327 | #define SD_RSP_LEN_17 0x02 | |
328 | /* SD/MMC Response Type Definition */ | |
329 | /* SD_CALCULATE_CRC7, SD_CHECK_CRC16, | |
330 | * SD_NO_WAIT_BUSY_END, SD_NO_CHECK_CRC7, | |
331 | * SD_RSP_LEN_0 */ | |
332 | #define SD_RSP_TYPE_R0 0x04 | |
333 | /* SD_CALCULATE_CRC7, SD_CHECK_CRC16, | |
334 | * SD_NO_WAIT_BUSY_END, SD_CHECK_CRC7, | |
335 | * SD_RSP_LEN_6 */ | |
336 | #define SD_RSP_TYPE_R1 0x01 | |
337 | /* SD_CALCULATE_CRC7, SD_CHECK_CRC16, | |
338 | * SD_WAIT_BUSY_END, SD_CHECK_CRC7, | |
339 | * SD_RSP_LEN_6 */ | |
340 | #define SD_RSP_TYPE_R1b 0x09 | |
341 | /* SD_CALCULATE_CRC7, SD_CHECK_CRC16, | |
342 | * SD_NO_WAIT_BUSY_END, SD_CHECK_CRC7, | |
343 | * SD_RSP_LEN_17 */ | |
344 | #define SD_RSP_TYPE_R2 0x02 | |
345 | /* SD_CALCULATE_CRC7, SD_CHECK_CRC16, | |
346 | * SD_NO_WAIT_BUSY_END, SD_NO_CHECK_CRC7, | |
347 | * SD_RSP_LEN_6 */ | |
348 | #define SD_RSP_TYPE_R3 0x05 | |
349 | /* SD_CALCULATE_CRC7, SD_CHECK_CRC16, | |
350 | * SD_NO_WAIT_BUSY_END, SD_NO_CHECK_CRC7, | |
351 | * SD_RSP_LEN_6 */ | |
352 | #define SD_RSP_TYPE_R4 0x05 | |
353 | /* SD_CALCULATE_CRC7, SD_CHECK_CRC16, | |
354 | * SD_NO_WAIT_BUSY_END, SD_CHECK_CRC7, | |
355 | * SD_RSP_LEN_6 */ | |
356 | #define SD_RSP_TYPE_R5 0x01 | |
357 | /* SD_CALCULATE_CRC7, SD_CHECK_CRC16, | |
358 | * SD_NO_WAIT_BUSY_END, SD_CHECK_CRC7, | |
359 | * SD_RSP_LEN_6 */ | |
360 | #define SD_RSP_TYPE_R6 0x01 | |
361 | /* SD_CALCULATE_CRC7, SD_CHECK_CRC16, | |
362 | * SD_NO_WAIT_BUSY_END, SD_CHECK_CRC7, | |
363 | * SD_RSP_LEN_6 */ | |
364 | #define SD_RSP_TYPE_R7 0x01 | |
365 | ||
366 | /* SD_CFG3 */ | |
367 | #define SD_RSP_80CLK_TIMEOUT_EN 0x01 | |
368 | ||
369 | /* SD_STAT1 */ | |
370 | #define SD_CRC7_ERR 0x80 | |
371 | #define SD_CRC16_ERR 0x40 | |
372 | #define SD_CRC_WRITE_ERR 0x20 | |
373 | #define SD_CRC_WRITE_ERR_MASK 0x1C | |
374 | #define GET_CRC_TIME_OUT 0x02 | |
375 | #define SD_TUNING_COMPARE_ERR 0x01 | |
376 | ||
377 | /* SD_STAT2 */ | |
378 | #define SD_RSP_80CLK_TIMEOUT 0x01 | |
379 | ||
380 | /* SD_BUS_STAT */ | |
381 | #define SD_CLK_TOGGLE_EN 0x80 | |
382 | #define SD_CLK_FORCE_STOP 0x40 | |
383 | #define SD_DAT3_STATUS 0x10 | |
384 | #define SD_DAT2_STATUS 0x08 | |
385 | #define SD_DAT1_STATUS 0x04 | |
386 | #define SD_DAT0_STATUS 0x02 | |
387 | #define SD_CMD_STATUS 0x01 | |
388 | ||
389 | /* SD_PAD_CTL */ | |
390 | #define SD_IO_USING_1V8 0x80 | |
391 | #define SD_IO_USING_3V3 0x7F | |
392 | #define TYPE_A_DRIVING 0x00 | |
393 | #define TYPE_B_DRIVING 0x01 | |
394 | #define TYPE_C_DRIVING 0x02 | |
395 | #define TYPE_D_DRIVING 0x03 | |
396 | ||
397 | /* SD_SAMPLE_POINT_CTL */ | |
398 | #define DDR_FIX_RX_DAT 0x00 | |
399 | #define DDR_VAR_RX_DAT 0x80 | |
400 | #define DDR_FIX_RX_DAT_EDGE 0x00 | |
401 | #define DDR_FIX_RX_DAT_14_DELAY 0x40 | |
402 | #define DDR_FIX_RX_CMD 0x00 | |
403 | #define DDR_VAR_RX_CMD 0x20 | |
404 | #define DDR_FIX_RX_CMD_POS_EDGE 0x00 | |
405 | #define DDR_FIX_RX_CMD_14_DELAY 0x10 | |
406 | #define SD20_RX_POS_EDGE 0x00 | |
407 | #define SD20_RX_14_DELAY 0x08 | |
408 | #define SD20_RX_SEL_MASK 0x08 | |
409 | ||
410 | /* SD_PUSH_POINT_CTL */ | |
411 | #define DDR_FIX_TX_CMD_DAT 0x00 | |
412 | #define DDR_VAR_TX_CMD_DAT 0x80 | |
413 | #define DDR_FIX_TX_DAT_14_TSU 0x00 | |
414 | #define DDR_FIX_TX_DAT_12_TSU 0x40 | |
415 | #define DDR_FIX_TX_CMD_NEG_EDGE 0x00 | |
416 | #define DDR_FIX_TX_CMD_14_AHEAD 0x20 | |
417 | #define SD20_TX_NEG_EDGE 0x00 | |
418 | #define SD20_TX_14_AHEAD 0x10 | |
419 | #define SD20_TX_SEL_MASK 0x10 | |
420 | #define DDR_VAR_SDCLK_POL_SWAP 0x01 | |
421 | ||
422 | /* SD_TRANSFER */ | |
423 | #define SD_TRANSFER_START 0x80 | |
424 | #define SD_TRANSFER_END 0x40 | |
425 | #define SD_STAT_IDLE 0x20 | |
426 | #define SD_TRANSFER_ERR 0x10 | |
427 | /* SD Transfer Mode definition */ | |
428 | #define SD_TM_NORMAL_WRITE 0x00 | |
429 | #define SD_TM_AUTO_WRITE_3 0x01 | |
430 | #define SD_TM_AUTO_WRITE_4 0x02 | |
431 | #define SD_TM_AUTO_READ_3 0x05 | |
432 | #define SD_TM_AUTO_READ_4 0x06 | |
433 | #define SD_TM_CMD_RSP 0x08 | |
434 | #define SD_TM_AUTO_WRITE_1 0x09 | |
435 | #define SD_TM_AUTO_WRITE_2 0x0A | |
436 | #define SD_TM_NORMAL_READ 0x0C | |
437 | #define SD_TM_AUTO_READ_1 0x0D | |
438 | #define SD_TM_AUTO_READ_2 0x0E | |
439 | #define SD_TM_AUTO_TUNING 0x0F | |
440 | ||
441 | /* SD_VPTX_CTL / SD_VPRX_CTL */ | |
442 | #define PHASE_CHANGE 0x80 | |
443 | #define PHASE_NOT_RESET 0x40 | |
444 | ||
445 | /* SD_DCMPS_TX_CTL / SD_DCMPS_RX_CTL */ | |
446 | #define DCMPS_CHANGE 0x80 | |
447 | #define DCMPS_CHANGE_DONE 0x40 | |
448 | #define DCMPS_ERROR 0x20 | |
449 | #define DCMPS_CURRENT_PHASE 0x1F | |
450 | ||
451 | /* SD_CMD_STATE */ | |
452 | #define SD_CMD_IDLE 0x80 | |
453 | ||
454 | /* SD_DATA_STATE */ | |
455 | #define SD_DATA_IDLE 0x80 | |
456 | ||
457 | /* MS_BLKEND */ | |
458 | #define SET_BLKEND 0x01 | |
459 | ||
460 | /* MS_CFG */ | |
461 | #define SAMPLE_TIME_RISING 0x00 | |
462 | #define SAMPLE_TIME_FALLING 0x80 | |
463 | #define PUSH_TIME_DEFAULT 0x00 | |
464 | #define PUSH_TIME_ODD 0x40 | |
465 | #define NO_EXTEND_TOGGLE 0x00 | |
466 | #define EXTEND_TOGGLE_CHK 0x20 | |
467 | #define MS_BUS_WIDTH_1 0x00 | |
468 | #define MS_BUS_WIDTH_4 0x10 | |
469 | #define MS_BUS_WIDTH_8 0x18 | |
470 | #define MS_2K_SECTOR_MODE 0x04 | |
471 | #define MS_512_SECTOR_MODE 0x00 | |
472 | #define MS_TOGGLE_TIMEOUT_EN 0x00 | |
473 | #define MS_TOGGLE_TIMEOUT_DISEN 0x01 | |
474 | #define MS_NO_CHECK_INT 0x02 | |
475 | ||
476 | /* MS_TRANS_CFG */ | |
477 | #define WAIT_INT 0x80 | |
478 | #define NO_WAIT_INT 0x00 | |
479 | #define NO_AUTO_READ_INT_REG 0x00 | |
480 | #define AUTO_READ_INT_REG 0x40 | |
481 | #define MS_CRC16_ERR 0x20 | |
482 | #define MS_RDY_TIMEOUT 0x10 | |
483 | #define MS_INT_CMDNK 0x08 | |
484 | #define MS_INT_BREQ 0x04 | |
485 | #define MS_INT_ERR 0x02 | |
486 | #define MS_INT_CED 0x01 | |
487 | ||
488 | /* MS_TRANSFER */ | |
489 | #define MS_TRANSFER_START 0x80 | |
490 | #define MS_TRANSFER_END 0x40 | |
491 | #define MS_TRANSFER_ERR 0x20 | |
492 | #define MS_BS_STATE 0x10 | |
493 | #define MS_TM_READ_BYTES 0x00 | |
494 | #define MS_TM_NORMAL_READ 0x01 | |
495 | #define MS_TM_WRITE_BYTES 0x04 | |
496 | #define MS_TM_NORMAL_WRITE 0x05 | |
497 | #define MS_TM_AUTO_READ 0x08 | |
498 | #define MS_TM_AUTO_WRITE 0x0C | |
499 | #define MS_TM_SET_CMD 0x06 | |
500 | #define MS_TM_COPY_PAGE 0x07 | |
501 | #define MS_TM_MULTI_READ 0x02 | |
502 | #define MS_TM_MULTI_WRITE 0x03 | |
503 | ||
504 | /* MC_DMA_CTL */ | |
505 | #define DMA_TC_EQ_0 0x80 | |
506 | #define DMA_DIR_TO_CARD 0x00 | |
507 | #define DMA_DIR_FROM_CARD 0x02 | |
508 | #define DMA_EN 0x01 | |
509 | #define DMA_128 (0 << 2) | |
510 | #define DMA_256 (1 << 2) | |
511 | #define DMA_512 (2 << 2) | |
512 | #define DMA_1024 (3 << 2) | |
513 | #define DMA_PACK_SIZE_MASK 0x0C | |
514 | ||
515 | /* CARD_INT_PEND */ | |
516 | #define XD_INT 0x10 | |
517 | #define MS_INT 0x08 | |
518 | #define SD_INT 0x04 | |
519 | ||
520 | /* MC_FIFO_CTL */ | |
521 | #define FIFO_FLUSH 0x01 | |
522 | ||
523 | /* AUTO_DELINK_EN */ | |
524 | #define AUTO_DELINK 0x02 | |
525 | #define FORCE_DELINK 0x01 | |
526 | ||
527 | /* MC_DMA_RST */ | |
528 | #define DMA_RESET 0x01 | |
529 | ||
530 | #define SSC_POWER_MASK 0x01 | |
531 | #define SSC_POWER_DOWN 0x01 | |
532 | #define SSC_POWER_ON 0x00 | |
533 | ||
534 | /* OCPCTL */ | |
535 | #define MS_OCP_DETECT_EN 0x08 | |
536 | #define MS_OCP_INT_EN 0x04 | |
537 | #define MS_OCP_INT_CLR 0x02 | |
538 | #define MS_OCP_CLEAR 0x01 | |
539 | ||
540 | /* OCPSTAT */ | |
541 | #define MS_OCP_DETECT 0x80 | |
542 | #define MS_OCP_NOW 0x02 | |
543 | #define MS_OCP_EVER 0x01 | |
544 | ||
545 | /* MC_FIFO_STAT */ | |
546 | #define FIFO_FULL 0x01 | |
547 | #define FIFO_EMPTY 0x02 | |
548 | ||
549 | /* RCCTL */ | |
550 | #define U_HW_CMD_EN_MASK 0x02 | |
551 | #define U_HW_CMD_EN 0x02 | |
552 | #define U_HW_CMD_DIS 0x00 | |
553 | ||
554 | /* Register address */ | |
555 | #define FPDCTL 0xFC00 | |
556 | #define SSC_DIV_N_0 0xFC07 | |
557 | #define SSC_CTL1 0xFC09 | |
558 | #define SSC_CTL2 0xFC0A | |
559 | #define CFG_MODE_1 0xFC0F | |
560 | #define RCCTL 0xFC14 | |
561 | #define SYS_DUMMY0 0xFC30 | |
562 | #define XD_CP_WAITTIME 0xFD00 | |
563 | #define XD_CP_PAGELEN 0xFD01 | |
564 | #define XD_CP_READADDR0 0xFD02 | |
565 | #define XD_CP_READADDR1 0xFD03 | |
566 | #define XD_CP_READADDR2 0xFD04 | |
567 | #define XD_CP_READADDR3 0xFD05 | |
568 | #define XD_CP_READADDR4 0xFD06 | |
569 | #define XD_CP_WRITEADDR0 0xFD07 | |
570 | #define XD_CP_WRITEADDR1 0xFD08 | |
571 | #define XD_CP_WRITEADDR2 0xFD09 | |
572 | #define XD_CP_WRITEADDR3 0xFD0A | |
573 | #define XD_CP_WRITEADDR4 0xFD0B | |
574 | #define XD_INIT 0xFD10 | |
575 | #define XD_DTCTL 0xFD11 | |
576 | #define XD_CTL 0xFD12 | |
577 | #define XD_TRANSFER 0xFD13 | |
578 | #define XD_CFG 0xFD14 | |
579 | #define XD_ADDRESS0 0xFD15 | |
580 | #define XD_ADDRESS1 0xFD16 | |
581 | #define XD_ADDRESS2 0xFD17 | |
582 | #define XD_ADDRESS3 0xFD18 | |
583 | #define XD_ADDRESS4 0xFD19 | |
584 | #define XD_DAT 0xFD1A | |
585 | #define XD_PAGE_CNT 0xFD1B | |
586 | #define XD_PAGE_STATUS 0xFD1C | |
587 | #define XD_BLOCK_STATUS 0xFD1D | |
588 | #define XD_BLOCK_ADDR1_L 0xFD1E | |
589 | #define XD_BLOCK_ADDR1_H 0xFD1F | |
590 | #define XD_BLOCK_ADDR2_L 0xFD20 | |
591 | #define XD_BLOCK_ADDR2_H 0xFD21 | |
592 | #define XD_BYTE_CNT_L 0xFD22 | |
593 | #define XD_BYTE_CNT_H 0xFD23 | |
594 | #define XD_PARITY 0xFD24 | |
595 | #define XD_ECC_BIT1 0xFD25 | |
596 | #define XD_ECC_BYTE1 0xFD26 | |
597 | #define XD_ECC_BIT2 0xFD27 | |
598 | #define XD_ECC_BYTE2 0xFD28 | |
599 | #define XD_RESERVED0 0xFD29 | |
600 | #define XD_RESERVED1 0xFD2A | |
601 | #define XD_RESERVED2 0xFD2B | |
602 | #define XD_RESERVED3 0xFD2C | |
603 | #define XD_CHK_DATA_STATUS 0xFD2D | |
604 | #define XD_CATCTL 0xFD2E | |
605 | ||
606 | #define MS_BLKEND 0xFD30 | |
607 | #define MS_READ_START 0xFD31 | |
608 | #define MS_READ_COUNT 0xFD32 | |
609 | #define MS_WRITE_START 0xFD33 | |
610 | #define MS_WRITE_COUNT 0xFD34 | |
611 | #define MS_COMMAND 0xFD35 | |
612 | #define MS_OLD_BLOCK_0 0xFD36 | |
613 | #define MS_OLD_BLOCK_1 0xFD37 | |
614 | #define MS_NEW_BLOCK_0 0xFD38 | |
615 | #define MS_NEW_BLOCK_1 0xFD39 | |
616 | #define MS_LOG_BLOCK_0 0xFD3A | |
617 | #define MS_LOG_BLOCK_1 0xFD3B | |
618 | #define MS_BUS_WIDTH 0xFD3C | |
619 | #define MS_PAGE_START 0xFD3D | |
620 | #define MS_PAGE_LENGTH 0xFD3E | |
621 | #define MS_CFG 0xFD40 | |
622 | #define MS_TPC 0xFD41 | |
623 | #define MS_TRANS_CFG 0xFD42 | |
624 | #define MS_TRANSFER 0xFD43 | |
625 | #define MS_INT_REG 0xFD44 | |
626 | #define MS_BYTE_CNT 0xFD45 | |
627 | #define MS_SECTOR_CNT_L 0xFD46 | |
628 | #define MS_SECTOR_CNT_H 0xFD47 | |
629 | #define MS_DBUS_H 0xFD48 | |
630 | ||
631 | #define CARD_DMA1_CTL 0xFD5C | |
632 | #define CARD_PULL_CTL1 0xFD60 | |
633 | #define CARD_PULL_CTL2 0xFD61 | |
634 | #define CARD_PULL_CTL3 0xFD62 | |
635 | #define CARD_PULL_CTL4 0xFD63 | |
636 | #define CARD_PULL_CTL5 0xFD64 | |
637 | #define CARD_PULL_CTL6 0xFD65 | |
638 | #define CARD_EXIST 0xFD6F | |
639 | #define CARD_INT_PEND 0xFD71 | |
640 | ||
641 | #define LDO_POWER_CFG 0xFD7B | |
642 | ||
643 | #define SD_CFG1 0xFDA0 | |
644 | #define SD_CFG2 0xFDA1 | |
645 | #define SD_CFG3 0xFDA2 | |
646 | #define SD_STAT1 0xFDA3 | |
647 | #define SD_STAT2 0xFDA4 | |
648 | #define SD_BUS_STAT 0xFDA5 | |
649 | #define SD_PAD_CTL 0xFDA6 | |
650 | #define SD_SAMPLE_POINT_CTL 0xFDA7 | |
651 | #define SD_PUSH_POINT_CTL 0xFDA8 | |
652 | #define SD_CMD0 0xFDA9 | |
653 | #define SD_CMD1 0xFDAA | |
654 | #define SD_CMD2 0xFDAB | |
655 | #define SD_CMD3 0xFDAC | |
656 | #define SD_CMD4 0xFDAD | |
657 | #define SD_CMD5 0xFDAE | |
658 | #define SD_BYTE_CNT_L 0xFDAF | |
659 | #define SD_BYTE_CNT_H 0xFDB0 | |
660 | #define SD_BLOCK_CNT_L 0xFDB1 | |
661 | #define SD_BLOCK_CNT_H 0xFDB2 | |
662 | #define SD_TRANSFER 0xFDB3 | |
663 | #define SD_CMD_STATE 0xFDB5 | |
664 | #define SD_DATA_STATE 0xFDB6 | |
665 | #define SD_VPCLK0_CTL 0xFC2A | |
666 | #define SD_VPCLK1_CTL 0xFC2B | |
667 | #define SD_DCMPS0_CTL 0xFC2C | |
668 | #define SD_DCMPS1_CTL 0xFC2D | |
669 | ||
670 | #define CARD_DMA1_CTL 0xFD5C | |
671 | ||
672 | #define HW_VERSION 0xFC01 | |
673 | ||
674 | #define SSC_CLK_FPGA_SEL 0xFC02 | |
675 | #define CLK_DIV 0xFC03 | |
676 | #define SFSM_ED 0xFC04 | |
677 | ||
678 | #define CD_DEGLITCH_WIDTH 0xFC20 | |
679 | #define CD_DEGLITCH_EN 0xFC21 | |
680 | #define AUTO_DELINK_EN 0xFC23 | |
681 | ||
682 | #define FPGA_PULL_CTL 0xFC1D | |
683 | #define CARD_CLK_SOURCE 0xFC2E | |
684 | ||
685 | #define CARD_SHARE_MODE 0xFD51 | |
686 | #define CARD_DRIVE_SEL 0xFD52 | |
687 | #define CARD_STOP 0xFD53 | |
688 | #define CARD_OE 0xFD54 | |
689 | #define CARD_AUTO_BLINK 0xFD55 | |
690 | #define CARD_GPIO 0xFD56 | |
691 | #define SD30_DRIVE_SEL 0xFD57 | |
692 | ||
693 | #define CARD_DATA_SOURCE 0xFD5D | |
694 | #define CARD_SELECT 0xFD5E | |
695 | ||
696 | #define CARD_CLK_EN 0xFD79 | |
697 | #define CARD_PWR_CTL 0xFD7A | |
698 | ||
699 | #define OCPCTL 0xFD80 | |
700 | #define OCPPARA1 0xFD81 | |
701 | #define OCPPARA2 0xFD82 | |
702 | #define OCPSTAT 0xFD83 | |
703 | ||
704 | #define HS_USB_STAT 0xFE01 | |
705 | #define HS_VCONTROL 0xFE26 | |
706 | #define HS_VSTAIN 0xFE27 | |
707 | #define HS_VLOADM 0xFE28 | |
708 | #define HS_VSTAOUT 0xFE29 | |
709 | ||
710 | #define MC_IRQ 0xFF00 | |
711 | #define MC_IRQEN 0xFF01 | |
712 | #define MC_FIFO_CTL 0xFF02 | |
713 | #define MC_FIFO_BC0 0xFF03 | |
714 | #define MC_FIFO_BC1 0xFF04 | |
715 | #define MC_FIFO_STAT 0xFF05 | |
716 | #define MC_FIFO_MODE 0xFF06 | |
717 | #define MC_FIFO_RD_PTR0 0xFF07 | |
718 | #define MC_FIFO_RD_PTR1 0xFF08 | |
719 | #define MC_DMA_CTL 0xFF10 | |
720 | #define MC_DMA_TC0 0xFF11 | |
721 | #define MC_DMA_TC1 0xFF12 | |
722 | #define MC_DMA_TC2 0xFF13 | |
723 | #define MC_DMA_TC3 0xFF14 | |
724 | #define MC_DMA_RST 0xFF15 | |
725 | ||
726 | /* Memory mapping */ | |
727 | #define RBUF_SIZE_MASK 0xFBFF | |
728 | #define RBUF_BASE 0xF000 | |
729 | #define PPBUF_BASE1 0xF800 | |
730 | #define PPBUF_BASE2 0xFA00 | |
731 | ||
732 | /* int monitor_card_cd */ | |
733 | #define CD_EXIST 0 | |
734 | #define CD_NOT_EXIST 1 | |
735 | ||
736 | #define DEBOUNCE_CNT 5 | |
737 | ||
738 | int monitor_card_cd(struct rts51x_chip *chip, u8 card); | |
739 | ||
355d8ae5 RT |
740 | void rts51x_do_remaining_work(struct rts51x_chip *chip); |
741 | void rts51x_do_rts51x_reset_sd_card(struct rts51x_chip *chip); | |
1dac4186 | 742 | void rts51x_init_cards(struct rts51x_chip *chip); |
743 | void rts51x_release_cards(struct rts51x_chip *chip); | |
355d8ae5 RT |
744 | int rts51x_switch_ssc_clock(struct rts51x_chip *chip, int clk); |
745 | int rts51x_switch_normal_clock(struct rts51x_chip *chip, int clk); | |
746 | int rts51x_card_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 sec_addr, | |
1dac4186 | 747 | u16 sec_cnt); |
355d8ae5 | 748 | u8 rts51x_get_lun_card(struct rts51x_chip *chip, unsigned int lun); |
1dac4186 | 749 | int rts51x_select_card(struct rts51x_chip *chip, int card); |
355d8ae5 RT |
750 | void rts51x_eject_card(struct rts51x_chip *chip, unsigned int lun); |
751 | void rts51x_trans_dma_enable(enum dma_data_direction dir, struct rts51x_chip *chip, | |
1dac4186 | 752 | u32 byte_cnt, u8 pack_size); |
355d8ae5 RT |
753 | int rts51x_enable_card_clock(struct rts51x_chip *chip, u8 card); |
754 | int rts51x_card_power_on(struct rts51x_chip *chip, u8 card); | |
755 | int rts51x_toggle_gpio(struct rts51x_chip *chip, u8 gpio); | |
756 | int rts51x_turn_on_led(struct rts51x_chip *chip, u8 gpio); | |
757 | int rts51x_turn_off_led(struct rts51x_chip *chip, u8 gpio); | |
1dac4186 | 758 | |
759 | static inline int check_card_ready(struct rts51x_chip *chip, unsigned int lun) | |
760 | { | |
761 | if (chip->card_ready & chip->lun2card[lun]) | |
762 | return 1; | |
763 | ||
764 | return 0; | |
765 | } | |
766 | ||
767 | static inline int check_card_exist(struct rts51x_chip *chip, unsigned int lun) | |
768 | { | |
769 | if (chip->card_exist & chip->lun2card[lun]) | |
770 | return 1; | |
771 | ||
772 | return 0; | |
773 | } | |
774 | ||
775 | static inline int check_card_wp(struct rts51x_chip *chip, unsigned int lun) | |
776 | { | |
777 | if (chip->card_wp & chip->lun2card[lun]) | |
778 | return 1; | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
783 | static inline int check_card_fail(struct rts51x_chip *chip, unsigned int lun) | |
784 | { | |
785 | if (chip->card_fail & chip->lun2card[lun]) | |
786 | return 1; | |
787 | ||
788 | return 0; | |
789 | } | |
790 | ||
791 | static inline int check_card_ejected(struct rts51x_chip *chip, unsigned int lun) | |
792 | { | |
793 | if (chip->card_ejected & chip->lun2card[lun]) | |
794 | return 1; | |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
799 | static inline int check_fake_card_ready(struct rts51x_chip *chip, | |
800 | unsigned int lun) | |
801 | { | |
802 | if (chip->fake_card_ready & chip->lun2card[lun]) | |
803 | return 1; | |
804 | ||
805 | return 0; | |
806 | } | |
807 | ||
808 | static inline u8 get_lun2card(struct rts51x_chip *chip, unsigned int lun) | |
809 | { | |
810 | return chip->lun2card[lun]; | |
811 | } | |
812 | ||
813 | static inline int check_lun_mc(struct rts51x_chip *chip, unsigned int lun) | |
814 | { | |
815 | return CHK_BIT(chip->lun_mc, lun); | |
816 | } | |
817 | ||
818 | static inline void set_lun_mc(struct rts51x_chip *chip, unsigned int lun) | |
819 | { | |
820 | SET_BIT(chip->lun_mc, lun); | |
821 | } | |
822 | ||
823 | static inline void clear_lun_mc(struct rts51x_chip *chip, unsigned int lun) | |
824 | { | |
825 | CLR_BIT(chip->lun_mc, lun); | |
826 | } | |
827 | ||
828 | static inline int switch_clock(struct rts51x_chip *chip, int clk) | |
829 | { | |
830 | int retval = 0; | |
831 | ||
832 | if (chip->asic_code) | |
355d8ae5 | 833 | retval = rts51x_switch_ssc_clock(chip, clk); |
1dac4186 | 834 | else |
355d8ae5 | 835 | retval = rts51x_switch_normal_clock(chip, clk); |
1dac4186 | 836 | |
837 | return retval; | |
838 | } | |
839 | ||
840 | static inline void rts51x_clear_xd_error(struct rts51x_chip *chip) | |
841 | { | |
842 | rts51x_ep0_write_register(chip, CARD_STOP, | |
843 | XD_STOP | XD_CLR_ERR, XD_STOP | XD_CLR_ERR); | |
844 | ||
845 | rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH, FIFO_FLUSH); | |
846 | rts51x_ep0_write_register(chip, MC_DMA_RST, DMA_RESET, DMA_RESET); | |
847 | rts51x_ep0_write_register(chip, SFSM_ED, 0xf8, 0xf8); | |
848 | } | |
849 | ||
850 | static inline void rts51x_clear_sd_error(struct rts51x_chip *chip) | |
851 | { | |
852 | rts51x_ep0_write_register(chip, CARD_STOP, | |
853 | SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); | |
854 | ||
855 | rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH, FIFO_FLUSH); | |
856 | rts51x_ep0_write_register(chip, MC_DMA_RST, DMA_RESET, DMA_RESET); | |
857 | rts51x_ep0_write_register(chip, SFSM_ED, 0xf8, 0xf8); | |
858 | } | |
859 | ||
860 | static inline void rts51x_clear_ms_error(struct rts51x_chip *chip) | |
861 | { | |
862 | rts51x_ep0_write_register(chip, CARD_STOP, | |
863 | MS_STOP | MS_CLR_ERR, MS_STOP | MS_CLR_ERR); | |
864 | ||
865 | rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH, FIFO_FLUSH); | |
866 | rts51x_ep0_write_register(chip, MC_DMA_RST, DMA_RESET, DMA_RESET); | |
867 | rts51x_ep0_write_register(chip, SFSM_ED, 0xf8, 0xf8); | |
868 | } | |
869 | ||
870 | #endif /* __RTS51X_CARD_H */ |