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staging: rtl8723bs: remove redundant statements
[linux-2.6-block.git] / drivers / staging / rtl8723bs / hal / HalPhyRf_8723B.c
CommitLineData
58391efd 1// SPDX-License-Identifier: GPL-2.0
4d17363d 2/*****************************************************************************
554c0a3a
HG		 3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
554c0a3a
HG		 6 ******************************************************************************/
7
8#include <drv_types.h>
9#include <rtw_debug.h>
10#include "odm_precomp.h"
11
12
13
14/*---------------------------Define Local Constant---------------------------*/
15/* 2010/04/25 MH Define the max tx power tracking tx agc power. */
16#define ODM_TXPWRTRACK_MAX_IDX8723B 6
17
18/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] */
19#define PATH_S0 1 /* RF_PATH_B */
20#define IDX_0xC94 0
21#define IDX_0xC80 1
22#define IDX_0xC4C 2
23#define IDX_0xC14 0
24#define IDX_0xCA0 1
25#define KEY 0
26#define VAL 1
27
28/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1] */
29#define PATH_S1 0 /* RF_PATH_A */
30#define IDX_0xC9C 0
31#define IDX_0xC88 1
32#define IDX_0xC4C 2
33#define IDX_0xC1C 0
34#define IDX_0xC78 1
35
36
37/*---------------------------Define Local Constant---------------------------*/
38
39/* In the case that we fail to read TxPowerTrack.txt, we use the table for
40 * 88E as the default table.
41 */
42static u8 DeltaSwingTableIdx_2GA_N_8188E[] = {
43 0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
44 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11
45};
46static u8 DeltaSwingTableIdx_2GA_P_8188E[] = {
47 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4,
48 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9
49};
50
51/* 3 ============================================================ */
52/* 3 Tx Power Tracking */
53/* 3 ============================================================ */
54
55
56static void setIqkMatrix_8723B(
57 PDM_ODM_T pDM_Odm,
58 u8 OFDM_index,
59 u8 RFPath,
60 s32 IqkResult_X,
61 s32 IqkResult_Y
62)
63{
64 s32 ele_A = 0, ele_D, ele_C = 0, value32;
65
66 if (OFDM_index >= OFDM_TABLE_SIZE)
67 OFDM_index = OFDM_TABLE_SIZE-1;
68
69 ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22;
70
71 /* new element A = element D x X */
72 if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) {
73 if ((IqkResult_X & 0x00000200) != 0) /* consider minus */
74 IqkResult_X = IqkResult_X | 0xFFFFFC00;
75 ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF;
76
77 /* new element C = element D x Y */
78 if ((IqkResult_Y & 0x00000200) != 0)
79 IqkResult_Y = IqkResult_Y | 0xFFFFFC00;
80 ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF;
81
82 /* if (RFPath == ODM_RF_PATH_A) */
83 switch (RFPath) {
84 case ODM_RF_PATH_A:
4d17363d
AH		 85 /* write new elements A, C, D to regC80 and regC94,
86 * element B is always 0
87 */
554c0a3a
HG		 88 value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
89 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, value32);
90
91 value32 = (ele_C&0x000003C0)>>6;
92 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
93
94 value32 = ((IqkResult_X * ele_D)>>7)&0x01;
95 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, value32);
96 break;
97 case ODM_RF_PATH_B:
4d17363d
AH		 98 /* write new elements A, C, D to regC88 and regC9C,
99 * element B is always 0
100 */
554c0a3a
HG		 101 value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
102 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
103
104 value32 = (ele_C&0x000003C0)>>6;
105 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
106
107 value32 = ((IqkResult_X * ele_D)>>7)&0x01;
108 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, value32);
109
110 break;
111 default:
112 break;
113 }
114 } else {
115 switch (RFPath) {
116 case ODM_RF_PATH_A:
117 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);
118 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);
119 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, 0x00);
120 break;
121
122 case ODM_RF_PATH_B:
123 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);
124 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);
125 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, 0x00);
126 break;
127
128 default:
129 break;
130 }
131 }
132
133 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n",
134 (u32)IqkResult_X, (u32)IqkResult_Y, (u32)ele_A, (u32)ele_C, (u32)ele_D, (u32)IqkResult_X, (u32)IqkResult_Y));
135}
136
137
138static void setCCKFilterCoefficient(PDM_ODM_T pDM_Odm, u8 CCKSwingIndex)
139{
140 if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
141 rtw_write8(pDM_Odm->Adapter, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]);
142 rtw_write8(pDM_Odm->Adapter, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]);
143 rtw_write8(pDM_Odm->Adapter, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]);
144 rtw_write8(pDM_Odm->Adapter, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]);
145 rtw_write8(pDM_Odm->Adapter, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]);
146 rtw_write8(pDM_Odm->Adapter, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]);
147 rtw_write8(pDM_Odm->Adapter, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]);
148 rtw_write8(pDM_Odm->Adapter, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]);
149 } else {
150 rtw_write8(pDM_Odm->Adapter, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]);
151 rtw_write8(pDM_Odm->Adapter, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]);
152 rtw_write8(pDM_Odm->Adapter, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]);
153 rtw_write8(pDM_Odm->Adapter, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]);
154 rtw_write8(pDM_Odm->Adapter, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]);
155 rtw_write8(pDM_Odm->Adapter, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]);
156 rtw_write8(pDM_Odm->Adapter, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]);
157 rtw_write8(pDM_Odm->Adapter, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]);
158 }
159}
160
161void DoIQK_8723B(
162 PDM_ODM_T pDM_Odm,
163 u8 DeltaThermalIndex,
164 u8 ThermalValue,
165 u8 Threshold
166)
167{
168}
169
170/*-----------------------------------------------------------------------------
171 * Function: odm_TxPwrTrackSetPwr88E()
172 *
68468503 173 * Overview: 88E change all channel tx power according to flag.
554c0a3a
HG		 174 * OFDM & CCK are all different.
175 *
176 * Input: NONE
177 *
178 * Output: NONE
179 *
180 * Return: NONE
181 *
182 * Revised History:
183 *When Who Remark
184 *04/23/2012 MHC Create Version 0.
185 *
186 *---------------------------------------------------------------------------*/
187void ODM_TxPwrTrackSetPwr_8723B(
188 PDM_ODM_T pDM_Odm,
189 PWRTRACK_METHOD Method,
190 u8 RFPath,
191 u8 ChannelMappedIndex
192)
193{
194 struct adapter *Adapter = pDM_Odm->Adapter;
195 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
196 u8 PwrTrackingLimit_OFDM = 34; /* 0dB */
197 u8 PwrTrackingLimit_CCK = 28; /* 2dB */
198 u8 TxRate = 0xFF;
199 u8 Final_OFDM_Swing_Index = 0;
200 u8 Final_CCK_Swing_Index = 0;
201
202 {
203 u16 rate = *(pDM_Odm->pForcedDataRate);
204
205 if (!rate) { /* auto rate */
206 if (pDM_Odm->TxRate != 0xFF)
207 TxRate = HwRateToMRate(pDM_Odm->TxRate);
208 } else /* force rate */
209 TxRate = (u8)rate;
210
211 }
212
213 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8723B\n"));
214
215 if (TxRate != 0xFF) {
216 /* 2 CCK */
217 if ((TxRate >= MGN_1M) && (TxRate <= MGN_11M))
218 PwrTrackingLimit_CCK = 28; /* 2dB */
219 /* 2 OFDM */
220 else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M))
221 PwrTrackingLimit_OFDM = 36; /* 3dB */
222 else if (TxRate == MGN_54M)
223 PwrTrackingLimit_OFDM = 34; /* 2dB */
224
225 /* 2 HT */
226 else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) /* QPSK/BPSK */
227 PwrTrackingLimit_OFDM = 38; /* 4dB */
228 else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) /* 16QAM */
229 PwrTrackingLimit_OFDM = 36; /* 3dB */
230 else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) /* 64QAM */
231 PwrTrackingLimit_OFDM = 34; /* 2dB */
232
233 else
234 PwrTrackingLimit_OFDM = pDM_Odm->DefaultOfdmIndex; /* Default OFDM index = 30 */
235 }
236 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxRate = 0x%x, PwrTrackingLimit =%d\n", TxRate, PwrTrackingLimit_OFDM));
237
238 if (Method == TXAGC) {
239 struct adapter *Adapter = pDM_Odm->Adapter;
240
241 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8723B CH =%d\n", *(pDM_Odm->pChannel)));
242
243 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
244
245 pDM_Odm->Modify_TxAGC_Flag_PathA = true;
246 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
247
248 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
249 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
250 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
251 } else if (Method == BBSWING) {
252 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
253 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
254
255 /* Adjust BB swing by OFDM IQ matrix */
256 if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM)
257 Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM;
258 else if (Final_OFDM_Swing_Index <= 0)
259 Final_OFDM_Swing_Index = 0;
260
261 if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE)
262 Final_CCK_Swing_Index = CCK_TABLE_SIZE-1;
263 else if (pDM_Odm->BbSwingIdxCck <= 0)
264 Final_CCK_Swing_Index = 0;
265
266 setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath,
267 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
268 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
269
270 setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index);
271
272 } else if (Method == MIX_MODE) {
273 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
274 ("pDM_Odm->DefaultOfdmIndex =%d, pDM_Odm->DefaultCCKIndex =%d, pDM_Odm->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n",
275 pDM_Odm->DefaultOfdmIndex, pDM_Odm->DefaultCckIndex, pDM_Odm->Absolute_OFDMSwingIdx[RFPath], RFPath));
276
277 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
278 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
279
280 if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { /* BBSwing higher then Limit */
281 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM;
282
283 setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, RFPath,
284 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
285 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
286
287 pDM_Odm->Modify_TxAGC_Flag_PathA = true;
288 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
289 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
290
291 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
292 ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n",
293 PwrTrackingLimit_OFDM, pDM_Odm->Remnant_OFDMSwingIdx[RFPath]));
294 } else if (Final_OFDM_Swing_Index <= 0) {
295 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index;
296
297 setIqkMatrix_8723B(pDM_Odm, 0, RFPath,
298 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
299 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
300
301 pDM_Odm->Modify_TxAGC_Flag_PathA = true;
302 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
303 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
304
305 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
306 ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n",
307 pDM_Odm->Remnant_OFDMSwingIdx[RFPath]));
308 } else {
309 setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath,
310 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
311 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
312
313 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
314 ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index));
315
316 if (pDM_Odm->Modify_TxAGC_Flag_PathA) { /* If TxAGC has changed, reset TxAGC again */
317 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = 0;
318 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
319 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
320 pDM_Odm->Modify_TxAGC_Flag_PathA = false;
321
322 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
323 ("******Path_A pDM_Odm->Modify_TxAGC_Flag = false\n"));
324 }
325 }
326
327 if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) {
328 pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK;
329 setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK);
330 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
331 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
332
333 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
334 ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx = %d\n", PwrTrackingLimit_CCK, pDM_Odm->Remnant_CCKSwingIdx));
335 } else if (Final_CCK_Swing_Index <= 0) { /* Lowest CCK Index = 0 */
336 pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index;
337 setCCKFilterCoefficient(pDM_Odm, 0);
338 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
339 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
340
341 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
342 ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx = %d\n", 0, pDM_Odm->Remnant_CCKSwingIdx));
343 } else {
344 setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index);
345
346 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
347 ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d\n", Final_CCK_Swing_Index));
348
349 if (pDM_Odm->Modify_TxAGC_Flag_PathA_CCK) { /* If TxAGC has changed, reset TxAGC again */
350 pDM_Odm->Remnant_CCKSwingIdx = 0;
351 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
352 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = false;
353
354 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
355 ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = false\n"));
356 }
357 }
358 } else
359 return; /* This method is not supported. */
360}
361
362static void GetDeltaSwingTable_8723B(
363 PDM_ODM_T pDM_Odm,
364 u8 **TemperatureUP_A,
365 u8 **TemperatureDOWN_A,
366 u8 **TemperatureUP_B,
367 u8 **TemperatureDOWN_B
368)
369{
370 struct adapter *Adapter = pDM_Odm->Adapter;
371 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
372 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
373 u16 rate = *(pDM_Odm->pForcedDataRate);
374 u8 channel = pHalData->CurrentChannel;
375
376 if (1 <= channel && channel <= 14) {
377 if (IS_CCK_RATE(rate)) {
378 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P;
379 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N;
380 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P;
381 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N;
382 } else {
383 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P;
384 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N;
385 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P;
386 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N;
387 }
388 } /*else if (36 <= channel && channel <= 64) {
389 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0];
390 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0];
391 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0];
392 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0];
393 } else if (100 <= channel && channel <= 140) {
394 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1];
395 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1];
396 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1];
397 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1];
398 } else if (149 <= channel && channel <= 173) {
399 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2];
400 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2];
401 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2];
402 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2];
403 }*/else {
404 *TemperatureUP_A = (u8 *)DeltaSwingTableIdx_2GA_P_8188E;
405 *TemperatureDOWN_A = (u8 *)DeltaSwingTableIdx_2GA_N_8188E;
406 *TemperatureUP_B = (u8 *)DeltaSwingTableIdx_2GA_P_8188E;
407 *TemperatureDOWN_B = (u8 *)DeltaSwingTableIdx_2GA_N_8188E;
408 }
554c0a3a
HG		 409}
410
411
412void ConfigureTxpowerTrack_8723B(PTXPWRTRACK_CFG pConfig)
413{
414 pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE;
415 pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE;
416 pConfig->Threshold_IQK = IQK_THRESHOLD;
417 pConfig->AverageThermalNum = AVG_THERMAL_NUM_8723B;
418 pConfig->RfPathCount = MAX_PATH_NUM_8723B;
419 pConfig->ThermalRegAddr = RF_T_METER_8723B;
420
421 pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723B;
422 pConfig->DoIQK = DoIQK_8723B;
423 pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723B;
424 pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723B;
425}
426
427/* 1 7. IQK */
428#define MAX_TOLERANCE 5
429#define IQK_DELAY_TIME 1 /* ms */
430
431/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
432static u8 phy_PathA_IQK_8723B(
433 struct adapter *padapter, bool configPathB, u8 RF_Path
434)
435{
436 u32 regEAC, regE94, regE9C, tmp, Path_SEL_BB /*, regEA4*/;
437 u8 result = 0x00;
438
439 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
440 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
441
442 /* Save RF Path */
443 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
444
445 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n"));
446
447 /* leave IQK mode */
448 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
449
450 /* enable path A PA in TXIQK mode */
451 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
452 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
453 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f);
454 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87);
455 /* disable path B PA in TXIQK mode */
456/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020); */
457/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1); */
458
459 /* 1 Tx IQK */
460 /* IQK setting */
461 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
462 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
463 /* path-A IQK setting */
464/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); */
465 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
466 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
467 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
468 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
469/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x8214010a); */
470 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea);
471 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
472 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
473 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
474
475 /* LO calibration setting */
476/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */
477 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
478
479 /* enter IQK mode */
480 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
481
482 /* Ant switch */
483 if (configPathB || (RF_Path == 0))
484 /* wifi switch to S1 */
485 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
486 else
487 /* wifi switch to S0 */
488 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
489
490 /* GNT_BT = 0 */
491 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
492
493 /* One shot, path A LOK & IQK */
494/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); */
495 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
496 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
497
498 /* delay x ms */
499/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B)); */
500 /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
501 mdelay(IQK_DELAY_TIME_8723B);
502
503 /* restore Ant Path */
504 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
505 /* GNT_BT = 1 */
506 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
507
508 /* leave IQK mode */
509 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
510
511
512 /* Check failed */
513 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
514 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
515 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
516 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
517 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));
518 /* monitor image power before & after IQK */
519 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK) = 0x%x, 0xe98(afer IQK) = 0x%x\n",
520 PHY_QueryBBReg(pDM_Odm->Adapter, 0xe90, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xe98, bMaskDWord)));
521
522
523 /* Allen 20131125 */
524 tmp = (regE9C & 0x03FF0000)>>16;
525 if ((tmp & 0x200) > 0)
526 tmp = 0x400 - tmp;
527
528 if (
529 !(regEAC & BIT28) &&
530 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
531 (((regE9C & 0x03FF0000)>>16) != 0x42) &&
532 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
533 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
534 (tmp < 0xf)
535 )
536 result |= 0x01;
537 else /* if Tx not OK, ignore Rx */
538 return result;
539
540 return result;
541}
542
543/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
544static u8 phy_PathA_RxIQK8723B(
545 struct adapter *padapter, bool configPathB, u8 RF_Path
546)
547{
548 u32 regEAC, regE94, regE9C, regEA4, u4tmp, tmp, Path_SEL_BB;
549 u8 result = 0x00;
550 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
551 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
552
553/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); */
554
555 /* Save RF Path */
556 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
557
558 /* leave IQK mode */
559 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
560
561 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK:Get TXIMR setting\n"));
562 /* 1 Get TXIMR setting */
563 /* modify RXIQK mode table */
564/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); */
565 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
566 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
567 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
568 /* LNA2 off, PA on for Dcut */
569 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
570/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
571 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
572
573 /* IQK setting */
574 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
575 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
576
577 /* path-A IQK setting */
578 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
579 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
580 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
581 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
582
583/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */
584 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0);
585 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
586 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
587 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
588
589 /* LO calibration setting */
590/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */
591 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
592
593 /* enter IQK mode */
594 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
595
596 /* Ant switch */
597 if (configPathB || (RF_Path == 0))
598 /* wifi switch to S1 */
599 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
600 else
601 /* wifi switch to S0 */
602 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
603
604 /* GNT_BT = 0 */
605 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
606
607 /* One shot, path A LOK & IQK */
608/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); */
609 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
610 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
611
612 /* delay x ms */
613/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B)); */
614 /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
615 mdelay(IQK_DELAY_TIME_8723B);
616
617 /* restore Ant Path */
618 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
619 /* GNT_BT = 1 */
620 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
621
622 /* leave IQK mode */
623 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
624
625 /* Check failed */
626 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
627 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
628 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
629 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
630 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));
631 /* monitor image power before & after IQK */
632 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK) = 0x%x, 0xe98(afer IQK) = 0x%x\n",
633 PHY_QueryBBReg(pDM_Odm->Adapter, 0xe90, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xe98, bMaskDWord)));
634
635 /* Allen 20131125 */
636 tmp = (regE9C & 0x03FF0000)>>16;
637 if ((tmp & 0x200) > 0)
638 tmp = 0x400 - tmp;
639
640 if (
641 !(regEAC & BIT28) &&
642 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
643 (((regE9C & 0x03FF0000)>>16) != 0x42) &&
644 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
645 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
646 (tmp < 0xf)
647 )
648 result |= 0x01;
649 else /* if Tx not OK, ignore Rx */
650 return result;
651
652 u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16);
653 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, u4tmp);
654 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", PHY_QueryBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord), u4tmp));
655
656
657 /* 1 RX IQK */
658 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK\n"));
659
660 /* modify RXIQK mode table */
661/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); */
662 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
663 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
664 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
665 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
666 /* LAN2 on, PA off for Dcut */
667 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77);
668/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
669
670 /* PA, PAD setting */
671 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80);
672 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f);
673
674
675 /* IQK setting */
676 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
677
678 /* path-A IQK setting */
679 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
680 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
681 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
682 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
683
684 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000);
685/* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */
686 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f);
687 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
688 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
689
690 /* LO calibration setting */
691/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */
692 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);
693
694 /* enter IQK mode */
695 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
696
697 /* Ant switch */
698 if (configPathB || (RF_Path == 0))
699 /* wifi switch to S1 */
700 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
701 else
702 /* wifi switch to S0 */
703 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
704
705 /* GNT_BT = 0 */
706 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
707
708 /* One shot, path A LOK & IQK */
709/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); */
710 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
711 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
712
713 /* delay x ms */
714/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); */
715 /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
716 mdelay(IQK_DELAY_TIME_8723B);
717
718 /* restore Ant Path */
719 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
720 /* GNT_BT = 1 */
721 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
722
723 /* leave IQK mode */
724 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
725
726 /* Check failed */
727 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
728 regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
729 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
730 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC));
731 /* monitor image power before & after IQK */
732 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK) = 0x%x, 0xea8(afer IQK) = 0x%x\n",
733 PHY_QueryBBReg(pDM_Odm->Adapter, 0xea0, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xea8, bMaskDWord)));
734
735 /* PA/PAD controlled by 0x0 */
736 /* leave IQK mode */
737 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
738 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780);
739
740 /* Allen 20131125 */
741 tmp = (regEAC & 0x03FF0000)>>16;
742 if ((tmp & 0x200) > 0)
743 tmp = 0x400 - tmp;
744
745 if (
746 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */
747 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
748 (((regEAC & 0x03FF0000)>>16) != 0x36) &&
749 (((regEA4 & 0x03FF0000)>>16) < 0x110) &&
750 (((regEA4 & 0x03FF0000)>>16) > 0xf0) &&
751 (tmp < 0xf)
752 )
753 result |= 0x02;
754 else /* if Tx not OK, ignore Rx */
755 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n"));
756 return result;
757}
758
759/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
760static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
761{
762 u32 regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEC4, regECC, Path_SEL_BB*/;
763 u8 result = 0x00;
764 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
765 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
766
767 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n"));
768
769 /* Save RF Path */
770 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
771
772 /* leave IQK mode */
773 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
774
775 /* in TXIQK mode */
776/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); */
777/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); */
778/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); */
779/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); */
780 /* enable path B PA in TXIQK mode */
781 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1);
782 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fc1);
783
784
785
786 /* 1 Tx IQK */
787 /* IQK setting */
788 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
789 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
790 /* path-A IQK setting */
791/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n")); */
792 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
793 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
794 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
795 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
796
797/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82140114); */
798 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea);
799 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
800 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
801 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
802
803 /* LO calibration setting */
804/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */
805 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
806
807 /* enter IQK mode */
808 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
809
810 /* switch to path B */
811 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
812/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
813
814 /* GNT_BT = 0 */
815 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
816
817 /* One shot, path B LOK & IQK */
818/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); */
819 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
820 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
821
822 /* delay x ms */
823/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E)); */
824 /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
825 mdelay(IQK_DELAY_TIME_8723B);
826
827 /* restore Ant Path */
828 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
829 /* GNT_BT = 1 */
830 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
831
832 /* leave IQK mode */
833 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
834
835/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x948 = 0x%x\n", PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord))); */
836
837
838 /* Check failed */
839 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
840 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
841 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
842 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
843 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));
844 /* monitor image power before & after IQK */
845 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK) = 0x%x, 0xe98(afer IQK) = 0x%x\n",
846 PHY_QueryBBReg(pDM_Odm->Adapter, 0xe90, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xe98, bMaskDWord)));
847
848 /* Allen 20131125 */
849 tmp = (regE9C & 0x03FF0000)>>16;
850 if ((tmp & 0x200) > 0)
851 tmp = 0x400 - tmp;
852
853 if (
854 !(regEAC & BIT28) &&
855 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
856 (((regE9C & 0x03FF0000)>>16) != 0x42) &&
857 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
858 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
859 (tmp < 0xf)
860 )
861 result |= 0x01;
862
863 return result;
864}
865
866/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
867static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
868{
869 u32 regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB;
870 u8 result = 0x00;
871 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
872 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
873
874/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n")); */
875
876 /* Save RF Path */
877 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
878 /* leave IQK mode */
879 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
880
881 /* switch to path B */
882 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
883
884 /* 1 Get TXIMR setting */
885 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK:Get TXIMR setting!\n"));
886 /* modify RXIQK mode table */
887/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); */
888 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
889 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
890 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
891 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
892 /* open PA S1 & SMIXER */
893 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1);
894 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fcd);
895
896
897 /* IQK setting */
898 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
899 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
900
901
902 /* path-B IQK setting */
903 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
904 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
905 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
906 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
907
908/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */
909 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0);
910 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
911 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
912 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
913
914 /* LO calibration setting */
915/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */
916 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
917
918 /* enter IQK mode */
919 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
920
921 /* switch to path B */
922 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
923/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
924
925 /* GNT_BT = 0 */
926 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
927
928 /* One shot, path B TXIQK @ RXIQK */
929/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); */
930 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
931 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
932
933
934 /* delay x ms */
935/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); */
936 /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
937 mdelay(IQK_DELAY_TIME_8723B);
938
939 /* restore Ant Path */
940 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
941 /* GNT_BT = 1 */
942 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
943
944 /* leave IQK mode */
945 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
946
947 /* Check failed */
948 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
949 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
950 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
951 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
952 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));
953 /* monitor image power before & after IQK */
954 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK) = 0x%x, 0xe98(afer IQK) = 0x%x\n",
955 PHY_QueryBBReg(pDM_Odm->Adapter, 0xe90, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xe98, bMaskDWord)));
956
957 /* Allen 20131125 */
958 tmp = (regE9C & 0x03FF0000)>>16;
959/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("tmp1 = 0x%x\n", tmp)); */
960 if ((tmp & 0x200) > 0)
961 tmp = 0x400 - tmp;
962/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("tmp2 = 0x%x\n", tmp)); */
963
964 if (
965 !(regEAC & BIT28) &&
966 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
967 (((regE9C & 0x03FF0000)>>16) != 0x42) &&
968 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
969 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
970 (tmp < 0xf)
971 )
972 result |= 0x01;
973 else /* if Tx not OK, ignore Rx */
974 return result;
975
976 u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16);
977 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, u4tmp);
978 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", PHY_QueryBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord), u4tmp));
979
980 /* 1 RX IQK */
981 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK\n"));
982
983 /* modify RXIQK mode table */
984 /* 20121009, Kordan> RF Mode = 3 */
985 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
986 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
987 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
988 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
989 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77);
990/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
991
992 /* open PA S1 & close SMIXER */
993 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1);
994 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30ebd);
995
996 /* PA, PAD setting */
997/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); */
998/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); */
999
1000 /* IQK setting */
1001 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
1002
1003 /* path-B IQK setting */
1004 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
1005 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
1006 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
1007 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
1008
1009 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000);
1010/* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */
1011 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f);
1012 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
1013 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
1014
1015 /* LO calibration setting */
1016/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */
1017 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);
1018
1019 /* enter IQK mode */
1020 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
1021
1022 /* switch to path B */
1023 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
1024/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
1025
1026 /* GNT_BT = 0 */
1027 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
1028
1029 /* One shot, path B LOK & IQK */
1030/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); */
1031 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
1032 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
1033
1034 /* delay x ms */
1035/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); */
1036 /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
1037 mdelay(IQK_DELAY_TIME_8723B);
1038
1039 /* restore Ant Path */
1040 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
1041 /* GNT_BT = 1 */
1042 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
1043
1044 /* leave IQK mode */
1045 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1046
1047 /* Check failed */
1048 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
66e3bc9c 1049 regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
554c0a3a
HG		 1050
1051 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
1052 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC));
1053 /* monitor image power before & after IQK */
1054 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK) = 0x%x, 0xea8(afer IQK) = 0x%x\n",
1055 PHY_QueryBBReg(pDM_Odm->Adapter, 0xea0, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xea8, bMaskDWord)));
1056
1057 /* PA/PAD controlled by 0x0 */
1058 /* leave IQK mode */
1059/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, 0xffffff00, 0x00000000); */
1060/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); */
1061
1062
1063
1064 /* Allen 20131125 */
1065 tmp = (regEAC & 0x03FF0000)>>16;
1066 if ((tmp & 0x200) > 0)
1067 tmp = 0x400 - tmp;
1068
1069 if (
1070 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */
1071 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
1072 (((regEAC & 0x03FF0000)>>16) != 0x36) &&
1073 (((regEA4 & 0x03FF0000)>>16) < 0x110) &&
1074 (((regEA4 & 0x03FF0000)>>16) > 0xf0) &&
1075 (tmp < 0xf)
1076 )
1077 result |= 0x02;
1078 else
1079 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n"));
1080
1081 return result;
1082}
1083
1084static void _PHY_PathAFillIQKMatrix8723B(
1085 struct adapter *padapter,
1086 bool bIQKOK,
1087 s32 result[][8],
1088 u8 final_candidate,
1089 bool bTxOnly
1090)
1091{
1092 u32 Oldval_0, X, TX0_A, reg;
1093 s32 Y, TX0_C;
1094 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1095 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1096
1097 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1098
1099 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n", (bIQKOK)?"Success":"Failed"));
1100
1101 if (final_candidate == 0xFF)
1102 return;
1103
1104 else if (bIQKOK) {
1105 Oldval_0 = (PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
1106
1107 X = result[final_candidate][0];
1108 if ((X & 0x00000200) != 0)
1109 X = X | 0xFFFFFC00;
1110 TX0_A = (X * Oldval_0) >> 8;
1111 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0));
1112 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
1113
1114 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(31), ((X*Oldval_0>>7) & 0x1));
1115
1116 Y = result[final_candidate][1];
1117 if ((Y & 0x00000200) != 0)
1118 Y = Y | 0xFFFFFC00;
1119
1120 /* 2 Tx IQC */
1121 TX0_C = (Y * Oldval_0) >> 8;
1122 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C));
1123 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));
1124 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;
1125 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskDWord);
1126
1127 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));
1128 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance;
1129 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord);
1130
1131 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(29), ((Y*Oldval_0>>7) & 0x1));
1132 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold;
1133 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord);
1134
1135 if (bTxOnly) {
1136 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix8723B only Tx OK\n"));
1137
1138 /* <20130226, Kordan> Saving RxIQC, otherwise not initialized. */
1139 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1140 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
1141 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1142/* pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */
1143 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100;
1144 return;
1145 }
1146
1147 reg = result[final_candidate][2];
1148
1149 /* 2 Rx IQC */
1150 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0x3FF, reg);
1151 reg = result[final_candidate][3] & 0x3F;
1152 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0xFC00, reg);
1153 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1154 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord);
1155
1156 reg = (result[final_candidate][3] >> 6) & 0xF;
1157 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
1158 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1159 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
1160
1161 }
1162}
1163
1164static void _PHY_PathBFillIQKMatrix8723B(
1165 struct adapter *padapter,
1166 bool bIQKOK,
1167 s32 result[][8],
1168 u8 final_candidate,
1169 bool bTxOnly /* do Tx only */
1170)
1171{
1172 u32 Oldval_1, X, TX1_A, reg;
1173 s32 Y, TX1_C;
1174 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1175 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1176
1177 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1178
1179 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n", (bIQKOK)?"Success":"Failed"));
1180
1181 if (final_candidate == 0xFF)
1182 return;
1183
1184 else if (bIQKOK) {
1185 Oldval_1 = (PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
1186
1187 X = result[final_candidate][4];
1188 if ((X & 0x00000200) != 0)
1189 X = X | 0xFFFFFC00;
1190 TX1_A = (X * Oldval_1) >> 8;
1191 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A));
1192
1193 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
1194
1195 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(27), ((X*Oldval_1>>7) & 0x1));
1196
1197 Y = result[final_candidate][5];
1198 if ((Y & 0x00000200) != 0)
1199 Y = Y | 0xFFFFFC00;
1200
1201 TX1_C = (Y * Oldval_1) >> 8;
1202 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C));
1203
1204 /* 2 Tx IQC */
1205 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
1206/* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE; */
1207/* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord); */
1208 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;
1209 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord);
1210
1211 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));
1212 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance;
1213 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord);
1214
1215 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(25), ((Y*Oldval_1>>7) & 0x1));
1216 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold;
1217 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord);
1218
1219 if (bTxOnly) {
1220 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathBFillIQKMatrix8723B only Tx OK\n"));
1221
1222 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1223/* pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */
1224 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100;
1225 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1226 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
1227 return;
1228 }
1229
1230 /* 2 Rx IQC */
1231 reg = result[final_candidate][6];
1232 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
1233 reg = result[final_candidate][7] & 0x3F;
1234 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
1235 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1236 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, bMaskDWord);
1237
1238 reg = (result[final_candidate][7] >> 6) & 0xF;
1239/* PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); */
1240 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1241 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord)&0x0fffffff);
1242 }
1243}
1244
1245/* */
1246/* 2011/07/26 MH Add an API for testing IQK fail case. */
1247/* */
1248/* MP Already declare in odm.c */
1249
1250void ODM_SetIQCbyRFpath(PDM_ODM_T pDM_Odm, u32 RFpath)
1251{
1252
1253 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1254
1255 if (
1256 (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) &&
1257 (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0) &&
1258 (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) &&
1259 (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0)
1260 ) {
1261 if (RFpath) { /* S1: RFpath = 0, S0:RFpath = 1 */
1262 /* S0 TX IQC */
1263 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]);
1264 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]);
1265 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]);
1266 /* S0 RX IQC */
1267 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]);
1268 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]);
1269 } else {
1270 /* S1 TX IQC */
1271 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]);
1272 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]);
1273 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]);
1274 /* S1 RX IQC */
1275 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]);
1276 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]);
1277 }
1278 }
1279}
1280
1281static bool ODM_CheckPowerStatus(struct adapter *Adapter)
1282{
1283 return true;
1284}
1285
1286static void _PHY_SaveADDARegisters8723B(
1287 struct adapter *padapter,
1288 u32 *ADDAReg,
1289 u32 *ADDABackup,
1290 u32 RegisterNum
1291)
1292{
1293 u32 i;
1294 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1295 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1296
941add8e 1297 if (!ODM_CheckPowerStatus(padapter))
554c0a3a
HG		 1298 return;
1299
1300 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n"));
1301 for (i = 0 ; i < RegisterNum ; i++) {
1302 ADDABackup[i] = PHY_QueryBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord);
1303 }
1304}
1305
1306
1307static void _PHY_SaveMACRegisters8723B(
1308 struct adapter *padapter, u32 *MACReg, u32 *MACBackup
1309)
1310{
1311 u32 i;
1312 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1313 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1314
1315 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n"));
1316 for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) {
1317 MACBackup[i] = rtw_read8(pDM_Odm->Adapter, MACReg[i]);
1318 }
1319 MACBackup[i] = rtw_read32(pDM_Odm->Adapter, MACReg[i]);
1320
1321}
1322
1323
1324static void _PHY_ReloadADDARegisters8723B(
1325 struct adapter *padapter,
1326 u32 *ADDAReg,
1327 u32 *ADDABackup,
1328 u32 RegiesterNum
1329)
1330{
1331 u32 i;
1332 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1333 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1334
1335 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n"));
1336 for (i = 0 ; i < RegiesterNum; i++) {
1337 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord, ADDABackup[i]);
1338 }
1339}
1340
1341static void _PHY_ReloadMACRegisters8723B(
1342 struct adapter *padapter, u32 *MACReg, u32 *MACBackup
1343)
1344{
1345 u32 i;
1346
1347 for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) {
1348 rtw_write8(padapter, MACReg[i], (u8)MACBackup[i]);
1349 }
1350 rtw_write32(padapter, MACReg[i], MACBackup[i]);
1351}
1352
1353
1354static void _PHY_PathADDAOn8723B(
1355 struct adapter *padapter,
1356 u32 *ADDAReg,
554c0a3a
HG		 1357 bool is2T
1358)
1359{
1360 u32 pathOn;
1361 u32 i;
1362 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1363 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1364
1365 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n"));
1366
5df20401 1367 pathOn = 0x01c00014;
941add8e 1368 if (!is2T) {
554c0a3a
HG		 1369 pathOn = 0x01c00014;
1370 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[0], bMaskDWord, 0x01c00014);
1371 } else {
1372 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[0], bMaskDWord, pathOn);
1373 }
1374
1375 for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) {
1376 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord, pathOn);
1377 }
1378
1379}
1380
1381static void _PHY_MACSettingCalibration8723B(
1382 struct adapter *padapter, u32 *MACReg, u32 *MACBackup
1383)
1384{
1385 u32 i = 0;
1386 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1387 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1388
1389 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n"));
1390
1391 rtw_write8(pDM_Odm->Adapter, MACReg[i], 0x3F);
1392
1393 for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) {
1394 rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT3)));
1395 }
1396 rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT5)));
1397
1398}
1399
1400static bool phy_SimularityCompare_8723B(
1401 struct adapter *padapter,
1402 s32 result[][8],
1403 u8 c1,
1404 u8 c2
1405)
1406{
1407 u32 i, j, diff, SimularityBitMap, bound = 0;
1408 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
1409 bool bResult = true;
554c0a3a
HG		 1410 s32 tmp1 = 0, tmp2 = 0;
1411
8a3f7b96 1412 bound = 8;
554c0a3a
HG		 1413 SimularityBitMap = 0;
1414
1415 for (i = 0; i < bound; i++) {
1416
1417 if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) {
1418 if ((result[c1][i] & 0x00000200) != 0)
1419 tmp1 = result[c1][i] | 0xFFFFFC00;
1420 else
1421 tmp1 = result[c1][i];
1422
1423 if ((result[c2][i] & 0x00000200) != 0)
1424 tmp2 = result[c2][i] | 0xFFFFFC00;
1425 else
1426 tmp2 = result[c2][i];
1427 } else {
1428 tmp1 = result[c1][i];
1429 tmp2 = result[c2][i];
1430 }
1431
1432 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
1433
1434 if (diff > MAX_TOLERANCE) {
1435 if ((i == 2 || i == 6) && !SimularityBitMap) {
1436 if (result[c1][i]+result[c1][i+1] == 0)
1437 final_candidate[(i/4)] = c2;
1438 else if (result[c2][i]+result[c2][i+1] == 0)
1439 final_candidate[(i/4)] = c1;
1440 else
1441 SimularityBitMap = SimularityBitMap|(1<<i);
1442 } else
1443 SimularityBitMap = SimularityBitMap|(1<<i);
1444 }
1445 }
1446
1447 if (SimularityBitMap == 0) {
1448 for (i = 0; i < (bound/4); i++) {
1449 if (final_candidate[i] != 0xFF) {
1450 for (j = i*4; j < (i+1)*4-2; j++)
1451 result[3][j] = result[final_candidate[i]][j];
1452 bResult = false;
1453 }
1454 }
1455 return bResult;
1456 } else {
1457
1458 if (!(SimularityBitMap & 0x03)) { /* path A TX OK */
1459 for (i = 0; i < 2; i++)
1460 result[3][i] = result[c1][i];
1461 }
1462
1463 if (!(SimularityBitMap & 0x0c)) { /* path A RX OK */
1464 for (i = 2; i < 4; i++)
1465 result[3][i] = result[c1][i];
1466 }
1467
1468 if (!(SimularityBitMap & 0x30)) { /* path B TX OK */
1469 for (i = 4; i < 6; i++)
1470 result[3][i] = result[c1][i];
1471 }
1472
1473 if (!(SimularityBitMap & 0xc0)) { /* path B RX OK */
1474 for (i = 6; i < 8; i++)
1475 result[3][i] = result[c1][i];
1476 }
1477 return false;
1478 }
1479}
1480
1481
1482
1483static void phy_IQCalibrate_8723B(
1484 struct adapter *padapter,
1485 s32 result[][8],
1486 u8 t,
1487 bool is2T,
1488 u8 RF_Path
1489)
1490{
1491 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1492 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1493
1494 u32 i;
1495 u8 PathAOK, PathBOK;
1496 u8 tmp0xc50 = (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC50, bMaskByte0);
1497 u8 tmp0xc58 = (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC58, bMaskByte0);
1498 u32 ADDA_REG[IQK_ADDA_REG_NUM] = {
1499 rFPGA0_XCD_SwitchControl,
1500 rBlue_Tooth,
1501 rRx_Wait_CCA,
1502 rTx_CCK_RFON,
1503 rTx_CCK_BBON,
1504 rTx_OFDM_RFON,
1505 rTx_OFDM_BBON,
1506 rTx_To_Rx,
1507 rTx_To_Tx,
1508 rRx_CCK,
1509 rRx_OFDM,
1510 rRx_Wait_RIFS,
1511 rRx_TO_Rx,
1512 rStandby,
1513 rSleep,
1514 rPMPD_ANAEN
1515 };
1516 u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = {
1517 REG_TXPAUSE,
1518 REG_BCN_CTRL,
1519 REG_BCN_CTRL_1,
1520 REG_GPIO_MUXCFG
1521 };
1522
1523 /* since 92C & 92D have the different define in IQK_BB_REG */
1524 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1525 rOFDM0_TRxPathEnable,
1526 rOFDM0_TRMuxPar,
1527 rFPGA0_XCD_RFInterfaceSW,
1528 rConfig_AntA,
1529 rConfig_AntB,
1530 rFPGA0_XAB_RFInterfaceSW,
1531 rFPGA0_XA_RFInterfaceOE,
1532 rFPGA0_XB_RFInterfaceOE,
1533 rCCK0_AFESetting
1534 };
1535 const u32 retryCount = 2;
1536
1537 /* Note: IQ calibration must be performed after loading */
1538 /* PHY_REG.txt , and radio_a, radio_b.txt */
1539
1540 /* u32 bbvalue; */
1541
1542 if (t == 0) {
1543/* bbvalue = PHY_QueryBBReg(pDM_Odm->Adapter, rFPGA0_RFMOD, bMaskDWord); */
1544/* RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E() ==>0x%08x\n", bbvalue)); */
1545
1546 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
1547
1548 /* Save ADDA parameters, turn Path A ADDA on */
1549 _PHY_SaveADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
1550 _PHY_SaveMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1551 _PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
1552 }
1553 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
1554
5df20401 1555 _PHY_PathADDAOn8723B(padapter, ADDA_REG, is2T);
554c0a3a
HG		 1556
1557/* no serial mode */
1558
1559 /* save RF path for 8723B */
1560/* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */
1561/* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff); */
1562
1563 /* MAC settings */
1564 _PHY_MACSettingCalibration8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1565
1566 /* BB setting */
1567 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_RFMOD, BIT24, 0x00); */
1568 PHY_SetBBReg(pDM_Odm->Adapter, rCCK0_AFESetting, 0x0f000000, 0xf);
1569 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
1570 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
1571 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
1572
1573
1574/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); */
1575/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); */
1576/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); */
1577/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); */
1578
1579
1580/* RX IQ calibration setting for 8723B D cut large current issue when leaving IPS */
1581
1582 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1583 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
1584 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
1585 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
1586 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
1587 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1);
1588 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd);
1589
1590/* path A TX IQK */
1591 for (i = 0 ; i < retryCount ; i++) {
1592 PathAOK = phy_PathA_IQK_8723B(padapter, is2T, RF_Path);
1593/* if (PathAOK == 0x03) { */
1594 if (PathAOK == 0x01) {
1595 /* Path A Tx IQK Success */
1596 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1597 pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x8, bRFRegOffsetMask);
1598
1599 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n"));
1600 result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1601 result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1602 break;
1603 }
1604 }
1605
1606/* path A RXIQK */
1607 for (i = 0 ; i < retryCount ; i++) {
1608 PathAOK = phy_PathA_RxIQK8723B(padapter, is2T, RF_Path);
1609 if (PathAOK == 0x03) {
1610 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n"));
1611/* result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1612/* result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1613 result[t][2] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1614 result[t][3] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1615 break;
1616 } else {
1617 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n"));
1618 }
1619 }
1620
1621 if (0x00 == PathAOK) {
1622 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n"));
1623 }
1624
1625/* path B IQK */
1626 if (is2T) {
1627
1628 /* path B TX IQK */
1629 for (i = 0 ; i < retryCount ; i++) {
1630 PathBOK = phy_PathB_IQK_8723B(padapter);
1631 if (PathBOK == 0x01) {
1632 /* Path B Tx IQK Success */
1633 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1634 pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B] = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, 0x8, bRFRegOffsetMask);
1635
1636 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n"));
1637 result[t][4] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1638 result[t][5] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1639 break;
1640 }
1641 }
1642
1643/* path B RX IQK */
1644 for (i = 0 ; i < retryCount ; i++) {
1645 PathBOK = phy_PathB_RxIQK8723B(padapter, is2T);
1646 if (PathBOK == 0x03) {
1647 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Success!!\n"));
1648/* result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1649/* result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1650 result[t][6] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1651 result[t][7] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1652 break;
1653 } else {
1654 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Fail!!\n"));
1655 }
1656 }
1657
1658/* Allen end */
1659 if (0x00 == PathBOK) {
1660 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n"));
1661 }
1662 }
1663
1664 /* Back to BB mode, load original value */
1665 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n"));
1666 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0);
1667
1668 if (t != 0) {
1669 /* Reload ADDA power saving parameters */
1670 _PHY_ReloadADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
1671
1672 /* Reload MAC parameters */
1673 _PHY_ReloadMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1674
1675 _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
1676
1677 /* Reload RF path */
1678/* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */
1679/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */
1680
1681 /* Allen initial gain 0xc50 */
1682 /* Restore RX initial gain */
1683 PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, 0x50);
1684 PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, tmp0xc50);
1685 if (is2T) {
1686 PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, 0x50);
1687 PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, tmp0xc58);
1688 }
1689
1690 /* load 0xe30 IQC default value */
1691 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1692 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1693
1694 }
1695 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8723B() <==\n"));
1696
1697}
1698
1699
1700static void phy_LCCalibrate_8723B(PDM_ODM_T pDM_Odm, bool is2T)
1701{
1702 u8 tmpReg;
1703 u32 RF_Amode = 0, RF_Bmode = 0, LC_Cal;
1704 struct adapter *padapter = pDM_Odm->Adapter;
1705
1706 /* Check continuous TX and Packet TX */
1707 tmpReg = rtw_read8(pDM_Odm->Adapter, 0xd03);
1708
1709 if ((tmpReg&0x70) != 0) /* Deal with contisuous TX case */
1710 rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg&0x8F); /* disable all continuous TX */
1711 else /* Deal with Packet TX case */
1712 rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0xFF); /* block all queues */
1713
1714 if ((tmpReg&0x70) != 0) {
1715 /* 1. Read original RF mode */
1716 /* Path-A */
1717 RF_Amode = PHY_QueryRFReg(padapter, ODM_RF_PATH_A, RF_AC, bMask12Bits);
1718
1719 /* Path-B */
1720 if (is2T)
1721 RF_Bmode = PHY_QueryRFReg(padapter, ODM_RF_PATH_B, RF_AC, bMask12Bits);
1722
1723 /* 2. Set RF mode = standby mode */
1724 /* Path-A */
1725 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
1726
1727 /* Path-B */
1728 if (is2T)
1729 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
1730 }
1731
1732 /* 3. Read RF reg18 */
1733 LC_Cal = PHY_QueryRFReg(padapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits);
1734
1735 /* 4. Set LC calibration begin bit15 */
1736 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); /* LDO ON */
1737 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
1738
1739 mdelay(100);
1740
1741 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); /* LDO OFF */
1742
1743 /* Channel 10 LC calibration issue for 8723bs with 26M xtal */
1744 if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2) {
1745 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal);
1746 }
1747
1748 /* Restore original situation */
1749 if ((tmpReg&0x70) != 0) { /* Deal with contisuous TX case */
1750 /* Path-A */
1751 rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg);
1752 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
1753
1754 /* Path-B */
1755 if (is2T)
1756 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
1757 } else /* Deal with Packet TX case */
1758 rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0x00);
1759}
1760
1761/* Analog Pre-distortion calibration */
1762#define APK_BB_REG_NUM 8
1763#define APK_CURVE_REG_NUM 4
1764#define PATH_NUM 2
1765
1766#define DP_BB_REG_NUM 7
1767#define DP_RF_REG_NUM 1
1768#define DP_RETRY_LIMIT 10
1769#define DP_PATH_NUM 2
1770#define DP_DPK_NUM 3
1771#define DP_DPK_VALUE_NUM 2
1772
1773
1774
1775/* IQK version:V2.5 20140123 */
1776/* IQK is controlled by Is2ant, RF path */
1777void PHY_IQCalibrate_8723B(
1778 struct adapter *padapter,
1779 bool bReCovery,
1780 bool bRestore,
1781 bool Is2ant, /* false:1ant, true:2-ant */
1782 u8 RF_Path /* 0:S1, 1:S0 */
1783)
1784{
1785 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1786
1787 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1788
1789 s32 result[4][8]; /* last is final result */
98ab51df 1790 u8 i, final_candidate;
554c0a3a
HG		 1791 bool bPathAOK, bPathBOK;
1792 s32 RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
1793 bool is12simular, is13simular, is23simular;
1794 bool bSingleTone = false, bCarrierSuppression = false;
1795 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1796 rOFDM0_XARxIQImbalance,
1797 rOFDM0_XBRxIQImbalance,
1798 rOFDM0_ECCAThreshold,
1799 rOFDM0_AGCRSSITable,
1800 rOFDM0_XATxIQImbalance,
1801 rOFDM0_XBTxIQImbalance,
1802 rOFDM0_XCTxAFE,
1803 rOFDM0_XDTxAFE,
1804 rOFDM0_RxIQExtAnta
1805 };
1806/* u32 Path_SEL_BB = 0; */
1807 u32 GNT_BT_default;
1808 u32 StartTime;
1809 s32 ProgressingTime;
1810
941add8e 1811 if (!ODM_CheckPowerStatus(padapter))
554c0a3a
HG		 1812 return;
1813
1814 if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
1815 return;
1816
1817 /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
1818 if (bSingleTone || bCarrierSuppression)
1819 return;
1820
1821#if DISABLE_BB_RF
1822 return;
1823#endif
1824 if (pDM_Odm->RFCalibrateInfo.bIQKInProgress)
1825 return;
1826
1827
1828 pDM_Odm->RFCalibrateInfo.bIQKInProgress = true;
1829
1830 if (bRestore) {
1831 u32 offset, data;
1832 u8 path, bResult = SUCCESS;
1833 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1834
1835 path = (PHY_QueryBBReg(pDM_Odm->Adapter, rS0S1_PathSwitch, bMaskByte0) == 0x00) ? ODM_RF_PATH_A : ODM_RF_PATH_B;
1836
1837 /* Restore TX IQK */
1838 for (i = 0; i < 3; ++i) {
1839 offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0];
1840 data = pRFCalibrateInfo->TxIQC_8723B[path][i][1];
1841 if ((offset == 0) || (data == 0)) {
1842 DBG_871X(
1843 "%s =>path:%s Restore TX IQK result failed\n",
1844 __func__,
1845 (path == ODM_RF_PATH_A)?"A":"B"
1846 );
1847 bResult = FAIL;
1848 break;
1849 }
1850 /* RT_TRACE(_module_mp_, _drv_notice_, ("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data)); */
1851 PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data);
1852 }
1853
1854 /* Restore RX IQK */
1855 for (i = 0; i < 2; ++i) {
1856 offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0];
1857 data = pRFCalibrateInfo->RxIQC_8723B[path][i][1];
1858 if ((offset == 0) || (data == 0)) {
1859 DBG_871X(
1860 "%s =>path:%s Restore RX IQK result failed\n",
1861 __func__,
1862 (path == ODM_RF_PATH_A)?"A":"B"
1863 );
1864 bResult = FAIL;
1865 break;
1866 }
1867 /* RT_TRACE(_module_mp_, _drv_notice_, ("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data)); */
1868 PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data);
1869 }
1870
1871 if (pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] == 0) {
1872 DBG_871X("%s => Restore Path-A TxLOK result failed\n", __func__);
1873 bResult = FAIL;
1874 } else {
1875 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A]);
1876 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B]);
1877 }
1878
1879 if (bResult == SUCCESS)
1880 return;
1881 }
1882
1883 if (bReCovery) {
1884 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8723B: Return due to bReCovery!\n"));
1885 _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
1886 return;
1887 }
1888 StartTime = jiffies;
1889 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n"));
1890
1891 /* save default GNT_BT */
1892 GNT_BT_default = PHY_QueryBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord);
1893 /* Save RF Path */
1894/* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */
1895/* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff); */
1896
1897 /* set GNT_BT = 0, pause BT traffic */
1898/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */
1899/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x1); */
1900
1901
1902 for (i = 0; i < 8; i++) {
1903 result[0][i] = 0;
1904 result[1][i] = 0;
1905 result[2][i] = 0;
1906 result[3][i] = 0;
1907 }
1908
1909 final_candidate = 0xff;
1910 bPathAOK = false;
1911 bPathBOK = false;
1912 is12simular = false;
1913 is23simular = false;
1914 is13simular = false;
1915
1916
1917 for (i = 0; i < 3; i++) {
1918 phy_IQCalibrate_8723B(padapter, result, i, Is2ant, RF_Path);
1919
1920 if (i == 1) {
1921 is12simular = phy_SimularityCompare_8723B(padapter, result, 0, 1);
1922 if (is12simular) {
1923 final_candidate = 0;
1924 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n", final_candidate));
1925 break;
1926 }
1927 }
1928
1929 if (i == 2) {
1930 is13simular = phy_SimularityCompare_8723B(padapter, result, 0, 2);
1931 if (is13simular) {
1932 final_candidate = 0;
1933 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n", final_candidate));
1934
1935 break;
1936 }
1937
1938 is23simular = phy_SimularityCompare_8723B(padapter, result, 1, 2);
1939 if (is23simular) {
1940 final_candidate = 1;
1941 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n", final_candidate));
1942 } else {
1943 for (i = 0; i < 8; i++)
1944 RegTmp += result[3][i];
1945
1946 if (RegTmp != 0)
1947 final_candidate = 3;
1948 else
1949 final_candidate = 0xFF;
1950 }
1951 }
1952 }
1953/* RT_TRACE(COMP_INIT, DBG_LOUD, ("Release Mutex in IQCalibrate\n")); */
1954
1955 for (i = 0; i < 4; i++) {
1956 RegE94 = result[i][0];
1957 RegE9C = result[i][1];
1958 RegEA4 = result[i][2];
1959 RegEAC = result[i][3];
1960 RegEB4 = result[i][4];
1961 RegEBC = result[i][5];
1962 RegEC4 = result[i][6];
1963 RegECC = result[i][7];
1964 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94 =%x RegE9C =%x RegEA4 =%x RegEAC =%x RegEB4 =%x RegEBC =%x RegEC4 =%x RegECC =%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
1965 }
1966
1967 if (final_candidate != 0xff) {
1968 pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0];
1969 pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1];
1970 RegEA4 = result[final_candidate][2];
1971 RegEAC = result[final_candidate][3];
1972 pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4];
1973 pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5];
1974 RegEC4 = result[final_candidate][6];
1975 RegECC = result[final_candidate][7];
1976 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n", final_candidate));
1977 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94 =%x RegE9C =%x RegEA4 =%x RegEAC =%x RegEB4 =%x RegEBC =%x RegEC4 =%x RegECC =%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
1978 bPathAOK = bPathBOK = true;
1979 } else {
1980 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n"));
1981
1982 pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; /* X default value */
1983 pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; /* Y default value */
1984 }
1985
1986 {
1987 if (RegE94 != 0)
1988 _PHY_PathAFillIQKMatrix8723B(padapter, bPathAOK, result, final_candidate, (RegEA4 == 0));
1989 }
1990 {
1991 if (RegEB4 != 0)
1992 _PHY_PathBFillIQKMatrix8723B(padapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
1993 }
1994
554c0a3a
HG		 1995/* To Fix BSOD when final_candidate is 0xff */
1996/* by sherry 20120321 */
1997 if (final_candidate < 4) {
1998 for (i = 0; i < IQK_Matrix_REG_NUM; i++)
98ab51df
MS		 1999 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[0].Value[0][i] = result[final_candidate][i];
2000 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[0].bIQKDone = true;
554c0a3a 2001 }
98ab51df 2002 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", 0));
554c0a3a
HG		 2003
2004 _PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
2005
2006 /* restore GNT_BT */
2007 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, GNT_BT_default);
2008 /* Restore RF Path */
2009/* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */
2010/* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */
2011
2012 /* Resotr RX mode table parameter */
2013 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
2014 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
2015 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
2016 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xe6177);
2017 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1);
2018 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd);
2019
2020 /* set GNT_BT = HW control */
2021/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */
2022/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x0); */
2023
2024 if (Is2ant) {
2025 if (RF_Path == 0x0) /* S1 */
2026 ODM_SetIQCbyRFpath(pDM_Odm, 0);
2027 else /* S0 */
2028 ODM_SetIQCbyRFpath(pDM_Odm, 1);
2029 }
2030
2031 pDM_Odm->RFCalibrateInfo.bIQKInProgress = false;
2032
2033 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n"));
2034 ProgressingTime = jiffies_to_msecs(jiffies - StartTime);
2035 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime));
2036
2037
2038}
2039
2040
2041void PHY_LCCalibrate_8723B(PDM_ODM_T pDM_Odm)
2042{
2043 bool bSingleTone = false, bCarrierSuppression = false;
2044 u32 timeout = 2000, timecount = 0;
2045 u32 StartTime;
2046 s32 ProgressingTime;
2047
2048#if DISABLE_BB_RF
2049 return;
2050#endif
2051
2052 if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
2053 return;
2054
2055 /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
2056 if (bSingleTone || bCarrierSuppression)
2057 return;
2058
2059 StartTime = jiffies;
2060 while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) {
2061 mdelay(50);
2062 timecount += 50;
2063 }
2064
2065 pDM_Odm->RFCalibrateInfo.bLCKInProgress = true;
2066
2067
2068 phy_LCCalibrate_8723B(pDM_Odm, false);
2069
2070
2071 pDM_Odm->RFCalibrateInfo.bLCKInProgress = false;
2072
2073 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex));
2074 ProgressingTime = jiffies_to_msecs(jiffies - StartTime);
2075 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime));
2076}
Linux 6.x block layer and io_uring tree(s)